Transistor and method of manufacturing the same

Abstract

The application provides a transistor and a manufacturing method thereof. The transistor comprises a substrate, a channel layer located above the substrate, a barrier layer located above the channel layer, a source, a drain and a gate in contact with and located above the barrier layer, the gate being located between the source and the drain, a field plate located above the barrier layer, and a first part of the field plate being projected between the gate and the drain in a vertical direction, a cavity structure being included between the first part of the field plate and the barrier layer, and a dielectric constant of the cavity structure being less than 3. The transistor provided by the application can reduce the leakage of radio frequency energy and improve the performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a transistor and a method for manufacturing the same. Background Technology

[0002] To improve the voltage withstand capability of power devices, the industry generally adopts a field-plate (FP) structure between the drain (D) and the gate (G) to form a critical electric field control region.

[0003] In a typical transistor structure, a channel layer, a barrier layer, and a dielectric layer are placed on the substrate. The source (S), drain (D), and gate (G) are in contact with and located above the barrier layer. The source (S) and drain (D) are connected to the channel layer through the barrier layer. A source-connected field-plate (SFP) is connected to the source (S), and at least part of the SFP is located between the gate (G) and drain (D). The barrier layer and dielectric layer separate the SFP from the channel layer. The SFP, dielectric layer, barrier layer, and channel layer form a capacitor structure. In high-frequency applications, a significant portion of the radio frequency (RF) energy leaks out through this structure, affecting the performance of power devices. Summary of the Invention

[0004] This application provides a transistor and a method for manufacturing the same, which can reduce radio frequency energy leakage and improve the performance of power devices.

[0005] In a first aspect, a transistor is provided, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source, a drain, and a gate, respectively contacting and located on the barrier layer, the gate being located between the source and the drain; a field plate located on the barrier layer, wherein a first portion of the field plate is projected in a vertical direction between the gate and the drain, the first portion comprising a cavity structure between the first portion and the barrier layer, the dielectric constant of the cavity structure being less than 3.

[0006] This application provides a transistor in which a cavity structure with a dielectric constant of less than 3 is included between the field plate and the barrier layer. This dielectric constant is smaller than that of conventional dielectric layers such as silicon dioxide (SiO2), thus reducing the equivalent dielectric constant of the overall structure, reducing dielectric loss, reducing RF energy leakage, and improving the performance of power devices.

[0007] It should be understood that the first part of the field plate is related to the shape and position of the field plate, and can be a part of the field plate or the entire field plate. This application does not limit this.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the cavity structure is a vacuum structure, or the cavity structure is filled with any one or more of the following: gas, material with a dielectric constant less than 3.

[0009] This application provides a transistor in which, when the cavity structure between the field plate and the barrier layer is a vacuum structure or filled with gas, it exhibits high stability, preventing dielectric degradation under high voltage and high temperature, reducing RF energy leakage, and improving power device performance. When the cavity structure is filled with a material with a dielectric constant less than 3, the transistor's capacitor structure has a lower dielectric constant than conventional dielectric layers such as silicon dioxide (SiO2), thus reducing the overall equivalent dielectric constant, lowering dielectric loss, reducing RF energy leakage, and improving power device performance.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the gas includes any one or more of nitrogen and inert gases.

[0011] The gas can be a chemically stable gas, such as nitrogen, or an inert gas, such as any one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn).

[0012] This application provides a transistor in which the cavity structure between the field plate and the barrier layer is a vacuum structure or the cavity structure is filled with gas. It has high stability and will not experience dielectric degradation under high pressure and high temperature, thereby reducing the leakage of radio frequency energy and improving the performance of power devices.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the material with a dielectric constant less than 3 includes any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0014] This application provides a transistor in which, when the cavity structure is filled with a material with a dielectric constant less than 3, the transistor includes a capacitor structure with a dielectric constant less than that of a conventional dielectric layer such as silicon dioxide (SiO2). This reduces the equivalent dielectric constant of the overall structure, reduces dielectric loss, reduces RF energy leakage, and improves the performance of power devices.

[0015] In conjunction with the first aspect, some implementations of the first aspect also include a support structure for supporting the field plate.

[0016] It should be understood that when the cavity structure is a vacuum structure, or when the cavity structure is filled with gas, a support structure can be used to support the field plate. When the cavity structure is filled with a material with a dielectric constant less than 3, a support structure is not required to support the field plate.

[0017] In some possible implementations, the material of the support structure can be metal.

[0018] This application provides a transistor in which a support structure can be used to support the field plate, thereby enhancing the stability of the transistor.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the second part of the support structure is located within the cavity structure, and one end of the second part is in contact with the field plate, and the other end is in contact with the barrier layer or with the dielectric layer located above the barrier layer.

[0020] For example, when there is no dielectric layer between the first portion and the barrier layer, one end of the second portion contacts the first portion of the field plate, and the other end contacts the barrier layer. When there is a dielectric layer between the first portion and the barrier layer, one end of the second portion contacts the first portion of the field plate, and the other end contacts the dielectric layer above the barrier layer.

[0021] It should be understood that the second part of the support structure can be a partial support structure or a complete support structure, and this application does not limit this. The partial support structure may also penetrate the barrier layer and the channel layer, and optionally, it may also penetrate part of the substrate.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the source, the drain, and the gate are disposed in a dielectric layer, and the first portion further includes the dielectric layer between it and the barrier layer.

[0023] This dielectric layer can also be called a passivation layer. The dielectric layer is typically composed of oxides or oxide-nitrogen compounds, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), or silicon oxynitride (SiON) x These materials can effectively reduce interface defects and prevent element diffusion, thereby improving the performance of power devices.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the transistor includes a gallium arsenide high electron mobility transistor (GaAs HEMT), a gallium nitride high electron mobility transistor (GaNHEMT), an indium phosphide high electron mobility transistor (InP HEMT), or a laterally diffused metal-oxide-semiconductor (LDMOS).

[0025] When the field plate in a transistor is electrically connected to the source, the field plate can be called the source field plate; when the field plate in a transistor is electrically connected to the drain, the field plate can be called the drain field plate. This application does not limit the type of field plate in a transistor.

[0026] This transistor can also be used in planar devices based on III-V (such as GaAs, InP) and II-VI (such as AlN) compound semiconductors, as well as in silicon carbide (SiC) or silicon (Si) based Schottky barrier diodes (SBDs) for high-power device termination designs, enabling higher performance or a wider range of applications.

[0027] In a second aspect, a method for fabricating a transistor is provided, the method comprising: forming a channel layer and a barrier layer on a substrate, the barrier layer being located on the channel layer; forming a source, a drain, and a gate on the barrier layer, the gate being located between the source and the drain; forming a cavity structure and a field plate on the barrier layer, the projection of a first portion of the field plate in a vertical direction being located between the gate and the drain, the first portion and the barrier layer comprising a cavity structure, the dielectric constant of the cavity structure being less than 3.

[0028] This application provides a method for fabricating a transistor, in which a cavity structure with a dielectric constant of less than 3 is included between the field plate and the barrier layer. This dielectric constant is smaller than that of traditional dielectric layers such as silicon dioxide (SiO2), thus reducing the equivalent dielectric constant of the overall structure, reducing dielectric loss, reducing RF energy leakage, and improving the performance of power devices.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, the cavity structure is a vacuum structure, or the cavity structure is filled with any one or more of the following: gas, material with a dielectric constant less than 3.

[0030] It should be understood that when the cavity structure is a vacuum structure or filled with gas, the cavity can be selectively recessed first, and then the suspended field plate structure can be formed using processes such as etching, multilayer photolithography, and vapor deposition lift-off. When the cavity structure is filled with a material with a dielectric constant less than 3, the cavity structure and dielectric filling can be formed first, and then the field plate can be formed.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the gas includes any one or more of nitrogen and inert gases.

[0032] In conjunction with the second aspect, in some implementations of the second aspect, the material with a dielectric constant less than 3 includes any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: forming a support structure on the barrier layer or dielectric layer to support the field plate, wherein the dielectric layer is located on the barrier layer.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the second part of the support structure is located within the cavity structure, and one end of the second part is in contact with the field plate, and the other end is in contact with the barrier layer or the dielectric layer.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, before forming the cavity structure and field plate on the barrier layer, the method further includes filling a dielectric over the barrier layer, the source, the drain, and the gate.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the transistor includes GaAs HEMT, GaNHEMT, InP HEMT, or LDMOS.

[0037] The beneficial effects of the second aspect and any possible implementation of the second aspect correspond to the beneficial effects of the first aspect and any possible implementation of the first aspect, which will not be elaborated further. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a transistor.

[0039] Figure 2 This is a schematic diagram of a transistor provided in an embodiment of this application.

[0040] Figure 3 This is a schematic diagram of another transistor provided in an embodiment of this application.

[0041] Figure 4 This is a schematic diagram of a transistor including different field plates provided in an embodiment of this application.

[0042] Figure 5 This is a schematic diagram of a transistor with different cavity structures provided in an embodiment of this application.

[0043] Figure 6 This is a top view schematic diagram of a transistor provided in an embodiment of this application.

[0044] Figure 7 This is a schematic diagram of a support structure provided in an embodiment of this application.

[0045] Figure 8 This is a schematic diagram of a transistor slice provided in an embodiment of this application.

[0046] Figure 9 This is a schematic diagram illustrating the effect of a transistor provided in an embodiment of this application.

[0047] Figure 10 This is an exemplary flowchart of a method for manufacturing a transistor provided in an embodiment of this application.

[0048] Figure 11 This is an exemplary flowchart of another method for manufacturing a transistor provided in this application embodiment.

[0049] Figure 12 This is an exemplary flowchart of another method for manufacturing a transistor provided in this application embodiment. Detailed Implementation

[0050] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0051] In the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0052] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0054] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0055] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0056] In radio frequency applications operating at 5 volts (V) and above, gallium arsenide (GaAs), gallium nitride (GaN), and laterally diffused metal-oxide-semiconductor (LDMOS) power device structures dominate. To improve the voltage withstand capability of power devices, the industry commonly uses a field-plate (FP) structure placed between the drain (D) and gate (G) to form a critical electric field modulation region.

[0057] When the field plate (FP) of a transistor is electrically connected to the source, the field plate can be called a source-connected field plate (SFP); when the FP of a transistor is electrically connected to the drain, the field plate can be called a drain-connected field plate (DFP). This application does not limit the type of field plate in a transistor. The following uses an SFP as an example to illustrate the transistor and its manufacturing method provided in the embodiments of this application. The same applies to DFP, and will not be described in detail here.

[0058] SFPs are widely used in lateral transistor structures and offer multiple technological advantages: First, by optimizing the electric field distribution between the gate and drain electrodes, they reduce the peak electric field intensity in high-field regions, effectively suppressing the risk of dielectric breakdown. Second, their metal layer structure can act as an electromagnetic shielding layer, suppressing the reverse coupling of high-frequency drain signals to the gate region, thereby improving signal integrity. This dual-action mechanism not only significantly improves the breakdown voltage and operational reliability of power devices but also enhances their power gain and efficiency.

[0059] Typically, an epitaxial layer and a dielectric layer exist between the SFP and the power device channel to support and form the FP structure. For example, above the active region of the semiconductor, an epitaxial layer with a specific doping concentration is first formed using epitaxial growth technology. This layer provides mechanical support for the field plate and also participates in constructing the lateral electric field gradient distribution. On the surface of the epitaxial layer, a dielectric layer prepared by chemical vapor deposition (CVD) provides electrical isolation; typical dielectric materials include silicon dioxide (SiO2) and silicon nitride (Si3N4). This layered composite structure forms a three-dimensional field plate electrode through photolithography and etching processes, ultimately achieving synergistic optimization of electric field modulation and electromagnetic shielding.

[0060] Figure 1 This is a schematic diagram of a transistor.

[0061] In this transistor structure, a channel layer, a barrier layer, and a dielectric layer are included on the substrate. The source (S), drain (D), and gate (G) are in contact with and located above the barrier layer. The source (S) and drain (D) are connected to the channel layer through the barrier layer. The gate (G) is in contact with the barrier layer and is located between the source (S) and drain (D). The SFP is connected to the source (S), and at least a portion of the SFP is located between the gate (G) and drain (D). A barrier layer and a dielectric layer separate the SFP from the channel layer.

[0062] The SFP, dielectric layer, barrier layer, and channel layer form a capacitor structure. The SFP and channel layer are equivalent to the conductive plates of this capacitor structure, and the dielectric layer and barrier layer are equivalent to the dielectric material between the two plates. In high-frequency scenarios, a considerable portion of the radio frequency energy will leak out through this structure, affecting the performance of power devices.

[0063] Figure 2 This is a schematic diagram of a transistor provided in an embodiment of this application.

[0064] The transistor includes a substrate 210, a channel layer 220, a barrier layer 230, a dielectric layer 240, a cavity structure 250, a source (S), a drain (D), a gate (G), and a field plate (FP). The channel layer 220 is located above the substrate 210, and the barrier layer 230 is located above the channel layer 220. The source (S), drain (D), and gate (G) are in contact with and located above the barrier layer 230, with the gate (G) located between the source (S) and drain (D). The field plate (FP) is located above the barrier layer 230, and the projection of the first portion 251 of the field plate (FP) in the vertical direction is located between the gate (G) and drain (D). The first portion 251 of the field plate (FP) and the barrier layer 230 include the cavity structure 250, and the dielectric constant of the cavity structure 250 is less than 3.

[0065] When the FP is electrically connected to the source (S), the FP is an SFP; when the FP is electrically connected to the drain (D), the FP is a DFP.

[0066] It should be understood that the first part 251 of the field plate FP is related to the shape and position of the field plate FP. The first part 251 can be part of the field plate FP or the entire field plate FP. This application does not limit this.

[0067] It should be understood that the first part 251 of the field plate FP and the barrier layer 230 include a cavity structure 250. The cavity structure 250 may be entirely disposed between the first part 251 and the barrier layer 230, or a portion of the cavity structure 250 may be disposed between the first part 251 and the barrier layer 230. This application does not limit this.

[0068] The substrate 210 serves as the supporting base for the transistor, and commonly used materials include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN). The substrate 210 can also be connected to the channel layer 220 through a buffer layer. The buffer layer (such as AlGaN or GaN) can suppress the difference in thermal expansion coefficients between the substrate 210 and the epitaxial layer, thus preventing cracking.

[0069] The channel layer 220 is the core region for carrier (electron or hole) transport in the transistor, located between the substrate 210 and the barrier layer 230. Its material needs to have high mobility and low defect density to achieve efficient conductivity. For example, in a GaN HEMT, the channel layer 220 is composed of undoped GaN.

[0070] The barrier layer 230, located above the channel layer 220, is used to modulate the distribution of charge carriers and form a heterojunction electric field. Its material must create a sufficient bandgap with the channel layer 220 to confine carrier movement. For example, in GaN HEMTs, the barrier layer 230 can be made of aluminum gallium nitride (AlGaN), whose higher bandgap forms a heterojunction with the GaN channel layer 220, inducing a high-density two-dimensional electron gas (2DEG) at the channel layer 220 interface. The barrier layer 230 can also be made of materials such as aluminum nitride (AlN) or indium aluminum nitride (InAlN) to further improve performance.

[0071] This dielectric layer 240 can also be referred to as a passivation layer. The dielectric layer 240 is typically composed of oxides or oxide-nitrogen compounds, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), or silicon oxynitride (SiON) x These materials can effectively reduce interface defects and prevent element diffusion, thereby improving the performance of power devices.

[0072] It should be understood that the dielectric layer 240 can be a single layer or multiple layers, or the dielectric layer 240 may not exist. For example, a fully hollow transistor can be formed by setting a support structure. This application does not limit this.

[0073] The cavity structure 250 can be a vacuum structure, or it can be filled with any one or more of the following materials: a gas with a dielectric constant less than 3. The gas can be a chemically stable gas, such as nitrogen, or an inert gas, such as any one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn). Materials with a dielectric constant less than 3 include any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0074] It should be understood that above the substrate 210 and below the channel layer 220, there may be other structures such as a nucleation layer and a buffer layer, and above the barrier layer 230, there may be other structures such as a cap layer. This application does not limit this.

[0075] The gate G can be a Schottky rectifier structure, a metal-insulator-semiconductor (MIS) structure, or a structure with a p-type gallium nitride (p-GaN) layer. A Schottky barrier formed by direct contact between the metal and semiconductor can be used as a rectifier structure. Compared to a pure Schottky gate, the MIS structure improves device performance by introducing an insulating layer (such as Al₂O₃, SiN, etc.). Structures with a p-type gallium nitride (p-GaN) layer can achieve enhancement-mode devices by introducing a p-type doped GaN layer into the power device.

[0076] Optional, such as Figure 3 As shown, the back side of the transistor can also be provided with a back gold layer 260 and a backside via 270 shorted to the source S. The back gold layer 260 is a metal layer deposited on the back side of the substrate 210. The backside via 270 is a through-hole formed on the back side of the substrate 210 by an etching process, used to realize front and back metal interconnects or heat conduction paths.

[0077] This transistor can be applied in gallium arsenide high electron mobility transistors (GaAs HEMTs), gallium nitride high electron mobility transistors (GaN HEMTs), indium phosphide high electron mobility transistors (InP HEMTs), or laterally diffused metal-oxide-semiconductors (LDMOS). It can also be applied in planar devices based on III-V (such as GaAs, InP) and II-VI (such as AlN) compound semiconductors, as well as in silicon carbide (SiC) or silicon (Si) based Schottky barrier diodes (SBDs), and in the terminal design of high-power devices, enabling higher performance or a wider range of applications.

[0078] Figure 4 This is a schematic diagram of a transistor including different field plates provided in an embodiment of this application.

[0079] The embodiments of this application do not limit the specific shape and position of the field plate FP, as long as the projection of the first part 251 of the field plate FP in the vertical direction is located between the gate G and the drain D. Figure 4 In (a), the projection of part of the field plate FP in the vertical direction is located above the gate G, and the projection of another part of the field plate FP in the vertical direction is located between the gate G and the drain D. The field plate FP and the gate G are connected through the dielectric layer 240, and the projection in the vertical direction completely covers the gate G. Figure 4 In (b), part of the field plate FP is projected in the vertical direction above the gate G, and another part of the field plate FP is projected in the vertical direction between the gate G and the drain D. The field plate FP and the gate G are connected through the dielectric layer 240, and the projection part in the vertical direction covers the gate G. Figure 4 In (c), the projection of part of the field plate FP in the vertical direction is located above the gate G, and the projection of another part of the field plate FP in the vertical direction is located between the gate G and the drain D. The field plate FP and the gate G are connected through the dielectric layer 240, and the projection in the vertical direction completely covers the gate G. Figure 4 In (d), the projection of the field plate FP in the vertical direction is located between the gate G and the drain D, and is connected to the gate G through the dielectric layer 240, and the projection in the vertical direction does not cover the gate G.

[0080] Figure 5 This is a schematic diagram of a transistor with different cavity structures provided in an embodiment of this application.

[0081] The embodiments of this application do not limit the specific shape and position of the cavity structure 250, as long as the first part 251 of the field plate FP and the barrier layer 230 include the cavity structure 250, and the dielectric constant of the cavity structure 250 is less than 3.

[0082] It should be understood that the first part 251 of the field plate FP and the barrier layer 230 include a cavity structure 250. The cavity structure 250 may be entirely disposed between the first part 251 and the barrier layer 230, or a portion of the cavity structure 250 may be disposed between the first part 251 and the barrier layer 230. This application does not limit this.

[0083] Figure 5 of (a), Figure 5 (b) and Figure 5 In (e), the first part 251 of the field plate FP and the barrier layer 230 include a cavity structure 250 and a dielectric layer 240. Figure 5 (c) Figure 5 (d) Figure 5 of (f), Figure 5 (g) and Figure 5In (h), the first part 251 of the field plate FP and the barrier layer 230 include only the cavity structure 250, excluding the dielectric layer 240.

[0084] It should be understood that the dielectric layer 240 can be a single layer or multiple layers, or the dielectric layer 240 may not exist, for example... Figure 5 The (h) transistor can be formed by setting the support structure 290 to form a fully hollow transistor, and this application does not limit this.

[0085] The cavity structure 250 can be a vacuum structure, or it can be filled with any one or more of the following materials: a gas with a dielectric constant less than 3. The gas can be a chemically stable gas, such as nitrogen, or an inert gas, such as any one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn). Materials with a dielectric constant less than 3 include any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0086] Figure 6 This is a top view schematic diagram of a transistor provided in an embodiment of this application.

[0087] It should be understood that when the cavity structure 250 is a vacuum structure, or when the cavity structure 250 is filled with gas, the support structure 290 can be used to support the field plate FP. When the cavity structure 250 is filled with a material with a dielectric constant less than 3, the support structure 290 is not required to support the field plate FP.

[0088] In some possible implementations, the material of the support structure 290 can be metal. This application does not limit the specific material, shape, quantity, or location of the support structure 290, as long as it can support the field plate FP.

[0089] The support structure 290 can be located in either the active region or the isolation region of the transistor. The active region is the area in a semiconductor device where active electronic components (such as transistors) are located, responsible for performing core circuit functions. The isolation region is a structure used to separate different device areas, prevent electrical interference or leakage, and ensure that each component operates independently. Figure 6 In (a), the support structure 290 is located in the active region; Figure 6 In (b), the support structure 290 is located in the isolation zone; Figure 6 (c) and Figure 6 In (d), part of the support structure 290 is located in the active zone, and part of the support structure 290 is located in the isolation zone.

[0090] Figure 7This is a schematic diagram of a support structure provided in an embodiment of this application.

[0091] The support structure 290 is used to support the field plate FP. The second part 252 of the support structure 290 is located inside the cavity structure 250, and one end of the second part 252 is in contact with the field plate FP, and the other end is in contact with the barrier layer 230 or the dielectric layer 240 located above the barrier layer 230.

[0092] It should be understood that the second part 252 of the support structure 290 can be a part or the entirety of the support structure 290, and this application does not limit it in this regard.

[0093] Figure 7 In (a), the second part 252 is the entirety of the support structure 290, and one end of the second part 252 is in contact with the field plate FP, and the other end is in contact with the barrier layer 230. Figure 7 In (b), the second part 252 is the entirety of the support structure 290, and one end of the second part 252 is in contact with the field plate FP, and the other end is in contact with the dielectric layer 240. Figure 7 In (c), the support structure 290 penetrates the dielectric layer 240, the second part 252 is a part of the support structure 290, and one end of the second part 252 is in contact with the field plate FP, and the other end is in contact with the dielectric layer 240. Figure 7 In (d), the support structure 290 penetrates the dielectric layer 240, the barrier layer 230 and the channel layer 220. The second part 252 is part of the support structure 290, and one end of the second part 252 is in contact with the field plate FP, and the other end is in contact with the dielectric layer 240.

[0094] Figure 8 This is a schematic diagram of a transistor slice provided in an embodiment of this application.

[0095] Figure 8 In (a), the two protrusions in the cavity structure 250 serve as support structures 290. By slicing the transistor along the directions of cutting point 1 and cutting point 2, the following can be obtained: Figure 8 (b) and Figure 8 (c) Cross-sectional view of the two transistors.

[0096] Figure 8 (b) shows the cavity structure 250 located below the field plate FP. Figure 8 In (c), the support structure 290 located below the field plate FP can be seen.

[0097] Figure 9 This is a schematic diagram illustrating the effect of a transistor provided in an embodiment of this application.

[0098] Figure 9 In (a), relative to Figure 1 While maintaining the same field plate capacitance C, the dielectric constant of cavity structure 250 is less than 3, which is less than the dielectric constant of traditional dielectric layers such as SiO2. Therefore, the equivalent dielectric constant of the overall structure is effectively reduced, dielectric loss is reduced, RF energy leakage is reduced, and the performance of power devices is improved.

[0099] Figure 9 In (b), relative to Figure 1 While maintaining the same height and the same gate-drain isolation effect, the introduction of cavity structure 250 reduces the parasitic effects of gate capacitance (Cgs) and drain capacitance (Cds).

[0100] Figure 10 This is an exemplary flowchart of a method for manufacturing a transistor provided in an embodiment of this application.

[0101] 1010, a channel layer 220 and a barrier layer 230 are formed on a substrate 210.

[0102] The substrate 210 serves as the supporting base for the transistor, and commonly used materials include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN). Exemplarily, a channel layer 220 and a barrier layer 230 can be formed on the substrate material (such as silicon or other semiconductor materials) using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques, with the barrier layer 230 situated above the channel layer 220.

[0103] The channel layer 220 is the core region for carrier (electron or hole) transport in the transistor. The thickness and material selection of this channel layer 220 depend on the application requirements of the power device to ensure good electrical characteristics. For example, in GaN HEMTs, the channel layer 220 is made of undoped GaN.

[0104] The barrier layer 230 is used to modulate the distribution of charge carriers and form a heterojunction electric field. Its material needs to create a sufficient bandgap with the channel layer 220 to confine carrier movement. For example, in GaN HEMTs, the barrier layer 230 can be made of aluminum gallium nitride (AlGaN), whose higher bandgap forms a heterojunction with the GaN channel layer 220, inducing a high-density two-dimensional electron gas (2DEG) at the channel layer 220 interface. The barrier layer 230 can also be made of materials such as aluminum nitride (AlN) or indium aluminum nitride (InAlN) to further improve performance.

[0105] A buffer layer can be formed on the substrate 210 to connect with the channel layer 220. The buffer layer (such as AlGaN or GaN) can suppress the difference in thermal expansion coefficients between the substrate 210 and the epitaxial layer and avoid cracking.

[0106] 1020, the source S, drain D and gate G are formed on the barrier layer 230 respectively.

[0107] A dielectric layer 240 is deposited on top of the barrier layer 230, forming the source (S), drain (D), and gate (G). The source (S) and drain (D) are typically made of highly conductive metals (such as aluminum, titanium, or copper), and their shapes and positions are defined by photolithography and etching processes. The gate (G) is located between the source (S) and drain (D), and is usually made of a metallic material. Appropriate processes are used to ensure good contact between the gate (S) and barrier layer 230 to achieve effective electric field control.

[0108] 1030, a cavity structure and field plate FP are formed on the barrier layer 230.

[0109] The field plate FP should be designed to ensure that it is at least partially located between the gate G and the drain D to enhance the electric field distribution and current conduction capability of the power device, thereby improving the performance and stability of the power device. For example, a dielectric layer can be filled over the barrier layer 230, the source S, the drain D, and the gate G before forming the field plate FP.

[0110] For example, the projection of the first portion 251 of the field plate FP in the vertical direction is located between the gate G and the drain D, and the first portion 251 and the barrier layer 230 include a cavity structure 250, the dielectric constant of the cavity structure being less than 3.

[0111] The cavity structure 250 can be a vacuum structure, or it can be filled with any one or more of the following materials: a gas with a dielectric constant less than 3. The gas can be a chemically stable gas, such as nitrogen, or an inert gas, such as any one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn). Materials with a dielectric constant less than 3 include any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0112] It should be understood that when the cavity structure 250 is a vacuum structure, or when the cavity structure 250 is filled with gas, a support structure can be used to support the field plate FP. When the cavity structure 250 is filled with a material with a dielectric constant less than 3, a support structure is not required to support the field plate FP.

[0113] It should be understood that when the cavity structure 250 is a vacuum structure, or when the cavity structure 250 is filled with gas, the cavity can be selectively recessed first, and then the suspended field plate structure can be formed using processes such as etching, multilayer photolithography, and vapor deposition lift-off. When the cavity structure 250 is filled with a material with a dielectric constant less than 3, the cavity structure 250 and dielectric filling can be formed first, and then the field plate FP can be formed.

[0114] Figure 11 This is an exemplary flowchart of another method for manufacturing a transistor provided in this application embodiment.

[0115] The cavity structure 250 formed by this method is either a vacuum or filled with gas, and therefore the field plate FP is supported by a support structure 290, the gas including any one or more of nitrogen and inert gases.

[0116] 1110, a channel layer 220 and a barrier layer 230 are formed on a substrate 210.

[0117] The substrate 210 serves as the supporting base for the transistor, and commonly used materials include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN). Exemplarily, a channel layer 220 and a barrier layer 230 can be formed on the substrate material (such as silicon or other semiconductor materials) using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition techniques, with the barrier layer 230 situated above the channel layer 220.

[0118] The channel layer 220 is the core region for carrier (electron or hole) transport in the transistor. The thickness and material selection of this channel layer 220 depend on the application requirements of the power device to ensure good electrical characteristics. For example, in GaN HEMTs, the channel layer 220 is made of undoped GaN.

[0119] The barrier layer 230 is used to modulate the distribution of charge carriers and form a heterojunction electric field. Its material needs to create a sufficient bandgap with the channel layer 220 to confine carrier movement. For example, in GaN HEMTs, the barrier layer 230 can be made of aluminum gallium nitride (AlGaN), whose higher bandgap forms a heterojunction with the GaN channel layer 220, inducing a high-density two-dimensional electron gas (2DEG) at the channel layer 220 interface. The barrier layer 230 can also be made of materials such as aluminum nitride (AlN) or indium aluminum nitride (InAlN) to further improve performance.

[0120] A buffer layer can be formed on the substrate 210 to connect with the channel layer 220. The buffer layer (such as AlGaN or GaN) can suppress the difference in thermal expansion coefficients between the substrate 210 and the epitaxial layer and avoid cracking.

[0121] In some possible implementations, the channel layer 220 and the barrier layer 230 can be locally isolated to reserve space for the subsequent formation of the support structure 290.

[0122] 1120, forming the source (S), drain (D), and gate (G).

[0123] A dielectric layer 240 is deposited above the barrier layer 230. This dielectric layer 240 may also be referred to as a passivation layer, and is typically composed of oxides or oxide nitrides, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), or silicon oxynitride (SiON) x These materials can effectively reduce interface defects and prevent element diffusion, thereby improving the performance of power devices.

[0124] The source (S), drain (D), and gate (G) are formed through the dielectric layer 240. The source (S) and drain (D) are typically made of highly conductive metals (such as aluminum, titanium, or copper), and their shapes and positions are defined by photolithography and etching processes. The gate (G) is located between the source (S) and drain (D), and is typically made of a metallic material. Appropriate processes are used to ensure good contact between the gate (G) and the barrier layer 230 to achieve effective electric field control.

[0125] 1130, forming a dielectric layer.

[0126] A dielectric layer 240 is deposited on top of the formed structure. Optionally, the dielectric layer 240 can be partially etched back to adjust the height of the field plate FP.

[0127] 1140, forming the cavity structure, support structure and field plate.

[0128] For example, a photolithography process can be used to form a cavity structure 250, a support structure 290, and a field plate FP. By utilizing the different photosensitive properties of the multilayer photoresist, the support structure 290 and the field plate FP are locally formed to meet the photoresist structure morphology for metal stripping. Combined with metal evaporation and stripping processes, a partially supported cavity structure 250 is formed, which is a cavity.

[0129] For example, the projection of the first portion 251 of the field plate FP in the vertical direction is located between the gate G and the drain D, and the first portion 251 and the barrier layer 230 include a cavity structure 250, the dielectric constant of the cavity structure being less than 3.

[0130] The cavity structure 250 can be a vacuum structure, or it can be filled with gas. The gas can be a chemically stable gas, such as nitrogen, or an inert gas, such as any one or more of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn).

[0131] The support structure 290 can penetrate the barrier layer 230 and the channel layer 220, and optionally, it can also penetrate part of the substrate 210 and protrude from the barrier layer 230.

[0132] The support structure 290 is used to support the field plate FP. A second portion 252 of the support structure 290 is located within the cavity structure 250, with one end of the second portion 252 contacting the field plate FP and the other end contacting the barrier layer 230 or the dielectric layer 240 located above the barrier layer 230. It should be understood that the second portion 252 of the support structure 290 can be a part or the entirety of the support structure 290, and this application does not impose any limitation on this.

[0133] The support structure 290 can also be referred to as a pier, support section, etc. This application does not limit the specific name.

[0134] It should be understood that the field plate FP may also be locally raised due to the presence of the cavity structure 250.

[0135] Figure 12 This is an exemplary flowchart of another method for manufacturing a transistor provided in this application embodiment.

[0136] The cavity structure 250 formed by this method is filled with a material with a dielectric constant less than 3. The material with a dielectric constant less than 3 includes any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0137] 1210, a channel layer 220 and a barrier layer 230 are formed on the substrate 210.

[0138] The substrate 210 serves as the supporting base for the transistor, and commonly used materials include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN). Exemplarily, a channel layer 220 and a barrier layer 230 can be formed on the substrate material (such as silicon or other semiconductor materials) using CVD, PVD, or other suitable deposition techniques, with the barrier layer 230 located above the channel layer 220.

[0139] The channel layer 220 is the core region for carrier (electron or hole) transport in the transistor. The thickness and material selection of this channel layer 220 depend on the application requirements of the power device to ensure good electrical characteristics. For example, in GaN HEMTs, the channel layer 220 is made of undoped GaN.

[0140] The barrier layer 230 is used to modulate the distribution of charge carriers and form a heterojunction electric field. Its material needs to create a sufficient bandgap with the channel layer 220 to confine carrier movement. For example, in GaN HEMTs, the barrier layer 230 can be made of aluminum gallium nitride (AlGaN), whose higher bandgap forms a heterojunction with the GaN channel layer 220, inducing a high-density two-dimensional electron gas (2DEG) at the channel layer 220 interface. The barrier layer 230 can also be made of materials such as aluminum nitride (AlN) or indium aluminum nitride (InAlN) to further improve performance.

[0141] A buffer layer can be formed on the substrate 210 to connect with the channel layer 220. The buffer layer (such as AlGaN or GaN) can suppress the difference in thermal expansion coefficients between the substrate 210 and the epitaxial layer and avoid cracking.

[0142] 1220, the source S, drain D and gate G are formed on the barrier layer 230 respectively.

[0143] A dielectric layer 240 is deposited on top of the barrier layer 230, forming the source (S), drain (D), and gate (G). The source (S) and drain (D) are typically made of highly conductive metals (such as aluminum, titanium, or copper), and their shapes and positions are defined by photolithography and etching processes. The gate (G) is located between the source (S) and drain (D), and is usually made of a metallic material. Appropriate processes are used to ensure good contact between the gate (S) and barrier layer 230 to achieve effective electric field control.

[0144] 1230, a cavity structure is formed on top of barrier layer 230.

[0145] The cavity structure 250 is filled with a material with a dielectric constant less than 3, which includes any one or more of polybenzoxazole (PBO), polyimide (PI), or benzocyclobutene (BCB).

[0146] For example, a cavity structure 250 can be formed in the dielectric layer 240 between the gate G and the drain D by an etching process, and then the cavity structure 250 can be filled with a material with a dielectric constant of less than 3.

[0147] 1240, forming the field plate FP.

[0148] A field plate is formed on the cavity structure 250. For example, a metallic material can be deposited on the cavity structure 250 to form the field plate FP, typically aluminum or gold as the material of the field plate FP.

[0149] The field plate FP is designed to ensure that it is at least partially located between the gate G and the drain D. For example, the projection of the first portion 251 of the field plate FP in the vertical direction is located between the gate G and the drain D, and the first portion 251 includes a cavity structure 250 between itself and the barrier layer 230.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transistor, characterized in that, include: Substrate; The channel layer is located on the substrate; A barrier layer is located above the channel layer; The source, drain, and gate are respectively in contact with the barrier layer and located on the barrier layer, with the gate located between the source and the drain; A field plate is located above the barrier layer, and the projection of a first portion of the field plate in the vertical direction is located between the gate and the drain. The first portion and the barrier layer include a cavity structure, and the dielectric constant of the cavity structure is less than 3.

2. The transistor according to claim 1, characterized in that, The cavity structure is a vacuum structure, or the cavity structure is filled with any one or more of the following: gas, material with a dielectric constant of less than 3.

3. The transistor according to claim 2, characterized in that, The gas includes any one or more of nitrogen and inert gases.

4. The transistor according to claim 2 or 3, characterized in that, The materials with a dielectric constant less than 3 include any one or more of polybenzoxazole PBO, polyimide PI, or benzocyclobutene BCB.

5. The transistor according to any one of claims 1 to 4, characterized in that, It also includes a support structure for supporting the field plate.

6. The transistor according to claim 5, characterized in that, The second part of the support structure is located inside the cavity structure, and one end of the second part is in contact with the field plate, and the other end is in contact with the barrier layer or with the dielectric layer located above the barrier layer.

7. The transistor according to any one of claims 1 to 6, characterized in that, The source, the drain, and the gate are disposed in a dielectric layer, and the first portion further includes the dielectric layer between it and the barrier layer.

8. The transistor according to any one of claims 1 to 7, characterized in that, The transistors include gallium arsenide high electron mobility transistors (GaAs HEMTs), gallium nitride high electron mobility transistors (GaN HEMTs), indium phosphide high electron mobility transistors (InP HEMTs), or laterally diffused metal oxide semiconductors (LDMOS).

9. A method for manufacturing a transistor, characterized in that, include: A channel layer and a barrier layer are formed on a substrate, wherein the barrier layer is located on the channel layer; A source, a drain, and a gate are formed on the barrier layer, with the gate located between the source and the drain. A cavity structure and a field plate are formed on the barrier layer. The projection of a first portion of the field plate in the vertical direction is located between the gate and the drain. The cavity structure is located between the first portion and the barrier layer. The dielectric constant of the cavity structure is less than 3.

10. The method according to claim 9, characterized in that, The cavity structure is a vacuum structure, or the cavity structure is filled with any one or more of the following: gas, material with a dielectric constant of less than 3.

11. The method according to claim 10, characterized in that, The gas includes any one or more of nitrogen and inert gases.

12. The method according to claim 10 or 11, characterized in that, The materials with a dielectric constant less than 3 include any one or more of polybenzoxazole PBO, polyimide PI, or benzocyclobutene BCB.

13. The method according to any one of claims 9 to 12, characterized in that, The method further includes: A support structure is formed on the barrier layer or dielectric layer to support the field plate, wherein the dielectric layer is located on the barrier layer.

14. The method according to claim 13, characterized in that, The second part of the support structure is located inside the cavity structure, and one end of the second part is in contact with the field plate, and the other end is in contact with the barrier layer or the dielectric layer.

15. The method according to any one of claims 9 to 14, characterized in that, Before forming the cavity structure and field plate on the barrier layer, the method further includes: A dielectric is filled over the barrier layer, the source, the drain, and the gate.

16. The method according to any one of claims 9 to 15, characterized in that, The transistors include gallium arsenide high electron mobility transistors (GaAs HEMTs), gallium nitride high electron mobility transistors (GaN HEMTs), indium phosphide high electron mobility transistors (InP HEMTs), or laterally diffused metal oxide semiconductors (LDMOS).

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