Semiconductor device

Abstract

The semiconductor device provided by the embodiment of the present application comprises a substrate, an epitaxial layer, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a first electrode layer and a gate structure. The fourth doped region comprises a plurality of doped sub-regions which are arranged along the circumference of the third doped region and are connected to the third doped region respectively. The third doped region and the fourth doped region are arranged below the trench and are spaced from the bottom surface of the trench, and the fifth doped region is arranged on both sides of the trench, so as to be used as a plurality of mask layers respectively, which can better protect the gate oxide layer of the device. Furthermore, the plurality of doped sub-regions are arranged in a three-dimensional manner, so as to increase the current path and reduce the resistance and power loss of the device. In addition, the third doped region is connected to the plurality of doped sub-regions, the fifth doped region and the first doped region in sequence, so as to realize better grounding of the third doped region.

Description

Technical Field

[0001] The present invention relates to the field of power electronic device technology, and more particularly to a semiconductor device. Background Technology

[0002] With the development of semiconductor devices such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), semiconductor devices have evolved from planar structures to trench structures to increase current density and reduce resistance.

[0003] For trench-type semiconductor devices, it is necessary to reduce the electric field in the gate oxide layer at the corner of the gate trench to ensure its reliability. One approach is to add a P-type masking layer at the bottom of the gate trench, using the PN junction formed at the bottom of the gate trench to protect the gate oxide layer at the corner of the gate trench. However, in this approach, when the spacing between the P-type masking layer and the P-type base region is too small and the P-type masking layer at the bottom of the gate trench is in a floating state, holes flow from the P-type masking layer to the P-type base region during the turn-off process and cannot flow back. This results in a larger depletion region when the device is turned on, increasing the resistance and power loss when the device is conducting, making it difficult to operate normally. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device to protect the gate oxide layer while reducing the resistance and power loss when the device is turned on.

[0005] Specifically, an embodiment of the present invention provides a semiconductor device, including, for example, a substrate, an epitaxial layer, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a first electrode layer, and a gate structure. The epitaxial layer is disposed on the substrate, and the epitaxial layer has trenches recessed into the top surface of the epitaxial layer opposite to the substrate. The first doped region is disposed within the epitaxial layer and has a first conductivity type. The second doped region is disposed within the epitaxial layer and located on the side of the first doped region opposite to the substrate, and the second doped region has a second conductivity type different from the first conductivity type. In a first direction, the trench extends from the top surface of the epitaxial layer through the second doped region and the first doped region, the first direction being from the epitaxial layer to the substrate. The third doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the third doped region is located below the trench and spaced apart from the bottom surface of the trench. The fourth doped region is disposed within the epitaxial layer and has the first conductivity type. In the first direction, the fourth doped region is located below the trench and spaced apart from the bottom surface of the trench. The fourth doped region includes a plurality of doped sub-regions, which are arranged circumferentially around the third doped region and connected to the third doped region respectively. The fifth doped region is disposed within the epitaxial layer and has the first conductivity type. In the first direction, the fifth doped region is located between the first doped region and the fourth doped region and connected to both the first and fourth doped regions respectively. In a second direction perpendicular to the first direction, the fifth doped region is spaced apart from the sidewall of the trench. The first electrode layer is disposed on the side of the epitaxial layer opposite to the substrate and forms ohmic contacts with the first doped region and the second doped region respectively. The gate structure includes a gate electrode and a gate insulating dielectric. The gate electrode is disposed within the trench, and the gate insulating dielectric partially fills the trench and insulates the gate electrode from the first doped region, the second doped region, the epitaxial layer, and the first electrode layer respectively.

[0006] Furthermore, another embodiment of the present invention provides a semiconductor device, for example including: a substrate, an epitaxial layer, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, a first electrode layer, a gate structure, and a second electrode layer. The epitaxial layer is disposed on the substrate, and the epitaxial layer is configured with trenches that are recessed within the top surface of the epitaxial layer opposite to the substrate. The first doped region is disposed within the epitaxial layer and has a first conductivity type. The second doped region is disposed within the epitaxial layer and located on the side of the first doped region opposite to the substrate, and the second doped region has a second conductivity type different from the first conductivity type; in a first direction, the trench extends from the top surface of the epitaxial layer through the second doped region and the first doped region, the first direction being from the epitaxial layer to the substrate. The third doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the third doped region is located below the trench and spaced apart from the bottom surface of the trench. The fourth doped region is disposed within the epitaxial layer and has the first conductivity type. In the first direction, the fourth doped region is located below the trench and spaced apart from the bottom surface of the trench. The fourth doped region includes multiple doped sub-regions, which extend radially outward from multiple corners of the third doped region. The fifth doped region is disposed within the epitaxial layer and has the first conductivity type. In the first direction, the fifth doped region is located between the first doped region and the fourth doped region and is connected to both the first and fourth doped regions. In a second direction perpendicular to the first direction, the fifth doped region is spaced apart from the sidewall of the trench. The first electrode layer is disposed on the side of the epitaxial layer opposite to the substrate and is electrically connected to the first doped region and the second doped region, respectively. The gate structure includes a gate electrode and a gate insulating dielectric. The gate electrode is disposed within the trench, and the gate insulating dielectric partially fills the trench and insulates the gate electrode from the first doped region, the second doped region, the epitaxial layer, and the first electrode layer, respectively. The second electrode layer is disposed on the side of the substrate opposite to the epitaxial layer and is electrically connected to the substrate.

[0007] The above embodiments of the present invention can have the following beneficial effects: By providing the third doped region and the fourth doped region spaced apart from the bottom surface of the trench below the trench, and providing the fifth doped region on both sides of the trench, respectively serving as multiple masking layers such as P-type masking layers, the electric field of the gate oxide layer during device breakdown is reduced, which can better protect the gate oxide layer of the device and improve the reliability of the device; furthermore, by constructing the multiple doped sub-regions distributed in three dimensions, the current path can be increased, reducing the resistance and power loss of the device; in addition, by connecting the third doped region sequentially to the multiple doped sub-regions of the fourth doped region, the fifth doped region and the first doped region, the third doped region is electrically connected to the first electrode layer, realizing the ground connection of the third doped region and no longer being in a floating state, thereby eliminating the problem of abnormal switching characteristics caused by excessively high potential of the P-type masking layer at the bottom of the trench in related technologies. Attached Figure Description

[0008] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0009] Figure 1 This is a partial three-dimensional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0010] Figure 2 for Figure 1 A three-dimensional structural schematic diagram of one embodiment of the semiconductor device shown, comprising a substrate, a first epitaxial sublayer, a second epitaxial sublayer, and a third doped region and a fourth doped region formed within the second epitaxial sublayer.

[0011] Figure 3 for Figure 1 A three-dimensional structural schematic diagram of another embodiment of the semiconductor device shown, including the substrate, the first epitaxial layer, the second epitaxial layer, and the third and fourth doped regions formed in the second epitaxial layer.

[0012] Figures 4 to 12 for Figure 1 The diagram shows a three-dimensional schematic representation of the process structure of multiple technological steps in a method for fabricating a semiconductor device.

[0013] [Explanation of Key Figure Markings]

[0014] 11-Substrate; 13-Epiaxial layer; 13T-Top surface of epitaxial layer; 130-Trench; 130B-Bottom surface of trench; 130S-Sidewall of trench; 131-First epitaxial sublayer; 133-Second epitaxial sublayer; 135-Third epitaxial sublayer; 133T-Upper surface of second epitaxial sublayer; 135B-Lower surface of third epitaxial sublayer; 1350-First doped region; 13501-Base region; 13503-Heavily doped region; 1352-Second doped region; 1330-Third doped region; 1330C-Third doped region Corner of the noxious region; 1332 - Fourth doped region; 1332a, 1332b, 1332c, 1332d - Doped sub-regions; 1354 - Fifth doped region; 15 - Gate structure; 151 - Gate electrode; 153 - Gate insulating dielectric; 1531 - Gate oxide layer; 1533 - Interlayer dielectric layer; 17 - First electrode layer; 171 - Ohmic contact layer; 1710 - Titanium layer; 1712 - Nickel layer; 173 - Front metal layer; 19 - Second electrode layer; 191 - Titanium layer; 192 - Nickel layer; 193 - Silver layer. Detailed Implementation

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0017] It should be noted that the terms "first," "second," "third," "fourth," "fifth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0019] Compared to silicon (Si), third-generation semiconductors such as silicon carbide (SiC) have a larger bandgap and a higher electric field strength. Therefore, at the same breakdown voltage, SiC-based semiconductor devices require only one-tenth the epitaxial layer thickness of Si-based semiconductor devices, and the doping concentration is one hundred times that of Si semiconductor devices. This significantly reduces drift region resistance, making it the core of next-generation power electronic devices. Currently, SiC-based semiconductor devices have been applied in wind power generation, new energy vehicles, charging piles, and other fields.

[0020] Similar to the development of Si-based semiconductor devices, SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have also evolved from planar MOSFETs to trench MOSFETs, increasing current density, reducing device resistance, and improving device performance. While trench MOSFETs further reduce resistance, they also introduce reliability issues. This is because SiC has a high breakdown electric field, meaning the gate oxide layer of SiC-based semiconductor devices experiences a large voltage during breakdown, potentially causing gate oxide leakage and threshold voltage drift. The curvature effect at the gate trench corners further concentrates the electric field, leading to even greater reliability problems. Therefore, when designing trench SiC MOSFETs, it is necessary to reduce the electric field in the gate oxide layer at the gate trench corners. To reduce the electric field, some technologies have proposed adding a P-type shielding layer (PShield) to the bottom of the gate trench, using the PN junction formed at the bottom of the gate trench to protect the corner of the gate trench. Although this structure protects the gate oxide layer, when the spacing between the P-type shielding layer and the P-type base region is too small and the P-type shielding layer at the bottom of the gate trench is in a floating state, holes flow from the P-type shielding layer to the P-type base region during the turn-off process and cannot flow back. This results in a larger depletion region when the device is turned on, increasing the resistance and loss during conduction, making it difficult to operate normally.

[0021] To address the issue of holes flowing from the P-type masking layer to the P-type base region and being unable to return, the P-type masking layer at the bottom of the gate trench needs to be grounded. One proposed technique involves connecting the P-type masking layer to the main junction outside the active region on both sides of the gate trench, achieving grounding through a source bar on the main junction. However, this grounding method results in a large gate trench width. An excessively large gate trench width makes it difficult to effectively reduce the series resistance of the P-type masking layer, and the potential of the P-type masking layer in the middle region of the gate trench is not zero, leading to a situation similar to the increased on-resistance in a floating state.

[0022] Therefore, embodiments of the present invention provide a semiconductor device that protects the gate oxide layer while reducing the resistance and loss when the device is turned on, and better grounds the P-type masking layer to eliminate the problem of abnormal switching characteristics caused by excessively high potential of the P-type masking layer at the bottom of the gate trench in related technologies.

[0023] See Figure 1 and Figure 2 The semiconductor device provided in this embodiment of the invention includes, for example, a substrate 11, an epitaxial layer 13, a first doped region 1350, a second doped region 1352, a third doped region 1330, a fourth doped region 1332, a fifth doped region 1354, a gate structure 15, and a first electrode layer 17.

[0024] The epitaxial layer 13 is disposed on the substrate 11, and the epitaxial layer 13 is provided with trenches 130 recessed into the top surface 13T of the epitaxial layer 13 facing away from the substrate 11. For example, the substrate 11 is an N-type SiC substrate with a concentration, for example, in the range of 1E19 cm⁻¹. -3 -1E20cm -3 The thickness of the epitaxial layer 13 is, for example, in the range of 150 micrometers (μm) to 350 μm; the epitaxial layer 13 is an N-type SiC epitaxial layer, and its doping concentration is, for example, lower than that of the substrate 11; the trench 130 has a depth H2, for example, in the range of 0.8 μm to 3 μm, in the first direction B1 from the epitaxial layer 13 to the substrate 11, and a width W1, for example, in the range of 0.3 μm to 3 μm, in the second direction B2 perpendicular to the first direction B1. Please refer to [reference needed]. Figure 6 As shown.

[0025] The first doped region 1350 is disposed within the epitaxial layer 13, and the first doped region 1350 has a first conductivity type. For example, the first doped region 1350 is a P-type doped region with a depth ranging from 0.6 μm to 3 μm.

[0026] The second doped region 1352 is disposed within the epitaxial layer 13 and located on the side of the first doped region 1350 facing away from the substrate 11. The second doped region 1352 has a second conductivity type different from the first conductivity type. In a first direction B1 from the epitaxial layer 13 to the substrate 11, the trench 130 passes through the second doped region 1352 and the first doped region 1350 from the top surface 13T of the epitaxial layer 13. For example, the second doped region 1352 is an N-type heavily doped region with a concentration range of 1E19 cm⁻¹. -3 -1E20cm -3 Its depth ranges from 0.2μm to 1μm.

[0027] The third doped region 1330 is disposed within the epitaxial layer 13 and has the first conductivity type; in the first direction B1, the third doped region 1330 is located below the trench 130 and spaced apart from the bottom surface 130B of the trench 130, i.e., it does not contact the trench 130. For example, the third doped region 1330 is a P-type doped region serving as a P-type masking layer at the bottom of the trench 130, with a concentration range of 1E17cm⁻¹. -3 -1E20cm -3 Its doping depth ranges from 1.3μm to 8μm.

[0028] The fourth doped region 1332 is disposed within the epitaxial layer 13 and has the first conductivity type. In the first direction B1, the fourth doped region 1332 is located below the trench 130 and spaced apart from the bottom surface 130B of the trench 130 (i.e., not in contact with the trench 130). The fourth doped region 1332 includes multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d, which are arranged circumferentially around the third doped region 1330 and connected to it respectively. For example, the fourth doped region 1332 is a P-type doped region with a concentration range of 1E17cm⁻¹. -3 -1E20cm -3 The doping depth ranges from 1.3 μm to 8 μm; correspondingly, the multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d are multiple P-type doped sub-regions, for example... Figure 2 As shown, these P-type doped subregions are distributed in three dimensions and can also be referred to as multiple split P-type masking layers.

[0029] The fifth doped region 1354 is disposed within the epitaxial layer 13 and has the first conductivity type; in the first direction B1, the fifth doped region 1354 is located between the first doped region 1350 and the fourth doped region 1332 and is respectively connected to the first doped region 1350 and the fourth doped region 1332; and in the second direction B2 perpendicular to the first direction B1, the fifth doped region 1354 is spaced apart from the sidewall 130S of the trench 130. For example, the fifth doped region 1354 is, for example, a p-type doped region with a concentration range of 1E17cm⁻¹. -3 -1E20cm -3 Its doping depth ranges from 1μm to 5μm, and it can also be called a deep P-type masking layer.

[0030] The first electrode layer 17 is disposed on the side of the epitaxial layer 13 away from the substrate 11 and forms electrical connections, such as ohmic contacts, with the first doped region 1350 and the second doped region 1352, respectively.

[0031] The gate structure 15 includes a gate electrode 151 and a gate insulating dielectric 153. The gate electrode 151 is disposed in the trench 130. The gate insulating dielectric 153 partially fills the trench 130 and insulates the gate electrode 151 from the first doped region 1350, the second doped region 1352, the epitaxial layer 13, and the first electrode layer 17, respectively. For example, the gate electrode 151 is a polysilicon layer, and the gate insulating dielectric 153 includes a gate oxide layer 1531 and an interlayer dielectric layer 1533. The gate oxide layer 1531 is disposed, for example, on the sidewalls 130S and the bottom surface 130B of the trench 130, and can be a silicon dioxide layer, so that the gate electrode 151 is insulated from the first doped region 1350, the second doped region 1352, and the epitaxial layer 13, respectively. The interlayer dielectric layer 1533 covers, for example, a portion of the second doped region 1352 and the trench 130, and can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, so that the gate electrode 151 is insulated from the first electrode layer 17. It is worth mentioning that, in some embodiments, the interlayer dielectric layer 1533 may also partially fill the trench 130, and / or the gate oxide layer 1531 may partially extend out of the trench 130.

[0032] As can be seen from the above, this embodiment, by providing a third doped region 1330 and a fourth doped region 1332 spaced apart from the bottom surface 130B of the trench 130 below the trench 130, and a fifth doped region 1354 on both sides of the trench 130, serves as multiple masking layers, reducing the electric field of the gate oxide layer during device breakdown. This better protects the gate oxide layer in the gate insulating dielectric 153 of the device, improving the reliability of the device. Furthermore, by constructing the three-dimensionally distributed multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d, the current path can be increased, reducing the resistance and power consumption of the device. Loss; Furthermore, by sequentially connecting the third doped region 1330 (e.g., the P-type masking layer at the bottom of trench 130) to the plurality of doped sub-regions 1332a, 1332b, 1332c, 1332d (e.g., the plurality of split P-type masking layers) of the fourth doped region 1332, the fifth doped region 1354 (e.g., the deep P-type masking layer), and the first doped region 1350, the third doped region 1330 is electrically connected to the first electrode layer 17, thereby achieving a ground connection for the third doped region 1330 and preventing it from being in a floating state. This eliminates the problem of abnormal switching characteristics caused by excessively high potential of the P-type masking layer at the bottom of the trench in related technologies.

[0033] In some embodiments, see Figure 1 and Figure 2 In the first direction B1, a portion of each doped sub-region 1332a, 1332b, 1332c, and 1332d of the fourth doped region 1332 is located directly below the trench 130; in other words, the orthographic projection of each doped sub-region 1332a, 1332b, 1332c, and 1332d of the fourth doped region 1332 onto the substrate 11 along the first direction B1 partially overlaps with the orthographic projection of the trench 130 onto the substrate 11 along the first direction B1. This relative positional arrangement helps protect the gate oxide layer 1531 at the bottom corner of the trench 130, thereby improving the reliability of the gate oxide layer 1531.

[0034] In some embodiments, see Figure 1 , Figure 2 and Figure 3 In the second direction B2 perpendicular to the first direction B1, the third doped region 1330 and the plurality of doped sub-regions 1332a, 1332b, 1332c, and 1332d of the fourth doped region 1332 are arranged alternately; and in the third direction B3 perpendicular to the first direction B1 and the second direction B2, the third doped region 1330 and the plurality of doped sub-regions 1332a, 1332b, 1332c, and 1332d of the fourth doped region 1332 are arranged alternately.

[0035] In some embodiments, see Figure 1 and Figure 3 The third doped region 1330 extends into the region between two adjacent doped sub-regions 1332a, 1332b (or 1332c, 1332d) in the second direction B2 of the plurality of doped sub-regions 1332a, 1332b, 1332c, 1332d of the fourth doped region 1332, and is connected to the two adjacent doped sub-regions 1332a, 1332b (or 1332c, 1332d) in the second direction B2; thus, compared to Figure 2 The width of the third doped region 1330 in the second direction B2 is smaller than the width W1 of the trench 130 in the second direction B2 (reference). Figure 6 ), Figure 3 The width of the third doped region 1330 shown in the second direction B2 can be equal to or greater than the width W1 of the trench 130 in the second direction B2. Furthermore, from... Figure 1 and Figure 3 It can also be seen that the third doped region 1330 extends into the region between two adjacent doped sub-regions 1332a, 1332b, 1332c, and 1332d on the third-direction B3 of the fourth doped region 1332 (or 1332b and 1332c), and is connected to the two adjacent doped sub-regions 1332a and 1332d (or 1332b and 1332c) on the third-direction B3. Furthermore, it is worth mentioning that the number of the multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d spaced apart from each other in the fourth doped region 1332 is not limited. Figure 3 The four shown could also be other quantities, such as two, three, or more.

[0036] In some embodiments, see Figure 1 and Figure 2 In the fourth doped region 1332, the spacing D1 between two adjacent doped sub-regions 1332a, 1332b (or 1332c, 1332d) in the second direction B2 is less than the width W1 of the trench 130 in the second direction B2 (reference). Figure 6This structural dimension design helps protect the gate oxide layer 1531 at the bottom corner of the trench 130, improving the reliability of the gate oxide layer 1531. For example, the spacing D1 between two adjacent doped sub-regions 1332a, 1332b (or 1332c, 1332d) in the second direction B2 of the plurality of doped sub-regions 1332a, 1332b, 1332c, 1332d of the fourth doped region 1332 is 0.2μm-2μm, and the width W1 of the trench 130 in the second direction B2 (refer to...) Figure 6 The thickness ranges from 0.3 μm to 3 μm. Furthermore, from... Figure 2 It can also be known that the spacing between two adjacent doped sub-regions 1332a, 1332b, 1332c, 1332d (or 1332b, 1332c) in the third direction B3 of the plurality of doped sub-regions 1332a, 1332b, 1332c, 1332d in the fourth doped region 1332 is D2, which is located, for example, in the range of 0.3μm-3μm.

[0037] In some embodiments, see Figure 1 and Figure 2 In the first direction B1, the fourth doped region 1332 and the bottom surface 130B of the trench 130 have a spacing D3, which is, for example, in the range of 0.2 μm-1 μm. In this way, the spacing between the fourth doped region 1332 and the first doped region 1350 can be avoided to be too small, thereby overcoming the problems of device pinch-off risk and loss of normal output characteristics existing in related technologies.

[0038] In some embodiments, see Figure 1 and Figure 2 In the first direction B1, there is a spacing D3 between the third doped region 1330 and the bottom surface 130B of the trench 130, which is, for example, in the range of 0.2 μm-1 μm. In this way, the spacing between the third doped region 1330 and the first doped region 1350 is not too small, thereby overcoming the problems of device pinch-off risk and loss of normal output characteristics existing in related technologies.

[0039] In some embodiments, see Figure 1 and Figure 2The epitaxial layer 13 includes a first epitaxial sublayer 131, a second epitaxial sublayer 133, and a third epitaxial sublayer 135. The first epitaxial sublayer 131 is disposed on the substrate 11, the second epitaxial sublayer 133 is disposed on the side of the first epitaxial sublayer 131 facing away from the substrate 11, and the third epitaxial sublayer 135 is disposed on the side of the second epitaxial sublayer 133 facing away from the substrate 11. The third doped region 1330 and the fourth doped region 1332 are respectively disposed within the second epitaxial sublayer 133. In the first direction B1, the third doped region 1330 and the fourth doped region 1332 extend from the upper surface 133T of the second epitaxial sublayer 133 facing away from the substrate 11 toward the first epitaxial sublayer 131, and the third doped region 1330 and the fourth doped region 1332 extend from the upper surface 133T of the second epitaxial sublayer 133 facing away from the substrate 11 toward the first epitaxial sublayer 131. The doping depth H1 of the third epitaxial sublayer 1350 and the fourth doped region 1332 (i.e., the depth from the upper surface 133T of the second epitaxial sublayer 133 in the first direction B1) is less than the thickness T1 of the second epitaxial sublayer (133); the first doped region 1350, the second doped region 1352 and the fifth doped region 1354 are respectively disposed in the third epitaxial sublayer 135, and in the first direction B1, the fifth doped region 1354 contacts the fourth doped region 1332 on the lower surface 135B of the third epitaxial sublayer 135 facing the substrate 11 and extends from the lower surface 135B to contact the first doped region 1350; the second doped region 1352 is located between the first doped region 1350 and the trench 130 in the second direction B2. For example, the first epitaxial sublayer 131 is an N-type SiC epitaxial layer with a concentration range of 1E15cm⁻¹. -3 -2E16cm -3 Its thickness is 5μm-60μm; the second epitaxial sublayer 133 is an N-type SiC epitaxial layer with a concentration range of 1E16cm⁻¹. -3 -1E17cm -3 Its thickness is 1μm-4μm; the third epitaxial sublayer 134 is an N-type SiC epitaxial layer with a concentration range of 1E16cm⁻¹. -3 -1E17cm -3 Its thickness is 2μm-5μm;

[0040] In some embodiments, see Figure 1The first doped region 1350 includes a base region 13501 and a heavily doped region 13503 formed on the side of the base region 13501 facing away from the substrate 11. The doping concentration of the heavily doped region 13503 is higher than that of the base region 13501. The heavily doped region 13503 is located on the outer side of the second doped region 1352 away from the trench 130 in the second direction B2. The first electrode layer 17 forms an electrical connection, such as an ohmic contact, with the heavily doped region 13503 of the first doped region 1350. For example, the base region 13501 is a P-type base region with a concentration range of 1E16cm⁻¹. -3 -1E18cm -3 The heavily doped region 13503 is a p-type heavily doped region with a concentration range of 1E18cm⁻¹. -3 -1E20cm -3 Its depth ranges from 0.2μm to 1μm.

[0041] In some embodiments, see Figure 1 The first electrode layer 17 includes an ohmic contact layer 171 and a front metal layer 173. The front metal layer 173 forms electrical connections, such as ohmic contacts, with the first doped region 1350 and the second doped region 1352 through the ohmic contact layer 171. For example, the first electrode layer 17 is, for example, the source of a MOSFET. The ohmic contact layer 171 includes, for example, a stacked titanium (Ti) layer 1710 and a nickel (Ni) layer 1712, and the front metal layer 173 is, for example, an aluminum layer.

[0042] In some embodiments, see Figure 1 The semiconductor device further includes, for example, a second electrode layer 19, which is disposed on the side of the substrate 11 opposite to the epitaxial layer 13 and forms an electrical connection, such as an ohmic contact, with the substrate 11. For example, the second electrode layer 19 may be the drain of a MOSFET, and may include, for example, a silver (Ag) layer 193 and alternating layers of titanium 191 and nickel 192 disposed between the silver layer 193 and the substrate 11.

[0043] Please see again. Figure 1 , Figure 2 and Figure 3Another embodiment of the present invention provides a semiconductor device, such as a substrate 11, an epitaxial layer 13, a first doped region 1350, a second doped region 1352, a third doped region 1330, a fourth doped region 1332, a fifth doped region 1354, a gate structure 15, a first electrode layer 17, and a second electrode layer 19. The epitaxial layer 13 is disposed on the substrate 11, and the epitaxial layer 13 has a trench 130 recessed into the top surface 13T of the epitaxial layer 13 facing away from the substrate 11. The first doped region 1350 is disposed within the epitaxial layer 13 and has a first conductivity type, such as P-type. The second doped region 1352 is disposed within the epitaxial layer 13 and located on the side of the first doped region 1350 facing away from the substrate 11, and has a second conductivity type different from the first conductivity type, such as N-type. In a first direction B1, the trench 1350... 30 extends from the top surface 13T of the epitaxial layer 13 through the second doped region 1352 and the first doped region 1350, the first direction B1 being the direction from the epitaxial layer 13 to the substrate 11; the third doped region 1330 is disposed within the epitaxial layer 13 and has the first conductivity type, such as P-type; in the first direction B1, the third doped region 1330 is located below the trench 130 and spaced apart from the bottom surface 130B of the trench 130; the fourth doped region 1332 is disposed within the epitaxial layer 13 and has the first conductivity type, such as P-type; in the first direction B1, the... The fourth doped region 1332 is located below the trench 130 and spaced apart from the bottom surface 130B of the trench 130. The fourth doped region 1332 includes multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d. The multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d extend radially outward from multiple corners 1330C of the third doped region 1330, such that each doped sub-region 1332a, 1332b, 1332c, and 1332d is spaced apart from each other. The fifth doped region 1354 is disposed within the epitaxial layer 13 and has The first conductivity type is, for example, P-type; in the first direction B1, the fifth doped region 1354 is located between the first doped region 1350 and the fourth doped region 1332 and is connected to the first doped region 1350 and the fourth doped region 1332 respectively; and in the second direction B2 perpendicular to the first direction B1, the fifth doped region 1354 is spaced apart from the sidewall 130S of the trench 130; the first electrode layer 17 is disposed on the side of the epitaxial layer 13 away from the substrate 11 and forms electrical connections, for example, ohmic contacts, with the first doped region 1350 and the second doped region 1352 respectively.The gate structure 15 includes a gate electrode 151 and a gate insulating dielectric 153. The gate electrode 151 is disposed within the trench 130. The gate insulating dielectric 153 partially fills the trench 130, insulating the gate electrode 151 from the first doped region 1350, the second doped region 1352, the epitaxial layer 13, and the first electrode layer 17, respectively. The second electrode layer 19 is disposed on the side of the substrate 11 opposite to the epitaxial layer 13 and forms an electrical connection with the substrate 11.

[0044] As can be seen from the above, this embodiment, by providing a third doped region 1330 and a fourth doped region 1332 spaced apart from the bottom surface 130B of the trench 130 below the trench 130, and a fifth doped region 1354 on both sides of the trench 130, serves as multiple masking layers, reducing the electric field of the gate oxide layer during device breakdown. This better protects the gate oxide layer in the gate insulating dielectric 153 of the device, improving the reliability of the device. Furthermore, by constructing the three-dimensionally distributed multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d, the current path can be increased, reducing the resistance and power consumption of the device. Loss; Furthermore, by sequentially connecting the third doped region 1330 (e.g., the P-type masking layer at the bottom of trench 130) to the plurality of doped sub-regions 1332a, 1332b, 1332c, 1332d (e.g., the plurality of split P-type masking layers) of the fourth doped region 1332, the fifth doped region 1354 (e.g., the deep P-type masking layer), and the first doped region 1350, the third doped region 1330 is electrically connected to the first electrode layer 17, thereby achieving a ground connection for the third doped region 1330 and preventing it from being in a floating state. This eliminates the problem of abnormal switching characteristics caused by excessively high potential of the P-type masking layer at the bottom of the trench in related technologies. For the specific details of the substrate 11, epitaxial layer 13, first doped region 1350, second doped region 1352, third doped region 1330, fourth doped region 1332, fifth doped region 1354, gate structure 15, first electrode layer 17 and second electrode layer 19 in the semiconductor device of this embodiment, please refer to the relevant descriptions in the foregoing embodiments, and they will not be repeated here.

[0045] To facilitate a clearer understanding of the semiconductor devices in the embodiments of the present invention, the following will be combined with... Figures 4 to 12 Brief description Figure 1 A method for manufacturing the semiconductor device shown may include the following process steps.

[0046] (1) An N-type SiC first epitaxial sublayer 131 is grown on a selected substrate 11, such as a SiC substrate, using a low-pressure chemical vapor deposition (LPCVD) apparatus, with a concentration range of 1E15cm⁻¹.-3 -2E16cm -3 The thickness is 5μm-60μm; then, an N-type SiC second epitaxial sublayer 133 is grown on the first epitaxial sublayer 131 using a low-pressure chemical vapor deposition apparatus, with a concentration range of 1E16cm. -3 -1E17cm -3 The thickness is 1μm-4μm. Then, using a high-temperature implantation device, P-type ion implantation is performed on the second epitaxial sublayer 133 to form a fourth doped region 1332 containing multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d (e.g., referred to as a split P-type masking layer), and a third doped region 1330 located below the bottom of the trench 130 (e.g., referred to as a P-type masking layer). Next, an N-type SiC third epitaxial sublayer 135 is grown on the second epitaxial sublayer 133 using low-pressure chemical vapor deposition (LPCVD) with a concentration range of 1E16cm⁻¹. -3 -1E17cm -3 The thickness is 2μm-5μm; thus, it is possible to obtain Figure 4 The structure shown.

[0047] (2) In the third epitaxial sublayer 135, P-type implantation is performed to form a fifth doped region 1354 (e.g., a deep P-type masking layer) and a base region 13501 (e.g., a P-type base region) and a heavily doped region 13503 (e.g., a heavily P-type doped region) of the first doped region 1350. In the third epitaxial sublayer 135, N-type implantation is performed to form a second doped region 1352 (e.g., a heavily N-type doped region), resulting in... Figure 5 The structure is shown. It is worth mentioning that the fifth doped region 1354 (e.g., a deep P-type masking layer) can be prepared by etching two grooves in the third epitaxial sublayer 135 using ICP (Inductively Coupled Plasma), and then performing P-type epitaxial growth in the etched grooves using a low-pressure chemical vapor deposition device.

[0048] (3) Use a high-temperature annealing device to activate the impurities in the fifth doping region 1354, the first doping region 1350 and the second doping region 1352. The activation temperature is 1600℃-1850℃ and the time is 5 minutes-1 hour.

[0049] (4) Trench 130 is formed by etching using an inductively coupled plasma device. The width W1 of trench 130 in the second direction B2 ranges from 0.3 μm to 3 μm, and the depth H2 of trench 130 in the first direction B1 ranges from 0.8 μm to 3 μm, resulting in the following: Figure 6 The structure shown.

[0050] (5) A gate oxide layer 1531 with a thickness ranging from 30 nm to 80 nm is formed using thermal oxidation or low-pressure chemical vapor deposition equipment, resulting in the following... Figure 7 The structure shown.

[0051] (6) A polycrystalline silicon layer with a thickness ranging from 0.3 μm to 1.5 μm is deposited using a low-pressure chemical vapor deposition (LPCVD) apparatus; then, the polycrystalline silicon layer is etched using an inductively coupled plasma (ICP-PAP) apparatus to form a gate electrode 151, resulting in the following: Figure 8 The structure shown.

[0052] (7) A silicon oxide layer was deposited using a low-pressure chemical vapor deposition (LPCVD) device to form an interlayer dielectric layer 1533 with a thickness ranging from 0.5 μm to 1.5 μm, resulting in the following: Figure 9 The structure shown.

[0053] (8) Using an inductively coupled plasma device, the interlayer dielectric layer 1533 is etched to form contact holes to expose a portion of the second doped region 1352 and the heavily doped region 13503, resulting in the following: Figure 10 The structure shown.

[0054] (9) A titanium (Ti) layer 1710 and a nickel (Ni) layer 1712 are deposited in the contact hole using a metal evaporation equipment. The thickness range of the titanium layer 1710 is as follows: Thickness range of nickel layer 1712 Then, the ohmic contact layer 171 of the first electrode layer 17 is formed by annealing in a rapid annealing furnace (RTA) at a temperature range of 700℃-980℃ for 100-300 seconds; resulting in the following: Figure 11 The structure shown.

[0055] (10) An aluminum layer is deposited using a metal evaporation device to cover the ohmic contact layer 171 and the interlayer dielectric layer 1533, the thickness of the aluminum layer being 1 μm-2 μm; then the aluminum layer is etched using an inductively coupled plasma device or a wet etching process to form Figure 12 The first electrode layer 17 shown includes a front metal layer 173 and a gate pad (not shown).

[0056] (11) A Ti layer and a Ni layer are deposited on the back side of the substrate 11 using a metal evaporation equipment, with thicknesses of respectively... and The second electrode layer 19, comprising a titanium layer 191 and a nickel layer 192, is then annealed in a rapid annealing furnace at a temperature ranging from 700°C to 980°C for 100 to 300 seconds. Next, the titanium layer 191, nickel layer 192, and silver layer 193, sequentially stacked, are deposited using a metal evaporation apparatus to form the back metal layer of the second electrode layer 19, such as a drain pad, with a thickness ranging from 1 μm to 2 μm. This completes the fabrication process. Figure 1 The semiconductor device shown.

[0057] More specifically, the following will provide Figure 1 A specific embodiment of a method for fabricating the semiconductor device shown is as follows:

[0058] (I) Growth of 8E15cm⁻¹ doped material on a 350μm SiC substrate using LPCVD -3 The first epitaxial sublayer of N-type SiC with a thickness of 10 μm;

[0059] (II) Continue to grow a doped layer of 4E16cm on the first epitaxial sublayer of N-type SiC using LPCVD. -3 A second epitaxial sublayer of N-type SiC with a thickness of 2 μm;

[0060] (III) After patterning the mask using a photolithography machine and ICP equipment, aluminum (Al) atoms are repeatedly implanted into the second epitaxial sublayer of N-type SiC at 500℃ using a high-temperature ion implantation device to form multiple split P-type masking layers (corresponding to multiple doped sub-regions 1332a, 1332b, 1332c, and 1332d) with a spacing of 0.2 μm on the second direction B2 and 0.3 μm on the third direction B3, and a P-type masking layer located below the bottom of the trench (corresponding to the third doped region 1330); the implantation energies are 500 keV, 350 keV, 240 keV, and 80 keV, and the implantation doses are 2E14cm. -2 2E14cm -2 3E14cm -2 8E13cm -2 ;

[0061] (IV) Continue to grow a doped layer of 4E16cm on the second epitaxial sublayer of N-type SiC using LPCVD. -3 A third epitaxial sublayer of N-type SiC with a thickness of 1.2 μm;

[0062] (V) After patterning the mask using a photolithography machine and ICP equipment, aluminum (Al) atoms were repeatedly implanted into the third epitaxial sublayer of N-type SiC at 500°C using a high-temperature ion implantation device to form a P-type base region (corresponding to base region 13501). The implantation energies were 450keV, 280keV, and 120keV, and the implantation doses were 2E13cm. -2 1E13cm -2 3E13cm -2Then, after masking and patterning again, aluminum (Al) was implanted multiple times to sequentially form an N-type heavily doped layer (corresponding to the first doped region 1352), a P-type heavily doped layer (corresponding to the heavily doped region 13503) on both sides, and a deep P-type masking layer (corresponding to the fifth doped region 1354); the implantation energies were 1.1 M keV, 930 keV, 750 keV, 580 keV, 360 keV, 180 keV, 80 keV, and 30 keV, and the implantation doses were 4E14cm. -2 2E14cm -2 4E14cm -2 2E14cm -2 2E14cm -2 3E14cm -2 2E14cm -2 Finally, nitrogen (N) atoms were implanted multiple times to form N-type heavily doped layers on both sides of the trench (corresponding to the first doped region 1352). The implantation energies were 200 keV, 100 keV, and 30 keV, and the implantation doses were 5E14cm. -2 2E14cm -2 3E14cm -2 ;

[0063] (VI) Sputtering on the wafer surface The carbon film was then annealed at 1650℃ for 30 minutes in a high-temperature annealing furnace under an Ar atmosphere of 20 mTorr to activate the doped atoms.

[0064] (VII) After mask patterning, SiC is etched using ICP equipment to form trenches 1 μm wide and 1 μm deep;

[0065] (VIII) Using a wet oxidation method, SiC is oxidized at 1000℃ for 1 hour to form a sacrificial oxide layer of about 20 nm;

[0066] (IX) Rinse the wafer for 10 minutes with BOE (Buffered Oxide Etchant) to remove the sacrificial oxide layer generated above;

[0067] (X) A 100nm SiO2 layer is deposited using LPCVD to form a gate oxide layer;

[0068] (XI) LPCVD was used to grow a material with a thickness of 0.8 μm and a concentration of 1E20cm. -3 N-type heavily doped polycrystalline silicon; the doping element can be phosphorus (P) atoms;

[0069] (XII) ICP etching is used to remove the polysilicon on the mesa, leaving the polysilicon in the trench to form the gate electrode;

[0070] (XIII) A 1 μm thick SiO2 layer is grown on the wafer using LPCVD to form an interlayer dielectric layer; then, using photoresist as a mask, ICP etching is used to remove part of the SiO2 on the mesa to form ohmic contact holes.

[0071] (XIV) A layer of thickness is deposited on the wafer using an evaporation deposition device. The Ti / Ni layer is then annealed at 950°C using an RTA device to form the ohmic contact layer of the source electrode (corresponding to ohmic contact layer 171).

[0072] (XV) The residual Ni on the photoresist is removed by a stripping method;

[0073] (XVI) Using photoresist as a mask, ICP etching removes some SiO2 and opens the contact hole in the gate region;

[0074] (XVII) A layer of aluminum (Al) with a thickness of 2 μm was deposited on the wafer using a metal evaporation equipment;

[0075] (XVIIII) A portion of the aluminum metal is removed using an ICP device to form the source (corresponding to the front metal layer 173) and the gate pad;

[0076] (XIX) Ti / Ni was deposited on the back side of the device using a metal evaporation deposition apparatus, with a thickness of [missing information]. Then, the drain electrode is annealed at 950°C using an RTA device to form an ohmic contact layer.

[0077] (XX) A 2μm thick Ti / Ni / Ag layer is deposited on the device using a metal evaporation deposition apparatus to form a drain metal layer. This allows the fabrication of... Figure 1 The semiconductor device shown is, for example, a MOSFET.

[0078] Finally, it is worth mentioning that the device material is not limited to SiC, but can also be Si, Ga2O3, GaN, diamond, etc.; the deep P-type masking layer (corresponding to the fifth doped region 1354) can also be formed by trenching in the third epitaxial sublayer of N-type and then using MOCVD to epitaxially form the P-type layer; the cell structure of the semiconductor device in this embodiment can be applied not only to strip distribution layouts, but also to layouts of square, circular, hexagonal, octagonal, dodecagonal, and other shapes.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate, the epitaxial layer having trenches recessed into the top surface of the epitaxial layer opposite to the substrate; A first doped region is disposed within the epitaxial layer, and the first doped region has a first conductivity type; A second doped region is disposed within the epitaxial layer and located on the side of the first doped region away from the substrate. The second doped region has a second conductivity type different from the first conductivity type. In a first direction, the trench extends from the top surface of the epitaxial layer through the second doped region and the first doped region, and the first direction is from the epitaxial layer to the substrate; A third doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the third doped region is located below the trench and spaced apart from the bottom surface of the trench. A fourth doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the fourth doped region is located below the trench and spaced apart from the bottom surface of the trench, and the fourth doped region includes a plurality of doped sub-regions, which are arranged circumferentially along the third doped region and are respectively connected to the third doped region; A fifth doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the fifth doped region is located between the first doped region and the fourth doped region and is respectively connected to the first doped region and the fourth doped region; and in a second direction perpendicular to the first direction, the fifth doped region is spaced apart from the sidewall of the trench. The first electrode layer is disposed on the side of the epitaxial layer away from the substrate and forms ohmic contacts with the first doped region and the second doped region, respectively. as well as A gate structure includes a gate electrode and a gate insulating dielectric. The gate electrode is disposed in the trench, and the gate insulating dielectric partially fills the trench and insulates the gate electrode from the first doped region, the second doped region, the epitaxial layer, and the first electrode layer, respectively.

2. The semiconductor device of claim 1, wherein, in the first direction, a portion of each of the fourth doped regions is located directly below the trench; In the second direction, the plurality of doped subregions of the third doped region and the fourth doped region are arranged alternately; In the third direction, the plurality of doped sub-regions of the third doped region and the fourth doped region are arranged alternately, and the third direction is a direction perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 2, characterized in that, The third doped region extends into the region between two adjacent doped sub-regions in the second direction within the plurality of doped sub-regions of the fourth doped region and is connected to the two adjacent doped sub-regions in the second direction. And / or, the third doped region extends into the region between two adjacent doped sub-regions in the third direction of the fourth doped region and is connected to the two adjacent doped sub-regions in the third direction.

4. The semiconductor device according to claim 2, characterized in that, In the fourth doped region, the spacing between two adjacent doped sub-regions in the second direction is less than the width of the trench in the second direction.

5. The semiconductor device according to claim 4, characterized in that, The spacing between two adjacent doped sub-regions in the second direction of the plurality of doped sub-regions in the fourth doped region is 0.2 μm-2 μm; the width of the trench in the second direction is 0.3 μm-3 μm.

6. The semiconductor device according to claim 1, characterized in that, In the first direction, the distance between the fourth doped region and the bottom surface of the trench is in the range of 0.2 μm-1 μm.

7. The semiconductor device according to claim 1, characterized in that, In the first direction, the distance between the third doped region and the bottom surface of the trench is in the range of 0.2 μm-1 μm.

8. The semiconductor device according to claim 1, characterized in that, The epitaxial layer includes a first epitaxial sublayer, a second epitaxial sublayer, and a third epitaxial sublayer. The first epitaxial sublayer is disposed on the substrate, the second epitaxial sublayer is disposed on the side of the first epitaxial sublayer facing away from the substrate, and the third epitaxial sublayer is disposed on the side of the second epitaxial sublayer facing away from the substrate. The third doped region and the fourth doped region are respectively disposed within the second epitaxial sublayer, and in the first direction, the third doped region and the fourth doped region extend from the upper surface of the second epitaxial sublayer away from the substrate toward the first epitaxial sublayer, and the doping depth of the third doped region and the fourth doped region is less than the thickness of the second epitaxial sublayer. The first doped region, the second doped region, and the fifth doped region are respectively disposed in the third epitaxial sublayer, and in the first direction, the fifth doped region contacts the fourth doped region on the lower surface of the third epitaxial sublayer facing the substrate, and extends from the lower surface to contact the first doped region; The second doped region is located between the first doped region and the trench in the second direction.

9. The semiconductor device according to claim 1, characterized in that, The first doped region includes a base region and a heavily doped region formed on the side of the base region away from the substrate. The doping concentration of the heavily doped region is higher than that of the base region. The heavily doped region is located on the outer side of the second doped region away from the trench in the second direction. The first electrode layer forms an ohmic contact with the heavily doped region of the first doped region. And / or, the first electrode layer includes an ohmic contact layer and a front metal layer, wherein the front metal layer forms ohmic contacts with the first doped region and the second doped region respectively through the ohmic contact layer; And / or, the semiconductor device further includes a second electrode layer disposed on the side of the substrate opposite to the epitaxial layer and forming an ohmic contact with the substrate.

10. A semiconductor device, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate, the epitaxial layer having trenches recessed into the top surface of the epitaxial layer opposite to the substrate; A first doped region is disposed within the epitaxial layer, and the first doped region has a first conductivity type; A second doped region is disposed within the epitaxial layer and located on the side of the first doped region away from the substrate. The second doped region has a second conductivity type different from the first conductivity type. In a first direction, the trench extends from the top surface of the epitaxial layer through the second doped region and the first doped region, and the first direction is from the epitaxial layer to the substrate; A third doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the third doped region is located below the trench and spaced apart from the bottom surface of the trench. A fourth doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the fourth doped region is located below the trench and spaced apart from the bottom surface of the trench, and the fourth doped region includes a plurality of doped sub-regions, which extend radially outward from a plurality of corners of the third doped region in a corresponding manner. A fifth doped region is disposed within the epitaxial layer and has the first conductivity type; in the first direction, the fifth doped region is located between the first doped region and the fourth doped region and is respectively connected to the first doped region and the fourth doped region; and in a second direction perpendicular to the first direction, the fifth doped region is spaced apart from the sidewall of the trench. The first electrode layer is disposed on the side of the epitaxial layer away from the substrate and is electrically connected to the first doped region and the second doped region, respectively. A gate structure includes a gate electrode and a gate insulating dielectric, wherein the gate electrode is disposed in the trench, and the gate insulating dielectric partially fills the trench and insulates the gate electrode from the first doped region, the second doped region, the epitaxial layer and the first electrode layer, respectively. as well as The second electrode layer is disposed on the side of the substrate opposite to the epitaxial layer and is electrically connected to the substrate.

11. The semiconductor device according to claim 10, characterized in that, A portion of each of the doped subregions of the fourth doped region is located directly below the trench.

12. The semiconductor device according to claim 10, characterized in that, The spacing between two adjacent doped sub-regions in the second direction of the plurality of doped sub-regions in the fourth doped region is in the range of 0.2 μm-2 μm; And / or, the width of the groove in the second direction is in the range of 0.3 μm-3 μm; And / or, the spacing between two adjacent doped sub-regions in the plurality of doped sub-regions of the fourth doped region in the third direction is in the range of 0.3 μm-3 μm, where the third direction is a direction perpendicular to the first direction and the second direction.

13. The semiconductor device according to claim 10, characterized in that, The distance between each of the third and fourth doped regions and the bottom surface of the trench is in the range of 0.2 μm-1 μm, and the third direction is a direction perpendicular to the first and second directions.

14. The semiconductor device according to claim 10, characterized in that, The epitaxial layer includes a first epitaxial sublayer, a second epitaxial sublayer, and a third epitaxial sublayer. The first epitaxial sublayer is disposed on the substrate, the second epitaxial sublayer is disposed on the side of the first epitaxial sublayer facing away from the substrate, and the third epitaxial sublayer is disposed on the side of the second epitaxial sublayer facing away from the substrate. The third doped region and the fourth doped region are respectively disposed within the second epitaxial sublayer, and in the first direction, the third doped region and the fourth doped region extend from the upper surface of the second epitaxial sublayer away from the substrate toward the first epitaxial sublayer, and the doping depth of the third doped region and the fourth doped region is less than the thickness of the second epitaxial sublayer. The first doped region, the second doped region, and the fifth doped region are respectively disposed in the third epitaxial sublayer, and in the first direction, the fifth doped region contacts the fourth doped region on the lower surface of the third epitaxial sublayer facing the substrate and extends from the lower surface to contact the first doped region; The second doped region is located between the first doped region and the trench in the second direction.

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