A global unipolar conductive SiC MOSFET device based on heterojunction and SSM cooperation

Abstract

This invention discloses a globally unipolar conductive SiC MOSFET device based on the synergy of a heterojunction and a self-biased MOSFET (SSM), belonging to the field of semiconductor power device technology. Based on an asymmetric trench structure, this device integrates an N-type polysilicon / N-type SiC heterojunction diode (HJD) on the right side of the cell, utilizing gate voltage to control the bandgap to achieve tunneling enhancement during forward conduction, and leveraging the low barrier characteristics of the heterojunction to achieve reverse freewheeling. On the left side of the cell, a short-channel self-biased MOSFET (SSM) is integrated, utilizing the drain-induced barrier reduction (DIBL) effect to construct a reverse unipolar conductive path. Through the synergistic effect of the right-side heterojunction and the left-side SSM, this invention achieves unipolar electronic conduction under all operating conditions, including forward conduction and reverse freewheeling, completely eliminating the bipolar degradation effect. Simulation results show that, compared with traditional asymmetric trench SiC MOSFETs (C-ATMOS), the device of this invention has a reverse turn-on voltage as low as 1.2V and a breakdown voltage of 1218V, maintaining comparable breakdown voltage characteristics. This invention combines ultra-low conduction loss, excellent reverse recovery characteristics, and withstand voltage characteristics, making it suitable for high-end power electronics applications such as new energy vehicles, smart grids, and photovoltaic inverters.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology and relates to a silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET), specifically to a global unipolar conductive SiC MOSFET device based on the synergy of heterojunction and short-channel self-biased MOSFET (SSM). Background Technology

[0002] New energy vehicles, smart grids, and photovoltaic inverters are placing higher demands on the performance of power semiconductor devices. Silicon carbide (SiC), as a wide bandgap semiconductor material, possesses advantages such as wide bandgap, high breakdown electric field, high thermal conductivity, and fast electron saturation drift velocity, making it the preferred material for next-generation power devices. SiC MOSFETs, with their low conduction losses, high switching speeds, and high-temperature stability, are gradually replacing traditional silicon-based IGBTs and becoming the mainstream device for high-voltage, high-frequency applications.

[0003] However, existing SiC MOSFET technology still faces three major bottlenecks.

[0004] First, there is the bipolar degradation effect of the body diode during reverse freewheeling. In inverter circuits, SiC MOSFETs need to operate in the third quadrant for freewheeling, at which point the parasitic body diode (the PN junction formed by the P-well and N-drift regions) is forced to conduct. Due to the wide bandgap characteristics of SiC, the body diode turn-on voltage is as high as 2.7-3.0V, resulting in a significant increase in freewheeling losses. More seriously, minority carrier injection can trigger bipolar degradation, forming stacking faults, leading to increased on-resistance and reduced breakdown voltage, severely threatening the long-term reliability of the device. Existing solutions such as integrated Schottky diodes (SBDs) suffer from high leakage current at high temperatures, while integrated heterojunction diodes (HJDs) struggle to balance forward conduction and reverse freewheeling performance. Single integrated short-channel self-biased MOSFETs (SSMs) have high on-resistance under high current, failing to cover the unipolar conduction requirements across the entire current range.

[0005] Second, there is an inherent trade-off between on-resistance and breakdown voltage. To address the problem of electric field concentration at the bottom of the trench gate, a P-well region extension design is typically used to shield the electric field. However, this creates a depletion region in the junction field-effect transistor (JFET) during conduction, increasing the specific on-resistance by 15%-20%.

[0006] Third, limitations imposed by switching losses and high-frequency performance. Traditional SiC MOSFETs have gate-drain capacitance (C... gd The large value leads to a long Miller plateau time and high switching losses, which limits the further increase of the device's operating frequency. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a globally unipolar conductive SiC MOSFET device based on the synergy of a heterojunction and a self-biased MOSFET (SSM). By integrating an L-shaped N-type polysilicon / N-type SiC heterojunction on the right side of the cell, the gate voltage is used to control the energy band and achieve tunneling enhancement during forward conduction. The low barrier characteristics of the heterojunction are also utilized to achieve reverse freewheeling. A short-channel self-biased MOSFET is integrated on the left side of the cell, utilizing the DIBL effect to construct a reverse unipolar conductive path. This invention achieves unipolar electronic conduction under both forward and reverse freewheeling conditions through the synergistic effect of the right-side heterojunction and the left-side SSM, completely eliminating the bipolar degradation effect and exhibiting both ultra-low conduction loss and excellent high-frequency switching characteristics.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy comprises, from bottom to top, a drain metal contact region, an N+ substrate region, an N-drift region, an N-csl region, a P-base1 region, a trench gate structure, a right-side P-well region, an L-shaped N-type polysilicon region, a left-side P-well region, a P-base2 region, an SSM N+ region, a second source P+ region, a first source N+ region, a first source P+ region, a second source N+ region, and a source metal contact region; an L-shaped N-type polysilicon / SiC heterojunction diode (HJD) is integrated on the right side of the cell, and a short-channel self-biased MOSFET (SSM) is integrated on the left side of the cell.

[0010] The trench gate structure includes a right main gate controlled trench gate, a left source auxiliary trench gate, and a trench gate oxide layer that wraps the two trenches, extending deep into the N-drift region and located on both sides of the P-base1 region and the N-csl region;

[0011] The right-side P-well region is formed on the upper right surface of the N-drift region, enclosing the L-shaped N-type polysilicon region; the L-shaped N-type polysilicon region is formed on the right side of the main gate controlled trench gate, and its lower end is connected to the N-csl region, forming an L-shaped N-type polysilicon / SiC heterojunction diode (HJD) with the N-csl region.

[0012] The left P-well region is formed on the upper left surface of the N-drift region; the P-base2 region, the SSM N+ region and the second source P+ region are formed from right to left on the upper surface of the left P-well region and below the source auxiliary trench gate.

[0013] The short-channel self-biased MOSFET (SSM) consists of a source auxiliary trench gate, a P-base2 region, an SSM N+ region, and an N-csl region. The source auxiliary trench gate serves as the gate of the SSM and is connected to the source at the same potential.

[0014] The first source N+ region and the first source P+ region are formed on the upper surface of the P-base1 region, to the left of the main gate control trench gate; the second source N+ region is formed on the right of the source auxiliary trench gate and embedded inside the P-base1 region;

[0015] Furthermore, when the device is forward-biased, a +15V positive bias is applied to the main gate controlled trench gate, forming an N-type inversion channel on the sidewall of the P-base1 region, thus enabling the main channel to conduct. Simultaneously, the positive gate voltage modulates the energy band of the L-shaped N-type polysilicon surface, allowing electrons to enter the N-csl region from the N-type polysilicon region through quantum tunneling, forming an additional tunneling conductive channel and reducing the specific on-resistance of the device. At this time, the SSM is in the off state because the gate-source voltage is 0V, and it does not affect the forward conduction performance.

[0016] Furthermore, when the device is forward blocked, a negative bias voltage of 0V or no more than 5V is applied to the main gate control trench gate, and the main channel is turned off; the right P-well region and the left P-well region, together with the N-drift region, form a reverse bias PN junction to bear the blocking voltage. At the same time, the electric field at the bottom of the shielding trench gate is concentrated, limiting the maximum electric field of the gate oxide layer to 3.75MV / cm, which meets the long-term reliability requirements of the SiC / SiO2 interface.

[0017] Furthermore, during reverse freewheeling, a negative bias of 0V or no more than 5V is applied to the gate of the main gate controlled trench, and the main channel remains off. At this time, the L-shaped N-type polysilicon / SiC heterojunction is forward biased and conducts, undertaking the small freewheeling current. When the reverse current increases, the SSM utilizes the DIBL effect to form a low-barrier electron conduction channel, which, together with the HJD, undertakes the large freewheeling current. Within the rated reverse current range of 0~300A, the reverse current flows entirely through the unipolar electron path, completely suppressing the parasitic diode turn-on and eliminating the bipolar degradation effect at its source.

[0018] Furthermore, the doping concentration of the L-shaped N-type polysilicon region is 1×10²¹cm⁻³, and the thickness is 0.15μm; the conduction band offset at the heterojunction interface is 0.84eV, and the gate voltage is adjusted during forward conduction to make the tunneling distance less than 10nm, ensuring that the tunneling current is large enough.

[0019] Furthermore, the channel length of the SSM is 0.4 μm, and the channel doping concentration is 7 × 10¹. 6 cm⁻³; Utilizing the DIBL effect, the source barrier height is reduced to 0.77eV under reverse voltage, forming a low-resistivity electronic conductive channel.

[0020] The beneficial effects of this invention are as follows:

[0021] Achieving unipolar conduction under all operating conditions and completely eliminating bipolar degradation effects: Through the synergistic design of HJD and SSM, a freewheeling mechanism of "small current HJD dominance and large current dual-path synergy" is formed. The reverse turn-on voltage is as low as 1.2V; within the rated current range of 0~300A, the parasitic diode does not turn on at all, with no minority carrier injection, thus solving the bipolar degradation problem at its root.

[0022] Excellent forward conduction performance: By controlling the heterojunction tunneling effect through gate voltage, an additional conductive channel is formed, which makes up for the deficiency of the single-sided channel of the asymmetric trench structure. The specific on-resistance is comparable to that of the traditional C-ATMOS, achieving a good balance between significantly improved reverse performance and forward performance.

[0023] Stable withstand voltage performance: The breakdown voltage of the device of this invention is 1218V, which is basically the same as that of the traditional device with the same specifications, 1204V, thus maintaining stable withstand voltage performance.

[0024] High process compatibility and limited cost increase: The structure of this invention is highly compatible with the traditional SiC asymmetric trench MOSFET process. It does not require an additional cell area, but only one N-type polysilicon deposition and etching step and one P-base2 region ion implantation step. The increase in process overhead is limited, making it suitable for large-scale mass production.

[0025] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0027] Figure 1 A schematic diagram of the cell cross-sectional structure of a globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy, provided by the present invention;

[0028] Figure 2 The equivalent circuit schematic diagram of the device provided in the embodiment of the present invention;

[0029] Figure 3 This is the band structure diagram of the L-shaped N-type polysilicon / SiC heterojunction of the device of the present invention under thermal equilibrium conditions;

[0030] Figure 4 The diagram shows the conduction band energy distribution of the SSM under different drain-source reverse bias voltages for the device of the present invention.

[0031] Figure 5 This is a diagram showing the band energy distribution of the device of the present invention under forward conduction tunneling conditions;

[0032] Figure 6 This is a comparison diagram of the current density distribution of the device of the present invention and a traditional asymmetric trench SiC MOSFET in the forward conduction state;

[0033] Figure 7 This is a comparison diagram of the current density distribution of the device of the present invention and a traditional asymmetric trench SiC MOSFET under reverse freewheeling state;

[0034] Figure 8 The curves show a comparison of the reverse conduction characteristics of the device of the present invention and a traditional asymmetric trench SiC MOSFET device.

[0035] Figure 9 The curves show a comparison of the forward conduction output characteristics of the device of the present invention and a traditional asymmetric trench SiC MOSFET device.

[0036] Figure 10 The voltage withstand characteristics of the device of this invention are compared with those of a conventional asymmetric trench SiC MOSFET device.

[0037] Explanation of reference numerals in the attached figures: Drain metal contact region (1), N+ substrate region (2), N- drift region (3), right P-well region (4), L-shaped N-type polysilicon region (5), main gate controlled trench gate (6), trench gate oxide layer (7) enclosing the main gate controlled trench gate (6), first source N+ region (8), first source P+ region (9), second source N+ region (10), source metal contact region (11), source auxiliary trench gate (12), P-base1 region (13), second source P+ region (14), SSM N+ region (15), P-base2 region (16), left P-well region (17), N-csl region (18). Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0039] like Figure 1As shown, a preferred embodiment of the present invention provides a globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy, which is a vertical trench gate structure, comprising, from bottom to top: Drain metal contact region (1): Located on the lower surface of N+ substrate region (2), forming an ohmic contact with N+ substrate region (2). N+ substrate region (2): 3 μm thick, 4H-SiC material, doped with N-type nitrogen impurity, concentration 2×10¹ 9 cm⁻³. N-drift region (3): 11 μm thick, 4H-SiC material, doped with N-type nitrogen impurity, concentration 6 × 10¹ 5 cm⁻³, designed breakdown voltage greater than 1200V. N-csl region (18): 1.5 μm thick, 4H-SiC material, doped with N-type nitrogen impurity, concentration 8 × 10¹ 6 cm⁻³ is used to reduce the resistance of the JFET region. P-base1 region (13): formed on the upper surface of N-csl region (18), with a thickness of 0.25 μm and a width of 0.4 μm, 4H-SiC material, doped with P-type aluminum impurity, concentration 2×10¹ 7 cm⁻³. Trench gate structure: includes main gate controlled trench gate (6), source auxiliary trench gate (12) and trench gate oxide layer (7), which penetrates into the N-drift region (3) and is located on both sides of P-base1 region (13) and N-csl region (18). Main gate controlled trench gate (6): 1.8 μm thick, 0.5 μm wide, made of heavily doped N-type polysilicon, connected to the gate input potential of the device. Source auxiliary trench gate (12): 1.8 μm thick, 0.5 μm wide, made of heavily doped N-type polysilicon, and electrically connected to the source metal contact area (11). Trench gate oxide layer (7): Envelops all trenches, with a sidewall thickness of 0.05μm and a bottom thickness of 0.08μm, and is made of silicon dioxide. Right-side P-well region (4): Formed on the upper right surface of the N-csl region (18), with a thickness of 0.5 μm and a width of 1 μm, made of 4H-SiC material, doped with P-type aluminum impurity at a concentration of 2 × 10¹ 7 cm⁻³, enclosing an L-shaped N-type polycrystalline silicon region (5). L-shaped N-type polysilicon region (5): formed on the right side of the main gate controlled trench gate (6), with a thickness of 0.15 μm, a width of 0.3 μm, and a doping concentration of 1×10²¹cm⁻³; the lower end is connected to the N-csl region (18), and the upper end is connected to the source metal contact region (11), forming an L-shaped N-type polysilicon / 4H-SiC heterojunction with the N-csl region (18). Left P-well region (17): formed on the upper left surface of N-csl region (18), with a thickness of 0.5 μm and a width of 1 μm, 4H-SiC material, doped with P-type aluminum impurity, concentration 2 × 10¹ 7 cm⁻³. P-base2 region (16), SSM N+ region (15) and second source P+ region (14): formed from right to left on the upper surface of left P-well region (17) and below source auxiliary trench gate (12). P-base2 region (16): thickness 0.25 μm, width 0.4 μm, doping concentration 7 × 10¹ 6 cm⁻³. SSM N+ region (15): thickness 0.3 μm, width 0.3 μm, doping concentration 1×10¹ 9 cm⁻³, connected to the source metal contact area (11). Second source P+ region (14): thickness 0.3 μm, width 0.2 μm, doping concentration 1 × 10¹ 9 cm⁻³, connected to the source metal contact area (11). SSM structure: It consists of a source-assisted trench gate (12), a P-base2 region (16), an SSM N+ region (15) and an N-csl region (18), with a channel length of 0.4 μm. The first source N+ region (8) and the first source P+ region (9) are formed on the upper surface of the P-base1 region (13) and to the left of the main gate control trench gate (6). First source N+ region (8): thickness 0.3 μm, width 0.4 μm, doping concentration 1 × 10¹ 9 cm⁻³, ohmic contact with the source metal contact area (11). First source P+ region (9): Adjacent to the first source N+ region (8), with a thickness of 0.3 μm, a width of 0.2 μm, and a doping concentration of 1 × 10¹ 9 cm⁻³ is used to suppress parasitic thyristor effects. Second source N+ region (10): Formed to the right of the source auxiliary trench gate (12) and embedded inside the P-base1 region (13), with a thickness of 0.3 μm, a width of 0.4 μm, and a doping concentration of 1 × 10¹ 9 cm⁻³, ohmic contact with the source metal contact area (11). Source metal contact region (11): Located at the top of the device, the material is nickel silicide, and it forms an ohmic contact with the first source N+ region (8), the first source P+ region (9), the second source N+ region (10), the second source P+ region (14), the SSM N+ region (15), the source auxiliary trench gate (12) and the L-shaped N-type polysilicon region (5).

[0040] like Figure 2 As shown, the equivalent circuit of the device of the present invention consists of three parts connected in parallel: a main MOSFET (composed of a main gate controlled trench gate 6, a P-base1 region 13, a first source N+ region 8, and an N-csl region 18), an HJD (composed of an L-shaped N-type polysilicon region 5 and an N-csl region 18), and an SSM (composed of a source auxiliary trench gate 12, a P-base2 region 16, an SSM N+ region 15, and an N-csl region 18). The main MOSFET is controlled to turn on and off by the gate voltage. The HJD and SSM work together during reverse freewheeling to share the reverse current.

[0041] The physical mechanisms of the device in this embodiment under three typical operating states are described in detail below with reference to the accompanying drawings.

[0042] When the device is forward-biased, a +15V positive bias is applied to the main gate controlled trench gate (6), the source auxiliary trench gate (12) is connected to a 0V potential, and a positive bias is applied to the drain. At this time, the positive gate voltage of the main gate controlled trench gate (6) forms an N-type inversion channel on the sidewall of the P-base1 region (13). Electrons flow from the first source N+ region (8) through the inversion channel into the N-csl region (18) and the N-drift region (3), and finally reach the drain, realizing the conduction of the main channel.

[0043] like Figure 3 As shown, under thermal equilibrium conditions, the L-shaped N-type polysilicon / SiC heterojunction exhibits a significant barrier that hinders electron tunneling. When a +15V positive bias is applied to the master gate controlled trench gate, as... Figure 5 As shown, the gate voltage controls the surface band of the heterojunction, causing the conduction band on the N-type polysilicon side to bend downwards. The distance that electrons tunnel from the L-shaped N-type polysilicon region (5) into the N-csl region (18) is shortened to less than 10 nm, forming an additional tunneling conductive channel, which effectively increases the current conduction area.

[0044] like Figure 6 As shown, the current density distribution of the device of the present invention in the forward conduction state is significantly better than that of the conventional device. In addition to the main channel current, there is also a significant heterojunction tunneling current. Figure 9 The forward conduction output characteristic curve further verifies this, achieving a good balance between a significant improvement in reverse performance and forward performance. At this time, because the gate-source voltage of the SSM is 0V, the channel is not open and it does not participate in forward conduction;

[0045] When the device is forward blocked, the main gate controlled trench gate (6) is given a negative bias voltage of 0V or not exceeding 5V, the source auxiliary trench gate (12) is connected to a potential of 0V, and the drain is given a high positive bias voltage. At this time, the negative bias voltage of the main gate controlled trench gate causes a hole accumulation layer to be formed on the surface of the P-base1 region (13), and the main channel is turned off; the right P-well region (4) and the left P-well region (17) together with the reverse bias PN junction formed by the N-drift region (3) bear the forward blocking voltage of the device, and the depletion region extends to the low-doped N-drift region (3);

[0046] like Figure 10 As shown, the breakdown voltage of the device of the present invention reaches 1218V, which is comparable to that of a conventional asymmetric trench SiC MOSFET (1204V). At the same time, the right P-well region (4) and the left P-well region (17) achieve electric field redistribution through depletion effect, and the electric field concentration at the bottom of the shielding trench gate is achieved.

[0047] When the device is reverse freewheeling, a negative bias voltage of 0V or no more than 5V is applied to the main gate controlled trench gate (6), the main channel remains off, and the drain potential is lower than the source potential. At this time, the heterojunction formed by the L-shaped N-type polysilicon region (5) and the N-csl region (18) is forward biased, and electrons flow from the N-csl region into the L-shaped N-type polysilicon region through the low barrier heterojunction interface, and then reach the source, forming the first unipolar freewheeling path, which carries the small current freewheeling.

[0048] like Figure 4 As shown, when the reverse voltage increases, the DIBL effect causes the source barrier height of the P-base2 region (16) to gradually decrease. When the reverse current increases to more than 50A, the source barrier height decreases to 0.77eV. Electrons flow from the N-csl region into the SSM N+ region (15) through the channel of the SSM, and then reach the source, forming a second unipolar freewheeling path, which together with the HJD bears the large current freewheeling.

[0049] like Figure 7 As shown, in the reverse freewheeling state, the reverse current of the device of the present invention flows entirely through the HJD and SSM paths, and there is no significant current in the parasitic diode region. Figure 8 The reverse conduction characteristic curves show that the reverse turn-on voltage of the device of the present invention is only 1.2V, which is much lower than the 2.7V of the traditional SiC body diode, thus eliminating the bipolar degradation effect and significantly reducing reverse freewheeling loss and circuit oscillation risk.

[0050] In summary, this invention achieves unipolar conduction under both forward and reverse freewheeling conditions through the synergistic design of a heterojunction and a SSM, completely solving the bipolar degradation problem; while maintaining excellent forward conduction characteristics and high-frequency switching performance. This invention has strong process compatibility, limited cost increase, and is suitable for high-end power electronics fields such as new energy vehicles, smart grids, and photovoltaic inverters.

[0051] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy, characterized in that, The device includes: Drain metal contact area (1); N+ substrate region (2) formed on the upper surface of the drain metal contact region (1); N- drift region (3) formed on the upper surface of the N+ substrate region (2); N-csl region (18) formed on the upper surface of the N-drift region (3); A P-base1 region (13) is formed on the upper surface of the N-csl region (18); a trench gate structure is formed deep inside the N-drift region (3) and located on both sides of the P-base1 region (13) and the N-csl region (18). The trench gate structure includes a right main gate controlled trench gate (6), a left source auxiliary trench gate (12), and a trench gate oxide layer (7) that wraps the main gate controlled trench gate (6) and the source auxiliary trench gate (12). The right-side P-well region (4) is formed on the upper right side of the N-drift region (3) and encloses the L-shaped N-type polycrystalline silicon region (5); An L-shaped N-type polysilicon region (5) is formed on the right side of the main gate control trench gate (6) and connected to the N-csl region (18) at its lower end. The L-shaped N-type polysilicon region (5) and the N-csl region (18) constitute an N-type polysilicon / N-type SiC heterojunction diode (HJD); a left P-well region (17) is formed on the upper left surface of the N-drift region (3). The P-base2 region (16), SSM N+ region (15) and second source P+ region (14) are formed on the upper surface of the left P-well region (17) and below the source auxiliary trench gate (12), and are distributed from right to left. A short-channel self-biased MOSFET (SSM) structure is formed below the source auxiliary trench gate (12), the SSM structure is composed of the source auxiliary trench gate (12), the P-base2 region (16), the SSM N+ region (15) and the N-csl region (18); The first source N+ region (8) and the first source P+ region (9) are formed on the upper surface of the P-base1 region (13) and on the left side of the main gate control trench gate (6). The second source N+ region (10) is formed on the right side of the source auxiliary trench gate (12) and embedded inside the P-base1 region (13); The source metal contact area formed at the top of the device (11). The main gate control trench gate (6) is connected to the device gate potential, and the source auxiliary trench gate (12) is electrically connected to the source metal contact area (11).

2. The globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, When the device is forward-biased, the main gate control trench gate (6) is given a positive bias of +15V relative to the source, forming an N-type inversion channel on the sidewall of the P-base1 region (13) to achieve the main channel conduction; at the same time, the positive gate voltage controls the surface energy band of the L-shaped N-type polysilicon region (5), allowing electrons to enter the N-csl region (18) from the N-type polysilicon region (5) through the quantum tunneling effect, forming an additional tunneling conductive channel and reducing the specific on-resistance of the device; at this time, the SSM is in the off state because the gate-source voltage is 0V and does not participate in forward conduction.

3. The globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, When the device is forward blocked, the main gate control trench gate (6) is subjected to a negative bias voltage of 0V or not exceeding 5V, and the main channel is turned off. The right P-well region (4) and the left P-well region (17) together with the N-drift region (3) form a reverse bias PN junction to bear the blocking voltage. At the same time, the electric field at the bottom of the shield trench gate is concentrated, limiting the maximum electric field of the gate oxide layer to 3.75MV / cm, which meets the long-term reliability requirements of the SiC / SiO2 interface.

4. The globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, When the device is reverse freewheeling, the main gate controlled trench gate (6) is given a negative bias of 0V or no more than 5V, and the main channel remains off. At this time, the L-shaped N-type polysilicon / N-type SiC heterojunction diode (HJD) is forward biased and conducts, while the short-channel self-biased MOSFET (SSM) forms an electronic conduction channel by utilizing the drain-induced barrier reduction (DIBL) effect. The reverse current flows through the two unipolar paths of HJD and SSM. Within the rated reverse current range of 0~300A, the conduction of the parasitic diode is completely suppressed, and the bipolar degradation effect is eliminated.

5. A globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, The doping concentration of the L-shaped N-type polysilicon region (5) is 1×10²¹cm⁻³, and the thickness is 0.15μm. The conduction band offset of the heterojunction interface formed by the N-type polysilicon region (5) and the N-csl region (18) is 0.84eV. When the forward conduction is performed, the gate voltage is adjusted to make the tunneling distance less than 10nm.

6. The globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, The short-channel self-biased MOSFET (SSM) has a channel length of 0.4 μm and a channel doping concentration of 7 × 10¹. 6 cm⁻³; The SSM utilizes the DIBL effect to reduce the source barrier height to 0.77eV under reverse voltage, forming a low-resistance electronic conductive channel.

7. The globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, The sidewall oxide layer thickness of the main gate control trench gate (6) and the source auxiliary trench gate (12) is 0.05 μm, and the oxide layer thickness at the bottom of the trench is 0.08 μm.

8. A globally unipolar conductive SiC MOSFET device based on heterojunction and SSM synergy according to claim 1, characterized in that, The source metal contact region (11) simultaneously achieves ohmic contact with the first source N+ region (8), the first source P+ region (9), the second source N+ region (10), the second source P+ region (14), the SSM N+ region (15), the source auxiliary trench gate (12), and the L-shaped N-type polysilicon region (5); the drain metal contact region (1) is located on the lower surface of the N+ substrate region (2) and forms an ohmic contact with the N+ substrate region (2).

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