An omega-gate single-crystal indium oxide nanowire transistor, a preparation method and a 2T0C DRAM memory cell

Abstract

The application belongs to the technical field of semiconductor storage and devices, and particularly relates to an Omega-gate single-crystal indium oxide nanowire transistor, a preparation method and a 2T0C DRAM storage unit. The Omega-gate single-crystal indium oxide nanowire transistor comprises a substrate, a channel layer arranged on the substrate, the channel layer being a single-crystal indium oxide nanowire, a source electrode and a drain electrode arranged on the channel layer in a conductive direction, and forming an ohmic contact with the channel layer, a gate dielectric layer at least partially covering a surface of the channel layer to form an Omega-shaped covering structure covering the channel layer, and a gate electrode arranged on a surface of the gate dielectric layer, at least a part of a projection of the gate electrode on the substrate overlapping a projection of the channel layer on the substrate, and the gate electrode and the gate dielectric layer together forming an Omega-shaped gate structure. The application solves the problems of low mobility, weak gate control ability and poor stability of existing oxide transistors by combining a single-crystal In2O3 nanowire channel with an Omega-shaped gate structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory and device technology, specifically relating to an Ω-type gate single-crystal indium oxide nanowire transistor, its fabrication method, and a 2T0C DRAM memory cell. Background Technology

[0002] Traditional DRAM uses a 1T1C (1 transistor, 1 capacitor) architecture. With the continuous miniaturization of devices, the contradiction between the scaling limits of capacitors and the increasing leakage current has become increasingly prominent, directly leading to a decrease in DRAM storage capacity and an increase in refresh power consumption. This has become a core bottleneck restricting the development of high-density, low-power DRAM. To overcome this bottleneck, the 2T0C (dual transistor, capacitor-free) DRAM architecture has received widespread attention in recent years. This architecture utilizes the parasitic capacitance or gate leakage current between the two transistors to achieve charge storage, completely avoiding the use of capacitors, and thus possesses extremely high miniaturization potential.

[0003] Metal-oxide-semiconductor (MOS) semiconductors possess wide bandgap values ​​greater than 3 eV, enabling transistors fabricated based on them to achieve extremely low leakage currents below 10⁻²¹ A / μm. Through novel circuit designs, MOS-based DRAMs can eliminate their reliance on capacitors, creating capacitor-free memory architectures. This promises to solve a series of problems caused by excessive leakage current in traditional 1T1C DRAMs, achieving longer data retention times, lower power consumption, and higher integration density. Furthermore, MOS semiconductors can be fabricated using low-temperature deposition techniques, exhibiting excellent back-to-end (BEOL) process compatibility and enabling their use in monolithic 3D semiconductor integration. Indium oxide (In₂O₃), as a wide-bandgap MOS semiconductor, possesses high electron mobility (theoretically several times that of single-crystal silicon) and extremely low off-state current, and can be fabricated using low-temperature processes. In recent years, it has shown great potential in high-performance thin-film transistors (TFTs) and 3D integration. However, most current Indium oxide-based transistors use amorphous or polycrystalline thin films as channels, resulting in high defect state densities that limit the full utilization of mobility and the improvement of device stability.

[0004] Existing technology proposes an Ω-type top-gate FinFET and its fabrication method (CN106158974A). This technology replaces the traditional rectangular top-gate with an Ω-type top-gate. Utilizing the gate control capability of the Ω-type gate structure, which is close to that of a gate-all-around structure, the gate control capability of the Ω-type top-gate FinFET at the upper 1 / 3 of the Fin is greater than that of the traditional rectangular top-gate FinFET (triple-gate structure), thus achieving lower leakage current. Simultaneously, since the channel cross-sectional area at the upper 1 / 3 of the Fin in the Ω-type top-gate FinFET is not reduced, severe degradation of the on-state current is avoided. Furthermore, this technology uses a thermal oxidation process to reduce the initial Fin channel region, controlling the width below the Ω-type Fin channel region and further optimizing the short-channel effect control capability of the device.

[0005] However, the aforementioned existing technologies still have the following shortcomings: First, their channel materials use traditional semiconductor materials such as silicon or germanium. As devices continue to shrink, the mobility bottleneck and interface state problems of silicon materials themselves gradually restrict the further improvement of on-state current and subthreshold swing. Summary of the Invention

[0006] The purpose of this invention is to provide an Ω-type gate single-crystal indium oxide nanowire transistor with high mobility and good stability, its fabrication method, and a 2T0C DRAM memory cell.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An Ω-type gate single-crystal indium oxide nanowire transistor, comprising: Substrate; A channel layer is disposed on the substrate surface, and the channel layer is a single-crystal indium oxide nanowire; A source electrode and a drain electrode are respectively disposed in the conductive direction of the channel layer, forming an ohmic contact with the channel layer; A gate dielectric layer, at least a portion of which covers the surface of the channel layer, forming an Ω-shaped covering structure covering the channel layer; A gate electrode is disposed on the surface of the gate dielectric layer, and at least a portion of its orthographic projection on the substrate coincides with the orthographic projection of the channel layer on the substrate, forming an Ω-shaped gate structure together with the gate dielectric layer. The source electrode and drain electrode are respectively located on both sides of the gate electrode; A first gap is left between the source electrode and the Ω-shaped gate structure, and a second gap is left between the drain electrode and the Ω-shaped gate structure.

[0008] This invention is the first to combine the high gate control capability (close to the gate-around structure) of the Ω-type gate with the high mobility and ultra-low off-state current characteristics of single-crystal indium oxide nanowires, achieving a synergistic effect of structural advantages and material advantages.

[0009] According to embodiments of the present invention, the present invention can be further optimized, and the optimized technical solution is as follows: In one preferred embodiment, the source electrode and the drain electrode are respectively disposed at both ends of the channel layer.

[0010] In one preferred embodiment, the substrate is a heavily p-type doped silicon substrate.

[0011] In one preferred embodiment, a thermally oxidized SiO2 buffer layer is provided between the substrate and the channel layer; the channel layer is disposed on the surface of the thermally oxidized SiO2 buffer layer.

[0012] Using a heavily p-type doped silicon substrate can effectively suppress substrate leakage current, while the thermally oxidized SiO2 buffer layer not only provides good insulation, but also optimizes the interface state between the nanowire and the substrate, providing a flat and clean substrate for subsequent Ω-type gate processes.

[0013] In one preferred embodiment, the thickness of the thermally oxidized SiO2 buffer layer is 80-120 nm.

[0014] Too small a thickness will lead to increased parasitic capacitance, aggravated substrate leakage, significant influence of interface states, and decreased process yield; too large a thickness will increase thermal stress, leading to the risk of nanowire cracking, weakening heat dissipation capacity and causing self-heating effect, reducing the uniformity of Ω-shaped gate coating and increasing process cost.

[0015] In one preferred embodiment, the diameter of the single-crystal indium oxide nanowire is 5-50 nm, and it is preferably a single-crystal structure without vacancy defects.

[0016] In one preferred embodiment, the length of the single-crystal indium oxide nanowire is 0.2-5µm; preferably 0.2-3µm.

[0017] Oxygen vacancy defects in single-crystal indium oxide nanowires can lead to decreased device stability and increased off-state current. A defect-free single-crystal structure is crucial for the performance of Ω-gate structures, as the full enclosure of the channel by the Ω-gate amplifies the negative impact of bulk defects on device performance.

[0018] The diameter of the single-crystal indium oxide nanowires is 5-50 nm, which ensures the mechanical stability and process compatibility of the nanowires in the subsequent Ω-type gate process.

[0019] In one preferred embodiment, the source electrode is one or a mixture of several of Ni, Al, Ti, Au, Bi, Ag, InSnO, Mo, TiN, Cr, W, Cu, and Pt.

[0020] In one preferred embodiment, the drain electrode is one or a mixture of several of Ni, Al, Ti, Au, Bi, Ag, InSnO, Mo, TiN, Cr, W, Cu, and Pt.

[0021] In one preferred embodiment, the thickness of the source electrode and the drain electrode is 20-50 nm.

[0022] If the electrode thickness is too small, the evaporated and deposited electrode is prone to breakage at the protrusions of the nanowire, which leads to deterioration of the contact performance between the electrode and the nanowire channel, increased contact resistance, and ultimately affects the electrical performance and fabrication yield of the device.

[0023] In one preferred embodiment, the gate electrode is a Ni metal layer.

[0024] In one preferred embodiment, the gate dielectric layer surrounds the single-crystal indium oxide nanowire.

[0025] In one preferred embodiment, the two ends of the gate dielectric layer extend to one side of the single-crystal indium oxide nanowire, respectively.

[0026] In one preferred embodiment, both ends of the gate electrode layer extend to one side of the single-crystal indium oxide nanowire; In one preferred embodiment, the thickness of the gate electrode is 10-100 nm.

[0027] In one preferred embodiment, the thickness of the gate electrode is 20-50 nm.

[0028] In one preferred embodiment, the gate dielectric layer is one or a mixture of several of Al2O3, HfO2, SiO2, ZrO2, Y2O3, La2O3, and SiN.

[0029] This invention employs a single Ni metal as both the source / drain electrode and the gate electrode. Ni can form a good ohmic contact with indium oxide (with Ar plasma treatment), and Ni, as the gate electrode, has a suitable work function, allowing it to form a good interface with the gate dielectric. The use of a single metal material simplifies the process steps and reduces manufacturing costs.

[0030] In one preferred embodiment, the thickness of the gate dielectric layer is 1-20 nm.

[0031] In one preferred embodiment, the thickness of the gate dielectric layer is 5-10 nm.

[0032] In one preferred embodiment, the width of the first gap is 100-500 nm.

[0033] In one preferred embodiment, the width of the second gap is 100-500 nm.

[0034] Based on the same inventive concept, this invention also claims protection for a method for fabricating the Ω-type gate single-crystal indium oxide nanowire transistor, comprising the following steps: S1. After cleaning the substrate, fix the single-crystal indium oxide nanowires onto the substrate; S2. Prepare source and drain electrodes in the conductive direction of the single-crystal indium oxide nanowire; S3. Deposit a gate dielectric layer on the substrate and the surface of the single crystal indium oxide nanowire, so that the gate dielectric layer covers the single crystal indium oxide nanowire to form an Ω-type covering structure; S4. Deposit a gate electrode on the surface of the gate dielectric layer to form an Ω-type gate structure; thus obtaining the Ω-type gate single-crystal indium oxide nanowire transistor.

[0035] In one preferred embodiment, the gate dielectric layer is prepared by atomic layer deposition.

[0036] This invention addresses the cylindrical geometry of single-crystal indium oxide nanowires by employing atomic layer deposition (ALD) technology. Leveraging the superior step coverage capability of ALD, conformal coating of the nanowire surface is achieved, forming an Ω-shaped gate dielectric layer. This solves the interface control challenge of integrating oxide nanowires with the gate dielectric.

[0037] In one preferred embodiment, the source electrode and drain electrode in step S2 are prepared using one of the following processes: electron beam evaporation, thermal evaporation, chemical vapor deposition, pulsed laser deposition, and physical vapor deposition. During the preparation process, the sample substrate is tilted at a preset angle away from the normal direction of the evaporation source, and the substrate is kept rotating continuously and uniformly throughout the deposition process.

[0038] In one preferred embodiment, during the fabrication of the source and drain electrodes in step S2, the chamber pressure of the evaporation process is maintained at 10. -4 Below Pa, the deposition rate is constantly controlled at 0.1-0.5 Å / s.

[0039] In one preferred embodiment, the gate electrode in step S3 is fabricated using atomic layer deposition (ALD) technology.

[0040] In one preferred embodiment, the deposition of the gate electrode in step S4 is performed using one of the following processes: electron beam evaporation, thermal evaporation, chemical vapor deposition, pulsed laser deposition, and physical vapor deposition. During the deposition process, the sample substrate is tilted at a preset angle away from the normal direction of the evaporation source, and the substrate is kept rotating continuously and uniformly throughout the deposition process.

[0041] This invention employs a tilted rotational deposition mode (the substrate is tilted at a preset angle away from the normal direction of the evaporation source while maintaining a uniform rotation speed), enabling metal atoms to be uniformly deposited on the top and sidewalls of the nanowires. This achieves a tight, conformal enclosure of the cylindrical nanowires, a crucial process for forming a complete Ω-shaped gate structure. The tilted rotational deposition mode of this invention allows metal atoms to be incident on the nanowire surface from multiple angles, significantly increasing the contact area between the source / drain electrodes and the nanowires, thereby reducing contact resistance.

[0042] In one preferred embodiment, during the deposition of the gate electrode in step S4, the deposition rate is constantly controlled at 0.1-0.5 Å / s.

[0043] In one preferred embodiment, the single-crystal indium oxide nanowires are prepared by chemical vapor deposition.

[0044] The chemical vapor deposition method for single-crystal indium oxide nanowires is based on existing technology (Cao Huanqi, Zhu Changjun, Wang Anxiang. Fabrication and electrical properties of indium oxide nanowire field-effect transistors [J]. Journal of Basic Science of Textile Colleges, 2018, 31(04): 446-451).

[0045] In one preferred embodiment, the fabrication method of the Ω-type gate single-crystal indium oxide nanowire transistor further includes step S5, performing plasma treatment on the fabricated device.

[0046] Based on the same inventive concept, this invention also claims protection for the application of the Ω-type gate single-crystal indium oxide nanowire transistor in the fabrication of 2T0C DRAM memory cells.

[0047] Based on the same inventive concept, this invention also claims a 2T0C DRAM memory cell, including a write transistor and a read transistor, wherein both the write transistor and the read transistor are the aforementioned Ω-type gate single-crystal indium oxide nanowire transistors.

[0048] In one preferred embodiment, the drain of the write transistor is electrically connected to the gate of the read transistor to form a memory node; the gate of the write transistor is connected to the write word line, and the source is connected to the write bit line; the drain of the read transistor is connected to the read bit line, and the source is grounded.

[0049] In one preferred embodiment, the write transistor and the read transistor are integrated on the same substrate.

[0050] This invention employs identical Ω-type gate single-crystal indium oxide nanowire transistors as two core devices. Utilizing their ultra-low off-state current characteristics, the charge retention time of the memory node is significantly extended, while their high mobility characteristics improve read / write speeds. Simultaneously, it achieves process standardization and simplified integration. The memory node utilizes the gate capacitance of the read transistor to store charge, completely avoiding the storage capacitor required by traditional 1T1C DRAM, thus possessing extremely high miniaturization potential.

[0051] In one preferred embodiment, the 2T0C DRAM memory cell is a capacitor-free 2T0C architecture; the write operation is completed by voltage regulation of the write word line and the write bit line; the read operation is realized by current monitoring of the read bit line, and the read process is non-destructive and does not interfere with the charge state of the memory node.

[0052] This invention utilizes the ultra-low gate leakage current and steep subthreshold swing characteristics of the Ω-type gate single-crystal indium oxide nanowire transistor read signal to achieve read line current monitoring that senses the charge state of the storage node without interference, i.e., non-destructive reading. This operating mode significantly reduces refresh power consumption and extends data retention time.

[0053] Compared with the prior art, the beneficial effects of the present invention are: This invention provides an Ω-type gate single-crystal indium oxide nanowire transistor and its 2T0C DRAM memory cell. By combining a single-crystal In2O3 nanowire channel with an Ω-type gate structure, its fabrication process is simple, solving the problems of low mobility, weak gate control capability, and poor stability of existing oxide transistors. At the same time, based on this transistor, a capacitor-free 2T0C DRAM can be constructed, solving the problems of limited integration, high power consumption, and short data retention time of traditional 1T1C DRAM.

[0054] Specifically, this invention achieves breakthroughs in three core areas: materials, structure, and process, and possesses significant beneficial effects and industry-leading comprehensive performance, as detailed below: Firstly, at the core design level, through collaborative innovation in materials and structure, this invention fundamentally solves the industry pain points of weak gate control capability and low performance upper limit of oxide nanowire transistors. This invention innovatively uses single-crystal In2O3 nanowires as the channel material. The complete single-crystal lattice fundamentally suppresses bulk and interface defects, laying a material foundation for efficient carrier transport and long-term stable device operation. Simultaneously, paired with an Ω-type fully enclosed gate structure, it achieves three-dimensional all-around gate control of the nanowire channel, completely breaking through the gate control capability bottleneck of planar gate structures, significantly optimizing device switching characteristics, and effectively suppressing short-channel effects. Compared with traditional planar gate nanowire transistors, the gate control capability of this invention achieves a qualitative leap. The threshold voltage is optimized from -4 V in the planar device to -1 V, the on-state current is increased by an order of magnitude, and the hysteresis window of the transfer characteristic curve is only 4mV, which is almost negligible. Interface state control reaches an industry-leading level.

[0055] Secondly, in terms of performance indicators, it achieves a technological breakthrough that combines high performance and low power consumption, fully meeting international advanced standards. The Ω-type gate single-crystal In2O3 nanowire transistor of this invention, under conventional test conditions of a 200 nm channel length and a 1 V drain-source voltage, achieves an ultra-high on-state current of 4000 μA / μm and a current of 321.7 cm⁻¹. 2 Ultra-high field-effect mobility / Vs, switching current ratio exceeding 10 9 With a subthreshold swing as low as 64.6mV / dec, infinitely close to the theoretical room temperature limit of 60mV / dec, all core indicators fully meet the technical requirements of the International Technology Roadmap for Semiconductors (ITRS) for high-performance, low-power logic devices, reaching the international advanced level of similar devices.

[0056] Thirdly, in terms of reliability and industrialization, it breaks through the core bottleneck that makes it difficult to mass-produce high-performance devices. Regarding reliability, the device exhibits extremely strong hydrogen tolerance and environmental stability in the stringent gate bias temperature stress test at 60 ℃ and ±2 V gate voltage, fully meeting the commercial reliability requirements for long-term operation. In terms of process compatibility, the fabrication process of this invention is fully compatible with standard semiconductor back-end processes. Compared to the complex fabrication schemes of existing Ω-type gate structures, this invention significantly simplifies the process steps, eliminating the need for complex processes such as high-precision overlay and multi-round deposition and etching. The process is simple and controllable, reducing fabrication costs and significantly improving process yield. At the same time, the process complexity is far lower than that of advanced node gate-all-around (GAA) transistors, possessing extremely strong potential for large-scale mass production and commercial value. More importantly, the capacitor-free 2T0C DRAM memory cell built based on the transistors of this invention eliminates the dependence on capacitors in the traditional 1T1C architecture, significantly increasing storage density; it also achieves ultra-long data retention time, making it extremely valuable for applications in next-generation DRAM devices. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of the Ω-type gate single-crystal In₂O₃ nanowire transistor prepared in Example 1; wherein Figure 1 In the diagram, A represents the overall structure of an Ω-type gate single-crystal In₂O₃ nanowire transistor. Figure 1 B in the diagram is a cross-sectional view of an Ω-type gate single-crystal In2O3 nanowire transistor; In the figure, 1-substrate, 2-thermally oxidized SiO2 buffer layer, 3-channel layer, 4-source electrode / drain electrode, 5-gate dielectric layer, 6-gate electrode; Figure 2 This is a TEM characterization image of the Ω-type gate single-crystal In2O3 nanowire transistor prepared in Example 1.

[0058] Figure 3 These are the output and transfer characteristic curves of an Ω-type gate single-crystal In₂O₃ nanowire transistor with a channel length of 3 μm; among them, Figure 3 In the figure, A represents the output characteristic curve. Figure 3 B in the figure represents the transfer characteristic curve.

[0059] Figure 4 These are the electrical performance test results of other Ω-type gate single-crystal In2O3 nanowire transistors with different channel lengths prepared in Example 1; among them, Figure 4 In the figure, A represents the output characteristic curve. Figure 4 B in the figure represents the transfer characteristic curve.

[0060] Figure 5These are the bias stability test results for other Ω-type gate single-crystal In2O3 nanowire transistors with different channel lengths prepared in Example 1, wherein... Figure 5 In the diagram, A represents the transfer characteristics under NBS stress at different time points. Figure 5 In the figure, B represents the transfer characteristic curves at different time points under positive bias stress. Figure 5 In the figure, C represents the transfer characteristic curve of negative bias temperature stress at different time points. Figure 5 D in the figure represents the transfer characteristic curve of positive bias temperature stress at different time points.

[0061] Figure 6 This is a schematic diagram of the equivalent circuit of the 2T0C DRAM memory cell in Example 1.

[0062] Figure 7 This is an SEM characterization image of the 2T0C DRAM memory cell of Example 1.

[0063] Figure 8 This is a test curve of the data retention characteristics of the 2T0C DRAM memory cell in Example 1; wherein, Figure 8 In the figure, A represents the graph showing the relationship between the storage node voltage and the read current during a read operation. Figure 8 B in the graph represents the long-term current reading curve for the "0 / 1" state. Figure 8 C in the figure represents the long-term retention characteristic curve of the storage node voltage.

[0064] Figure 9 This is a schematic diagram of the back gate structure of a single-crystal In2O3 nanowire. In the figure, 7-back gate heavily p-type doped silicon substrate, 8-Al2O3 gate dielectric layer, 9-single crystal In2O3 nanowire channel layer, 10-source / drain electrode.

[0065] Figure 10 This is a SEM image of the back gate structure of a single-crystal In2O3 nanowire.

[0066] Figure 11 The results show the electrical performance test results of the back gate structure of the single-crystal In2O3 nanowires prepared in Comparative Example 1.

[0067] Figure 12 The results show the electrical performance test results of the Ω-gate structure prepared in Comparative Example 2. Detailed Implementation

[0068] This invention is not limited to the specific embodiments listed below. Those skilled in the art can implement this invention using various other specific embodiments based on the content disclosed herein. Any modifications or alterations made to the design structure and concept of this invention fall within the protection scope of this invention. It should be noted that, unless otherwise specified, the embodiments and features described in this invention can be combined with each other.

[0069] Example 1 A schematic diagram of the Ω-type gate single-crystal In₂O₃ nanowire transistor prepared in Example 1 is shown below. Figure 1 As shown. Among them. Figure 1 In the diagram, A represents the overall structure of an Ω-type gate single-crystal In₂O₃ nanowire transistor. Figure 1 B in the diagram is a cross-sectional view of an Ω-type gate single-crystal In2O3 nanowire transistor.

[0070] like Figure 1 As shown, the Ω-type gate single-crystal In2O3 nanowire transistor provided by the present invention includes a substrate 1, a channel layer 3, source / drain electrodes 4, a gate dielectric layer 5, and a gate electrode 6. The substrate 1 is a heavily p-type doped silicon substrate, and a 100 nm thick thermally oxidized SiO2 buffer layer 2 is provided on the surface of the substrate 1. The channel layer 3 is a single-crystal In2O3 nanowire disposed on the substrate 1; the diameter of the single-crystal In2O3 nanowire is 50 nm, and it is a single-crystal structure prepared by chemical vapor deposition without vacancy defects. The source / drain electrodes 4 are respectively disposed at both ends of the channel layer 3, forming ohmic contacts with the channel layer 3; the source / drain electrodes 4 are 50 nm thick Ni metal layers. The channel layers 3 have lengths of 0.2 μm, 1 μm, 2 μm, and 3 μm, respectively. The width of the cross-section where the channel layer 3 contacts the thermally oxidized SiO2 buffer layer 2 is approximately 3 / 4 of the circumference of the nanowire cylinder. The gate dielectric layer 5 is a 10 nm thick Al2O3 layer deposited atomically, covering the surface of the channel layer 3 to form an Ω-shaped coating structure. The gate electrode 6 is disposed on the surface of the gate dielectric layer 5, and its partial orthographic projection on the substrate 1 coincides with the orthographic projection of the channel layer 3 on the substrate 1, forming an Ω-shaped gate structure together with the gate dielectric layer 5. The gate electrode 6 is a 50 nm thick Ni metal layer. The source electrode 4 and drain electrode 4 are respectively disposed on both sides of the gate electrode 6; a first gap is left between the source electrode 4 and the Ω-shaped gate structure, and a second gap is left between the drain electrode 4 and the Ω-shaped gate structure. The width of the first gap and the second gap is 200 nm. The gate dielectric layer 6 surrounds the single-crystal In2O3 nanowire.

[0071] The Ω-type gate single-crystal In2O3 nanowire transistor of this embodiment can be prepared by referring to existing technology (Cao Huanqi, Zhu Changjun, Wang Anxiang. Preparation and electrical properties of indium oxide nanowire field-effect transistors [J]. Journal of Basic Science of Textile Colleges, 2018, 31(04): 446-451.), or by following these steps: Single-crystal indium oxide (In2O3) nanostructures are synthesized in a horizontal tube furnace using conventional chemical vapor deposition (CVD) technology. The specific preparation steps are as follows: Indium oxide powder and carbon powder are mixed and ground thoroughly at a mass ratio of 1:2 to obtain a reaction precursor; the ground mixed precursor powder is placed in a quartz crucible, and then the crucible is placed in the heating zone of the horizontal tube furnace; the surface with 1 A high-conductivity silicon substrate with a nm-thick gold seed layer was placed in the downstream gas flow zone of a tube furnace. The furnace tube was evacuated using a vacuum pump, and then an Ar / O2 mixed gas was introduced into the tube at a volume ratio of 100:1 (Ar:O2) and a total flow rate of 200 sccm. This evacuation and purging cycle was repeated three times to ensure a pure Ar / O2 atmosphere within the furnace tube. The furnace was heated to 1000 °C, and the reaction was carried out for 1 hour under continuous Ar / O2 gas flow. After the reaction, heating was stopped, and the furnace was allowed to cool naturally to room temperature, thus obtaining single-crystal indium oxide nanowires on the silicon substrate. To meet the requirements of subsequent device fabrication, the obtained indium oxide nanowires were peeled off from the silicon substrate and dispersed in anhydrous ethanol to obtain an indium oxide nanowire solution.

[0072] A 100 nm thick SiO2 layer was grown on a heavily p-type doped silicon substrate using a thermal oxidation process as a substrate buffer layer. The substrate was then ultrasonically cleaned sequentially with deionized water, isopropanol, and anhydrous ethanol to remove particulate impurities and organic contaminants, resulting in a clean substrate. The grown single-crystal In2O3 nanowires were transferred to the prepared substrate surface to serve as the channel layer for a transistor. The procedure involved drop-coating an ethanol dispersion of the In2O3 nanowires onto the SiO2 dielectric layer surface, followed by placing the substrate on a 100°C heating plate for 10 min to allow residual ethanol to completely evaporate, thus completing the transfer and fixation of the nanowires.

[0073] The source / drain regions were patterned using electron beam lithography (EBL). A 50 nm thick layer of metallic Ni was deposited using electron beam evaporation, followed by a lift-off process to fabricate the source / drain electrodes, which formed ohmic contacts with the two ends of the channel layer. The steps were as follows: a substrate with nanowires was spin-coated sequentially with methyl methacrylate (MMA) and polymethyl methacrylate (PMMA) at 4000 rpm. After spin-coating, the substrate was placed on a hot plate at 150 °C for 5 min to cure the photoresist. The source / drain electrode regions were patterned using an electron beam lithography (EBL) system. The exposed substrate was then developed in a developer solution of methyl isobutyl ketone (MIBK):isopropanol (IPA) = 1:3. A 50 nm thick layer of metallic Ni was deposited using electron beam evaporation, with the chamber pressure maintained at 10 during the evaporation process. -4 Below Pa, the deposition rate was kept constant at 0.1 Å / s, while the sample substrate was tilted at a preset angle away from the normal direction of the evaporation source, and the substrate was kept rotating continuously and uniformly throughout the deposition process. MMA and PMMA were removed by acetone stripping to obtain patterned Ni source / drain electrodes.

[0074] Atomic layer deposition (ALD) was then used to deposit a 10 nm Al₂O₃ layer as the gate dielectric layer on the substrate and channel layer surfaces. The ALD process achieved an Ω-shaped encapsulation of the In₂O₃ nanowires by the gate dielectric layer, resulting in clear interfaces between functional layers and extremely low interface defects. The gate region was patterned using electron beam lithography. A 50 nm thick layer of metallic Ni was deposited as the gate electrode on the surface of the gate dielectric layer corresponding to the channel layer using electron beam evaporation. During deposition, the evaporation rate was strictly controlled at a constant 0.1 Å / s, while the sample substrate was tilted at a predetermined angle away from the normal direction of the evaporation source, and the substrate was continuously rotated at a uniform speed throughout the deposition process. This process ensured step coverage and film uniformity of metal atoms through stable low-rate deposition. Combined with the tilted rotation deposition mode, Ni atoms were uniformly deposited on the top and sidewalls of the nanowires, achieving a tight, conformal, and continuous encapsulation of the nanowires, ultimately forming a uniform and fully encapsulated Ω-shaped gate structure. The main transistor structure was then fabricated. Finally, the fabricated device was subjected to Ar plasma treatment for 2 minutes to reduce the contact resistance between the metal electrode and the In2O3 semiconductor.

[0075] Then, TEM characterization images were obtained of the Ω-type gate single-crystal In2O3 nanowire transistor prepared in Example 1, and the results are as follows. Figure 2 As shown, the interfaces between functional layers are clear, indicating extremely low interface defects in the device. Figure 2 The illustration shows that single-crystal grains can be observed throughout the entire cross-section of the nanowire, with the scale bar of the illustration being 2 nm.

[0076] The electrical performance of Ω-gate single-crystal In₂O₃ nanowire transistors with different channel lengths prepared in Example 1 was tested using a Keysight B1500A semiconductor analyzer and a LakeShore probe station. The results for the Ω-gate single-crystal In₂O₃ nanowire transistor with a channel length of 3 μm are as follows: Figure 3 As shown. Among them, Figure 3 In the figure, A represents the output characteristic curve. Figure 3 B in the figure represents the transfer characteristic curve. The results show that the transistor with a channel length of 3 μm exhibits a clear linear region and saturation region in its output characteristic curve, with no current crowding phenomenon. This indicates that the single-crystal In2O3 and Ni electrode have excellent contact characteristics and have the potential for further size reduction. Figure 3 The A in the figure shows that high V GS (2 V) and V DS At 2 V, the normalized current reaches approximately 1.5 mA / μm, indicating good conduction performance of the device. From Figure 3 Considering the hysteresis of B (only 4 mV / V), the Ω-type gate structure can effectively improve the gate electric field's ability to control the channel, achieving a large output current and a threshold voltage close to 0 V. V th Meanwhile, the device exhibited a hysteresis as low as 4 mV, a characteristic attributed to the extremely low bulk defect density of the single-crystal In2O3 nanowires.

[0077] The electrical performance test results of other Ω-type gate single-crystal In₂O₃ nanowire transistors with different channel lengths prepared in Example 1 are as follows: Figure 4 As shown. Among them, Figure 4 In the figure, A represents the output characteristic curve. Figure 4 B in the figure represents the transfer characteristic curve.

[0078] The results show that when the channel length is reduced to 200 nm, the on-state current of the device is significantly increased, while the threshold voltage and off-state current remain almost unchanged, proving that the Ω-type gate structure has extremely strong gate control capability and can effectively suppress short-channel effects. V DS At 1 V, a device with a channel length of 200 nm achieved a maximum on-state current of 4000 μA / μm and a maximum transconductance of 1800 μS / μm; the extracted average field-effect mobility of the device reached 321.7 cm⁻¹. 2 / Vs, with a subthreshold swing as low as 64.6 mV / dec, close to the theoretical limit of 60 mV / dec.

[0079] At an ambient temperature of 60 °C, +2 V and -2 V gate voltages were applied to the Ω-type gate single-crystal In2O3 nanowire transistor with a channel length of 3 μm in Example 1, respectively, for 10... 4 The positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) of the s were tested. The test results are as follows: Figure 5 As shown. Among them, Figure 5 In the figure, A represents the transfer characteristics under NBS stress at different time points. Figure 5 In the figure, B represents the transfer characteristic curves at different time points under positive bias stress. Figure 5 In the figure, C represents the transfer characteristic curve of negative bias temperature stress at different time points. Figure 5 In the figure, D represents the transfer characteristic curve of positive bias temperature stress at different time points. The results show that 10 4 After testing, under NBS and PBS stresses, the device exhibits excellent stability under negative bias stress, with almost no effect from room temperature bias stress. Under PBTS and NBTS, the threshold and subthreshold swings show no significant changes, further demonstrating excellent reliability and proving the device's superior long-term operational stability. This excellent stability stems from the low-defect structure of the single-crystal In2O3 channel. Simultaneously, single-crystal In2O3 exhibits extremely strong hydrogen tolerance, effectively suppressing device performance drift caused by hydrogen residue in the ALD Al2O3 dielectric layer.

[0080] Based on the 3 μm channel length transistor fabricated according to this invention, a 2T0C DRAM memory cell is fabricated. This memory cell includes a write transistor and a read transistor, both of which are Ω-type gate single-crystal In2O3 nanowire transistors. The drain of the write transistor is connected to the gate of the read transistor, forming a memory node. Charge storage is achieved using the gate capacitance of the read transistor. The gate of the write transistor is connected to the write word line, and the source is connected to the write bit line. The drain of the read transistor is connected to the read bit line, and the source is grounded. This memory cell is a capacitor-free 2T0C architecture. The write operation is completed by voltage regulation of the write word line and the write bit line, and the write speed is determined by the on-state current of the write transistor. The data retention time is jointly determined by the off-state current of the write transistor and the drain current of the read transistor. The read operation is achieved by monitoring the current of the read bit line, which is a non-destructive read operation. The read process does not interfere with the charge storage state of the memory node, forming a core difference from the traditional 1T1C architecture. The equivalent circuit diagram of this 2T0C DRAM memory cell is shown below. Figure 6 As shown, the SEM characterization image is as follows: Figure 7 As shown.

[0081] Data retention characteristics were tested on the 2T0C DRAM memory cells, and the results are as follows: Figure 8 As shown. Among them, Figure 8In the graph, A represents the relationship between the storage node voltage and the read current during a read operation. Figure 8 The B value in the graph represents the long-term current reading from the "0 / 1" state. Figure 8 C in the figure represents the long-term retention characteristic curve of the storage node voltage. The results show that the fitted curve highly coincides with the experimental data, indicating that the readout characteristics of this device are stable and predictable, making it suitable for signal reading from the storage cell. After writing data "1" to the write bit line pulse, even after 10... 5 s, storage node voltage change Δ V SN Less than 0.1 V indicates extremely low leakage current and excellent data retention capability. After writing data "0" to the write bit line pulse, the read transistor is completely exhausted, achieving an effective data retention time of over 40,000 s. This demonstrates that the device has an extremely high switching ratio, good state differentiation, and no crosstalk during reading, far exceeding the millisecond-level retention time of traditional DRAM.

[0082] Comparative Example 1 The back gate structure was fabricated using the same single-crystal In₂O₃ nanowires as in Example 1. The specific steps are as follows: Using the same preparation method as for indium oxide nanowires in Example 1, an indium oxide nanowire solution was obtained. A heavily p-type doped silicon substrate was used, and an atomic layer deposition (ALD) technique was employed to deposit a 10 nm Al₂O₃ layer on the substrate surface as the gate dielectric layer. The substrate was then ultrasonically cleaned sequentially with deionized water, isopropanol, and anhydrous ethanol to remove particulate impurities and organic contaminants from the substrate surface, resulting in a clean substrate. The grown single-crystal In₂O₃ nanowires were transferred to the prepared substrate surface to serve as the channel layer of the transistor. The steps were as follows: the above-mentioned In₂O₃ nanowire ethanol dispersion was drop-coated onto the surface of the Al₂O₃ dielectric layer. The substrate was then placed on a heating plate at 100 °C for 10 min to allow the residual ethanol to completely evaporate, thus completing the transfer and fixation of the nanowires.

[0083] The source / drain regions were patterned using electron beam lithography (EBL). A 50 nm thick layer of metallic Ni was deposited using electron beam evaporation, followed by a lift-off process to fabricate the source / drain electrodes. The source / drain electrodes formed ohmic contacts with both ends of the channel layer. The steps were as follows: a substrate with nanowires was spin-coated sequentially with methyl methacrylate (MMA) and polymethyl methacrylate (PMMA) at 4000 rpm. After spin-coating, the substrate was placed on a hot plate at 150 °C for 5 min to cure the photoresist. The source / drain electrode regions were patterned using an electron beam lithography (EBL) system. The exposed substrate was then developed in a developer solution of methyl isobutyl ketone (MIBK):isopropanol (IPA) = 1:3. A 50 nm thick layer of metallic Ni was deposited using electron beam evaporation, with the chamber pressure maintained at 10 during the evaporation process.-4 Below Pa, the deposition rate was kept constant at 0.1 Å / s, while the sample substrate was tilted at a preset angle away from the normal direction of the evaporation source, and the substrate was continuously rotated at a uniform speed throughout the deposition process. MMA and PMMA were removed by acetone stripping to obtain patterned Ni source / drain electrodes. The main transistor structure was then fabricated. Finally, the fabricated device was subjected to 2 min of Ar plasma treatment to reduce the contact resistance between the metal electrodes and the In₂O₃ semiconductor.

[0084] The back gate structure of the obtained single-crystal In2O3 nanowires is as follows: Figure 9 As shown, the back-gate structure single-crystal In2O3 nanowire transistor comprises, from bottom to top: A heavily p-type doped silicon substrate 7 serves as the back gate electrode of a transistor. Al2O3 gate dielectric layer 8 is deposited on the upper surface of the back gate heavily p-type doped silicon substrate 7 by atomic layer deposition technology; Single-crystal In2O3 nanowire channel layer 9 is laid flat on the upper surface of Al2O3 gate dielectric layer 8; Source / drain electrodes 10 are respectively disposed at both ends of the single-crystal In2O3 nanowire channel layer 9 and are in contact with the upper surface of Al2O3 gate dielectric layer 8; an ohmic contact is formed between the source / drain electrodes 10 and the single-crystal In2O3 nanowire channel layer 9.

[0085] The back-gate heavily p-type doped silicon substrate 7 is located at the bottom layer. The Al2O3 gate dielectric layer 8 covers the back-gate heavily p-type doped silicon substrate 7. The single-crystal In2O3 nanowire channel layer 9 is located on the Al2O3 gate dielectric layer 8. The source / drain electrodes 10 are located on the Al2O3 gate dielectric layer 8 and cover both ends of the single-crystal In2O3 nanowire channel layer 9.

[0086] Then, TEM characterization images of the back grating structure of the single-crystal In2O3 nanowires prepared in Comparative Example 1 were obtained, and the results are as follows: Figure 10 As shown, the length of its channel layer is 3 μm, and the width of the contact surface between the channel layer and the Al2O3 gate dielectric layer 8 is approximately 3 / 4 of the circumference of the cylindrical nanowire.

[0087] The electrical properties of the back gate structure of the single-crystal In2O3 nanowires prepared in Comparative Example 1 were tested, and the results are as follows: Figure 11 As shown. Gate-source voltage from -6 V to 2 V. V GS Threshold voltage within the scanning range V THThe gate control capability is weaker, exhibiting a more negative threshold voltage (up to -4 V), a smaller on-state current, and a larger hysteresis (approximately 1 V). Compared to the back-gate nanowire transistor of Comparative Example 1, the Ω-type gate structure prepared in Example 1 demonstrates a qualitative leap in gate control capability at the same channel length. The threshold voltage is optimized from -4 V in the planar device to -1 V, the on-state current is increased by an order of magnitude, and the hysteresis window of the transfer characteristic curve is only 4 mV, which is almost negligible.

[0088] Comparative Example 2

[0089] The fabrication method for Ω-type gate p-GaN MIS-HEMT, referring to existing technologies, involves the following steps:

[0090] 1. Heterojunction epitaxial growth: The epitaxial wafer was prepared by metal-organic chemical vapor deposition (MOCVD) technology. A 2 μm thick GaN buffer layer, an 85 nm thick GaN channel layer, a 15 nm thick AlGaN barrier layer, and a 110 nm thick p-GaN layer were epitaxially grown on the substrate from bottom to top to form the core heterojunction structure of the device.

[0091] 2. Device mesa isolation fabrication: The inductively coupled plasma reactive ion etching (ICP-RIE) dry etching process based on the Cl2 / BCl3 mixed gas system is adopted. After the isolation pattern is defined by photolithography, the epitaxial wafer is selectively etched to the GaN buffer layer to form an independent device isolation mesa, thereby achieving electrical isolation between adjacent devices.

[0092] 3. Source and drain ohmic electrode fabrication: The source and drain pattern windows are defined by photolithography, and an ohmic contact metal system is deposited within the window. After rapid thermal annealing, the source and drain ohmic contact electrodes are formed, achieving low-resistance ohmic contact with the heterojunction.

[0093] 4. Gate Pattern Definition and Gate Dielectric Layer Fabrication: The gate region is precisely defined using photolithography. An Ω-shaped etching process is performed on the preset gate region of the p-GaN layer to form a three-dimensional patterned structure of the Ω-shaped gate. Subsequently, atomic layer deposition (ALD) is used to controllably grow an HfO2 gate dielectric layer only on the surface of the gate region of the p-GaN cap layer. This ensures that the gate dielectric layer conformally covers the Ω-shaped etched gate region surface, while the remaining non-gate regions remain exposed.

[0094] 5. Ω-type gate fabrication: Ni / Au multilayer metal is deposited using electron beam evaporation to form an Ω-type metal gate on the surface of the gate dielectric layer. Simultaneously, a self-alignment process is used to achieve precise alignment between the gate metal and the gate pattern formed by the previous etching, eliminating the need for additional photolithography masking steps. After the gate metal deposition is completed, a rapid thermal annealing process is performed to optimize the metal-semiconductor interface contact characteristics between the gate metal and the p-GaN cap layer. This process can achieve nanometer-level control over the coverage area of ​​the gate dielectric layer and the gate alignment accuracy, ensuring the electrical performance and reliability of the device.

[0095] 6. Surface passivation layer preparation: SiN is deposited on the overall surface of the device after electrode fabrication using plasma-enhanced chemical vapor deposition (PECVD). x A passivation layer is applied to achieve surface passivation and environmental protection of the device, ultimately completing the fabrication of the Ω-type gate p-GaNMIS-HEMT.

[0096] The electrical performance of the Ω-gate p-GaN MIS-HEMT transistor prepared in Comparative Example 2 was tested, and the results are as follows: Figure 12 As shown, at a gate voltage of 7 V and a source-drain voltage of 5 V, the maximum on-state current of Comparative Example 2 is only 1 mA / μm. In contrast, the Ω-gate nanowire structure device of Example 1 achieves a maximum on-state saturation current of 4 mA / μm, with a current density four times that of Comparative Example 2, demonstrating a significant improvement in device conduction performance. Furthermore, the subthreshold swing of Comparative Example 2 is far higher than the theoretical limit of 60 mV / dec, while the subthreshold swing (SS) of the Ω-gate nanowire structure device of Example 1 of this invention is close to the theoretical physical limit of 60 mV / dec for semiconductor devices at room temperature. The subthreshold characteristics of the device of this invention are significantly better than those of Comparative Example 2, exhibiting stronger electrostatic control of the channel by the gate, lower switching losses, and superior switching characteristics.

[0097] Comparative Example 3

[0098] Based on Example 1, the diameter of the single-crystal In2O3 nanowire was changed to 100 nm, while other aspects remained the same as in Example 1.

[0099] Electrical performance tests were conducted on the Ω-type gate single-crystal In₂O₃ nanowire transistor prepared in Comparative Example 3. The results showed that, compared with Example 1, further increasing the nanowire diameter could increase the channel carrier concentration and further improve the device output current, but it would lead to a decrease in the device threshold voltage V. th A significant negative drift occurs, which greatly increases the off-state leakage current of transistors in the 2T0C DRAM memory cell, shortening the data retention time of the memory cell. When the holding voltage is 0V, the off-state leakage current can be reduced from less than 10V in Example 1. -13 A level rises to 10 -11 A to 10-9 The magnitude is A. Correspondingly, the effective data retention time of the 2T0C DRAM memory cell is drastically reduced from over 40,000 seconds in Example 1 to less than 1,000 seconds, and the data retention capability is severely degraded.

[0100] It should be noted that the above embodiments are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is impossible to exhaustively list all possible implementations here. All obvious variations or modifications derived from the technical solutions of this invention are still within the scope of protection of this invention.

Claims

1. An Ω-type gate single-crystal indium oxide nanowire transistor, characterized in that, include: Substrate; A channel layer is disposed on the substrate, and the channel layer is a single-crystal indium oxide nanowire; A source electrode and a drain electrode are respectively disposed in the conductive direction of the channel layer, forming an ohmic contact with the channel layer; A gate dielectric layer, at least a portion of which covers the surface of the channel layer, forming an Ω-shaped covering structure covering the channel layer; A gate electrode is disposed on the surface of the gate dielectric layer, and at least a portion of its orthographic projection on the substrate coincides with the orthographic projection of the channel layer on the substrate, forming an Ω-shaped gate structure together with the gate dielectric layer. The source electrode and drain electrode are respectively located on both sides of the gate electrode; A first gap is left between the source electrode and the Ω-shaped gate structure, and a second gap is left between the drain electrode and the Ω-shaped gate structure.

2. The Ω-type gate single-crystal indium oxide nanowire transistor according to claim 1, characterized in that, A thermally oxidized SiO2 buffer layer is provided between the substrate and the channel layer, and the channel layer is disposed on the surface of the thermally oxidized SiO2 buffer layer. Preferably, the thickness of the thermally oxidized SiO2 buffer layer is 80-120 nm.

3. The Ω-type gate single-crystal indium oxide nanowire transistor according to claim 1, characterized in that, The diameter of the single-crystal indium oxide nanowire is 5-50 nm.

4. The Ω-type gate single-crystal indium oxide nanowire transistor according to claim 1, characterized in that, The source electrode is one or a mixture of several of Ni, Al, Ti, Au, Bi, Ag, InSnO, Mo, TiN, Cr, W, Cu, and Pt, and the drain electrode is one or a mixture of several of Ni, Al, Ti, Au, Bi, Ag, InSnO, Mo, TiN, Cr, W, Cu, and Pt; the thickness of the source electrode and the drain electrode is 20-50 nm.

5. The Ω-type gate single-crystal indium oxide nanowire transistor according to claim 1, characterized in that, The gate dielectric layer surrounds the single-crystal indium oxide nanowire. Preferably, both ends of the gate dielectric layer extend to one side of the single-crystal indium oxide nanowire. Preferably, both ends of the gate electrode layer extend to one side of the single-crystal indium oxide nanowire. Preferably, the thickness of the gate electrode is 10-100 nm.

6. The Ω-type gate single-crystal indium oxide nanowire transistor according to any one of claims 1-5, characterized in that, The gate dielectric layer is one or a mixture of several of Al2O3, HfO2, SiO2, ZrO2, Y2O3, La2O3, and SiN; the thickness of the gate dielectric layer is 1-20 nm.

7. The method for fabricating an Ω-type gate single-crystal indium oxide nanowire transistor according to any one of claims 1-6, characterized in that, Includes the following steps: S1. After cleaning the substrate, fix the single-crystal indium oxide nanowires onto the substrate; S2. Prepare source and drain electrodes in the conductive direction of the nanowire; S3. Deposit a gate dielectric layer on the substrate and the surface of the single crystal indium oxide nanowire, so that the gate dielectric layer covers the single crystal indium oxide nanowire to form an Ω-type covering structure; S4. Deposit a gate electrode on the surface of the gate dielectric layer to form an Ω-shaped gate structure, thereby obtaining the Ω-shaped gate single-crystal indium oxide nanowire transistor.

8. The preparation method according to claim 7, characterized in that, The source and drain electrodes in step S2 are fabricated using one of the following processes: electron beam evaporation, thermal evaporation, chemical vapor deposition, pulsed laser deposition, or physical vapor deposition. During fabrication, the sample substrate is tilted at a preset angle away from the normal direction of the evaporation source, and the substrate is kept rotating continuously and uniformly throughout the deposition process. Preferably, during the fabrication of the source and drain electrodes in step S2, the chamber pressure during the evaporation process is maintained at 10. -4 Below Pa, the deposition rate is constantly controlled at 0.1-0.5 Å / s.

9. The preparation method according to claim 7, characterized in that, The deposition of the gate electrode in step S4 is performed using one of the following processes: electron beam evaporation, thermal evaporation, chemical vapor deposition, pulsed laser deposition, or physical vapor deposition. During the deposition process, the sample substrate is tilted away from the normal direction of the evaporation source at a preset tilt angle, and the substrate is kept rotating continuously and uniformly throughout the deposition process. Preferably, during the deposition of the gate electrode in step S4, the deposition rate is constantly controlled at 0.1-0.5 Å / s.

10. A 2T0C DRAM memory cell, characterized in that, It includes a write transistor and a read transistor, wherein the write transistor and the read transistor are both Ω-type gate single-crystal indium oxide nanowire transistors as described in any one of claims 1-6.

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