Semiconductor device and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and an electronic device, and relates to the technical field of semiconductor chips, and aims to solve the problem of low channel electron mobility. The semiconductor structure comprises a substrate, and a first semiconductor layer, a second epitaxial sheet and a third epitaxial sheet arranged in sequence on one side of the substrate. The first semiconductor layer comprises a first doped part and a second doped part, and the second doped part is embedded in the surface of the first doped part away from the substrate. The doping types of the first doped part and the second doped part are opposite. The second epitaxial sheet comprises a channel part, the channel part is in contact with the second doped part and the first doped part, and the doping type of the channel part is the same as that of the first doped part. The third epitaxial sheet comprises a gate semiconductor part, the gate semiconductor part is in contact with the channel part, and the doping type of the gate semiconductor part is opposite to that of the channel part. The above semiconductor structure is applied to an electronic device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] Junction Field-Effect Transistors (JFETs) have advantages such as simple structure and reliable performance, and are widely used as electronic control switching structures in traditional silicon (Si) and wide-bandgap semiconductors (such as silicon carbide (SiC) and gallium nitride (GaN)). A JFET is a unipolar electronic device, meaning that when the JFET is in the on state, only one type of charge carrier flows in the channel to form a conduction current between the source and drain.

[0003] However, current JFET devices suffer from low channel electron mobility, resulting in poor threshold voltage consistency and thus affecting the stability of the JFET devices. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, as well as an electronic device, aimed at solving the problem of low electron mobility in the channel of a semiconductor device.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is disposed on one side of the substrate. The first semiconductor layer includes a first doped portion and a second doped portion, the second doped portion being embedded in the surface of the first doped portion away from the substrate; the first doped portion and the second doped portion have opposite doping types. The second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate; the second semiconductor layer includes a channel portion; the channel portion is in contact with the second doped portion and the first doped portion of the first semiconductor layer; the channel portion has the same doping type as the first doped portion. The third semiconductor layer is disposed on the side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a gate semiconductor portion, the gate semiconductor portion being in contact with the channel portion of the second semiconductor layer, the gate semiconductor portion having an opposite doping type to the channel portion.

[0006] The semiconductor device provided in the above embodiments of this disclosure is formed by epitaxial growth of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. Specifically, during the fabrication of the semiconductor device, an N-type ion implantation is performed on the first semiconductor layer epitaxially grown on the substrate to form a first doped portion. Then, a P-type ion implantation is performed on the first semiconductor layer to form a second doped portion. Next, a second semiconductor layer is epitaxially grown on the first semiconductor layer, and an N-type ion implantation is performed on the second semiconductor layer to form a channel portion. Finally, a third semiconductor layer is epitaxially grown on the second semiconductor layer, and a P-type ion implantation is performed on the third semiconductor layer to form a gate semiconductor portion.

[0007] In this configuration, the second semiconductor layer used to form the channel undergoes only one ion implantation, reducing the risk of lattice damage and simplifying the control of doping concentration in the channel. Furthermore, the third semiconductor layer used to form the gate semiconductor undergoes only one ion implantation, reducing the risk of doping tailing on the side of the gate semiconductor near the channel 31, improving electron mobility in the channel, and consequently enhancing the threshold voltage uniformity and stability of the semiconductor device.

[0008] In some embodiments, the first semiconductor layer further includes a first source contact portion, which is at least partially embedded in the surface of the second doped portion away from the substrate, and the first source contact portion is electrically connected to the channel portion.

[0009] In some embodiments, the first source contact is embedded in the surface of the second doped portion away from the substrate. The first semiconductor layer further includes an ohmic contact, which includes a first ohmic contact portion and a second ohmic contact portion connected together; the first ohmic contact portion is embedded in the surface of the first source contact portion away from the substrate; the second ohmic contact portion is embedded in the surface of the second doped portion away from the substrate and contacts the channel portion.

[0010] In some embodiments, a plurality of first source contacts are spaced apart; a portion of the second ohmic contact is located between two adjacent first source contacts.

[0011] In some embodiments, the orthographic projection of one of the ohmic contacts onto the substrate covers the plurality of first source contacts.

[0012] In some embodiments, the first source contact portion includes an integrally formed first source contact sub-portion and a second source contact sub-portion, wherein the first source contact sub-portion is embedded in the surface of the second doped portion away from the substrate; and the second source contact sub-portion is embedded in and penetrates the channel portion and is in contact with the channel portion.

[0013] In some embodiments, the second semiconductor layer further includes a second source contact portion disposed on the side of the channel portion away from the substrate; the semiconductor device further includes a gate connection structure extending through the channel portion and contacting the gate semiconductor portion and the second doped portion.

[0014] In some embodiments, the channel portion includes a first channel sub-portion and a second channel sub-portion, the first channel sub-portion surrounding the second channel sub-portion; the second source contact portion is embedded in the surface of the second channel sub-portion away from the substrate; and the doping concentration of the second channel sub-portion is less than the doping concentration of the first channel sub-portion.

[0015] In some embodiments, the channel portion includes a third channel sub-portion and a fourth channel sub-portion, the fourth channel sub-portion being located on the side of the third channel sub-portion away from the substrate; the second source contact portion is embedded in and penetrates the fourth channel sub-portion; the orthographic projection of the second source contact portion on the substrate does not overlap with the orthographic projection of the gate semiconductor portion on the substrate; the doping concentration of the fourth channel sub-portion is less than the doping concentration of the third channel sub-portion.

[0016] In some embodiments, the gate connection structure includes a first gate connection structure and a second gate connection structure connected to each other; the first gate connection structure is disposed on the side of the second gate connection structure away from the substrate; the first gate connection structure passes through the channel portion and the second doped portion; the second gate connection structure is embedded in the first doped portion; a protrusion is provided at one end of the second gate connection structure near the substrate; in a first cross section, the two sides forming the protrusion are straight lines; the first cross section is perpendicular to the substrate.

[0017] In some embodiments, the channel portion is provided with a boss, and the gate semiconductor portion is disposed on the boss.

[0018] On the other hand, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device as described in the above embodiments. This fabrication method includes: A first semiconductor layer is formed on a substrate; the first semiconductor layer includes a first doped portion and a second doped portion, the second doped portion being embedded in the surface of the first doped portion away from the substrate; the first doped portion and the second doped portion have opposite doping types; A second semiconductor layer is formed on the side of the first semiconductor layer away from the substrate; the second semiconductor layer includes a channel portion; the channel portion is in contact with a second doped portion and a first doped portion of the first semiconductor layer; the channel portion and the first doped portion have the same doping type; A third semiconductor layer is formed on the side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a gate semiconductor portion; the gate semiconductor portion is in contact with the channel portion of the second semiconductor layer; the doping type of the gate semiconductor portion is opposite to that of the channel portion.

[0019] In another aspect, an electronic device is provided, including the semiconductor device as described in the above embodiments.

[0020] It is understood that the beneficial effects of the semiconductor device fabrication method and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below.

[0022] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments; Figure 2 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 1 ; Figure 3 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 2 ; Figure 4 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 3 ; Figure 5 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 4 ; Figure 6 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 5 ; Figure 7 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 6 ; Figure 8 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 7 ; Figure 9 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 8 ; Figure 10 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 9 ; Figure 11 A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 10 ; Figure 12A schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 10 one; Figure 13 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments; Figure 14 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 1 ; Figure 15 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 2 ; Figure 16 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 3 ; Figure 17 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 4 ; Figure 18 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 5 ; Figure 19 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 6 ; Figure 20 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 7 ; Figure 21 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 8 ; Figure 22 The structures corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. Figure 9 . Detailed Implementation

[0023] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0024] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0025] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0026] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0027] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0028] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0029] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0030] In this disclosure, the meaning of “on the side away from” should be interpreted in the broadest sense, such that “on the side away from” means not only “directly on the side away from”, but also includes the meaning of “on the side away from” where there are intermediate features or layers.

[0031] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0032] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0033] The technical terms used in the embodiments of this application are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. When the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, this type of impurity semiconductor is also called a conductive semiconductor, for example, conductive silicon carbide material doped with nitrogen (N), boron (B), aluminum (Al), etc. Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this application, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0034] Unless otherwise defined, all technical terms used herein have the same meaning as those known to one of ordinary skill in the art. In this application, "at least one" means one or more, and "more than one" means two or more. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0035] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0036] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] like Figure 1 As shown, some embodiments of this disclosure provide an electronic device 1000. This electronic device 1000 can be applied to scenarios such as power grids, high-voltage photovoltaic systems, automobiles, and high-speed rail. The embodiments of this disclosure do not specifically limit the application scenarios of this electronic device.

[0038] The electronic device 1000 can be a power electronic device, that is, a device whose main functional components are power electronic devices (also known as power semiconductor devices). For example, the electronic device 1000 can be a converter, electronic switch, electronic AC power controller, power factor correction (PFC) circuit, etc. The converter includes, but is not limited to, a DC / DC converter (or DC-to-DC power supply) and a rectifier (AC / DC converter). DC-DC converters and inverters (DC / AC, or DC-DC converters) Electronic switches include, but are not limited to, power switching power supply circuits, etc. (such as AC converters).

[0039] Please continue reading. Figure 1 The electronic device 1000 includes a semiconductor device 100 and a circuit board 200. The semiconductor device 100 is disposed on and electrically connected to the circuit board 200. The circuit board 200 is used to provide the semiconductor device 100 with the required electrical signals. For example, the circuit board 200 may include multiple conductive layers. The multiple conductive layers within the circuit board 200 can be separated from each other by dielectric layers.

[0040] It is understood that the structure illustrated in the embodiments of this disclosure does not constitute a specific limitation on the electronic device 1000.

[0041] In other embodiments of this disclosure, the electronic device 1000 may include more components than those illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0042] In some embodiments, such as Figure 2 As shown, some embodiments of this disclosure also provide a semiconductor device 100. This semiconductor device can be applied in the aforementioned electronic device 1000. Optionally, the semiconductor device 100 provided in the embodiments of this disclosure can be used as a semiconductor device in the aforementioned electronic device 1000. Of course, the specific application scenarios of the aforementioned semiconductor device 100 are not limited thereto. It is understood that any electronic device that requires the use of the semiconductor device 100 falls within the application scenarios of the embodiments of this disclosure. Alternatively, the semiconductor device 100 provided in the embodiments of this disclosure can be used alone.

[0043] Please continue reading. Figure 2 The semiconductor device 100 includes a substrate 10, a first source contact 21, a channel 31, and a gate semiconductor portion 41. The first source contact 21, the channel 31, and the gate semiconductor portion 41 are disposed on the same side of the substrate 10. The substrate 10, the channel 31, and the first source contact 21 are electrically connected, and the gate semiconductor portion 41 is in contact with the channel 31. The substrate 10, the channel 31, and the first source contact 21 have the same doping type, while the gate semiconductor portion 41 has the opposite doping type to the channel 31.

[0044] For example, the material of substrate 10 includes a wide bandgap semiconductor material, such as silicon carbide, gallium nitride, and diamond. For instance, the material of substrate 10 is silicon carbide.

[0045] It is understood that the substrate 10, the channel portion 31, and the first source contact portion 21 may include a first type of doped ions, and the gate semiconductor portion 41 may include a second type of doped ions. For example, the first type of doped ions are N-type ions, such as phosphorus ions or nitrogen ions. The second type of doped ions are P-type ions, such as aluminum ions. Alternatively, the first type of doped ions are P-type ions, and the second type of doped ions are N-type ions. The following illustrative description uses the example of N-type doping of the substrate 10, the channel portion 31, and the first source contact portion 21, and P-type doping of the gate semiconductor portion 41, to illustrate some embodiments of this disclosure, but this disclosure is not limited thereto.

[0046] Based on the above, the gate semiconductor portion 41 can control the conduction and cutoff of the channel portion 31 to realize the control of the on / off state of the semiconductor device 100. When the semiconductor device 100 is in the conducting state, electrons flow from the first source contact portion 21 through the channel portion 31 and then to the substrate 10, thereby forming a current flowing from the substrate 10 to the first source contact portion 21.

[0047] However, in related technologies, a channel is formed by high-energy ion implantation into an epitaxial layer grown on a substrate. Then, a gate semiconductor is formed by lower-energy ion implantation into the same epitaxial layer. During this process, the portion of the epitaxial layer used to form the gate semiconductor undergoes multiple ion implantations, resulting in lattice damage to that portion of the epitaxial layer. Furthermore, after the gate semiconductor is formed, ion implantation near the channel exhibits tailing, making it difficult to control the doping concentration in the channel, reducing the electron mobility of the channel, and consequently leading to poor threshold voltage consistency and decreased stability of the semiconductor device.

[0048] Based on this, such as Figure 2 As shown, the semiconductor device 100 provided in this disclosure further includes a first semiconductor layer 20, a second semiconductor layer 30, and a third semiconductor layer 40. The first semiconductor layer 20 is disposed on one side of the substrate 10, the second semiconductor layer 30 is disposed on the side of the first semiconductor layer 20 away from the substrate 10, and the third semiconductor layer 40 is disposed on the side of the second semiconductor layer 30 away from the substrate 10.

[0049] The first semiconductor layer 20 includes a first doped portion 22 and a second doped portion 23. The second doped portion 23 is embedded in the surface of the first doped portion 22 away from the substrate 10, and the doping types of the first doped portion 22 and the second doped portion 23 are opposite. The second semiconductor layer 30 includes a channel portion 31, which contacts the second doped portion 23 and the first doped portion 22 of the first semiconductor layer 20. The channel portion 31 has the same doping type as the first doped portion 22. The third semiconductor layer 40 includes a gate semiconductor portion 41, which contacts the channel portion 31 of the second semiconductor layer 30.

[0050] It should be noted that the first semiconductor layer 20, the second semiconductor layer 30, and the third semiconductor layer 40 are each formed through a single epitaxial growth. Specifically, during the fabrication of the semiconductor device 100, the first semiconductor layer 20 epitaxially grown on the substrate 10 is subjected to N-type ion implantation to form a first doped portion 22. Then, the first semiconductor layer 20 is subjected to P-type ion implantation to form a second doped portion 23. Next, the second semiconductor layer 30 is epitaxially grown on the first semiconductor layer 20, and the second semiconductor layer 30 is subjected to N-type ion implantation to form a channel portion 31. Finally, the third semiconductor layer 40 is epitaxially grown on the second semiconductor layer 30, and the third semiconductor layer 40 is subjected to P-type ion implantation to form a gate semiconductor portion 41.

[0051] In this configuration, the second semiconductor layer 30 used to form the channel portion 31 undergoes only one ion implantation, reducing the risk of lattice damage to the second semiconductor layer 30 and making it easier to control the doping concentration of the channel portion 31. Furthermore, the third semiconductor layer 40 used to form the gate semiconductor portion 41 undergoes only one ion implantation, reducing the risk of doping tailing on the side of the gate semiconductor portion 41 near the channel portion 31, improving the electron mobility of the channel portion 31, and thereby improving the threshold voltage uniformity and stability of the semiconductor device 100.

[0052] It is understood that the channel portion 31 and the first doped portion 22 have the same doping type; for example, both the channel portion 31 and the first doped portion 22 contain N-type ions. In this case, electrons flow through the channel portion 31 and the first doped portion 22 towards the substrate 10, thereby forming a current. The first doped portion 22 is treated with light N-type doping (also called N-doping) to guide the electrons in the channel portion 31 towards the substrate 10, reducing electron scattering.

[0053] For example, such as Figure 2 As shown, the second doped portion 23 is embedded in the surface of the first doped portion 22 away from the substrate 10, the first doped portion 22 surrounds the second doped portion 23, and the channel portion 31 contacts the second doped portion 23 and the first doped portion 22 so that electrons can flow through the channel portion 31 through the first doped portion 22 and flow to the substrate 10, thereby forming a current.

[0054] It should be noted that when the second doped portion 23 is embedded in the surface of the first doped portion 22 away from the substrate 10, it means that the second doped portion 23 is completely embedded in the surface of the first doped portion 22 away from the substrate 10, that is, the surface of the second doped portion 23 away from the substrate 10 is flush with the surface of the first doped portion 22 away from the substrate 10. The understanding of "embedded" in the following text is also the same, and will not be repeated here.

[0055] In some embodiments, such as Figure 2As shown, the first semiconductor layer 20 further includes a first source contact portion 21, which is at least partially embedded in the surface of the second doped portion 23 away from the substrate 10, and is electrically connected to the channel portion 31. When the semiconductor device 100 is turned on, electrons from the first source contact portion 21 flow through the channel portion 31 to the first doped portion 22, and then to the substrate 10, thereby forming a current.

[0056] It should be noted that the partial embedding of the first source contact 21 into the surface of the second doped portion 23 away from the substrate 10 means that a portion of the first source contact 21 is embedded into the surface of the second doped portion 23 away from the substrate 10, i.e., the distance between the surface of the first source contact 21 away from the substrate 10 and the substrate 10 is greater than the distance between the surface of the second doped portion 23 away from the substrate 10 and the substrate 10. The interpretation of "partial embedding" in the following text will also be similar and will not be elaborated further.

[0057] In some examples, such as Figure 2 and Figure 4 As shown, the channel portion 31 has an opening, and the first source contact portion 21 is embedded in the surface of the second doped portion 23 away from the substrate 10 and located within the opening. In other examples, such as Figure 6 As shown, the first source contact 21 penetrates the channel 31 and is partially embedded in the surface of the second doped portion 23 away from the substrate 10.

[0058] Please continue reading. Figure 2 The first semiconductor layer 20 also includes an ohmic contact portion 24, which includes a first ohmic contact sub-portion 241 and a second ohmic contact sub-portion 242 connected to each other. The first ohmic contact sub-portion 241 is embedded in the surface of the first source contact portion 21 away from the substrate 10, and the second ohmic contact sub-portion 242 is embedded in the surface of the second doped portion 23 away from the substrate 10 and contacts the channel portion 31.

[0059] Based on this, the first ohmic contact portion 241 contacts the first source contact portion 21, and can be used to connect the source electrode and the first source contact portion 21 with an ohmic contact, thereby reducing the contact resistance. The second ohmic contact portion 242, through the first ohmic contact portion 241, achieves an ohmic contact between the first source contact portion 21 and the channel portion 31, so that when the semiconductor device 100 is turned on, electrons in the first source contact portion 21 can flow to the channel portion 31.

[0060] Furthermore, the second ohmic contact portion 242 also contacts the second doped portion 23, enabling the first source contact portion 21 and the second doped portion 23 to achieve ohmic contact. At this time, the potential of the second doped portion 23 is clamped by the first source contact portion 21, and the second doped portion 23 can act as a "shielding wall" to reduce the gate-drain capacitance (CGD) of the semiconductor device 100, thereby improving the switching response speed of the semiconductor device 100, reducing power consumption, and enabling the device to achieve discrete direct drive applications.

[0061] Furthermore, the ohmic contact 24 simultaneously achieves ohmic contact between the first source contact 21 and the channel 31, and ohmic contact between the first source contact 21 and the second doped portion 23, saving the area of ​​the active region of the semiconductor device 100, thereby reducing the specific on-resistance of the semiconductor device 100, thereby improving the switching response speed of the semiconductor device 100 and reducing power consumption.

[0062] It is understandable that the specific on-resistance of semiconductor device 100 is affected by factors including the total resistance when the device is turned on and the area of ​​the active region of the device. The smaller the area of ​​the active region, the smaller the specific on-resistance.

[0063] For example, such as Figure 2 and Figure 4 As shown, the second ohmic contact portion 242 is disposed around the first ohmic contact portion 241. After the ohmic contact portion 24 is fabricated, the first ohmic contact portion 241 is embedded in the surface of the first ohmic contact portion 241 away from the substrate 10, and the second ohmic contact portion 242 extends along the surface of the second doped portion 23 away from the substrate 10 in a direction away from the first ohmic contact portion 241. For example, the material of the ohmic contact portion 24 includes nickel silicide. The method for fabricating the ohmic contact portion 24 is described in the following fabrication method and will not be repeated here.

[0064] In some embodiments, such as Figure 3 and Figure 5 As shown, multiple first source contacts 21 are spaced apart, and a portion of the second ohmic contact portion 242 is located between two adjacent first source contacts 21. In this case, two adjacent first source contacts 21 expose a portion of the second doped portion 23, and a portion of the second ohmic contact portion 242 contacts the exposed second doped portion 23, increasing the area for ohmic contact between the first source contacts 21 and the second doped portion 23, thereby further reducing the CGD of the semiconductor device 100.

[0065] For example, such as Figure 3 and Figure 5As shown, the orthographic projection of an ohmic contact 24 on the substrate 10 covers multiple first source contacts 21 to maximize the area of ​​ohmic contact between the first source contacts 21 and the second doped portion 23. Furthermore, the ohmic contact 24 can be formed through a single deposition and annealing process, thereby improving production efficiency.

[0066] In some embodiments, such as Figure 6 As shown, the first source contact 21 includes an integrally formed first source contact sub-part 211 and a second source contact sub-part 212. The first source contact sub-part 211 is embedded in the surface of the second doped part 23 away from the substrate 10, and the second source contact sub-part 212 is embedded in and penetrates the channel part 31, and is in contact with the channel part 31. In other words, the first source contact 21 penetrates the channel part 31 and is partially embedded in the second doped part 23. At this time, the first source contact 21 and the second doped part 23 form a PN junction. When the semiconductor device 100 is forward-biased, the holes in the first source contact 21 are drawn away through the source electrode on the first source contact 21 by diffusion and recombination current, thereby reducing the risk of device breakdown caused by hole accumulation and improving the device breakdown voltage. When the semiconductor device 100 is reverse biased, the potential of the second doped part 23 is clamped by the first source contact part 21. The second doped part 23 can act as a "shielding wall" to reduce the CGD of the semiconductor device 100, thereby improving the switching response speed of the device and reducing power consumption.

[0067] Furthermore, the second doped portion 23 contacts the first source contact portion 21, allowing the second doped portion 23 to achieve the aforementioned function without needing to be connected to the source electrode. This means that while improving the device's breakdown voltage and reducing its CGD (Gas-Coefficient of Performance), it also saves area in the active region of the semiconductor device 100, thereby reducing the device's specific on-resistance, improving its switching response speed, and reducing power consumption.

[0068] In some embodiments, such as Figure 7 and Figure 8 As shown, the second semiconductor layer 30 further includes a second source contact 32, which is embedded in the surface of the channel 31 away from the substrate 10. The semiconductor device 100 also includes a gate connection structure 50, which extends through the channel 31 and contacts the gate semiconductor portion 41 and the second doped portion 23. The gate connection structure 50 is used to connect the gate semiconductor portion 41 and the second doped portion 23. In this case, the gate semiconductor portion 41 can be an upper gate semiconductor portion, and the second doped portion 23 can be a lower gate semiconductor portion.

[0069] For example, the gate connection structure 50 may have the same doping type as the gate semiconductor portion 41 and the second doped portion 23. For instance, the gate connection structure 50 may include P-type ions. The gate connection structure 50 may be processed by heavy P-type doping (also known as P+ doping) to reduce the contact resistance between the gate semiconductor portion 41 and the second doped portion 23. Furthermore, the surface of the gate connection structure 50 away from the substrate 10 may be sufficiently heavily doped with P-type ions to form a good ohmic contact with the gate electrode.

[0070] In some embodiments, such as Figure 10 As shown, the channel portion 31 includes a first channel sub-port 311 and a second channel sub-port 312, with the first channel sub-port 311 surrounding the second channel sub-port 312. A second source contact portion 32 is disposed on the side of the second channel sub-port 312 away from the substrate 10. The doping concentration of the second channel sub-port 312 is lower than the doping concentration of the first channel sub-port 311. In this case, the second channel sub-port 312 can separate the second source contact portion 32 and the second doped portion 23, thereby increasing the breakdown voltage between the gate and source of the semiconductor device 100, improving the short-circuit characteristics of the device, and enhancing the reliability of the device.

[0071] For example, the processing of the second channel sub-section 312 may include light doping or intrinsic doping. For instance, the second channel sub-section 312 is formed by N-light doping.

[0072] In some embodiments, such as Figure 11 As shown, the channel portion 31 includes a third channel sub-portion 313 and a fourth channel sub-portion 314, with the fourth channel sub-portion 314 located on the side of the third channel sub-portion 313 away from the substrate 10. A second source contact portion 32 is embedded in and extends through the fourth channel sub-portion 314. The orthographic projection of the second source contact portion 32 onto the substrate 10 does not overlap with the orthographic projection of the gate semiconductor portion 41 onto the substrate 10. The doping concentration of the fourth channel sub-portion 314 is lower than that of the third channel sub-portion 313. In this case, the fourth channel sub-portion 314 surrounds the second source contact portion 32, effectively separating the second source contact portion 32 from the gate semiconductor portion 41, thereby increasing the breakdown voltage between the gate and source of the semiconductor device 100, improving the short-circuit characteristics of the device, and enhancing the device reliability.

[0073] For example, the processing of the fourth channel sub-section 314 includes light doping. For instance, the doping concentration of the fourth channel sub-section 314 is two orders of magnitude lower than the doping concentration of the third channel sub-section 313.

[0074] In some embodiments, such as Figure 12As shown, the gate connection structure 50 includes a first gate connection structure 51 and a second gate connection structure 52 connected to each other. The first gate connection structure 51 is disposed on the side of the second gate connection structure 52 away from the substrate 10. The first gate connection structure 51 penetrates the channel portion 31 and the second doped portion 23, and the second gate connection structure 52 is embedded in the first doped portion 22. A protrusion R1 is provided at the end of the second gate connection structure 52 near the substrate 10. In a first cross-section, the two sides forming the protrusion R1 are straight lines. The first cross-section is perpendicular to the substrate.

[0075] Understandably, in the first cross-section, the sides of two straight lines extend and intersect to form a protrusion R1. In this case, the protrusion R1 is a sharp angle. For example, in the first cross-section, the protrusion R1 is any one of an acute angle, a right angle, or an obtuse angle. In this situation, the protrusion R1 can share the electric field at the corner R2 of the second doped portion 23, thereby reducing the highest effective electric field inside the semiconductor device 100 and improving the device's reverse voltage tolerance.

[0076] In some examples, such as Figure 12 As shown, the gate connection structure 50 can be formed through multiple ion implantations of different energies, so that one end of the gate connection structure 50 near the substrate 10 penetrates the second doped portion 23 and is partially embedded in the first doped portion 22. Furthermore, the tip R1 of the gate connection structure 50 is located within the internal electric field of the device, thereby sharing the internal electric field and improving the reverse voltage withstand capability of the device. For example, the tip R1 is a right-angled region of the gate connection structure 50. Alternatively, the tip R1 can be an acute or obtuse angle obtained through process control.

[0077] In some embodiments, such as Figure 2 As shown, the channel portion 31 has a boss 315, and the gate semiconductor portion 41 is disposed on the boss 315. That is, the thickness of the channel portion 31 at the location where the gate semiconductor portion 41 does not contact the channel portion 31 is thinner than the thickness at the location where the gate semiconductor portion 41 contacts the channel portion 31. Based on this, when the control semiconductor device 100 is turned off, a reverse voltage is applied to the gate semiconductor portion 41, causing the depletion region to expand, thereby clamping off the channel portion 31. At this time, during the process of the channel portion 31 being clamped off, the depletion region can expand into the channel portion 31 simultaneously from multiple directions toward the sidewalls and the top. Since the edge region of the channel portion 31 is thinner, the depletion region is more likely to clamp off the channel portion 31, thereby improving the turn-off reliability of the semiconductor device 100.

[0078] For example, during the formation of the gate semiconductor portion 41, a boss 315 can be formed by over-etching the channel portion 31, and the thickness of the boss 315 is the depth of the over-etching. The thickness of the boss 315 can be 1 / 10 to 1 / 5 of the thickness of the channel portion 31. For example, the thickness of the boss 315 can be any one of 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 6, and 1 / 5 of the thickness of the channel portion 31.

[0079] Please continue reading. Figure 2 , Figure 8 and Figure 9 The semiconductor device 100 also includes a source electrode 60, a gate electrode 70, and a drain electrode. The source electrode 60 is in ohmic contact with a first source contact 21 or a second source contact 32, the gate electrode 70 is in ohmic contact with a gate semiconductor portion 41, and the drain electrode is in ohmic contact with a substrate 10, so as to realize the transmission of current and control signals.

[0080] For example, the source electrode 60 and the gate electrode 70 are made of the same material. The material of either the source electrode 60 or the gate electrode 70 includes, but is not limited to, metals such as titanium, aluminum, gold, silver, and copper, and their alloys, or conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide. The material of the drain electrode includes, but is not limited to, metals such as nickel, aluminum, titanium, and tungsten, and their alloys.

[0081] In some examples, such as Figure 2 and Figure 9 As shown, the source electrode 60 and the first source contact portion 21 achieve ohmic contact through the ohmic contact portion 24. The gate electrode 70 has ohmic contact with the gate semiconductor portion 41, and the drain electrode has ohmic contact with the substrate 10 to achieve current transmission and control signal transmission. Ohmic contact layers may be provided between the gate electrode 70 and the gate semiconductor portion 41, and between the drain electrode and the substrate 10. The material of the ohmic contact layer may be the same as the material of the ohmic contact portion 24.

[0082] In other examples, such as Figure 8 and Figure 9 As shown, the source electrode 60 has an ohmic contact with the first source contact portion 21, the gate electrode 70 has an ohmic contact with the gate semiconductor portion 41, and the drain electrode has an ohmic contact with the substrate 10 to transmit current and control signals. Ohmic contact layers may be provided between the source electrode 60 and the first source contact portion 21, between the gate electrode 70 and the gate semiconductor portion 41, and between the drain electrode and the substrate 10. The material of the ohmic contact layer may include nickel silicide.

[0083] In some embodiments, the semiconductor device 100 may further include a buffer layer disposed between the substrate 10 and the first semiconductor layer 20 to transition the abrupt ion concentration gradient between the substrate 10 and the first doped portion 22, so that the electric field decreases gradually from the substrate 10 to the first doped portion 22, thereby preventing the electric field peak at the interface between the substrate 10 and the first doped portion 22 from exceeding the breakdown threshold of the material, thereby improving the withstand voltage of the semiconductor device 100.

[0084] like Figure 13 As shown, some embodiments of this disclosure also provide a method for fabricating a semiconductor, such as for fabricating the semiconductor device 100 in the above embodiments. This fabrication method includes steps S100-S300.

[0085] S100: A first semiconductor layer 20 is formed on the substrate 10.

[0086] In the above steps, such as Figure 14 As shown, the first semiconductor layer 20 includes a first doped portion 22 and a second doped portion 23. The second doped portion 23 is embedded in the surface of the first doped portion 22 away from the substrate 10. The doping types of the first doped portion 22 and the second doped portion 23 are opposite.

[0087] Specifically, S100 may include: providing an N+ doped substrate 10; obtaining a first epitaxial layer on the substrate 10 using epitaxial growth technology; performing N- doping on the first epitaxial layer to form a first doped portion 22; forming a hard mask layer 101 on the surface of the first doped portion 22, the hard mask layer 101 having an opening that exposes a portion of the first doped portion 22; performing P-type ion implantation on this portion of the first doped portion 22 to form a second doped portion 23; and removing the hard mask layer 101.

[0088] For example, the substrate 10 and the first semiconductor layer 20 are made of the same material. For instance, the materials of the substrate 10 and the first semiconductor layer 20 include silicon carbide.

[0089] As can be understood, epitaxial growth technology is a technique for growing one or more single-crystal thin films on a substrate along the substrate's crystal orientation, with the films matching the substrate's crystal lattice. Epitaxial growth technology can include chemical vapor deposition (CVD).

[0090] S200: A second semiconductor layer 30 is formed on the side of the first semiconductor layer 20 away from the substrate 10.

[0091] In the above steps, such as Figure 14 As shown, the second semiconductor layer 30 includes a channel portion 31, which is in contact with the second doped portion 23 and the first doped portion 22. The channel portion 31 and the first doped portion 22 have the same doping type.

[0092] S200 may specifically include: depositing a second epitaxial layer on the first semiconductor layer 20, and performing N-type ion doping on the second epitaxial layer to form a channel portion 31.

[0093] For example, the thickness of the N-type ion doping is 0.3 μm-0.4 μm, and the doping concentration is 5×10¹⁶ / cm³-2×10¹⁷ / cm³.

[0094] S300: A third semiconductor layer 40 is formed on the side of the second semiconductor layer 30 away from the substrate 10.

[0095] In the above steps, such as Figure 14 As shown, the third semiconductor layer 40 includes a gate semiconductor portion 41, which is in contact with the channel portion 31, and the doping types of the gate semiconductor portion 41 and the channel portion 31 are opposite.

[0096] Specifically, S300 may include: depositing a third epitaxial layer on the second semiconductor layer 30, and p-type doping the third epitaxial layer. A hard mask layer is formed on the surface of the third epitaxial layer, the hard mask layer having an opening that exposes a portion of the third epitaxial layer. This portion of the third epitaxial layer is etched to form a gate semiconductor portion 41.

[0097] For example, the thickness of the P-type ion doping is 0.1 μm-0.2 μm, and the doping concentration is 1×1020 / cm3-2×1020 / cm3.

[0098] In some embodiments, after S300, the preparation method further includes S410-S420. S410: The channel portion 31 is etched to form an opening, exposing a portion of the second doped portion 23. This portion of the second doped portion 23 is then ion-doped to form a first source contact portion 21.

[0099] In the above steps, such as Figure 15 As shown, the first source contact 21 is embedded in the surface of the second doped portion 23 away from the substrate 10.

[0100] Specifically, S410 may include: etching the channel portion 31 to form an opening, exposing a portion of the second doped portion 23. This portion of the second doped portion 23 is then N+ doped to form a first source contact portion 21.

[0101] S420: A metal thin film is deposited on the first source contact 21 and then annealed at high temperature to form an ohmic contact 24.

[0102] In the above steps, such as Figure 15As shown, the ohmic contact portion 24 includes a first ohmic contact portion 241 and a second ohmic contact portion 242 connected to each other. The first ohmic contact portion 241 is embedded in the surface of the first source contact portion 21 away from the substrate 10, and the second ohmic contact portion 242 is embedded in the surface of the second doped portion 23 away from the substrate 10 and is in contact with the channel portion 31.

[0103] Specifically, S420 may include: depositing a metal thin film, such as a nickel thin film, on the sidewalls of the first source contact 21 and the channel 31, and annealing it at high temperature to form a first ohmic contact portion 241 embedded in the first source contact 21 and a second ohmic contact portion 242 embedded in the second doped portion 23.

[0104] For example, in S410, N+ doping is performed in a selected area within the opening to form a plurality of first source contacts 21. In S420, a metal thin film is deposited on the sidewalls of the first semiconductor layer 20 and the channel portion 31 located within the opening, and after high-temperature annealing, a first ohmic contact portion 241 embedded in the first source contact portion 21 and a second ohmic contact portion 242 embedded in the second doped portion 23 are formed. A portion of the second ohmic contact portion 242 is located between two adjacent first source contacts 21.

[0105] In some other embodiments, the preparation method further includes S510 after S300. S510: Ion doping is performed on the channel portion 31 to form the first source contact portion 21.

[0106] In the above steps, such as Figure 16 As shown, the first source contact portion 21 includes an integrally formed first source contact sub-portion 211 and a second source contact sub-portion 212. The first source contact sub-portion 211 is embedded in the surface of the second doped portion 23 away from the substrate 10, and the second source contact sub-portion 212 is embedded in and penetrates the channel portion 31 and is in contact with the channel portion 31.

[0107] Specifically, S510 may include: forming a hard mask layer on the surface of the channel portion 31, the hard mask layer having an opening that exposes a portion of the channel portion 31; and performing N-type ion doping on this portion of the channel portion 31 to form a first source contact portion 21.

[0108] For example, the concentration of N-type ion doping is greater than 1×10¹⁹ / cm³, and the doped ion can be at least one of phosphorus ions and nitrogen ions.

[0109] In some other embodiments, after S300, the preparation method further includes S610-S620. S610: Ion doping is performed on the channel portion 31 to form the second source contact portion 32.

[0110] In the above steps, such as Figure 17 As shown, the second source contact 32 is embedded in the channel 31 away from the surface of the substrate 10.

[0111] Specifically, S610 may include: forming a hard mask layer on the surface of the channel portion 31, the hard mask layer having an opening that exposes a portion of the channel portion 31; and performing N-type ion doping on this portion of the channel portion 31 to form a first source contact portion 21.

[0112] For example, the concentration of N-type ion doping is greater than 1×10¹⁹ / cm³, and the doped ion can be at least one of phosphorus ions and nitrogen ions.

[0113] S620: Ion doping is performed on the gate semiconductor section 41 to form a gate connection structure 50.

[0114] In the above steps, such as Figure 18 As shown, the gate connection structure 50 extends through the channel portion 31 and contacts the gate semiconductor portion 41 and the second doped portion 23.

[0115] Specifically, S620 may include: forming a hard mask layer on the surface of the gate semiconductor portion 41, the hard mask layer having an opening that exposes a portion of the gate semiconductor portion 41; and performing P-type ion doping on this portion of the gate semiconductor portion 41 to form a gate connection structure 50. The doping concentration at the surface of the gate connection structure 50 is greater than 1 × 10¹⁹ / cm³ to ensure good ohmic contact. The doping concentration in the region between the gate semiconductor portion 41 and the second doped portion 23 is greater than 1 × 10¹⁸ / cm³ to compensate for the N-type doping of the channel portion 31.

[0116] For example, a hard mask layer is formed on the surface of the gate connection structure 50. The hard mask layer has an opening that exposes a portion of the gate connection structure 50. This portion of the gate connection structure 50 is then p-type ion doped to form a partial gate connection structure 50 with an embedded first doped portion 22. The energy of this ion doping is higher than the energy of the ion doping used when forming the gate connection structure 50.

[0117] In some embodiments, S200 includes S210. S210: Forming the first channel subsection 311 and the second channel subsection 312.

[0118] In the above steps, such as Figure 19 As shown, the channel portion 31 includes a first channel sub-portion 311 and a second channel sub-portion 312, with the first channel sub-portion 311 surrounding the second channel sub-portion 312. The second source contact portion 32 is embedded in the surface of the second channel sub-portion 312 away from the substrate 10, and the doping concentration of the second channel sub-portion 312 is less than the doping concentration of the first channel sub-portion 311.

[0119] S210 may specifically include: depositing a second epitaxial layer on the first semiconductor layer 20, and performing N-type ion doping on the second epitaxial layer twice to form a first channel sub-section 311 and a second channel sub-section 312. The ion doping concentration for forming the second channel sub-section 312 is less than the ion doping concentration for forming the first channel sub-section 311.

[0120] In other embodiments, S200 includes S220. S220: Forms the third channel subsection 313 and the fourth channel subsection 314.

[0121] In the above steps, such as Figure 20 As shown, the channel portion 31 includes a third channel sub-portion 313 and a fourth channel sub-portion 314, with the fourth channel sub-portion 314 located on the side of the third channel sub-portion 313 away from the substrate 10. A second source contact portion 32 is embedded in and extends through the fourth channel sub-portion 314. The orthographic projection of the second source contact portion 32 onto the substrate 10 does not overlap with the orthographic projection of the gate semiconductor portion 41 onto the substrate 10. The doping concentration of the fourth channel sub-portion 314 is lower than that of the third channel sub-portion 313.

[0122] Specifically, S220 may include: depositing a second epitaxial layer on the first semiconductor layer 20, and performing N-type ion doping on the second epitaxial layer twice to form a third channel sub-section 313 and a fourth channel sub-section 314. The ion doping concentration for forming the fourth channel sub-section 314 is lower than the ion doping concentration for forming the third channel sub-section 313.

[0123] In some embodiments, after S510 or S620, the preparation method further includes S710. S710: Forms the source electrode 60 and the gate electrode 70.

[0124] In the above steps, such as Figure 21 and Figure 22 As shown, the source electrode 60 is in ohmic contact with the first source contact portion 21 or the second source contact portion 32, the gate electrode 70 is in ohmic contact with the gate semiconductor portion 41, and the drain electrode is in ohmic contact with the substrate 10.

[0125] Specifically, S710 may include: forming a passivation layer on the first source contact 21 or the second source contact 32, etching an opening in the passivation layer to expose a portion of the first source contact 21 or the second source contact 32; depositing metal within the opening to form a source electrode 60.

[0126] A passivation layer is formed on the gate semiconductor portion 41, and an opening is etched into the passivation layer to expose a portion of the gate semiconductor portion 41. Metal is deposited within the opening to form a gate electrode 70.

[0127] For example, the source electrode 60 and the gate electrode 70 are made of the same material. The material of either the source electrode 60 or the gate electrode 70 includes, but is not limited to, metals such as titanium, aluminum, gold, silver, and copper, and their alloys, or conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide.

[0128] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first semiconductor layer is disposed on one side of a substrate; the first semiconductor layer includes a first doped portion and a second doped portion, the second doped portion being embedded in the surface of the first doped portion away from the substrate; the first doped portion and the second doped portion have opposite doping types; A second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate; the second semiconductor layer includes a channel portion; the channel portion is in contact with a second doped portion and a first doped portion of the first semiconductor layer; the channel portion and the first doped portion have the same doping type; A third semiconductor layer is disposed on the side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a gate semiconductor portion; the gate semiconductor portion is in contact with a channel portion of the second semiconductor layer; the doping type of the gate semiconductor portion is opposite to that of the channel portion.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor layer further includes a first source contact portion, which is at least partially embedded in the surface of the second doped portion away from the substrate, and the first source contact portion is electrically connected to the channel portion.

3. The semiconductor device according to claim 2, characterized in that, The first source contact is embedded in the surface of the second doped portion away from the substrate; the first semiconductor layer further includes: The ohmic contact portion includes a first ohmic contact portion and a second ohmic contact portion connected together; the first ohmic contact portion is embedded in the surface of the first source contact portion away from the substrate; the second ohmic contact portion is embedded in the surface of the second doped portion away from the substrate and contacts the channel portion.

4. The semiconductor device according to claim 3, characterized in that, Multiple first source electrode contacts are spaced apart; a portion of the second ohmic contact portion is located between two adjacent first source electrode contacts.

5. The semiconductor device according to claim 4, characterized in that, The orthographic projection of one of the ohmic contacts onto the substrate covers the plurality of first source contacts.

6. The semiconductor device according to claim 2, characterized in that, The first source contact portion includes an integrally formed first source contact sub-portion and a second source contact sub-portion. The first source contact sub-portion is embedded in the surface of the second doped portion away from the substrate. The second source contact sub-portion is embedded in and penetrates the channel portion and is in contact with the channel portion.

7. The semiconductor device according to claim 1, characterized in that, The second semiconductor layer further includes a second source contact portion embedded in the surface of the channel portion away from the substrate; the semiconductor device further includes a gate connection structure extending through the channel portion and contacting the gate semiconductor portion and the second doped portion.

8. The semiconductor device according to claim 7, characterized in that, The channel portion includes a first channel sub-portion and a second channel sub-portion, the first channel sub-portion surrounding the second channel sub-portion; the second source contact portion is disposed on the side of the second channel sub-portion away from the substrate; the doping concentration of the second channel sub-portion is less than the doping concentration of the first channel sub-portion.

9. The semiconductor device according to claim 7, characterized in that, The channel portion includes a third channel sub-portion and a fourth channel sub-portion, the fourth channel sub-portion being located on the side of the third channel sub-portion away from the substrate; the second source contact portion is embedded in and penetrates the fourth channel sub-portion; the orthographic projection of the second source contact portion on the substrate does not overlap with the orthographic projection of the gate semiconductor portion on the substrate; the doping concentration of the fourth channel sub-portion is less than the doping concentration of the third channel sub-portion.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that, The gate connection structure includes a first gate connection structure and a second gate connection structure connected to each other; the first gate connection structure is disposed on the side of the second gate connection structure away from the substrate; the first gate connection structure passes through the channel portion and the second doped portion; the second gate connection structure is embedded in the first doped portion; The second gate connection structure has a protrusion at one end near the substrate; in the first cross section, the two sides forming the protrusion are straight lines; the first cross section is perpendicular to the substrate.

11. The semiconductor device according to claim 1, characterized in that, The channel portion is provided with a boss, and the gate semiconductor portion is disposed on the boss.

12. A method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in any one of claims 1 to 11, characterized in that, include: A first semiconductor layer is formed on a substrate; the first semiconductor layer includes a first doped portion and a second doped portion, the second doped portion being embedded in the surface of the first doped portion away from the substrate; the first doped portion and the second doped portion have opposite doping types; A second semiconductor layer is formed on the side of the first semiconductor layer away from the substrate; the second semiconductor layer includes a channel portion; the channel portion is in contact with a second doped portion and a first doped portion of the first semiconductor layer; the channel portion and the first doped portion have the same doping type; A third semiconductor layer is formed on the side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a gate semiconductor portion; the gate semiconductor portion is in contact with the channel portion of the second semiconductor layer; the doping type of the gate semiconductor portion is opposite to that of the channel portion.

13. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 11.

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