Super junction devices and methods for forming super junction devices

Abstract

A method for forming a super junction device and a super junction device are disclosed. The method includes forming a super junction region including a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type. Forming the super junction region includes forming a plurality of semiconductor layers over one another to form a layer stack, implanting first type dopant atoms in each semiconductor layer through openings of a first implantation mask to form first implanted regions, implanting second type dopant atoms in each semiconductor layer through openings of a second implantation mask to form second implanted regions, and performing an annealing process to diffuse and activate the implanted first type dopant atoms and the second type dopant atoms. Each of the first implantation mask and the second implantation mask has a pitch selected from between 3 micrometers and 5 micrometers, and each semiconductor layer has a thickness selected from between 1.9 micrometers and 3.5 micrometers.

Description

Technical Field

[0001] This disclosure generally relates to superjunction devices, and in particular to vertical superjunction transistor devices and methods for manufacturing the same. Background Technology

[0002] A superjunction transistor device includes multiple transistor cells and a superjunction region. The superjunction region has multiple first regions of a first doping type and multiple second regions of a second doping type complementary to the first doping type. The first regions may also be referred to as drift regions, and the second regions may also be referred to as compensation regions. The first regions (drift regions) are coupled to the drain node, and the second regions (compensation regions) are coupled to the source node of the transistor device.

[0003] A transistor device can operate in either an on or off state. In the on state, current can flow from the source node through the transistor cell and the first region of the superjunction region to the drain node. In the off state, the space charge region (depletion region) expands in the first and second regions of the superjunction region, causing the superjunction region to be depleted of charge, thus interrupting the current flow between the source and drain regions.

[0004] On-resistance is the resistance between the source and drain nodes of a transistor device when it is in the on-state. The on-resistance is primarily determined by the resistance of the first region within the superjunction region. On-resistance causes power loss in circuit applications involving transistor devices, such as power converters and motor drivers. This power loss is undesirable.

[0005] Therefore, there is a need for a superjunction device, especially a superjunction transistor device with reduced on-resistance. Summary of the Invention

[0006] One example relates to a method for forming a superjunction device. The method includes: forming a superjunction region comprising a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping types. Forming the superjunction region includes: forming a plurality of semiconductor layers, the plurality of semiconductor layers being positioned above each other to form a layer stack; implanting first-type dopant atoms into each of the semiconductor layers through an opening in a first implantation mask to form a first implantation region; implanting second-type dopant atoms into each of the semiconductor layers through an opening in a second implantation mask to form a second implantation region; and performing an annealing process to diffuse and activate the implanted first-type and second-type dopant atoms. Each of the first and second implantation masks has a spacing selected between 3 micrometers and 5 micrometers, and each of the semiconductor layers has a thickness selected between 1.9 micrometers and 3.5 micrometers.

[0007] Another example relates to a superjunction device. The superjunction device includes: a superjunction region comprising a plurality of first regions of a first doped type and a plurality of second regions of a second doped type complementary to the first doped types within a stack, the stack comprising a plurality of semiconductor layers formed on top of each other to form the stack. The spacing between the superjunction regions is selected between 3 micrometers and 5 micrometers, and each of the semiconductor layers has a thickness selected between 1.9 micrometers and 3.5 micrometers. Attached Figure Description

[0008] The examples are explained below with reference to the accompanying drawings. The drawings are intended to illustrate certain principles, showing only aspects necessary for understanding these principles. The drawings are not drawn to scale. In the drawings, the same reference numerals denote similar features.

[0009] Figure 1 A schematic vertical cross-sectional view of a superjunction transistor device including transistor cells and a superjunction region is shown.

[0010] Figure 2 A schematic diagram of a horizontal cross-sectional view of a superjunction region according to an example is shown;

[0011] Figure 3 An example of a method for forming a superjunction region is shown, which includes forming a plurality of semiconductor layers and implanting first-type dopant atoms and second-type dopant atoms into each semiconductor layer, the plurality of semiconductor layers being on top of each other;

[0012] Figures 4A-4B An example of a method for implanting a first type of dopant atom and a second type of dopant atom into one of a semiconductor layer is shown in detail;

[0013] Figure 5 This shows the process after forming another semiconductor layer. Figure 3 The layout shown;

[0014] Figures 6A to 6B Each shows the electric field in a pair of adjacent first and second regions of the superjunction region in the off state of the transistor device;

[0015] Figure 7 The doping distribution of a first region or a second region according to an example is shown;

[0016] Figure 8 The dependence of the specific on-resistance (Ron·A) of a transistor device on the spacing of the superjunction region is shown;

[0017] Figures 9A to 9B It shows Figures 4A to 4B Modification of the method shown;

[0018] Figure 10 An annealing process in an oxidizing environment during manufacturing is shown according to an example.

[0019] Figure 11 A-11C shows an example of the dopant dose introduced into each semiconductor layer depending on the position of the semiconductor layer in the stack of layers formed by the semiconductor layers;

[0020] Figure 12 A schematic diagram of a vertical cross-sectional view of several transistor cells according to an example is shown.

[0021] Figure 13 A schematic horizontal cross-sectional view of a transistor cell according to Figure 11 is shown; and

[0022] Figure 14-15 A top view of a transistor device according to different examples is shown. Detailed Implementation

[0023] In the following detailed description, reference is made to the accompanying drawings. The drawings form part of the specification and, for illustrative purposes, illustrate examples of how the invention can be used and implemented. It should be understood that, unless otherwise specifically stated, features of the various embodiments described herein can be combined with each other.

[0024] Figure 1 A superjunction transistor device according to an example is schematically shown. More specifically, Figure 1 A schematic vertical cross-sectional view of a portion of a transistor device is shown. The transistor device includes a semiconductor body 100 having a first surface 101 and a second surface 102 opposite to the first surface. Figure 1 A vertical cross-sectional view of the semiconductor body 100 in a vertical cross-sectional plane substantially orthogonal to the first surface 101 and the second surface 102 is shown.

[0025] According to one example, the semiconductor body 100 includes a single-crystal semiconductor material. For example, the single-crystal semiconductor material is silicon (Si) or silicon carbide (SiC).

[0026] The semiconductor body 100 also includes a first lateral direction x and a second lateral direction y, the second lateral direction y being substantially orthogonal to the first lateral direction x. The first and second lateral directions are substantially parallel to the first surface 101 and the second surface 102 and orthogonal to the vertical direction z. Regarding the first lateral direction x, it should be noted that, unless otherwise stated, "first lateral direction x" includes the direction indicated by the arrow marked with x in the figure and its opposite direction. The same applies to the second lateral direction y and the vertical direction z, the second lateral direction y including the direction indicated by the arrow marked with y in the figure and its opposite direction, and the vertical direction z including the direction indicated by the arrow marked with z in the figure and its opposite direction.

[0027] refer to Figure 1 The superjunction transistor device includes a superjunction region 1. The superjunction region 1 includes a first region 11 of a first doping type and a second region 12 of a second doping type complementary to the first doping type. The first region 11 and the second region 12 are arranged alternately in a first lateral direction x of the semiconductor body 100. The first region 11 of the superjunction region 1 may also be referred to as a drift region, and the second region 12 may also be referred to as a compensation region. It goes without saying that the doped region of the first doping type used herein is a doped region having an effective doping concentration of the first doping type, and the doped region of the second doping type used herein is a doped region having an effective doping concentration of the second doping type.

[0028] according to Figure 2 As shown in one example, the first region 11 and the second region 12 are elongated in the second lateral direction y. Figure 2 schematically shown Figure 1 A horizontal cross-sectional view of a transistor device of the type shown in a horizontal cross-sectional plane AA intersecting a superjunction region 1 having a first region 11 and a second region 12. As used herein, the elongated length comprising the first region 11 and the second region 12 is much greater than the corresponding width of the first region 11 and the second region 12. According to one example, the length is at least 50 times, at least 100 times, or at least 500 times the width. The length is the dimension of the first region 11 and the second region 12 in the second lateral direction y. The width is the dimension of the first region 11 and the second region 12 in the first lateral direction x. Furthermore, the first region 11 and the second region 12 are not necessarily continuous in the second lateral direction y, but each of the first region 11 and the second region 12 may include one or more elongated portions arranged spaced apart from each other in the second lateral direction y.

[0029] refer to Figure 1 The transistor device also includes a drain region 51 of a first doped type. The drain region 51 is disposed between the superjunction region 1 and the second surface 102 and may be adjacent to the second surface 102. The drain region 51 forms a drain node D or is connected to a drain node D of the transistor device.

[0030] Based on an example, such as Figure 1 As shown, the drain region 51 is spaced apart from the superjunction region 1 in the vertical z-direction. In this example, a buffer region 52 of a first doping type is arranged between the drain region 51 and the superjunction region 1. The doping concentration of the buffer region 52 is lower than that of the drain region 51, for example, by more than two orders of magnitude.

[0031] For example, the doping concentration of the drain region 51 is 5E18cm.-3 With 5E20cm - The doping concentration in buffer region 52 is within the range of 3, and the doping concentration is within 3E15cm. -3 With 3E16cm -3 Within the range between.

[0032] Drain region 51 and optional buffer region 52 couple (connect) the first region 11 of superjunction region 1 to the drain node D of the transistor device.

[0033] refer to Figure 1 The transistor device also includes transistor cells 4 that are at least partially integrated into the semiconductor body 100. "At least partially integrated" means that at least active device regions (such as source regions and body regions (explained further below)) are integrated into the semiconductor body 100. Each transistor cell 4 is coupled between at least one of the first regions 11 of the superjunction region 1 and the source node S of the transistor device. Furthermore, each transistor cell 4 is configured to control a conductive channel between the source node S and the corresponding first region 11. Figure 1 Transistor unit 4 is not shown in detail. Instead, in Figure 1 In the diagram, each transistor unit 2 is represented by a controllable electronic switch with a parallel diode, symbolizing the function of the transistor unit. A detailed example of transistor unit 4 is explained further below.

[0034] Figure 1 The transistor device shown can operate in either forward-biased mode (forward-biased state) or reverse-biased mode (reverse-biased state). Reverse-biased mode can also be referred to as diode mode of the transistor device. The transistor device is in reverse-biased mode when the polarity of the voltage applied between the drain node D and the source node S causes the diode in transistor cell 4 to be forward-biased; and in forward-biased mode when the polarity of the voltage applied between the drain node D and the source node S causes the diode in transistor cell 4 to be reverse-biased. In forward-biased mode, the transistor device can operate in either an on or off state. The transistor device is in an on state when a conductive channel exists in transistor cell 4 between the source node S and the first region 11 of the first superjunction region 1; and in a off state when the conductive channel is interrupted.

[0035] According to one example, the transistor device is a gate-controlled transistor device. In this example, the presence of a conductive channel in transistor cell 4 depends on the voltage applied between the gate node G and the source node S (gate-source voltage), such that the transistor device is in an on-state or off-state depending on the gate-source voltage.

[0036] The second region 12 of the superjunction region 1 is coupled to the source node S. This coupling between the second region 12 and the source node S occurs only when... Figure 1 The diagram is schematically shown. According to one example, the second region 12 is coupled to the source node S via transistor cell 4. An example of coupling the second region 12 to the source node S is further explained below. Furthermore, the first region 11 of the first superjunction region 1 is coupled to the drain region 51 and the drain node D. The first region 11 is coupled to the drain region 51 directly through an adjacent drain region 51 or via a buffer region 52.

[0037] When the transistor device is in the off state and a voltage is applied between the drain node D and the source node S, the charge region (depletion region) begins at the PN junction formed between adjacent first regions 11 and second regions 12 and extends into the first and second regions 12. This allows the first superjunction region 1 to essentially absorb the voltage applied between the drain node D and the source node S of the transistor device. This is the well-known operating principle of superjunction devices and therefore requires no further explanation.

[0038] According to one example, forming the first and second superjunction regions 1, 2 involves forming multiple semiconductor layers and implanting first-type and second-type dopant atoms into each semiconductor layer, the multiple semiconductor layers being on top of each other. According to one example, the semiconductor layers are epitaxial growth layers (epitaxy layers), making this type of process sometimes referred to as multi-epitaxy-multi-implantation (MEMI) process. Figure 3 A portion of the method for forming the first region 11 and the second region 12 using MEMI processes is shown.

[0039] Figure 3 A vertical cross-sectional view of a portion of a semiconductor body 100 is shown after a plurality of semiconductor layers 221 are formed on top of a carrier 210 and after first-type dopant atoms and second-type dopant atoms are implanted into each semiconductor layer 221. Before forming (growing) the next semiconductor layer 221, first-type and second-type dopant atoms included in a corresponding one of the semiconductor layers 221 are implanted into the semiconductor layer 221.

[0040] Semiconductor layers 221 formed on top of each other form a layer stack 220 on top of the carrier 210. The layer stack includes a lowermost semiconductor layer 2211 and an uppermost semiconductor layer 2221. N The bottom semiconductor layer 2211 is the first semiconductor layer 221 generated in the stack 220, and the top semiconductor layer 221... N It is the last semiconductor layer 221 produced in the manufacturing process of the stacked body 220. The bottommost semiconductor layer 2211 is produced directly on top of the carrier 210.

[0041] According to one example, the carrier 210 includes a semiconductor substrate 211 in which a drain region 51 is formed in the completed device, and an epitaxial layer 212 grown on top of the substrate 211 to form a buffer region 52 in the completed device. The epitaxial layer forming the buffer region can be doped in situ during the epitaxial growth process.

[0042] refer to Figure 3 First-type dopant atoms are implanted into each semiconductor layer 220 to form a first implantation region 11i, and second-type dopant atoms are implanted into each semiconductor layer 221 to form a second implantation region 12i. (See reference) Figure 3 The lateral positions of the first implantation regions 11i in the semiconductor layer 221 are selected such that the plurality of first implantation regions 11i form a plurality of groups, each group including one first implantation region 11i in each semiconductor layer 221, and the first implantation regions 11i in each group are arranged above each other in the vertical direction z. Similarly, the lateral positions of the second implantation regions 12i in the semiconductor layer 221 are selected such that the plurality of second implantation regions 12i form a plurality of groups, each group including one second implantation region 12i in each semiconductor layer 221, and the second implantation regions 12i in each group are arranged above each other in the vertical direction z.

[0043] According to one example, the first implantation region 11i and the second implantation region 12i formed in each semiconductor layer 221 do not overlap. According to one example, the first implantation region 11i and the second implantation region 12i formed in each semiconductor layer are spaced apart from each other in a first lateral direction x.

[0044] It should be noted that the above implantation process can occur at the wafer level. That is, implantation can be performed when multiple semiconductor bodies are part of a wafer that is ultimately diced to form individual semiconductor bodies.

[0045] In order to form the first region 11 and the second region 12 based on the first implantation region 11i and the second implantation region 12i, the method further includes a temperature process (annealing process) for diffusing and electrically activating the implanted first and second type dopants atoms.

[0046] Implanting first and second type dopant atoms into semiconductor layer 221 to form first implantation region 11i and second implantation region 12i may include adjusting the implantation energy in the implantation process such that the first and second type dopant atoms are implanted only into one of the second semiconductor layers 221, 222, i.e., the semiconductor layer 221 that was last produced before the respective implantation process. Figure 3It can be seen that the first implanted regions 11i formed above each other in the vertical direction z can be spaced apart, and the second implanted regions 12i formed above each other in the vertical direction z can also be spaced apart. In this case, in order to form continuous first regions 11 and continuous second regions 12 in the vertical direction z, it is desirable for the first and second types of dopant atoms implanted in the annealing process to diffuse in the vertical direction z. The temperature and duration of the annealing process are selected such that the desired vertical diffusion of the first and second types of dopant atoms is achieved.

[0047] It should be noted that the semiconductor substrate 100 with carrier 210 and the stacked layer 220 with semiconductor layers 221 are single-crystal semiconductor substrates 100. That is, the boundaries between carrier 210 and stacked layer 220, and between individual semiconductor layers 221 within stacked layer 220, are not visible. Figure 3 For illustrative purposes, only the boundaries between individual semiconductor layers 221 are shown.

[0048] Before forming the first implantation region 11i and the second implantation region 12i by implanting first and second types of dopant atoms, a semiconductor layer 221 can be generated (grown) to have a low base doping concentration. According to one example, the base doping concentration is below 1E14cm. -3 or below 1E13cm -3 And it can be as low as intrinsic.

[0049] Referring to the above, forming superjunction regions 1 and 2 involves implanting first and second type dopant atoms into each of a plurality of semiconductor layers 221 formed above each other. Figures 4A-4B An example of a method for implanting first and second type dopant atoms into one of semiconductor layers 221 is shown in the figure, each figure showing a vertical cross-sectional view of a semiconductor layer 221 during the implantation process.

[0050] Figure 4A The implantation of first-type dopant atoms into semiconductor layer 221 is illustrated. This includes implanting first-type dopant atoms into semiconductor layer 221 through openings in a first implantation mask 310 disposed above the surface of semiconductor layer 221. The openings 311 in the first implantation mask 310 are spaced apart from each other in a first lateral direction x. First-type dopant atoms are implanted into semiconductor layer 221 through openings 311 such that the openings 311 define the location and size of a first implantation region 11i in semiconductor layer 221.

[0051] Referring to the above, the first region 11 can be elongated in the second lateral direction y. In this example, the opening 311 in the first injection mask 310 is elongated in the second lateral direction y.

[0052] The amount of dopant atoms included in each first region 11i is crucial to the function of the superjunction transistor device. At a given implantation dose, the amount of dopant atoms included in each first implantation region 11i can be adjusted by appropriately selecting the width w11 of the opening 311. The width w11 is the dimension of the opening 311 in the first lateral direction x. Adjacent openings 311 are spaced apart from each other by a distance d11 in the first lateral direction x.

[0053] According to one example, the openings 311 in the first injection mask 310 have substantially the same width w 11, such that each first injection region 11i in the semiconductor layer 221 includes substantially the same amount of dopant atoms.

[0054] In the following text, Dz1 represents Figure 4A The implantation dose in the implantation process is shown. This implantation dose is referred to below as the first implantation dose Dz1. The first implantation dose Dz1 represents the amount of first-type dopant atoms pointing in the vertical direction z toward the first surface 101 of the semiconductor body 100.

[0055] The first injection dose Dz1 represents the total injection dose in the injection process. For example, if the injection process includes two or more injection steps using different injection energies (as explained further below), then the injection dose Dz1 represents the total injection dose in each injection step.

[0056] In the implantation process, the size of the opening 311 determines how many type-1 dopant atoms reach the first surface 101 and are introduced into the semiconductor body 100. Hereinafter, the implantation dose A... 11i Indicates in Figure 4A The process shown includes the amount of dopant atoms in the first implantation region 11i. Implantation dose A 11i The value is given by multiplying the first injection dose Dz1 by the width w11 of the opening 311 in the first injection mask 310. A 11i = Dz1∙w11 (1a). The dimension of the first injected dose Dz1 is, for example, per square centimeter (cm²). -2 The dopant atoms of ) make the implanted dose A 11i The dimension is dopant atoms per centimeter (cm²) -1 Therefore, the injected dose A 11i This represents the amount of dopant atoms per centimeter in the second lateral direction y within each first region 11i.

[0057] Figure 4BThe implantation of second-type dopant atoms into semiconductor layer 221 is illustrated. This includes forming a second implantation mask 320 on top of the surface of semiconductor layer 221. The second implantation mask 320 includes openings 321 spaced apart from each other in a first lateral direction x. First-type dopant atoms are implanted into semiconductor layer 221 through openings 321, such that openings 321 define the location and size of a second implantation region 12i in semiconductor layer 221.

[0058] Referring to the above, the first region 11 can be elongated in the second lateral direction y. In this example, the opening 321 in the second injection mask 320 is elongated in the second lateral direction y.

[0059] At a given implantation dose, the amount of dopant atoms included in each second implantation region 12i can be adjusted by appropriately selecting the width w12 of the opening 321. The width w12 is the dimension of the opening 321 in the first lateral direction x. Adjacent openings 321 are spaced apart from each other by a distance d12 in the first lateral direction x.

[0060] According to one example, the openings 321 in the second injection mask 321 have substantially the same width w 12, such that each second injection region 12i in the semiconductor layer 221 includes substantially the same amount of dopant atoms.

[0061] In the following text, Dz2 means Figure 4B The implantation dose in the implantation process is shown. This implantation dose is referred to below as the second implantation dose Dz2. The second implantation dose Dz2 represents the amount of second-type dopant atoms pointing towards the first surface 101 of the semiconductor body 100 in the vertical direction z.

[0062] Similar to the first injection dose Dz1, the second injection dose Dz2 represents the total injection dose in the injection process.

[0063] In the implantation process, the size of the opening 321 determines how many type-2 dopant atoms reach the first surface 101 and are introduced into the semiconductor body 100. In the following text, the implantation dose A... 12i Indicates in Figure 4B The process shown includes the amount of dopant atoms in the second implantation region 12i. Implantation dose A 12i The value is given by multiplying the second injection dose Dz1 by the width w12 of the opening 321 in the second injection mask 320. A 12i = Dz2∙w12 (1b). Similar to the first injection dose, the second injection dose Dz2 is measured in units such as per square centimeter (cm²). -2 The dopant atoms of ) make the implanted dose A 12iThe dimension is dopant atoms per centimeter (cm²) -1 ).

[0064] As an example, the injection doses Dz1 and Dz2 in the first and second injection processes are selected from 2E12cm. -2 With 2E13cm -2 Between. For example, the widths w11, w12 of the openings 311, 312 of the injection mask are selected between 0.5 micrometers (μm) and 2 micrometers. In these examples, the injection dose A 11i A 12i At 1E8cm -1 With 1E9cm -1 Within the range between.

[0065] According to one example, the opening 311 in the first implantation mask 310 and the opening 312 in the second implantation mask 320 have substantially the same width, such that w11≈w12, and the first implantation dose Dz1 is substantially equal to the second implantation dose Dz2, such that Dz1≈Dz2. In this example, the first implantation region 11i and the second implantation region 12i in the semiconductor layer 221 substantially comprise the same amount of dopant atoms, i.e., the same implantation dose A. 11i ≈A 12i .

[0066] According to one example, the lateral position of the opening 311 in the first injection mask 310 and the lateral position of the opening 321 in the second injection mask 320 are adjusted such that after the first injection process and the second injection process, each first injection region 11i is substantially disposed in the middle between two adjacent second injection regions 12i in the first lateral direction x, and each second injection region 12i is substantially disposed in the middle between two adjacent first injection regions 11i.

[0067] exist Figures 4A to 4B In the example shown, first-type dopant atoms are implanted in semiconductor layer 221 before second-type dopant atoms are implanted. However, this is merely an example. The order in which the first and second types of dopant atoms are implanted is arbitrary.

[0068] exist Figures 4A to 4BIn the diagram, the sidewalls of the first opening 311 and the second opening 312 in the first injection mask 310 and the second injection mask 320 are drawn as vertical. However, this is merely an example and for illustrative purposes only. The sidewalls of the openings 311 and 312 can be slopes with positive or negative slopes, such that the widths w11 and w12 and the distances d11 and d12 between them can vary with the depth of the openings 311 and 321. Therefore, as used herein, "width w11 of the first opening 311" represents the average width of the corresponding first opening 311; "width w12 of the second opening 312" represents the average width of the corresponding second opening 312; "distance d11 between the two first openings 311" represents the average distance between the corresponding first openings 311; and "distance d12 between the two second openings 321" represents the average distance between the corresponding second openings 312.

[0069] refer to Figure 1 The superjunction region 1 has a spacing p, which is the dimension of the pair including the first region 11 and the second region 12 in the first lateral direction x. The spacing p is also given by the center-to-center distance between two adjacent first regions 11 or between two adjacent second regions 12.

[0070] refer to Figures 4A-4B The spacing p of the superjunction region 1 is defined by the first and second injection masks 310 and 320 having the same spacing p. More specifically, the spacing p is defined by the center-to-center distance between adjacent openings 311 in the first injection mask 310 and the center-to-center distance between adjacent openings 312 in the second injection mask 320.

[0071] According to one example, the widths w11 and w12 of the openings 311 and 321 in the first and second injection masks 310 and 320 are selected between 20% and 40% of the spacing, particularly between 30% and 45%, such that adjacent first injection regions 11i and second injection regions 12i are spaced apart from each other in the lateral direction x.

[0072] refer to Figure 5 The transistor forming device further includes forming an additional semiconductor layer 230 on top of the layer stack 220 and forming transistor cells 4 in the third semiconductor layer 230. Transistor cells 4 are formed only in... Figure 5 The transistor cell is schematically illustrated below. A detailed example of the transistor cell is further explained below. It is formed on top of the layer stack 220 (i.e., on the uppermost layer 220 of the layer stack 220). N The first semiconductor layer 230 (on top of the semiconductor body 100) forms the first surface 101 of the semiconductor body 100 and may be referred to as the top layer.

[0073] Forming transistor cell 4 may include an implantation process and one or more annealing processes. Specifically, the body region forming the transistor cell (see...) Figure 12 42) may include a relatively long annealing process. The same annealing process (single or multiple) can be used to form the superjunction region 1 based on the first implantation region 11i and the second implantation region 12i, and to form the transistor unit 4 based on dopant atoms implanted into the additional semiconductor layer 230.

[0074] Referring to the above, applying a voltage between the drain node D and the source node S in the off-state of the transistor device has the effect of expanding a space charge region (depletion region) in the first region 11 and the second region 12, which begins at the PN junction formed between adjacent first regions 11 and second regions 12. According to... Figure 1 and Figure 2 In a transistor device, the PN junction between adjacent first regions 11 and second regions 12 extends in the vertical direction z and the second lateral direction y. The depletion region extends substantially in a direction orthogonal to the PN junction, such that, according to... Figure 1 and Figure 2 In a transistor device, the depletion region extends in the first lateral direction x.

[0075] It should be noted that, as used herein, "PN junction" refers to any kind of junction (boundary) between adjacent first region 11 and second region 12. Specifically, the PN junction is located between adjacent first and second regions where the effective doping concentration is substantially zero. The presence of a PN junction does not necessarily require adjacent first region 11 and second region 12 to be adjacent to each other. It is also possible that adjacent first and second regions are spaced apart from each other, wherein the regions have a base doping of the semiconductor layer 221 disposed therebetween.

[0076] The expansion of the depletion regions in the first region 11 and the second region 12 is associated with an electric field, which is referred to below as the transverse electric field. (See below for reference...) Figures 6A to 6B Explain the expansion of the depletion region and the associated transverse electric field.

[0077] Figures 6A to 6B Each of the above shows portions of two adjacent first and second regions of the superjunction region 1, where Figure 6A The superjunction region 1 shown has a first spacing p1, and Figure 6B The superjunction region shown has a second spacing p2 smaller than the first spacing p1. For example, the semiconductor body 100 may have an inner region and an edge region, the inner region being the area in which transistor cells are arranged, and the edge region surrounding the inner region and including edge termination structures. This is essentially known and therefore requires no further explanation.

[0078] Within the inner region, each first region 11 is arranged between two second regions 12, and each second region 12 is arranged between two first regions 11. In this case, when the depletion region in the first lateral direction x has reached the middle of each of the first regions 11 and second regions 12, a pair of adjacent first regions 11 and second regions 12 are completely depleted. This is in Figure 6A and Figure 6B The diagram is shown schematically, where DR represents the depletion region.

[0079] Apart from Zone 11 and Zone 12 Figures 6A to 6B The transverse electric field Ex is shown. More specifically, Figures 6A to 6B The amplitude (field strength) of the transverse electric field Ex is shown. Figures 6A to 6B The scenario is illustrated where the first region 11 and the second region 12 are completely depleted, causing the magnitude of the lateral electric field to reach its maximum value, Emax. The value of this maximum value at a certain vertical position z in the superjunction region 1 depends on the lateral dopant dose of the first region 11 and the second region 12 at that vertical position. The lateral dopant dose of the first region 11 is the integral of the doping concentration of the first region 11 along the first lateral direction x, and the lateral dopant dose of the second region 12 is the integral of the doping concentration of the second region 12 along the first lateral direction x. Essentially, the higher the lateral dopant dose at the corresponding vertical position z, the higher the maximum value Emax of the electric field.

[0080] As an example, the lateral dopant dosages of the first region 11 and the second region 12 are chosen such that the maximum electric field strength is below a critical value. When the field strength is about to reach the critical value, avalanche breakdown may occur, which is undesirable. The electric field and the critical value of the dopant dosage that may cause the electric field to reach the critical value depend on the type of semiconductor material of the semiconductor body 100. This is common knowledge in the field of superjunction devices, and therefore requires no further explanation.

[0081] In the following text, Dx 11 This represents the lateral dopant dose at a certain vertical position z in the first region 11. This lateral dopant dose, Dx, is... 11 This will be referred to below as the first lateral dopant dose. The first lateral dopant dose, Dx 11 The value is given by the integral of the doping concentration of the first region 11 over the first lateral direction x (i.e., the direction substantially orthogonal to the PN junction between adjacent first regions 11 and second regions 12). Equivalently, Dx 12 This represents the lateral dopant dose at a certain vertical position z in the second region 12. This lateral dopant dose is referred to below as the second lateral dopant dose. Second lateral dopant dose Dx 12The result is given by the integral of the doping concentration of the second region 12 over the first lateral direction x (i.e., the direction substantially orthogonal to the PN junction).

[0082] The amount of dopant atoms in the first implantation region 11i and the second implantation region 12i (implantation dose A) can be appropriately selected. 11i A 12i To adjust the first lateral dopant dose Dx 11 Second lateral dopant dose Dx 12 As described above, in the annealing process, first-type dopant atoms in the first implantation region 11i and second-type dopant atoms in the second implantation region 12i diffuse in the vertical direction z (and the lateral direction), such that the dopant atoms are dispersed in the vertical direction z, and each of the first implantation regions 11i forms a portion of the corresponding first region 11, and each of the second implantation regions 12i forms a portion of the corresponding second region 12. The amount of first-type dopant atoms included in the portion of the first region 11 formed by the corresponding first implantation region 11i is substantially equal to the amount of first-type dopant atoms in the first implantation region 11i (implantation dose A). 11i The amount of second-type dopant atoms included in a portion of the second region 12 formed by the corresponding second implantation region 12i is substantially equal to the amount of second-type dopant atoms in the second implantation region 12i (implantation dose A). 12i ).

[0083] After the annealing process, the first and second type dopant atoms are non-uniformly distributed in the vertical z-direction in the first region 11 and the second region 12, resulting in a lateral dopant dose Dx. 11 Dx 12 It can vary in the vertical direction. However, the approximate value of the lateral dopant dose in the cross-section of the first region 11 obtained from the first implantation region 11i is determined by the first lateral dopant dose Dx. 11 average <Dx 11 The approximate value of the lateral dopant dose in the cross section of the second region 12 obtained from the second implantation region 12i is given by the second lateral dopant dose Dx. 12 average <Dx 12 >Given.

[0084] From having an injection dose A 11i The first lateral dopant dose Dx in the cross section of the first region 11 obtained from the first implantation region 11i 11 average <Dx 11 The following formula is given <Dx 11 >=A 11i ∙d221 (2a), Where d221 represents the thickness of the semiconductor layer 221 in which the first implantation region 11i has been formed. Equivalently, from the implantation dose A... 12i The second lateral dopant dose Dx in the cross section of the second region 12 obtained from the second implantation region 12i 12 average <Dx 12 The following formula is given <Dx 12 >=A 12i ∙d221 (2b), Where d221 represents the thickness of the semiconductor layer 221 in which the second implantation region 12i has been formed.

[0085] As can be seen from equations (2a) and (2b), the lateral dopant dose can be varied in the vertical direction by changing the injection dose introduced into the individual semiconductor layer 221.

[0086] Referring to the above, after the annealing process, the first and second types of dopant atoms are non-uniformly distributed in the vertical direction z. Therefore, even if each of the first implantation regions 11i has the same amount of A... 11i Type 1 dopant atom, first lateral dopant dose Dx 11 The distribution in the vertical direction will also be non-constant. Equivalently, even if each of the second injection regions 12i has the same amount A... 12i The second type of dopant atom, the second lateral dopant dose Dx 12 The distribution in the vertical direction will also be non-constant. This variation in the lateral dopant dosage... Figure 8 As shown in the image.

[0087] Figure 8 The lateral dopant dose Dx in a first region 11 in the vertical direction z between the upper and lower ends of the superjunction region 1 is shown. 11 Or the lateral dopant dose Dx in a second region 12 12 The upper end of superjunction region 1 is at the vertical position z0, and the lower end of superjunction region 1 is at... Figure 1 The vertical position z1 shown in the figure has its upper end facing the first surface 101 and located at the junction between the superjunction region 1 and the transistor cell 4. Its lower end faces the second surface 102 and is located at the junction between the superjunction region 1 and the buffer region 52 or the drain region 51.

[0088] from Figure 8 It can be seen that the lateral dopant dose Dx 11 Dx 12The values ​​vary and include several maximum and minimum values. The maximum value is essentially located at a vertical position in the implanted region 11i, such as in the middle of semiconductor layer 221, and the minimum value is essentially located at a vertical position between two adjacent semiconductor layers 221 in the previously explained layer stack 220.

[0089] The maximum electric field, Emax, depends primarily on the lateral dopant dose and is largely independent of how the dopant atoms are distributed in the first lateral direction x across the first region 11 and the second region 12. This is in Figures 6A to 6B As shown in [the image]. Figure 6B In the example shown, the first region 11 and the second region 12 have the same characteristics as in... Figure 6A In the example shown, the first region 11 and the second region 12 have the same lateral dopant dose. Therefore, in both examples, although the superjunction regions have different spacings p1 and p2, the electric field reaches the same maximum value Emax.

[0090] Referring to the above, in the on-state of the transistor device, each first region 11 provides a conductive channel in the superjunction region 1 between the transistor cell 1 and the drain region 51 and the buffer region 52. The resistance of a first region 11 is substantially defined by the effective amount of first-type dopant atoms included in the first region 11, rather than by how the dopant atoms are distributed in the first lateral direction x. Therefore, according to Figure 6B The first region 11 in the superjunction region 1 with a smaller spacing p2 can have substantially the same resistance as the first region 11 in the superjunction region 1 with a larger spacing p1. The first region 11 has an effective doping concentration of a first doping type. That is, the total number of first-type dopant atoms in the first region 11 is dominant, and the total number of second-type dopant atoms can also be included in the first region 11. The effective amount of first-type dopant atoms is the amount by which the first-type dopant atoms exceed the second-type dopant atoms in the first region 11.

[0091] Figure 1 The on-resistance Ron of the transistor device of the type shown is the resistance between the drain node D and the source node S when the transistor device is in the on state. The on-resistance is essentially defined by the overall resistance of the first region 11 in the superjunction region 1. The (area) ratio on-resistance Ron∙A is the on-resistance Ron multiplied by the area A of the transistor device. The area A of the transistor device is essentially given by the area of ​​the semiconductor body 100 in the horizontal plane defined by the first lateral direction x and the second lateral direction y.

[0092] For reference Figures 6A to 6BAs explained, the spacing of the superjunction regions 1 can be reduced without increasing the maximum electric field and without increasing the resistance of the individual first regions 11. However, reducing the spacing p increases the number of first regions 11 that can be implemented in a transistor device with a given area, thus reducing the spacing p can help reduce the specific on-resistance. This is in Figure 8 It is shown schematically in the diagram.

[0093] Figure 8 The curve shown illustrates the dependence of the on-resistance Ron∙A on the spacing p. Figure 8 based on Figure 1 Simulations of transistor devices of the type shown, wherein the simulated transistor devices have the same voltage blocking capability, and wherein the maximum value of the transverse electric field in the superjunction region 1 is substantially the same in each transistor device.

[0094] from Figure 8 It can be seen that reducing the spacing within a certain range leads to a decrease in resistivity Ron∙A. However, from Figure 8 It can be seen that the specific on-resistance reaches a minimum at a certain spacing, which is referred to below as the optimal spacing p_opt, and the specific on-resistance increases as the spacing decreases below the optimal spacing p_opt. This increase in specific resistance can be caused by the increased lateral diffusion of second-type dopant atoms from the second region 12 to the first region 11, thereby reducing the effective amount of first-type dopant atoms in the first region 11.

[0095] Ideally, the first region 11 and the second region 12 in the transistor device are directly adjacent to each other, or spaced apart from each other in the first lateral direction x, and there is no lateral diffusion of first-type dopant atoms from the first region 11 to the adjacent second region 12 and from the second region 12 to the adjacent first region 11. That is, in the annealing process used to form the first region 11 and the second region 12 based on the first implantation region 11i and the second implantation region 12i, the diffusion of first-type dopant atoms into the second region 12 and the diffusion of second-type dopant atoms into the first region 11 are not desired. Diffusion of first-type dopant atoms into the second region 12 reduces the amount of first-type dopant atoms available for conducting current in the first region 11, and thus increases the on-resistance.

[0096] The first lateral dopant dose D mentioned above x11 Second lateral dopant dose D x12 This is the total (absolute) first lateral dopant dose and second lateral dopant dose generated by the corresponding implantation process. Effective first lateral dopant dose (Deff) x11It is the integral of the effective doping concentration of the first doping type in the first region 11 at the corresponding vertical position over the first lateral direction x, and the effective second lateral dopant dose Deff x12 It is the integral of the effective doping concentration of the second doping type in the second region 12 at the corresponding vertical position over the first lateral direction x. Due to the (almost inevitable) diffusion of first-type dopant atoms from the first region 11 to the adjacent second region 12 and from the second region 12 to the adjacent first region 12, the effective first lateral dopant dose Deff... x11 Below the absolute first lateral dopant dose D x11 And effective second lateral dopant dose Deff x12 Below the absolute second lateral dopant dose D x12 .

[0097] Ineffective first lateral dopant dose Din x11 It is the integral of the doping concentration of the first doping type in the second region 12 (of the second doping type) at the corresponding vertical position along the first lateral direction x, and the invalid second lateral dopant dose Din x12 It is the integral of the doping concentration of the second doping type in the first region 11 (of the first doping type) at the corresponding vertical position along the first lateral direction x. Basically, the stronger the lateral diffusion, the less effective the first or second lateral dopant Din. x11 Din x12 Relative to the corresponding absolute first or second lateral dopant D x11 D x12 The higher the level, and the more effective the first or second lateral dopant Def fx11 Deff x12 Relative to the corresponding absolute first or second lateral dopant dose D x11 D x12 The lower.

[0098] Effective first lateral dopant dose Def fx11 (In the first region 11) the on-resistance is essentially defined. The effective first lateral dopant dose Def of the first region 11. fx11 The average value is the effective first lateral dopant dose Def in the vertical direction z. fx11 The average value over the length of the corresponding first region 11. Referring to the above, the first regions 11 are formed by the same process, such that each of the first regions 11 has substantially the same absolute lateral dopant dose D. x11 (and effective first lateral dopant Def) fx11 The distribution of ) and the substantially the same effective first lateral dopant dose Def fx11 (and the absolute first lateral dopant D) x11The average value of ). Basically, the effective first lateral dopant dose Def in the first region 11 of a given number and size. fx11 The higher the average value, the lower the on-resistance of the transistor device.

[0099] Reducing the spacing may require reducing diffusion in the lateral direction in order to avoid [affecting] a given absolute first lateral dopant dose D. x11 Reduced effective first lateral dopant dose Def fx11 and increased ineffective first lateral dopant dose Def fx11 .

[0100] In the annealing process, the first and second types of dopant atoms diffuse in the first lateral direction x to substantially the same extent as in the vertical direction z, such that diffusion in the lateral direction can only be reduced by simultaneously reducing the diffusion required in the vertical direction z. However, as described above, diffusion in the vertical direction z is desirable so that the first region 11 and the second region 12 can be generated based on the first implantation region 11i and the second implantation region 12i.

[0101] By reducing the thickness d221 of the second semiconductor layer 221, the desired vertical diffusion can be reduced, and simultaneously, the (inevitable) lateral diffusion of dopant atoms can be reduced. Therefore, reducing the spacing p to lower the specific on-resistance can be associated with reducing the thickness d221 of the semiconductor layer 221 in the layer stack 220.

[0102] The voltage blocking capability, which is the maximum voltage that a transistor device can withstand in the off state, is essentially determined by the size of the superjunction region 1 in the vertical z-direction. Therefore, reducing the thickness d221 of individual semiconductor layers 221 makes it necessary to increase the total number of semiconductor layers 221 in order to maintain a certain voltage capability.

[0103] According to one example, the transistor device is implemented to have a voltage blocking capability selected between 600 V and 800 V, particularly between 600 V and 700 V.

[0104] consider Figure 8 Taking into account the lateral diffusion problem explained above, it has been found that in a superjunction transistor device based on a semiconductor body 100 including monocrystalline silicon, a spacing p selected between 3 micrometers and 5 micrometers, particularly between 3 micrometers and 4.5 micrometers, combined with a layer thickness d221 selected between 1.9 micrometers and 2.5 micrometers, particularly between 1.9 micrometers and 2.1 micrometers, results in a favorable specific on-resistance Ron∙A.

[0105] Referring to the above, the total number of first semiconductor layers 221 in the stack 220 affects the voltage blocking capability. As an example, to achieve a voltage blocking capability between 600 V and 800 V, the total number of semiconductor layers is selected from 17 to 21.

[0106] At a given number of semiconductor layers 221, the voltage blocking capability can be increased by increasing the thickness d221 of the semiconductor layers 221. At a given thickness of semiconductor layers 221, the voltage blocking capability can be increased by increasing the total number of semiconductor layers. For illustrative purposes only, parameters for three different examples of transistor devices are summarized below. These parameters include the voltage blocking capability Vbr, the spacing p, the number N221 of semiconductor layers 221, and the thickness d221 of each individual semiconductor layer 221. For example, the annealing process temperature is selected between 950°C and 1150°C, and the duration is selected between 20 minutes and 400 minutes. Basically, the higher the temperature, the shorter the duration. Furthermore, the smaller the spacing, the shorter the duration of the annealing process at a given temperature.

[0107] Example 1 Voltage blocking capability (Vbr): 600 V Spacing (p): 4.4 micrometers Number of layers (N221): 19 Layer thickness (d221) 2.1 micrometers

[0108] Example 2 Voltage blocking capability (Vbr): 650 V Spacing (p): 4.4 micrometers Number of layers (N221): 19 Layer thickness (d221) 2.15 micrometers

[0109] Example 3 Voltage blocking capability (Vbr): 600 V Spacing (p): 3 micrometers Number of layers (N221): 19 Layer thickness (d221) 2.1 micrometers

[0110] As can be seen from Examples 1 and 2, slightly increasing the layer thickness d221 can result in increased voltage blocking capability (at the cost of slightly increased on-resistance).

[0111] In the manufacturing process, the reduction in spacing can be supported by taking into account additional measures to address the unavoidable lateral diffusion during the annealing process.

[0112] According to one example, each of the first and second injection processes includes two or more injection steps. An example of a method in which each of the first and second injection processes includes two injection steps is shown in... Figures 9A to 9B As shown in the image.

[0113] Figure 9A A vertical cross-sectional view of a semiconductor layer 221 after the first implantation process is shown. In this implantation process, first-type dopant atoms are implanted into the semiconductor layer 221 through an opening 311 in a first implantation mask 310 in two implantation steps: a first implantation step to form an implantation region 111i at a first vertical location in the semiconductor layer 221; and a second implantation step to form an implantation region 112i at a second vertical location different from the first vertical location. The implantation doses in the first and second implantation steps may be substantially equal or may be different.

[0114] Figure 9B A vertical cross-sectional view of a semiconductor layer 221 after the second implantation process is shown. In this implantation process, second-type dopant atoms are implanted into the semiconductor layer 221 via openings 312 in a second implantation mask 320 in two implantation steps: a first implantation step forming an implantation region 121i at a first vertical location in the semiconductor layer 221; and a second implantation step forming an implantation region 122i at a second vertical location different from the first vertical location. The implantation doses in the first and second implantation steps may be substantially equal or may be different.

[0115] Based on one example, Figure 9A The injection regions 111i, 112i and in the first injection process shown are shown. Figure 9B The vertical positions of the injection regions 121i and 122i in the second injection process shown are selected such that, including Figure 9B In the stack of multiple semiconductor layers of the type shown, the implantation regions 111i and 112i generated by the first implantation process are substantially uniformly spaced in the vertical direction z, and the implantation regions 121i and 122i generated by the second implantation process are uniformly spaced in the vertical direction z.

[0116] refer to Figures 9A to 9B In both the first and second implantation processes, two implantation regions are formed in the semiconductor layer 221 below the openings 311 and 321 of the corresponding implantation masks, spaced apart from each other in the vertical direction z. The presence of the two vertically spaced implantation regions 111i, 112i and 121i, 122i allows for reduction of the diffusion of implanted dopant atoms or an increase in the thickness d221 of the semiconductor layer 221 during the annealing process, thereby reducing the total number of semiconductor layers 221.

[0117] In other words, at a given layer thickness d221, the duration of the annealing process can be reduced, thereby reducing lateral diffusion and enabling a reduction in the spacing p. Alternatively, the presence of two implantation regions formed in each implantation process within a given annealing process allows for an increase in layer thickness, which helps reduce the number of semiconductor layers 221 to be produced and thus reduces the costs associated with the manufacturing process.

[0118] In the fabrication process of superjunction region 1, there are two possible effects that may lead to stronger diffusion of dopant atoms in semiconductor layer 221 arranged closer to drain region 51 and buffer region 52 than that of dopant atoms in semiconductor layer 221 arranged closer to transistor cell 4.

[0119] As described above, a layer stack 220 having a semiconductor layer 221 can be formed on top of a substrate 211. Specifically, when the substrate 211 is based on a Czochralski (CZ) material, the substrate 211 may include oxygen and voids. During the annealing process used to form the first region 11 and the second region 12, the combination of oxygen and voids may cause interstitial atoms to diffuse from the substrate 211 into the layer stack 220, with the interstitial atom concentration decreasing towards the first surface 101. The interstitial atoms support the diffusion of first and second types of dopant atoms included in the layer stack 220. As the interstitial atom concentration decreases towards the first surface 101, the diffusion of first and second types of dopant atoms facilitated by the interstitial atoms is stronger in regions closer to the drain region 51 and the buffer region 52 than in regions closer to the first surface 101. This imbalance in diffusion along the vertical z-direction may result in variations in the lateral dopant dosage in the first region 11 and the second region 12.

[0120] According to one example, to counteract this imbalance caused by interstitial atoms diffusing from substrate 211 into the stacked layers 220 along the vertical z-direction, the annealing process occurs at least partially in an oxidizing atmosphere. For example, the annealing temperature is selected between 950°C and 1150°C, and the duration is selected between 20 minutes and 400 minutes. Essentially, the higher the temperature, the shorter the duration.

[0121] exist Figure 10 The diagram schematically illustrates an annealing process in an oxidizing atmosphere. In this annealing process, an oxide layer 400 is formed on top of a first surface 101. This oxide layer 400 allows interstitial atoms to diffuse through the first surface 101 into the semiconductor body 100, resulting in interstitial-promoted diffusion also present in the semiconductor layer 221 near the first surface 101. This can help to at least partially offset the imbalance in lateral dopant dosage caused by interstitial atoms diffusing from the substrate 211 into the stack 220.

[0122] Another reason for the stronger diffusion of first-type and second-type dopant atoms in the semiconductor layer 221 closer to the drain region 51 and buffer region 52 is the temperature involved in the process of forming the semiconductor layer 221. Referring to the above, for example, the semiconductor layer 221 is an epitaxially grown layer. The temperature during the epitaxial growth process may cause already implanted first- and second-type dopant atoms to diffuse in the previously formed semiconductor layer 221. In the layer stack 220, this has the effect of some degree of diffusion of implanted dopant atoms already occurring in some of the semiconductor layers 221 prior to the annealing process used to form the first region 11 and the second region 12 based on the first implantation region 11i and the second implantation region 12i.

[0123] from Figure 7 This effect can be observed. Figure 7 The lateral dopant dosages in the first region 11 and the second region 12 are shown. From Figure 7 As can be seen, the ripples in the distribution decrease towards the lower end z1 of the superjunction region 1. The semiconductor layer 2021 near the lower end is first generated in the manufacturing process, resulting in stronger diffusion within these semiconductor layers 221 throughout the manufacturing process.

[0124] During the process of forming individual semiconductor layers 221, the diffusion of first and second type dopant atoms in some semiconductor layers 221 not only reduces ripple in the lateral dopant dose but may also cause the first and second type dopant atoms to diffuse more in the lateral direction than desired. Therefore, after the annealing process, first type dopant atoms in the semiconductor layers to the drain region 51 and buffer region 52 may have diffused into the second region 12, and second type dopant atoms may have diffused into the first region 11 more than desired. In other words, in the first region 11 and the second region 12, the ineffective first lateral dopant dose Din x11 and ineffective second lateral dopant dose Din x12 The resistance increases towards the bottommost layer 2211 in the stacked layers 220. This can locally increase the resistance of the superjunction region 1.

[0125] according to Figure 11A One example shown is to counteract the increased ineffective first lateral dopant dose Din in the second region 12 towards the bottommost layer 2211. x11 Or the reduced effective first lateral dopant dose Deff in the first region 11 x11 The injected dose A in at least a portion of the stacked body 12i A 11i At least one of them can vary in the vertical direction z, such that the injected dose is directed toward the uppermost layer 221N decreases and increases toward the lowermost layer 2211. According to one example, the implantation dose A 11i , A 12i all decrease toward the uppermost layer 2211. In this example, to achieve the decreasing direction, the variation of the dose may be the same or different.

[0126] Figure 11A illustrates an example of implantation dose in a portion of a layer stack 220 including a plurality of semiconductor layers 221, wherein in the layer stack 220, the lowermost semiconductor layer 2211 is produced first and the uppermost semiconductor layer 221 N is produced last. Figure 11A the portion of the layer stack shown in includes the uppermost layer 221 of the layer stack portion 1+m and the lowermost layer 221 of the layer stack portion N-n , wherein N, m and n are positive integers, 1+m<N-n and N>n.

[0127] According to one example, over the entire layer stack 220, the implantation dose A 11i , A 12i decreases toward the uppermost layer 221 N and increases toward the lowermost layer 2211. In this example, the uppermost layer 221 of the layer stack portion N-n is equal to the uppermost layer 221 of the layer stack N , and the lowermost layer 221 of the layer stack portion 1+m is equal to the lowermost layer of the layer stack 220.

[0128] According to another example, doping conditions in the lowermost semiconductor layer 2211 and the uppermost semiconductor layer 221 N are slightly different from those in other semiconductor layers of the layer stack, such that the layer stack portion, the doping condition of which is shown in Figure 11A may include the layer stack 220 except the uppermost layer 221 N and the lowermost layer 2211. That is, the layer stack portion may include the layer stack from layer 221 Figure 5 shown in from layer 2212 to layer 221 N-2 of the layer stack.

[0129] According to one example, the portion of the layer stack where the implantation dose A 11i , A 12i decreases toward the first surface 101 and increases toward the second surface 102 includes at least 70%, 80% or 90% of the layers 221 of the layer stack 220.

[0130] The implantation dose A 11i , A 12iIt can increase toward the second surface 102 (towards the lowest layer 2211 in the stack) in various ways within the stacked portion.

[0131] according to Figure 11A As shown in one example, the injected dose A in the layer stack portion 11i A 12i Facing the lowest level 221 1+m As stability increases, the corresponding layer in the stacked volume becomes closer to the bottom layer.221 1+m The higher the dose, the better. According to one example, the increase is essentially linear.

[0132] However, a steady increase is merely an example. It is also possible for at least one injection dose to increase in such a manner that two or more adjacent layers have substantially the same injection dose A. 11i A 12i And the dose is directed toward the lowest layer 221 in the stacked body portion. 1+m Increase. This is in Figure 11B As shown in the image.

[0133] according to Figure 11C Another example illustrated herein shows that there is a local maximum or local minimum (indicated by dashed lines) of at least one of the dopant doses in a portion of the stacked body. The local maximum is lower than the absolute maximum of at least one of the dopant doses at the lower end of the stacked body portion, or the local minimum is higher than the dopant dose A at the upper end of the stacked body portion. 11i A 12i The absolute minimum of at least one of them.

[0134] According to one example, the bottom layer of the stacked volume portion is 220. 1+m The injection dose in the middle is 220 compared to the top layer N The injected dose is higher than 30% or 40%, such as between 40% and 80%, especially between 50% and 70%, and higher.

[0135] According to one example, increasing the dopant dose toward the lower end of the stacked portion includes: the total implantation dose in the three adjacent bottom layers of the stacked portion being greater than 30% or greater than 40% higher than the total implantation dose in the three adjacent top layers of the stacked portion. The three adjacent bottom layers of the stacked portion include the bottom layer 221 of the stacked portion. 1+m And two adjacent layers. The three uppermost adjacent layers of the layer stack include the uppermost layer 221 of the layer stack. N-n And two adjacent layers.

[0136] According to one example, a portion of a stack where the total injected dose in the three lowest layers is greater than 30% higher than the total injected dose in the three highest layers includes a layer with the highest layer 221. N And the entire stack of layers 220, including the bottom layer 2211.

[0137] Figures 11A to 11C Each in the figure represents the injection dose A in each layer of the stacked body. 11i A 12i One of them. According to one example, Figures 11A to 11C Indicates the injection dose A 11i A 12i Both. In this example, the injected dose A 11i A 12i They are essentially equal. Basically, the injection dose A in the same layer is... 11i A 12i Differences are also possible, for example, in order to counteract the underlying doping of semiconductor layer 221.

[0138] refer to Figure 12 Each transistor unit 4 includes a source region 41 of a first doped type, a body region 42 of a second doped type (complementary to the first doped type), and a gate electrode 43. The gate electrode 43 is adjacent to the body region 42, dielectrically insulated from the body region 42 by a gate dielectric 44, and disposed in a gate trench 40 extending from the first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0139] refer to Figure 12 The source regions 41 and body regions 42 of two adjacent transistor cells 4 can be arranged in a mesa region between adjacent gate trenches 40. In this example, the body regions 42 of the two adjacent transistor cells 4 can be formed by a continuous doped region of a second doping type. Furthermore, the two (other) adjacent transistor cells can share a gate electrode 43. That is, the gate electrodes 43 of the two adjacent transistor cells can be formed by a continuous electrode arranged in a gate trench 40.

[0140] Gate electrode 43 comprises a conductive material. Examples of conductive materials include metals or doped polysilicon. For example, gate dielectric 44 comprises an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0141] Referring to the above, the source region 41 of transistor cell 4 is connected to the source node S of the transistor device. The transistor device may include a source electrode 72, which forms or is connected to the source node S. The source electrode 72 includes a conductive material, such as, for example, aluminum (Al), copper (Cu), or an aluminum-copper alloy (AlCu).

[0142] The source electrode 72 is electrically connected to the source region 41 and the body region 42 of the transistor unit 40. The connection between the source electrode 72 and the source and body regions 41, 42 is only present in the source region 41. Figure 12 The diagram is schematically shown. This connection can be implemented using a conductive via that extends from the source electrode 72 through the insulating layer 71 to the source and body regions 41, 42.

[0143] Gate electrode 43 is connected to gate node G. The connection between gate electrode 43 and gate node G is not shown in Figure 11. An example of this connection is explained further below.

[0144] An insulating layer 71 is formed on the first surface 101 of the semiconductor body 100 and on top of the gate electrode 43, and separates the source electrode 72 from the semiconductor body 100 and the gate electrode 43.

[0145] Referring to the above, the second region 12 of the first superjunction region 1 is coupled to the source node S. In Figure 12 In the example shown, each second region 12 is adjacent to the body region 42 of the corresponding transistor cell and is coupled to the source node S via the body region 42 of the transistor cell 4.

[0146] The transistor forming unit 4 may include forming a gate electrode 43 in a gate trench 40, implanting first-type dopant atoms to form a source region 41, and implanting second-type dopant atoms to form a body region 42. Dopant atoms may be implanted before or after forming the gate electrode 43. The transistor forming unit 4 also includes an annealing process in which the implanted dopant atoms are activated. The annealing process may be the same annealing process used to activate the first and second superjunction regions 1, 2 and the first and second terminal regions 31, 32.

[0147] Referring to the above, the transistor device can operate in either an on or off state. The transistor device is in the on state when the gate-source voltage causes a conductive channel to be formed in the body region 42 by the gate electrode 43 along the gate dielectric. The transistor device is in the off state when the conductive channel is interrupted. To allow current to flow from the source node S to the drain node D when the transistor device is in the on state, this portion of the body region 42 where the conductive channel is formed is adjacent to the corresponding first region 11. In this way, in the on state, charge carriers can move from the source region 41 along the conductive channel in the body region 42, the first region 11 of the first superjunction region 1, and the buffer region 52 to the drain region 51.

[0148] exist Figure 1In the circuit symbol of transistor unit 4 shown, the electronic switch represents the conductive channel along the gate dielectric 44 in the body region 42. The diode in the circuit symbol represents the diode formed by the PN junction between the first region 11 (drift region) and the body region 42, which is usually referred to as a body diode.

[0149] according to Figure 12 In one example shown, the gate trench 40 with the gate electrode is elongated. An example of an elongated gate electrode 43 is... Figure 13 As shown in the image.

[0150] Figure 13 A portion of the semiconductor body 100 in the first horizontal cross-sectional plane BB shown in FIG11 is illustrated, which cuts through the gate trench 40 through the gate electrode 43 and the gate dielectric 44. The horizontal cross-sectional plane BB is substantially parallel to the first surface 101 and the second surface 102.

[0151] Based on an example, such as Figure 12 and Figure 13 As shown, gate trenches 40 with gate electrodes 43 are spaced apart from each other in a first lateral direction x and extend longitudinally in a second lateral direction y. In this example, the gate trenches 40 extend longitudinally in the same direction as the first region 11 and the second region 12. According to another example (not shown), the longitudinal direction of the gate trenches 40 with gate electrodes 43 is orthogonal to the longitudinal direction of the first region 11 and the second region 12.

[0152] According to one example, the transistor device is an N-type transistor device. In this example, regions of a first doping type (such as drain region 51 and buffer region 52, first region 11 and third region 13, first termination region 31 and source region 41) are N-type regions, and regions of a second doping type (such as second region 12 and fourth region 22 and second termination region 32) are P-type regions. When a positive voltage is applied between drain node D and source node S, the N-type transistor device is in a forward bias mode. For example, the N-type dopant atoms used to form the N-type regions are phosphorus (P) atoms, and the P-type dopant atoms used to form the P-type regions are boron (B) atoms.

[0153] According to another example, the transistor device is a P-type transistor device. In this example, the region with the first doping type is a P-type region, and the region with the second doping type is an N-type region.

[0154] It should be noted that, such as Figure 12 The transistor cell 4 shown is merely an example, containing a gate electrode 43 disposed in a gate trench 40. According to another example (not shown), the gate electrode is a planar gate electrode disposed above the first surface 101.

[0155] Referring to the above, the second terminal region 32 is coupled to the source node S. In Figure 13 An example of connecting the second terminal region 32 to the source node S is shown.

[0156] Figure 14 and Figure 15 Each of these shows a top view of a transistor device of the type explained earlier in this article. More specifically, Figure 14 and Figure 15 Each of these figures shows a top view of a semiconductor body 100 having a source electrode 72 formed on top of an insulating layer 71.

[0157] The transistor device also includes a gate runner 74 and a gate pad 75, both formed on top of the insulating layer 71 and spaced apart from the source electrode 72. The gate runner 74 surrounds the source electrode 72 in the lateral direction of the semiconductor body 100. The gate pad 75 forms a gate node G or is connected to a gate node G of the transistor device. The gate pad 75 may be adjacent to the gate runner 74, such as... Figure 14 and 15 As shown. Alternatively, the gate pad 75 is spaced apart from the gate trace 74, and a resistor (gate resistor) is connected between the gate pad 75 and the gate trace 74.

[0158] exist Figure 14 In the example shown, the gate pad 75 is positioned substantially midway between the two opposing sidewalls 103 of the semiconductor body 100. According to... Figure 15 In this example, the gate pad 75 is positioned near the corner formed by two adjacent sidewalls 103 of the semiconductor body 100. The sidewalls 103 terminate the semiconductor body 100 in the lateral direction.

[0159] Transistor unit in Figure 14 and 15 Not visible in the image. For illustrative purposes, the positions of the three gate electrodes 43 relative to the source electrode 72 and the gate trace 74 are shown in the image. Figure 14 and 15 It is shown in thick lines. Figure 14 and Figure 15 In the example shown, gate electrode 43 is an elongated electrode, wherein the longitudinal direction of gate electrode 43 corresponds to the second transverse direction y explained earlier herein. The vertical cross-sectional view of the transistor cell shown in Figure 11 is, for example... Figure 14 and Figure 15 The cross-sectional view in the cross-sectional plane CC shown.

[0160] To connect the gate electrode 43 to the gate pad 75, the region of the gate electrode 43 near its longitudinal end is connected to the gate trace 75. Figure 14 and Figure 15 In the example shown, the "longitudinal end" terminates the gate electrode 43 in the longitudinal direction, which corresponds to the second lateral direction y. According to one example, the gate electrode 43 is connected to the gate trace 74 via a conductive via (not shown) extending vertically through the insulating layer 71.

[0161] Some of the aspects explained above are summarized in the examples in the reference numbers below.

[0162] Example 1: A method for forming a superjunction device, the method comprising: forming a superjunction region including a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type, wherein forming the superjunction region comprises: forming a plurality of semiconductor layers, the plurality of semiconductor layers being positioned above each other to form a layer stack; implanting first type dopant atoms into each of the semiconductor layers through an opening in a first implantation mask to form a first implantation region; implanting second type dopant atoms into each of the semiconductor layers through an opening in a second implantation mask to form a second implantation region; and performing an annealing process to diffuse and activate the implanted first type dopant atoms and second type dopant atoms, wherein each of the first implantation mask and the second implantation mask has a spacing selected between 3 micrometers and 5 micrometers, and wherein each of the semiconductor layers has a thickness selected between 1.9 micrometers and 3.5 micrometers.

[0163] Example 2: According to the method of Example 1, wherein the spacing is selected between 3 micrometers and 4.5 micrometers.

[0164] Example 3: The method according to Example 1 or 2, wherein the thickness is selected between 1.9 micrometers and 2.5 micrometers.

[0165] Example 4: The method according to any one of Examples 1 to 3, wherein the width of the opening in the first injection mask and the width of the opening in the second injection mask are selected between 20% and 45% of the spacing.

[0166] Example 5: The method according to any one of Examples 1 to 4, wherein the annealing process occurs in an oxidizing environment.

[0167] Example 6: The method according to any one of Examples 1 to 5, wherein the layer stack includes a bottom semiconductor layer, wherein each of the first injection regions has a first injection dose and each of the second injection regions has a second injection dose, and wherein the first injection region and the second injection region are formed such that at least one of the first injection dose and the second injection dose increases toward the bottom semiconductor layer on said portion of the layer stack, at least in a portion of the layer stack.

[0168] Example 7: The method according to Example 6, wherein the portion of the layer stack comprises at least 70% of the semiconductor layers of the layer stack.

[0169] Example 8: According to the method of Example 7, wherein the maximum value of at least one of the first injection dose and the second injection dose in the portion of the layer stack is at least 30% higher than the minimum value of the first injection dose in the portion of the layer stack.

[0170] Example 9: The method according to any one of Examples 6 to 8, wherein at least one of the first injection dose and the second injection dose increases steadily toward the lowermost semiconductor layer.

[0171] Example 10: The method according to any one of Examples 6 to 8, wherein at least one of the first injection dose and the second injection dose increases in a stepwise manner toward the lowest semiconductor layer.

[0172] Example 11: The method according to any one of Examples 6 to 8, wherein at least one of the first implantation dose and the second implantation dose increases toward the lowest semiconductor layer such that at least one of the first implantation dose and the second implantation dose in the lowest layer of the portion of the layer stack is more than 30% higher than at least one of the first implantation dose and the second implantation dose in the uppermost layer of the portion of the layer stack.

[0173] Example 12: The method according to any one of Examples 6 to 8, wherein at least one of the first implantation dose and the second implantation dose increases toward the lowest semiconductor layer such that the total dose of the first implantation dose and the second implantation dose in the three adjacent lowest layers of the portion of the layer stack is more than 30% higher than the total dose of the first implantation dose and the second implantation dose in the three adjacent uppermost layers of the portion of the layer stack.

[0174] Example 13: According to the method of Example 12, wherein the portion of the layer stack comprises the entire layer stack.

[0175] Example 14: The method according to any of Examples 6 to 13, wherein, in each of the semiconductor layers of the portion of the layer stack, the first implantation dose is substantially equal to the second implantation dose.

[0176] Example 15: The method according to any of Examples 1 to 14, wherein implanting the first type of dopant atoms into each of the semiconductor layers comprises at least two implantation steps at different implantation energies; and wherein implanting the second type of dopant atoms into each of the semiconductor layers comprises at least two implantation steps at different implantation energies.

[0177] Example 16: The method according to Example 15, wherein the at least two injection steps comprise exactly two injection steps.

[0178] Example 17: The method according to any of Examples 1 to 16, wherein the number of semiconductor layers in the layer stack is selected between 17 and 21.

[0179] Example 18: The method according to any of Examples 1 to 16, wherein forming the layer stack includes forming the layer stack on top of the carrier.

[0180] Example 19: The method according to Example 18, wherein the carrier comprises a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate.

[0181] Example 20: The method according to any one of Examples 1 to 19 further includes: forming an additional semiconductor layer on top of the layer stack; and forming a transistor unit at least partially integrated in the additional semiconductor layer.

[0182] Example 21: According to the method of Example 20, forming the transistor cell includes performing an annealing process, and wherein the annealing process for forming the transistor cell and the annealing process for forming the superjunction region are the same annealing process.

[0183] Example 22: The method according to any of Examples 1 to 21, wherein the first injection region and the second injection region are formed to be spaced apart in a first lateral direction of the layer stack and are elongated in a second lateral direction orthogonal to the first lateral direction.

[0184] Example 23: The method according to any of Examples 1 to 22, wherein the semiconductor layer comprises monocrystalline silicon.

[0185] Example 24: A superjunction device comprising: a superjunction region including a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type in a stacked body, the stacked body including a plurality of semiconductor layers formed on top of each other to form the stacked body, wherein the spacing between the superjunction regions is selected between 3 micrometers and 5 micrometers, and wherein each of the semiconductor layers has a thickness selected between 1.9 micrometers and 3.5 micrometers.

[0186] Example 25: A superjunction device according to Example 24, wherein the layer stack includes a bottom semiconductor layer, wherein in each of the semiconductor layers of the layer stack, each in the first region has a first implantation dose and each in the second implantation region has a second implantation dose, and wherein, at least in a portion of the layer stack, at least one of the first implantation dose and the second implantation dose increases toward the bottom semiconductor layer in that portion of the layer stack.

[0187] Example 26: A superjunction device according to Example 24 or 25, wherein the layer stack includes a bottom semiconductor layer, and wherein, in the second region, the ineffective lateral dopant dose of first type dopant atoms increases toward the bottom semiconductor layer, and in the first region, the ineffective lateral dopant dose of second type dopant atoms increases toward the bottom semiconductor layer.

Claims

1. A method for forming a superjunction device, the method comprising: A superjunction region (1) is formed, the superjunction region (1) comprising a plurality of first regions (11) of a first doping type and a plurality of second regions (12) of a second doping type complementary to the first doping type. The formation of the superjunction region (1) includes: Multiple semiconductor layers (221) are formed on top of each other to form a layer stack (220); A first type of dopant atoms are implanted in each of the semiconductor layers (221) through the opening (311) of the first implantation mask (310) to form a first implantation region (11i); Second type dopant atoms are implanted in each of the semiconductor layers (221) through the opening (321) of the second implantation mask (320) to form a second implantation region (12i); and An annealing process is performed to diffuse and activate the implanted type-1 and type-2 dopant atoms. Each of the first injection mask (310) and the second injection mask (320) has a spacing (p) selected between 3 micrometers and 5 micrometers, and Each of the semiconductor layers (221) has a thickness (d221) selected between 1.9 micrometers and 3.5 micrometers.

2. The method according to claim 1, in, The spacing (p) is selected between 3 micrometers and 4.5 micrometers.

3. The method according to claim 1 or 2, in, The thickness (d221) is selected between 1.9 micrometers and 2.5 micrometers.

4. The method according to any one of claims 1 to 3, in, The width (w311) of the opening (311) in the first injection mask (310) and the width (w321) of the opening (321) in the second injection mask (320) are selected between 20% and 45% of the spacing (p).

5. The method according to any one of claims 1 to 4, in, The annealing process takes place in an oxidizing environment.

6. The method according to any one of claims 1 to 5, in, The stacked layers (220) include a bottom semiconductor layer (2211), Each of the first injection regions (11i) has a first injection dose (A). 11i And each of the second injection regions (12i) has a second injection dose (A) 12i ),and Wherein, the first injection region (11i) and the second injection region (12i) are formed such that, at least in a portion of the layer stack (220), the first injection dose (A) is... 11i ) and the second injection dose (A 12i At least one of the layers increases toward the lowest semiconductor layer (2211) on the portion of the stacked body (220).

7. The method according to claim 6, in, The portion of the stacked structure (220) comprises at least 70% of the semiconductor layer (221) of the stacked structure (220).

8. The method according to claim 7, in, The first injected dose (A) in said portion of the stacked body (220) 11i The maximum value of at least one of the second injection dose and the first injection dose (A) in the portion of the layer stack (220) is greater than that of the first injection dose (A). 11i The minimum value is at least 30% higher.

9. The method according to any one of claims 6 to 8, in, The first injection dose (A) 11i ) and the second injection dose (A 12i At least one of them steadily increases toward the lowest semiconductor layer (2211).

10. The method according to any one of claims 6 to 8, in, The first injection dose (A) 11i ) and the second injection dose (A 12i The at least one of them increases in a stepwise manner toward the lowest semiconductor layer (2211).

11. The method according to any one of claims 6 to 8, in, The first injection dose (A) 11i ) and the second injection dose (A 12i At least one of the layers increases toward the lowest semiconductor layer (2211), such that the lowest layer (221) of the portion of the layer stack increases toward the lowest semiconductor layer (2211). 1+m The first injected dose (A) in ) 11i ) and the second injection dose (A 12i The at least one of the layers in the stack is greater than the uppermost layer (221) of the portion of the stack. N-n The first injected dose (A) in ) 11i ) and the second injection dose (A 12i At least one of the above is more than 30% higher.

12. The method according to any one of claims 6 to 8, in, The first injection dose (A) 11i ) and the second injection dose (A 12i At least one of the layers increases toward the lowest semiconductor layer (2211), such that the three adjacent lowest layers (2211) of the portion of the layer stack increase toward the lowest semiconductor layer (2211). 1+m The first injected dose (A) in ) 11i ) and the second injection dose (A 12i The total dose of at least one of the layers in the stack is greater than that of the three adjacent uppermost layers (221) of the portion of the stack. N-n The first injected dose (A) in ) 11i ) and the second injection dose (A 12i The total dose of at least one of the items mentioned in the document is more than 30% higher.

13. The method according to claim 12, in, The portion of the layer stack includes the entire layer stack.

14. The method according to any one of claims 6 to 13, in, In each of the semiconductor layers (221) of the portion of the layer stack (220), the first implantation dose (A) 11i ) is essentially equal to the second injected dose (A) 12i ).

15. The method according to any one of claims 1 to 14, in, Implanting the first type of dopant atoms into each of the semiconductor layers (221) comprises at least two implantation steps at different implantation energies; and The implantation of the second type of dopant atoms into each of the semiconductor layers (221) includes at least two implantation steps at different implantation energies.

16. The method according to claim 15, in, The at least two injection steps exactly include two injection steps.

17. The method according to any one of claims 1 to 16, in, The number of semiconductor layers (221) in the stacked body (220) is selected between 17 and 21.

18. The method according to any one of claims 1 to 16, in, Forming the layer stack (220) includes forming the layer stack on top of the carrier (210).

19. The method according to claim 18, in, The carrier (210) includes a semiconductor substrate (211) and a semiconductor layer (212) formed on the semiconductor substrate (211).

20. The method according to any one of claims 1 to 19, further comprising: An additional semiconductor layer (230) is formed on top of the stacked body (220); as well as Transistor units (4) are formed that are at least partially integrated in the additional semiconductor layer (230).

21. The method according to claim 20, in, Forming the transistor cell includes performing an annealing process, and The annealing process used to form the transistor unit (4) and the annealing process used to form the superjunction region (1) are the same annealing process.

22. The method according to any one of claims 1 to 21, in, The first injection region (11i) and the second injection region (12i) are formed to be spaced apart in a first lateral direction (x) of the layer stack (220) and to be elongated in a second lateral direction (y) orthogonal to the first lateral direction (x).

23. The method according to any one of claims 1 to 22, in, The semiconductor layer (221) comprises monocrystalline silicon.

24. A superjunction device, comprising: The superjunction region (1) includes a plurality of first regions (11) of a first doping type and a plurality of second regions (12) of a second doping type complementary to the first doping type in the stacked body (220), the stacked body (220) including a plurality of semiconductor layers (221) formed on top of each other to form the stacked body (220). The spacing (p) of the superjunction regions (1) is selected between 3 micrometers and 5 micrometers, and Each of the semiconductor layers (221) has a thickness (d221) selected between 1.9 micrometers and 3.5 micrometers.

25. The superjunction device according to claim 24, in, The stacked layers (220) include a bottom semiconductor layer (2211), In each of the semiconductor layers (221) of the stacked body (220), each of the first regions (11) has a first injection dose (A). 11i And each of the second injection regions (12) has a second injection dose (A) 12i ),and Wherein, at least in a portion of the layer stack (220), the first injected dose (A) 11i ) and the second injection dose (A 12i At least one of the layers increases toward the lowest semiconductor layer (2211) on the portion of the stacked body (220).

26. The superjunction device according to claim 24 or 25, in, The stacked layer (220) includes a bottom semiconductor layer (2211), and In the second region (12), the ineffective lateral dopant dose of the first type of dopant atoms increases toward the bottom semiconductor layer (2211), and in the first region (11), the ineffective lateral dopant dose of the second type of dopant atoms increases toward the bottom semiconductor layer (2211).

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