MOS device with shield gate and method of forming the same
Patent Information
- Application Number
- CN202610955863.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-29
- Publication Date
- 2026-09-29
AI Technical Summary
[0004]本发明的目的在于提供一种具有屏蔽栅的MOS器件及其形成方法，以解决沟槽填充后的多晶硅回刻工艺中，不同开口尺寸的沟槽之间的深度差异的问题
[0027]在本发明提供的一种具有屏蔽栅的MOS器件的形成方法中，衬底内包括至少两个沟槽且相邻沟槽之间的间距满足预设阈值；先执行第一沉积工艺，在沟槽内形成第一屏蔽栅材料层，沟槽内的第一屏蔽栅材料层内形成有孔隙；接着执行第一刻蚀工艺，刻蚀沟槽内的第一屏蔽栅材料层至目标深度，相邻沟槽内的第一屏蔽栅材料层的剩余高度不同；接着执行第二沉积工艺，形成第二屏蔽栅材料层，第二屏蔽栅材料层覆盖第一屏蔽栅材料层并填满沟槽；继续执行第二刻蚀工艺，刻蚀沟槽内的第二屏蔽栅材料层至目标深度，以形成屏蔽栅；最后依次形成栅间隔离层和栅极，栅间隔离层覆盖屏蔽栅，栅极位于栅间隔离层上。本发明通过在第一次多晶硅回刻之后，通过二次沉积工艺在沟槽中补充沉积多晶硅，随后进行第二次回刻，利用二次沉积对刻蚀深度进行补偿和修正，最终获得深度均一性显著改善的多晶硅层。
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Figure CN122846785A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a MOS device with a shielded gate and a method for forming the same. Background Technology
[0002] Power MOSFET devices with shielded gate trench (SGT) structures represent the most advanced power MOSFET technology currently available. They can simultaneously achieve low on-resistance (Rdson) and low reverse recovery capacitance (Crss), thereby reducing both conduction and switching losses and improving system efficiency.
[0003] In existing SGT manufacturing processes, the uniformity of etching depth in polysilicon (poly1) is one of the key factors affecting device performance. However, in the polysilicon etch-back process after trench filling, the depth difference between trenches with different opening sizes has become a long-standing technical challenge. Summary of the Invention
[0004] The purpose of this invention is to provide a MOS device with a shielded gate and a method for forming the same, so as to solve the problem of depth difference between trenches with different opening sizes in the polysilicon etch-back process after trench filling.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a MOS device with a shielding gate, comprising:
[0006] A substrate is provided, wherein the substrate includes at least two trenches and the spacing between adjacent trenches satisfies a preset threshold.
[0007] A first deposition process is performed to form a first shielding grid material layer in the trench, wherein pores are formed in the first shielding grid material layer in the trench.
[0008] A first etching process is performed to etch the first shielding gate material layer in the trench to a target depth, and the remaining height of the first shielding gate material layer in adjacent trenches is different.
[0009] A second deposition process is performed to form a second shielding grid material layer, which covers the first shielding grid material layer and fills the trench.
[0010] A second etching process is performed to etch the second shielding gate material layer within the trench to a target depth to form a shielding gate;
[0011] An inter-gate isolation layer is formed, which covers the shielding gate;
[0012] A gate is formed on the inter-gate isolation layer.
[0013] Optionally, during the second deposition process, the second shielding gate material layer fills the trench and extends to the top surface of the substrate.
[0014] Optionally, the second etching process includes a first sub-etching process and a second sub-etching process.
[0015] Optionally, the first sub-etching process stops etching on the top surface of the substrate, and the second sub-etching process etches the second shielding gate material layer in the trench to the target depth to form the shielding gate.
[0016] Optionally, the inter-gate isolation layer may be formed using a high-density plasma chemical vapor deposition process.
[0017] Optionally, the step of forming the inter-gate isolation layer includes:
[0018] An inter-gate isolation material layer is formed, which covers the shielding gate and extends to the top surface of the substrate;
[0019] A third etching process is performed to etch the inter-gate isolation material layer to the target thickness to form the inter-gate isolation layer.
[0020] Optionally, the step of forming the gate includes:
[0021] The step of forming the gate includes:
[0022] A gate material layer is formed, which fills the trench and extends to the top surface of the substrate;
[0023] A fourth etching process is performed, with etching stopping at the top surface of the substrate, so that the top surface of the gate is flush with the top surface of the substrate.
[0024] Optionally, the gate material layer is made of polycrystalline silicon.
[0025] Optionally, the material of the first shielding gate material layer and the material of the second shielding gate material layer are the same and both are polycrystalline silicon.
[0026] Based on the same inventive concept, the present invention also provides a MOS device with a shielded gate, which is prepared by the method for forming a MOS device with a shielded gate as described above.
[0027] In a method for forming a MOS device with a shielded gate provided by the present invention, the substrate includes at least two trenches with a spacing between adjacent trenches satisfying a preset threshold. First, a first deposition process is performed to form a first shielded gate material layer within the trenches, wherein pores are formed within the first shielded gate material layer within the trenches. Next, a first etching process is performed to etch the first shielded gate material layer within the trenches to a target depth, with different remaining heights of the first shielded gate material layers in adjacent trenches. Then, a second deposition process is performed to form a second shielded gate material layer, which covers the first shielded gate material layer and fills the trenches. The second etching process continues, etching the second shielded gate material layer within the trenches to a target depth to form the shielded gate. Finally, an inter-gate isolation layer and a gate are formed sequentially, with the inter-gate isolation layer covering the shielded gate and the gate located on the inter-gate isolation layer. The present invention, by supplementing the trenches with polysilicon deposition through a secondary deposition process after the first polysilicon etch-back, followed by a second etch-back, utilizes the secondary deposition to compensate and correct the etching depth, ultimately obtaining a polysilicon layer with significantly improved depth uniformity. Attached Figure Description
[0028] Figure 1 This is a flowchart of a method for forming a MOS device with a shielding gate according to an embodiment of the present invention.
[0029] Figure 2 This is a schematic diagram of a MOS device structure with a shielding gate after the formation of the first shielding gate material layer according to an embodiment of the present invention.
[0030] Figure 3 This is a schematic diagram of a MOS device structure with a shielded gate after the first etching process is performed according to an embodiment of the present invention.
[0031] Figure 4 This is a schematic diagram of the MOS device structure with a shielding gate after the formation of the second shielding gate material layer according to an embodiment of the present invention.
[0032] Figure 5 This is a schematic diagram of a MOS device structure with a shielded gate after the second etching process is performed according to an embodiment of the present invention.
[0033] Figure 6 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of an inter-gate isolation material layer according to an embodiment of the present invention.
[0034] Figure 7 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of an inter-gate isolation layer according to an embodiment of the present invention.
[0035] Figure 8 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of the gate material layer according to an embodiment of the present invention.
[0036] Figure 9 This is a schematic diagram of a MOS device structure with a shielded gate after the gate is formed, according to an embodiment of the present invention.
[0037] Figure 10 This is a SEM image of a MOS device with a shielded gate according to an embodiment of the present invention.
[0038] In the figure: 10-substrate; 11-trench; 12-gate oxide layer; 13-shielding gate; 13a-first shielding gate material layer; 13b-second shielding gate material layer; 14-pore; 15-inter-gate isolation layer; 15a-inter-gate isolation material layer; 16-gate; 16a-gate material layer. Detailed Implementation
[0039] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.
[0040] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.
[0041] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.
[0042] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values that vary within, for example, 10% of the value. It is understood that for numerical values not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values described in the embodiments are merely exemplary.
[0043] Figure 1 This is a flowchart illustrating a method for forming a MOS device with a shielded gate according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a MOS device with a shielded gate, including:
[0044] Step S10: Provide a substrate, wherein the substrate includes at least two trenches and the spacing between adjacent trenches satisfies a preset threshold.
[0045] Step S20: Perform the first deposition process to form a first shielding grid material layer in the trench, wherein pores are formed in the first shielding grid material layer in the trench;
[0046] Step S30: Perform the first etching process to etch the first shielding gate material layer in the trench to the target depth. The remaining height of the first shielding gate material layer in adjacent trenches is different.
[0047] Step S40: Perform a second deposition process to form a second shielding grid material layer, which covers the first shielding grid material layer and fills the trench;
[0048] Step S50: Perform a second etching process to etch the second shielding gate material layer in the trench to the target depth to form a shielding gate;
[0049] Step S60: Form an inter-gate isolation layer, which covers the shielding gate;
[0050] Step S70: Form a gate, which is located on the inter-gate isolation layer.
[0051] Figures 2 to 9 This is a schematic diagram showing the structural steps corresponding to the formation method of a MOS device with a shielded gate according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 9 Specific embodiments of the present invention will be described in detail below.
[0052] Figure 2 This is a schematic diagram of a MOS device structure with a shielding gate after the formation of the first shielding gate material layer, according to an embodiment of the present invention. Figure 2 As shown, in step S10, a substrate 10 is provided. The substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate. The substrate 10 includes at least two trenches 11, and the spacing d between adjacent trenches 11 satisfies a preset threshold; the preset threshold can be the minimum spacing allowed by the process.
[0053] Please continue to refer to this. Figure 1In step S20, a first deposition process is performed to form a first shielding gate material layer 13a within the trench 11, and pores 14 are formed within the first shielding gate material layer 13a within the trench 11. The material of the first shielding gate material layer 13a is, for example, polycrystalline silicon, and the first deposition process is, for example, chemical vapor deposition. When the pitch between adjacent trenches 11 is relatively small, pores 14 are more likely to appear in the first shielding gate material layer 13a formed within the trench 11.
[0054] Figure 3 This is a schematic diagram of a MOS device structure with a shielded gate after performing the first etching process according to an embodiment of the present invention. In step S30, the first etching process is performed to etch the first shielded gate material layer 13a in the trench 11 to a target depth. The depths of the first shielded gate material layer 13a in adjacent trenches 11 are different. The first etching process is, for example, a dry etching process. Since some trenches 11 have pores 14, during the first etching process, the etching depth h2 of the first shielded gate material layer 13a in the trench with pores 14 will be greater than the etching depth h1 of the first shielded gate material layer 13a in the trench without pores 14. That is, if h1 is the target depth, then h2 is greater than the target depth. In other words, the remaining height of the first shielded gate material layer 13a in the trench with pores 14 is less than the remaining height of the first shielded gate material layer 13a in the trench without pores 14. The remaining heights of the first shielded gate material layer 13a in different trenches 11 are different, resulting in poor uniformity.
[0055] Figure 4 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of the second shielding gate material layer according to an embodiment of the present invention. In step S40, a second deposition process is performed to form a second shielding gate material layer 13b, which covers the first shielding gate material layer 13a and fills the trench 11. The material of the second shielding gate material layer 13b is, for example, polysilicon, and the second deposition process is, for example, chemical vapor deposition. During the second deposition process, the second shielding gate material layer 13b fills the trench 11 and extends to the top surface of the substrate 10.
[0056] Figure 5This is a schematic diagram of a MOS device structure with a shielded gate after performing the second etching process according to an embodiment of the present invention. In step S50, the second etching process is performed to etch the second shielded gate material layer 13b in the trench 11 to a target depth to form the shielded gate 13. The second etching process is, for example, a dry etching process. The second etching process includes a first sub-etching process and a second sub-etching process. The first sub-etching process stops etching at the top surface of the substrate 10, and the second sub-etching process etches the second shielded gate material layer 13b in the trench 11 to the target depth to form the shielded gate 13. The first sub-etching process removes excess second shielded gate material layer 13b from the substrate surface to prevent short circuits and to create a flat, uniform starting surface for subsequent precise control of the shielded gate height. The etching gas in the first sub-etching process includes, for example, Cl2. The etching gas in the second etching process includes HBr (hydrogen bromide). The Br· radicals generated by HBr can form a dense sidewall protective layer, ensuring that the etched shielded gate has vertical sides and a flat top. The first sub-etching process typically employs higher pressure and lower bias voltage, primarily focusing on isotropic etching to improve etching efficiency. The higher pressure is, for example, greater than 50 mTorr. The second sub-etching process uses an ICP / RIE mode with a higher bias voltage to achieve a strongly anisotropic vertical etching effect. The lower pressure is, for example, 5 mTorr-30 mTorr. Those skilled in the art can adjust the first and second sub-etching processes according to specific circumstances.
[0057] In other embodiments, the first sub-etching process can also be a chemical mechanical polishing process. That is, even if the thickness of the second shielding gate material layer 13b on the substrate 10 of adjacent trenches is different, it does not affect the height of the shielding gate 13 in the final formed trench 11. In this embodiment, polysilicon is deposited in the trench through a secondary deposition process, followed by a second etch, and the etching depth is compensated and corrected by the secondary deposition, finally obtaining a shielding gate 13 with significantly improved depth uniformity.
[0058] Figure 6 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of an inter-gate isolation material layer according to an embodiment of the present invention. Figure 7 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of an inter-gate isolation layer, according to an embodiment of the present invention. Figure 6 and Figure 7 As shown, in step S60, an inter-gate isolation layer 15 is formed, which covers the shielding gate 13. The step of forming the inter-gate isolation layer 15 includes: as follows Figure 6 As shown, an inter-gate isolation material layer 15a is formed, which covers the shielding gate 13 and extends to the top surface of the substrate 10. The inter-gate isolation material layer 15a is made of silicon oxide and can be formed using a high-density plasma chemical vapor deposition process. Figure 7As shown, a third etching process is performed to etch the inter-gate isolation material layer 15a to the target thickness to form the inter-gate isolation layer 15.
[0059] Figure 8 This is a schematic diagram of a MOS device structure with a shielded gate after the formation of the gate material layer according to an embodiment of the present invention. Figure 9 This is a schematic diagram of a MOS device structure with a shielded gate after the gate has been formed, according to an embodiment of the present invention. Figure 8 and Figure 9 As shown, in step S70, a gate 16 is formed, and the gate 16 is located on the inter-gate isolation layer 15. The step of forming the gate 16 includes: as shown in the figure. Figure 8 As shown, a gate material layer 16a is formed, which fills the trench 11 and extends to the top surface of the substrate 10. The gate material layer 16a is made of polysilicon. Figure 9 As shown, the fourth etching process is performed, and the etching stops at the top surface of the substrate 10 so that the top surface of the gate 16 is flush with the top surface of the substrate 10.
[0060] Please continue to refer to this. Figure 9 This embodiment also provides a MOS device with a shielded gate, which is fabricated using the method for forming a MOS device with a shielded gate as described above.
[0061] Figure 10 This is a SEM image of a MOS device with a shielded gate according to an embodiment of the present invention. For example... Figure 10 As shown, the height uniformity of the shielding gate 13 of the MOS device with shielding gate is consistent. In other words, the height uniformity of the shielding gate 13 of the MOS device with shielding gate in this embodiment is improved, thereby increasing the yield of the device.
[0062] In summary, in the method for forming a MOS device with a shielded gate provided in this embodiment of the invention, the substrate includes at least two trenches with the spacing between adjacent trenches meeting a preset threshold. First, a first deposition process is performed to form a first shielded gate material layer within the trenches, with pores formed within the first shielded gate material layer. Next, a first etching process is performed to etch the first shielded gate material layer within the trenches to a target depth, with different remaining thicknesses in adjacent trenches. Then, a second deposition process is performed to form a second shielded gate material layer, which covers the first shielded gate material layer and fills the trenches. The second etching process continues, etching the second shielded gate material layer within the trenches to a target depth to form a shielded gate. Finally, an inter-gate isolation layer and a gate are formed sequentially, with the inter-gate isolation layer covering the shielded gate and the gate located on the inter-gate isolation layer. This invention, by supplementing the trenches with polysilicon deposition through a secondary deposition process after the first polysilicon etch-back, followed by a second etch-back, utilizes the secondary deposition to compensate and correct the etching depth, ultimately obtaining a polysilicon layer with significantly improved depth uniformity.
[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming a MOS device with a shielded gate, characterized in that, include: A substrate is provided, wherein the substrate includes at least two trenches and the spacing between adjacent trenches satisfies a preset threshold. A first deposition process is performed to form a first shielding grid material layer in the trench, wherein pores are formed in the first shielding grid material layer in the trench. A first etching process is performed to etch the first shielding gate material layer in the trench to a target depth, and the remaining height of the first shielding gate material layer in adjacent trenches is different. A second deposition process is performed to form a second shielding grid material layer, which covers the first shielding grid material layer and fills the trench. A second etching process is performed to etch the second shielding gate material layer within the trench to a target depth to form a shielding gate; An inter-gate isolation layer is formed, which covers the shielding gate; A gate is formed on the inter-gate isolation layer.
2. The method for forming a MOS device with a shielded gate as claimed in claim 1, characterized in that, During the second deposition process, the second shielding gate material layer fills the trench and extends to the top surface of the substrate.
3. The method for forming a MOS device with a shielded gate as claimed in claim 2, characterized in that, The second etching process includes a first sub-etching process and a second sub-etching process.
4. The method for forming a MOS device with a shielded gate as claimed in claim 3, characterized in that, The first sub-etching process stops etching on the top surface of the substrate, and the second sub-etching process etches the second shielding gate material layer in the trench to the target depth to form the shielding gate.
5. The method for forming a MOS device with a shielded gate as claimed in claim 1, characterized in that, The inter-gate isolation layer is formed using a high-density plasma chemical vapor deposition process.
6. The method for forming a MOS device with a shielded gate as claimed in claim 1, characterized in that, The steps for forming the inter-gate isolation layer include: An inter-gate isolation material layer is formed, which covers the shielding gate and extends to the top surface of the substrate; A third etching process is performed to etch the inter-gate isolation material layer to the target thickness to form the inter-gate isolation layer.
7. The method for forming a MOS device with a shielded gate as claimed in claim 1, characterized in that, The step of forming the gate includes: A gate material layer is formed, which fills the trench and extends to the top surface of the substrate; A fourth etching process is performed, with etching stopping at the top surface of the substrate, so that the top surface of the gate is flush with the top surface of the substrate.
8. The method for forming a MOS device with a shielded gate as claimed in claim 7, characterized in that, The gate material layer is made of polycrystalline silicon.
9. The method for forming a MOS device with a shielded gate as claimed in claim 1, characterized in that, The material of the first shielding gate material layer and the material of the second shielding gate material layer are the same, and both are polycrystalline silicon.
10. A MOS device with a shielded gate, characterized in that, It is prepared by the method for forming a MOS device with a shielded gate as described in any one of claims 1 to 9.