Metal gate cut process method

Abstract

The application discloses a metal gate cutting process method, which comprises the following steps: performing back etching of an interlayer film to form a groove in a spacing region between metal gates, the bottom surface of the groove being higher than the highest surface of an active region located on the side surface of the metal gate; filling a cutting protection layer in the groove; forming a hard mask layer and performing patterned etching on the hard mask layer to form a first groove; performing metal gate cutting etching to completely remove the metal gate in the first groove opening region, wherein the cutting protection layer stops the metal gate cutting etching on the cutting protection layer in the spacing region opened by the first groove, and a second groove is formed after the metal gate cutting etching is completed; and filling a first dielectric layer in the second groove. The application can realize complete cutting of the metal gate in the cutting region, reduce cutting of the interlayer film in the cutting region, and prevent damage to the epitaxial structure of the active region adjacent to the cutting region when the interlayer film is cut too much in the transverse and longitudinal directions.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for metal gate dicing. Background Technology

[0002] In some current device manufacturing processes, due to process window considerations, gate etching has gradually shifted from front-end processes to mid-end processes, that is, from pseudo-gate forming processes to pseudo-gate cutting processes, and then to metal gate cutting processes.

[0003] Currently, there are generally two paths for dummy gate dicing: partial gate removal and full gate removal. The main difference lies in the etch-back depth of the dielectric interlayer (interlayer film) between the gate and the dielectric layer. In full gate removal, the etch-back depth of the dielectric layer is roughly equal to the etch-back depth at the gate, while in partial gate removal, the etch-back interface of the dielectric layer is roughly equal to the top height of the convex strip structure in the active region. Considering the risk of damage to the epitaxial layer (epi) if it is embedded in the active region, dummy gate dicing typically adopts the partial gate removal mode. In contrast, metal gate dicing, to remove heavier metal byproducts and high-k dielectric (HK) materials, requires a more robust dielectric etching step and employs a full gate removal process.

[0004] In current manufacturing processes, to achieve miniaturization, the gate cut and the active region are positioned even closer together.

[0005] In the metal gate dicing process, excessive dielectric etching inevitably leads to dielectric layer lateral push, that is, the critical dimensions of the dielectric isolation layer increase to a certain extent.

[0006] The miniaturization of the device and the side-pushing of the dielectric layer by the metal gate cutting process make the metal gate cutting process very easy to damage the epi structure in terms of physical size, resulting in loss of device electrical performance. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a metal gate cutting process that can completely cut the metal gate in the cutting region while reducing the cutting of the interlayer film in the cutting region, thereby preventing damage to the epitaxial structure of the active region adjacent to the cutting region when the interlayer film is cut too much in the lateral and longitudinal directions.

[0008] To solve the above-mentioned technical problems, the metal gate cutting process method provided by the present invention includes the following steps: An interlayer film is etched back to form a groove in the spacer region between the metal gates, the bottom surface of which is higher than the highest surface of the active region located on the side of the metal gate.

[0009] A cutting protective layer is filled in the groove, and the material of the cutting protective layer is different from that of the interlayer film.

[0010] A hard mask layer is formed and the hard mask layer is patterned and etched to form a first trench, the first trench defining a metal gate dicing region, the first trench intersecting with the metal gate to be diced and extending into the spacer region adjacent to the metal gate to be diced and located between the active regions.

[0011] Using the hard mask layer as a mask, metal gate cutting and etching are performed to remove all the metal gate in the first trench opening area. In the interval area opened by the first trench, the cutting protection layer stops the metal gate cutting and etching on the cutting protection layer, so that the interlayer film at the bottom of the cutting protection layer is retained. After the metal gate cutting and etching is completed, a second trench is formed.

[0012] The second trench is filled with a first dielectric layer.

[0013] A further improvement is that each of the active regions has a convex strip structure and is formed by patterned etching of a semiconductor substrate.

[0014] A further improvement is that an embedded epitaxial layer is formed in the active region on the side of the metal gate to improve the stress in the channel region of the device and enhance the carrier mobility.

[0015] A further improvement is that the material of the interlayer film includes an oxide layer.

[0016] A further improvement is that the material of the cutting protective layer includes a nitrided layer.

[0017] A further improvement is that the hard mask layer and the cutting protection layer are made of the same material.

[0018] A further improvement is that the metal gate is obtained by gate replacement of a dummy gate, and the gate replacement includes planarization of the metal gate.

[0019] A further improvement is that the etchback of the interlayer film is performed after the metal gate is planarized.

[0020] After the groove is formed, the cutting protective layer and the hard mask layer are formed simultaneously using the same process.

[0021] A further improvement is that, prior to the gate replacement, a planarization process is performed on the interlayer film to make the top surface of the interlayer film and the top surface of the dummy gate flush.

[0022] The etching back of the interlayer film is performed after the planarization process of the interlayer film is completed.

[0023] The cutting protective layer and the hard mask layer are formed separately and independently.

[0024] A further improvement is that the thickness of the cutting protective layer is 200 Å to 500 Å.

[0025] A further improvement is that the etch back of the interlayer film is achieved using gas dry etching.

[0026] A further improvement is that the gas used in the dry etching process includes C4F6.

[0027] A further improvement is that, after the hard mask layer is formed, the step of forming a capping layer composed of an oxide layer on the top surface of the hard mask layer is also included.

[0028] A further improvement is that the first dielectric layer is formed by a deposition process, and after the deposition process of the first dielectric layer is completed, the first dielectric layer completely fills the second trench and extends to the outer surface of the second trench.

[0029] The process then includes performing a first CMP to remove the first dielectric layer outside the second trench.

[0030] A further improvement is that the first CMP or the first CMP combined with etching also removes the cutting protective layer, the hard mask layer and the first dielectric layer above the bottom surface of the cutting protective layer.

[0031] This invention adds a step of re-etching the interlayer film and filling the groove formed by the re-etching into the groove before the metal gate is etched. Thus, during the metal gate etching process, since no cutting protective layer is formed on top of the metal gate, it can be removed. However, in the area defined by the first trench, the interlayer film adjacent to the metal gate has a cutting protective layer on top, so the interlayer film is not etched. Compared to existing methods where the interlayer film is completely removed and the removal area is laterally expanded to completely remove the metal gate, the top surface position of the interlayer film in this invention is entirely determined by the re-etching process of the interlayer film before the metal gate is etched. Therefore, the situation where the top surface of the interlayer film in the area defined by the first trench descends or is completely removed does not occur, achieving a semi-removal process in metal gate etching. Furthermore, since the top surface of the interlayer film does not descend, the region between the metal gates remains as defined by the first trench, avoiding the lateral expansion of the second trench in the region between the metal gates as seen in existing methods. Because the position of the top surface of the interlayer film within the second trench in the region between the metal gates can be controlled, and the lateral position of the second trench can also be precisely controlled, the problem of damage to epitaxial layers, such as embedded epitaxial layers, formed in adjacent active regions when the second trench in the region between the metal gates expands laterally and the interlayer film is longitudinally etched too deeply can be eliminated. Therefore, this invention can achieve complete cutting of the metal gates in the cutting region while reducing the cutting of the interlayer film in the cutting region, thereby preventing damage to the epitaxial structure of the active region adjacent to the cutting region when the interlayer film is cut too much laterally and longitudinally.

[0032] Since this invention does not damage the epitaxial structure of the active region adjacent to the metal gate dicing region, the integrity of the active region epitaxial layer (EPI) is protected, the active region carrier concentration is maintained, and the driving current can be maintained at an ideal level.

[0033] Furthermore, since the key dimensions, such as the width, of the metal gate dicing region on the interlayer film (ILD) layer are controlled in this invention, the second trench can be completely filled when the isolation layer, i.e. the first dielectric layer, is subsequently filled in the second trench. Therefore, the problem of insufficient filling when filling the isolation layer in the second trench can be avoided. In turn, the defect of abnormal metal filling that may occur at the intersection with the metal gate dicing region when forming subsequent metal layers, such as the zeroth metal layer, can be avoided, thereby reducing the risk of leakage current. Attached Figure Description

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figures 1-5 This is a schematic diagram of the device cross-sectional structure in each step of the existing metal gate cutting process. Figure 6 yes Figure 3 Corresponding top view structural diagram; Figure 7 It is along Figure 6 A schematic diagram of the cross-sectional structure at the centerline CC; Figure 8 This is a flowchart of the metal gate cutting process method according to an embodiment of the present invention; Figures 9-14 This is a schematic diagram of the device cross-sectional structure in each step of the metal gate cutting process method according to an embodiment of the present invention; Figure 15 yes Figure 12 The corresponding top view structural diagram. Detailed Implementation

[0035] The embodiments of the present invention are derived based on the analysis of the technical problems of existing metal gate cutting processes. Before describing the embodiments of the present invention in detail, the existing metal gate cutting processes are explained as follows: like Figures 1 to 5 The diagram shown is a schematic cross-sectional view of the device in each step of the existing metal gate cutting process. Figure 6 yes Figure 3 Corresponding top view structural diagram; Figure 7 It is along Figure 6 A schematic diagram of the cross-sectional structure at the center line CC; existing metal gate cutting processes include: like Figure 1 As shown, a device structure is provided to complete the planarization of the metal gate 103. Figure 1 The corresponding section position is located at Figure 6 At point AA (center line). An interlayer film 102 is present between the metal gates 103. Figure 6 As shown, line AA is located in the active region between 109, therefore Figure 1 The active region 109 is not shown in the corresponding cross-section. Figure 1 The dashed box 104 represents the formation region of the active region 109, that is, along the perpendicular to Figure 1 Viewed in cross-sectional direction, after passing through the interlayer membrane 102, the outline of the cross-sectional view corresponding to the active region 109 corresponds to the dashed frame 104, but in Figure 9 In the diagram, the active region 109 cannot be observed, so it is represented by a dashed line.

[0036] The metal gate 103 is obtained by gate replacement of a dummy gate. After the gate replacement is completed, the metal gate 103 is further planarized. During the gate replacement process, the metal gate 103 extends beyond the gate trench corresponding to the dummy gate removal region after filling. Therefore, planarization is required to remove the metal gate 103 outside the gate trench and make the top surface of the metal gate 103 flush with the top surface of the interlayer film 102.

[0037] Prior to the gate replacement, a planarization process is performed on the interlayer film 102 to make the top surface of the interlayer film 102 and the top surface of the dummy gate flush.

[0038] Each of the active regions 109 has a convex strip-shaped structure and is formed by patterning etching of a semiconductor substrate. Shallow trench isolation 101 is also formed between the active regions 109, with the top surface of the shallow trench isolation 101 lower than the top surface of the active regions 109, thus giving the active regions 109 their convex strip-shaped structure. When the stripe of the metal gate 103 intersects with the stripe of the active region 109, the metal gate 103 simultaneously covers both the top surface and the side surface of the active region 109.

[0039] Depend on Figure 6 As shown, an embedded epitaxial layer 110 is also formed in the active region 109 corresponding to a portion of the side surface of the metal gate 103. The embedded epitaxial layer 110 is used to improve the stress in the channel region of the device and thereby improve the carrier mobility in the channel region. For example, for NMOS, the material of the embedded epitaxial layer 110 includes SiP; for PMOS, the material of the embedded epitaxial layer 110 includes SiGe.

[0040] The material of the interlayer membrane 102 includes an oxide layer.

[0041] like Figure 2 As shown, a hard mask layer 105 is formed.

[0042] The material of the hard mask layer 105 is typically a nitrided layer.

[0043] After the hard mask layer 105 is formed, the method further includes the step of forming a capping layer 106 composed of an oxide layer on the top surface of the hard mask layer 105.

[0044] like Figure 3 As shown, the hard mask layer 105 is patterned and etched to form a first trench. The first trench defines a cutting region for the metal gate 103. The first trench intersects with the metal gate 103 to be cut and extends to the spacer region adjacent to the metal gate 103 to be cut and located between the active regions 109. Figure 6As shown, Figure 3 The image shows the intersection of the first trench and the two metal gates 103.

[0045] like Figure 3 As shown, the hard mask layer 105 is used as a mask for metal gate dicing and etching to completely remove the metal gate 103 in the first trench opening area. In the interval area opened by the first trench, the dicing protection layer 303 also completely removes the interlayer film 102, that is, a full wall removal process is adopted. After the metal gate dicing and etching is completed, a second trench 107 is formed.

[0046] like Figure 6 As shown, the width of the second trench 107 is not uniform at various locations. Only in the region corresponding to the metal gate 103 is the width of the second trench 107 d1; however, in the spacing region of the metal gate 107, due to the lateral push of the interlayer film 102, the width of the second trench 107 increases to d2. Therefore, the spacing between the second trench 107 and the embedded epitaxial layer 110 is greatly reduced. Especially with the miniaturization of the critical dimensions of the device, the spacing between the active regions 109, and further, the spacing between the second trench 107 and the embedded epitaxial layer 110, can easily damage the embedded epitaxial layer 110 during the metal gate dicing and etching.

[0047] like Figure 4 As shown, the second trench 107 is filled with a first dielectric layer 108.

[0048] like Figure 4 As shown, the first dielectric layer 108 is formed by a deposition process. After the deposition process of the first dielectric layer 108 is completed, the first dielectric layer 108 completely fills the second trench 107 and extends to the outer surface of the second trench 107. The material of the first dielectric layer 108 is typically a nitride layer, and therefore the same as the material of the hard mask layer 105. Figure 4 The same fill pattern is used to represent them.

[0049] like Figure 5 As shown, the process then includes CMP to remove the first dielectric layer 108 outside the second trench 107, and the hard mask layer 105 is also removed at the same time.

[0050] like Figure 7As can be seen, during the metal gate cutting and etching, the interlayer film 102 in the spacer region between the metal gates 103 will be pushed laterally, which will reduce the gap between the second trench 107 and the embedded epitaxial layer 110 or even expose the embedded epitaxial layer 110 to the second trench 107, so the embedded epitaxial layer 110 is very easy to be damaged.

[0051] like Figure 8 The diagram shown is a flowchart of the metal gate 203 cutting process according to an embodiment of the present invention; as shown Figures 9 to 14 The diagram shown is a schematic cross-sectional view of the device in each step of the metal gate 203 cutting process method according to an embodiment of the present invention. Figure 15 yes Figure 12 The corresponding top view structural diagram; the metal gate 203 cutting process method of this embodiment includes the following steps: Step S101, as follows Figure 9 As shown, a device structure is provided to complete the planarization of the metal gate 203. Figure 9 The cross-sectional position corresponds to Figure 15 At point AA (center line). An interlayer film 202 is present between the metal gates 203. Figure 15 As shown, line AA is located within the active region 209, therefore Figure 9 The active region 209 is not shown in the corresponding cross-section.

[0052] Figure 9 The dashed box 204 represents the formation region of the active region 209, that is, along the perpendicular to Figure 1 Viewed in cross-sectional direction, after passing through the interlayer membrane 202, the outline of the cross-sectional view corresponding to the active region 209 corresponds to the dashed frame 204, but in Figure 9 In the diagram, the active region 209 cannot be observed, so it is represented by a dashed line.

[0053] In this embodiment of the invention, the metal gate 203 is obtained by gate replacement of a dummy gate. After the gate replacement is completed, the metal gate 203 is further planarized. During the gate replacement process, the metal gate 203 extends beyond the gate trench corresponding to the dummy gate removal region after filling; therefore, planarization is required to remove the metal gate 203 outside the gate trench and make the top surface of the metal gate 203 flush with the top surface of the interlayer film 202.

[0054] Prior to the gate replacement, a planarization process is performed on the interlayer film 202 to make the top surface of the interlayer film 202 and the top surface of the dummy gate flush.

[0055] In this embodiment of the invention, each active region 209 has a convex strip-shaped structure and is formed by patterning etching of a semiconductor substrate. Shallow trench isolation 201 is also formed between the active regions 209, and the top surface of the shallow trench isolation 201 is lower than the top surface of the active regions 209, thus the active regions 209 have a convex strip-shaped structure. When the stripe of the metal gate 203 intersects with the stripe of the active region 209, the metal gate 203 simultaneously covers the top surface and side surface of the active region 209.

[0056] Depend on Figure 15 As shown, an embedded epitaxial layer 210 is also formed in the active region 209 corresponding to a portion of the side surface of the metal gate 203. The embedded epitaxial layer 210 is used to improve the stress in the channel region of the device and thereby improve the carrier mobility in the channel region. For example, for NMOS, the material of the embedded epitaxial layer 210 includes SiP; for PMOS, the material of the embedded epitaxial layer 210 includes SiGe.

[0057] In this embodiment of the invention, the material of the interlayer membrane 202 includes an oxide layer.

[0058] like Figure 10 As shown, the interlayer film 202 is etched back to form a groove 301 in the spacer region between the metal gates 203. The bottom surface of the groove 301, i.e., surface 302, is higher than the highest surface of the active region 209 located on the side of the metal gate 203. When an embedded epitaxial layer 210 is formed in the active region 209, surface 302 is higher than the top surface of the embedded epitaxial layer 210.

[0059] In some embodiments, the etch-back of the interlayer film 202 is achieved using gas dry etching. The gas used in the gas dry etching includes C4F6.

[0060] In some embodiments, the gas dry etching is performed using a Certas etching apparatus.

[0061] Step S102, as follows Figure 11 As shown, the groove 301 is filled with a cutting protective layer 303, and the material of the cutting protective layer 303 is different from the material of the interlayer film 202.

[0062] In this embodiment of the invention, the material of the cutting protective layer 303 includes a nitrided layer.

[0063] In some embodiments, the thickness of the cutting protective layer 303 is 200 Å to 500 Å. The etching depth of the groove 301 is set according to the thickness of the cutting protective layer 303.

[0064] Step S103, as follows Figure 11As shown, a hard mask layer 205 is formed.

[0065] In this embodiment of the invention, the hard mask layer 205 and the cutting protection layer 303 are made of the same material. Figure 11 In this process, after the hard mask layer 205 is formed, the hard mask layer 205 and the cutting protection layer 303 form an integral structure and are represented by the same filling pattern.

[0066] In this embodiment of the invention, the etch-back of the interlayer film 202 is performed after the metal gate 203 has been planarized.

[0067] After the groove 301 is formed, the cutting protective layer 303 and the hard mask layer 205 are formed simultaneously using the same process.

[0068] In other embodiments, the etching back of the interlayer film 202 may be performed after the planarization process of the interlayer film 202 is completed.

[0069] The cutting protective layer 303 and the hard mask layer 205 are formed separately and independently.

[0070] In this embodiment of the invention, after the hard mask layer 205 is formed, the method further includes forming a capping layer 206 composed of an oxide layer on the top surface of the hard mask layer 205.

[0071] like Figure 12 As shown, the hard mask layer 205 is patterned and etched to form a first trench 207a. The first trench 207a defines a cutting region of the metal gate 203. The first trench 207a intersects with the metal gate 203 to be cut and extends to the spacer region adjacent to the metal gate 203 to be cut and located between the active regions 209. Figure 12 The image shows the intersection of the first trench 207a and the two metal gates 203.

[0072] Step S104, as follows Figure 12 As shown, the metal gate is etched using the hard mask layer 205 as a mask to remove all the metal gate 203 in the open area of ​​the first trench 207a. In the gap area opened by the first trench 207a, the cutting protection layer 303 stops the metal gate etching on the cutting protection layer 303, so that the interlayer film 202 at the bottom of the cutting protection layer 303 is retained. After the metal gate etching is completed, the second trench 207b is formed.

[0073] After the second trench 207b is formed, Figure 12 The corresponding cross-sectional position is shown in line BB.

[0074] Depend on Figure 12 As shown, at the bottom of the first trench 207a, only the metal gate 203 is removed, while the interlayer film 202 remains. Therefore, the second trench 207b includes a gate trench formed by removing the metal gate 203; the interlayer film 202 is still retained between the two gate trenches. Since the interlayer film 202 is retained, the metal gate dicing and etching is a semi-removal process.

[0075] like Figure 15 As shown, the width of the second groove 207b at all locations is d1. Therefore, the critical dimension of the second groove 207b, namely its width, can be precisely controlled, avoiding the problems encountered in existing methods. Figure 6 The corresponding defect is that the width of the interval region increases to d2.

[0076] At the same time, by Figure 12 As shown, at each location, the top surface of the interlayer membrane 202 is located on surface 302, and surface 302 is higher than... Figure 15 The height of the top surface of the embedded epitaxial layer 210 is such that the second trench 207b has a height difference between the bottom surface 302 of the spacing region and the top surface of the embedded epitaxial layer 210. Furthermore, in the lateral position, the side surface of the second trench 207b and the side surface of the embedded epitaxial layer 210 are significantly spaced apart. Therefore, the metal gate etch corresponding to the second trench 207b will not damage the embedded epitaxial layer 210.

[0077] Step S105, as follows Figure 13 As shown, the second trench 207b is filled with a first dielectric layer 208.

[0078] In embodiments of the present invention, such as Figure 13 As shown, the first dielectric layer 208 is formed by a deposition process. After the deposition process of the first dielectric layer 208 is completed, the first dielectric layer 208 completely fills the second trench 207b and extends to the outer surface of the second trench 207b.

[0079] In some embodiments, the first dielectric layer 208 is also made of a nitride layer, and therefore has the same material as the hard mask layer 205. Figure 13 The same filling pattern is used in the first dielectric layer 208. In other embodiments, other materials may be selected as needed.

[0080] like Figure 14As shown, the process then includes performing a first CMP to remove the first dielectric layer 208 outside the second trench 207b. Preferably, the first CMP, or the first CMP combined with etching, also removes the cutting protection layer 303, the hard mask layer 205, and the first dielectric layer 208 above the bottom surface of the cutting protection layer 303.

[0081] In this embodiment of the invention, before the metal gate dicing and etching, a step of re-etching the interlayer film 202 and filling the groove 301 formed by the re-etching with a cutting protection layer 303 is added. Thus, during the metal gate dicing and etching process, since the top of the metal gate 203 does not have a cutting protection layer 303, the metal gate 203 can be removed. However, in the dicing area of ​​the metal gate 203, i.e., the area defined by the first trench 207a, the top of the interlayer film 202 adjacent to the metal gate 203 has a cutting protection layer 303, so the interlayer film 202 will not be diced. Compared to existing methods where the interlayer film 202 is completely removed and the removal area of ​​the interlayer film 202 is laterally expanded to completely remove the metal gate 203, in this embodiment of the invention, the position of the top surface of the interlayer film 202 is entirely determined by the re-etching process of the interlayer film 202 before the metal gate 203 is diced. Therefore, the situation where the top surface of the interlayer film 202 in the area defined by the first trench 207a descends or is completely removed will not occur. This achieves the use of [missing information - likely a specific method or technique] in the dicing of the metal gate 203. The process involves a partial wall removal; simultaneously, since the top surface of the interlayer film 202 does not descend, the area between the metal gates 203 remains as defined by the first trench 207a, avoiding the lateral expansion of the second trench 207b in the area between the metal gates 203 as seen in existing methods. Because the position of the top surface of the interlayer film 202 within the second trench 207b in the area between the metal gates 203 can be controlled, and the lateral position of the second trench 207b can be precisely controlled, the problem of damage to epitaxial layers, such as embedded epitaxial layers, formed in adjacent active regions 209 when the second trench 207b in the area between the metal gates 203 expands laterally and the interlayer film 202 is longitudinally etched too deeply can be eliminated. Therefore, this embodiment of the invention can achieve complete cutting of the metal gates 203 in the cutting area while reducing the cutting of the interlayer film 202 in the cutting area, thereby preventing damage to the epitaxial structure of the adjacent active regions 209 when the interlayer film 202 is cut too much laterally and longitudinally.

[0082] Since the embodiments of the present invention do not damage the epitaxial structure of the active region 209 adjacent to the metal gate 203 cutting region, the integrity of the epitaxial layer (EPI) of the active region 209 is protected, the carrier concentration of the active region 209 is maintained, and the driving current can be maintained at an ideal level.

[0083] Furthermore, since the key dimensions, such as the width, of the metal gate 203 dicing region on the interlayer film 202 layer in this embodiment of the invention are controlled, the second trench 207b can be completely filled when the isolation layer, i.e. the first dielectric layer 208, is subsequently filled into the second trench 207b. Therefore, the problem of insufficient filling when filling the isolation layer into the second trench 207b can be avoided. In turn, the defect of abnormal metal filling that may occur at the intersection with the metal gate 203 dicing region when forming subsequent metal layers, such as the zeroth metal layer, can be avoided, thereby reducing the risk of leakage.

[0084] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A metal gate cutting process, characterized in that, Includes the following steps: An interlayer film is etched back to form a groove in the spacer region between the metal gates, the bottom surface of the groove being higher than the highest surface of the active region located on the side of the metal gate; A cutting protective layer is filled in the groove, and the material of the cutting protective layer is different from the material of the interlayer film. A hard mask layer is formed and the hard mask layer is patterned and etched to form a first trench, the first trench defining a metal gate dicing region, the first trench intersecting with the metal gate to be diced and extending into the spacer region adjacent to the metal gate to be diced and located between the active regions. Using the hard mask layer as a mask, metal gate cutting and etching are performed to remove all the metal gate in the first trench opening area. In the interval area opened by the first trench, the cutting protection layer stops the metal gate cutting and etching on the cutting protection layer, so that the interlayer film at the bottom of the cutting protection layer is retained. After the metal gate cutting and etching is completed, a second trench is formed. The second trench is filled with a first dielectric layer.

2. The metal gate cutting process method as described in claim 1, characterized in that: Each active region has a convex strip structure and is formed by patterned etching of a semiconductor substrate.

3. The metal gate cutting process method as described in claim 2, characterized in that: An embedded epitaxial layer is also formed in the active region on the side of the metal gate to improve the stress in the channel region of the device and enhance the carrier mobility.

4. The metal gate cutting process method as described in claim 1, characterized in that: The material of the interlayer membrane includes an oxide layer.

5. The metal gate cutting process method as described in claim 4, characterized in that: The material of the cutting protective layer includes a nitrided layer.

6. The metal gate cutting process method as described in claim 5, characterized in that: The hard mask layer and the cutting protection layer are made of the same material.

7. The metal gate cutting process method as described in claim 6, characterized in that: The metal gate is obtained by gate replacement of a dummy gate, and the gate replacement includes planarization of the metal gate.

8. The metal gate cutting process method as described in claim 7, characterized in that: The etch-back of the interlayer film is performed after the metal gate is planarized; After the groove is formed, the cutting protective layer and the hard mask layer are formed simultaneously using the same process.

9. The metal gate cutting process method as described in claim 7, characterized in that: Prior to the gate replacement, a planarization process is performed on the interlayer film to make the top surface of the interlayer film and the top surface of the dummy gate flat. The etching back of the interlayer film is performed after the planarization process of the interlayer film is completed; The cutting protective layer and the hard mask layer are formed separately and independently.

10. The metal gate cutting process method as described in claim 1, characterized in that: The thickness of the cutting protective layer is 200 Å to 500 Å.

11. The metal gate cutting process method as described in claim 1, characterized in that: The etching back of the interlayer film is achieved by gas dry etching.

12. The metal gate cutting process method as described in claim 11, characterized in that: The gas used in the dry etching process includes C4F6.

13. The metal gate cutting process method as described in claim 6, characterized in that: After the hard mask layer is formed, the method further includes the step of forming a capping layer composed of an oxide layer on the top surface of the hard mask layer.

14. The metal gate cutting process method as described in claim 1, characterized in that: The first dielectric layer is formed by a deposition process. After the deposition process of the first dielectric layer is completed, the first dielectric layer completely fills the second trench and extends to the outer surface of the second trench. The process then includes performing a first CMP to remove the first dielectric layer outside the second trench.

15. The metal gate cutting process method as described in claim 14, characterized in that: The first CMP or the first CMP combined with etching also removes the cutting protective layer, the hard mask layer and the first dielectric layer above the bottom surface of the cutting protective layer.

Images