Wafer processing method and processing apparatus

Abstract

This application provides a wafer processing method and apparatus. The method includes transferring a wafer to be processed into a first reaction chamber, forming a gate oxide layer in the first reaction chamber, and providing a nitrogen-containing gas and exciting the nitrogen-containing gas into nitrogen-containing ions which are then introduced into the first reaction chamber to perform in-situ plasma nitriding treatment on the wafer with the gate oxide layer formed. This reduces the interface state density at the interface between the gate oxide layer and the wafer, thereby improving the channel carrier mobility. This application is beneficial for optimizing the insulation reliability of the gate oxide layer and improving the conduction performance and long-term operational stability of the corresponding semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and more specifically, to a wafer processing method and processing apparatus. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, boasts excellent properties such as high breakdown field strength, high thermal conductivity, and high saturated electron drift velocity, making it the core substrate for high-performance silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs). It has been widely applied in high-end power electronics fields such as new energy vehicles, smart grids, and aerospace. The performance and reliability of SiC MOSFET devices hinge on the interface quality between the gate oxide layer and the SiC substrate. This interface quality directly determines the device's channel mobility, threshold voltage stability, and long-term operational reliability, making it a critical control point in the device manufacturing process.

[0003] In the manufacturing process of SiC MOSFET devices, after the gate oxide process is completed, the SiC substrate needs to be transported to the polysilicon deposition process to prepare the gate polysilicon. However, during this transport and waiting process, the interface between the newly formed gate oxide layer and the SiC substrate is in an unstable state and is susceptible to degradation due to environmental factors. The longer the SiC substrate waits in the atmospheric environment, the more severe the interface degradation becomes, ultimately leading to an increase in interface state density. This, in turn, reduces channel mobility, disrupts threshold voltage stability, and directly affects device performance and production yield.

[0004] Therefore, how to effectively suppress the interface quality degradation during the transition stage from the completion of the gate oxide process to the polysilicon deposition process, and reduce the adverse effects of environmental factors on the interface between the gate oxide layer and the SiC substrate, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned problems, the first aspect of this application aims to provide a wafer processing method, comprising: The wafer to be processed is transferred to the first reaction chamber, and a gate oxide layer is formed in the first reaction chamber; Nitrogen-containing gas is introduced into the first reaction chamber and excited into nitrogen-containing ions to perform in-situ plasma nitriding treatment on the wafer with the gate oxide layer formed in the first reaction chamber.

[0006] The aforementioned wafer processing method includes directly introducing nitrogen-containing gas into the same reaction chamber after the gate oxide layer is completed on the wafer, and exciting the nitrogen-containing gas into nitrogen-containing plasma, thereby reducing the interface state density at the interface between the gate oxide layer and the wafer, improving the channel carrier mobility, and also helping to optimize the insulation reliability of the gate oxide layer, reduce threshold voltage drift, and improve the conduction performance and long-term operating stability of the corresponding semiconductor device.

[0007] To address the aforementioned problems, a second aspect of this application provides a wafer processing apparatus, including... A transfer module is used to transfer the wafer from the first reaction chamber to the second reaction chamber in a closed transfer path protected by inert gas. The preprocessing module is connected to the first reaction chamber and is used to perform in-situ plasma nitriding on the wafer in the first reaction chamber that has a gate oxide layer formed thereon. The control module, signal-connected to both the transmission module and the preprocessing module, is used to drive the preprocessing module to perform in-situ plasma nitriding on the wafer with the gate oxide layer completed in the first reaction chamber; and to drive the transmission module to transfer the wafer with the plasma nitriding completed in the first reaction chamber to the second reaction chamber. The wafer processing apparatus described above is adapted to the wafer processing method described in the first aspect, and therefore possesses all the beneficial effects of the semiconductor device described in the first aspect, which will not be repeated here. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart illustrating a wafer processing method according to an embodiment of this application.

[0009] Figure 2 This is a schematic diagram of a wafer processing apparatus according to an embodiment of this application.

[0010] Figure 3 This is a structural block diagram of a wafer processing apparatus according to an embodiment of this application.

[0011] Explanation of key component symbols: 100 Wafer processing unit; 110 First reaction chamber; 120 Remote plasma generation module; 130 Second reaction chamber; 140 Crystal boat; 150 Standard mechanical interface compartment; 160 Wafer transfer compartment; 161 Crystal boat loading position; 162 Crystal boat unloading position.

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments of this application will be described below in conjunction with specific implementation methods. Obviously, the drawings and embodiments described below only involve some embodiments of this application and are not intended to limit this disclosure. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0014] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0015] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0016] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0017] In the description of the embodiments of this application, unless otherwise stated, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections, electrical connections, or connections that can communicate with each other; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two components or interactive relationships between two components.

[0018] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0019] To address the technical problems described in the background, this application provides a wafer processing method and a wafer processing apparatus. The wafer processing method includes, after the gate oxide layer is completed on the wafer, directly introducing a nitrogen-containing gas into the same reaction chamber and exciting the nitrogen-containing gas into a nitrogen-containing plasma, thereby reducing the interface state density at the interface between the gate oxide layer and the wafer, improving the channel carrier mobility, and also helping to optimize the insulation reliability of the gate oxide layer, reduce threshold voltage drift, and improve the conduction performance and long-term operating stability of the corresponding semiconductor device.

[0020] To make the above-mentioned objectives, features and beneficial effects of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0021] According to a first aspect of this application, a wafer processing method is provided.

[0022] Please see Figure 1 and Figure 2 The wafer processing method of this application includes the following steps: In step S100, the wafer to be processed is transferred to the first reaction chamber 110, and a gate oxide layer is formed in the first reaction chamber 110.

[0023] Here, the wafer to be processed refers to a semiconductor substrate wafer that has completed the preceding isolation and doping processes. Its surface has been prepared with shallow trench isolation structures, well doped regions (or bulk doped regions), active regions and other functional areas through processes such as photolithography, etching, ion implantation and annealing activation. It has the conditions to prepare the gate oxide layer and can be used to form a complete gate structure in the future.

[0024] For example, the wafer to be processed may include, but is not limited to, silicon carbide wafers, such as silicon carbide wafers composed of single-crystal silicon carbide substrates of crystal types such as 4H-SiC and 6H-SiC, and single-crystal silicon carbide epitaxial layers.

[0025] The first reaction chamber 110 refers to an independent process chamber used for the preparation of the gate oxide layer. It can be used to grow the gate oxide film on the wafer surface using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), or it can be used to directly grow the gate oxide film on the wafer surface using a high-temperature thermal oxidation process. The internal parameters of the first reaction chamber 110, such as temperature, reaction gas source, pressure, and growth rate, can be precisely controlled while maintaining a high-cleanliness film-forming environment. This effectively avoids gate oxide layer defects caused by metal impurities and particle contamination, ensuring the density, interface quality, and electrical reliability of the gate oxide layer.

[0026] It should be noted that the specific process steps for preparing the gate oxide layer on the wafer surface within the first reaction chamber 110 can be implemented using conventional techniques known in the art, and will not be elaborated upon here.

[0027] In step S200, a nitrogen-containing gas is provided and excited into a nitrogen-containing plasma, which is then introduced into the first reaction chamber 110 to perform in-situ plasma nitriding on the wafer with the gate oxide layer formed thereon within the first reaction chamber 110.

[0028] Here, nitrogen-containing gas refers to one or a combination of at least two of nitrogen-containing gaseous media, such as nitric oxide (NO), nitrous oxide (N2O), nitrogen (N2), and ammonia (NH3). By exciting the nitrogen-containing gas introduced into the first reaction chamber 110 into a highly active nitrogen-containing plasma, in-situ plasma nitriding treatment can be performed on the wafer with the gate oxide layer formed within the first reaction chamber 110 without transferring the wafer to other process chambers. This directly achieves the incorporation of nitrogen into the gate oxide layer and the interface between the gate oxide layer and the wafer to be treated.

[0029] Simultaneously, the wafer with the gate oxide layer is directly subjected to in-situ plasma nitriding treatment within the first reaction chamber 110. This not only helps to avoid particle contamination and natural oxidation degradation of the interface introduced during wafer transfer, ensuring the cleanliness and compositional uniformity of the nitrided interface, but also reduces the temperature threshold of the nitriding process by leveraging the high reactivity of active nitrogen plasma. This allows for precise control of the nitrogen doping depth and concentration distribution, effectively passivating interface defects in the gate oxide layer and reducing the interface state density, ultimately significantly improving the breakdown characteristics and long-term electrical reliability of the gate oxide layer.

[0030] The method of exciting the nitrogen-containing gas introduced into the first reaction chamber 110 into a highly active nitrogen-containing plasma includes, but is not limited to, any one or at least a combination of two of the plasma nitriding processes applicable to vertical diffusion furnaces, such as remote plasma nitriding (RPN), decoupled plasma nitriding (DPN), inductively coupled plasma (ICP) nitriding, and capacitively coupled plasma (CCP) nitriding.

[0031] For example, the nitrogen-containing gas is nitric oxide (NO), and the nitric oxide can be excited into nitrogen-containing plasma using a remote plasma nitriding process to complete the nitriding passivation treatment of the gate oxide layer.

[0032] Specifically, nitric oxide (NO) gas can be first introduced into a remote plasma generation module 120 connected to the first reaction chamber 110, and excited and ionized inside the remote plasma generation module 120 into a nitrogen-containing plasma composed of nitrogen-containing active free radicals, nitrogen-oxygen active groups and low-energy plasma particles, and then transported to the wafer surface in the first reaction chamber 110 by gas flow, thereby performing in-situ nitriding modification on the gate oxide layer.

[0033] Therefore, this application helps to avoid problems such as lattice damage and surface roughening caused by direct bombardment of the gate oxide layer surface by high-energy ions. It can achieve uniform doping of nitrogen into the gate oxide layer and the contact interface between the gate oxide layer and the wafer to be processed under relatively mild reaction conditions, thereby effectively passivating interface state defects, repairing oxygen vacancies inside the gate oxide layer, and significantly improving the breakdown field strength, resistance to bias temperature instability and long-term electrical reliability of the gate oxide layer without compromising the density and interface flatness of the gate oxide layer.

[0034] In this process, the nitrogen-containing plasma generated by the excitation is transported to the wafer surface within the first reaction chamber 110 to perform in-situ plasma nitriding treatment on the prepared gate oxide layer. The reaction temperature range is 400℃ to 600℃. The low reaction temperature range of 400℃ to 600℃ can provide sufficient diffusion driving force and interfacial reaction activity for nitrogen-containing active groups, ensuring the effective incorporation of nitrogen into the interior of the gate oxide layer and the contact interface between the gate oxide layer and the wafer to be treated, thus completing the passivation of interface defects and the modification of the gate oxide layer performance. It can also avoid problems such as thermal diffusion of doped impurities in the functional regions of the wafer, device threshold voltage drift, and abnormal growth of gate oxide layer thickness caused by high-temperature conditions, strictly control the process thermal budget, maintain the stability of electrical parameters of functional regions such as well-dopated regions and active regions prepared by previous processes, and at the same time, meet the low-temperature process adaptation requirements of wide bandgap semiconductor devices such as silicon carbide.

[0035] Furthermore, the nitrogen-containing plasma generated by the excitation is transported to the wafer surface within the first reaction chamber 110, and the reaction time range for in-situ plasma nitriding of the prepared gate oxide layer is 15s to 45s. A reaction time of 15s to 45s allows for precise control of the nitrogen doping depth and interface concentration. The lower limit of 15s ensures sufficient nitriding reaction, effectively passivating interface states and improving the breakdown reliability of the gate oxide layer; the upper limit of 45s avoids problems such as increased fixed charge in the gate oxide layer, interface defect rebound, and deterioration of device electrical performance caused by excessive nitriding.

[0036] It should be noted that, before performing step S200, the first reaction chamber 110 is evacuated to remove any residual oxidizing gas after the preparation of the gate oxide layer that could adversely affect subsequent step S200.

[0037] In step S300, the wafer after plasma nitriding is transferred to the second reaction chamber 130, and a gate electrode is formed in the second reaction chamber 130.

[0038] Here, the second reaction chamber 130 refers to an independent process chamber for growing gate electrode films. It can be adapted to different gate fabrication processes such as polysilicon chemical vapor deposition and metal gate physical vapor deposition. It can precisely control the film thickness, composition uniformity and electrical properties, and provide a stable electrode film substrate for subsequent gate patterning processes.

[0039] To reduce the exposure time of the wafer in the atmosphere during the transfer to the second reaction chamber 130 after plasma nitriding, this application can also optimize the transfer path and configuration of the wafer between the first reaction chamber 110 and the second reaction chamber 130. For example, the first reaction chamber 110 and the second reaction chamber 130 can be connected to the transfer platform of the same semiconductor cluster process equipment, and the wafer can be transferred between the chambers by a robot in a closed or inert protective atmosphere. This reduces the contact between the surface of the nitrided gate oxide layer and water vapor, suspended particles and impurity gases in the atmosphere, effectively avoiding performance degradation problems such as secondary natural oxidation of the interface, external diffusion of surface nitrogen elements and resurgence of interface state density, stabilizing the interface passivation modification effect of plasma nitriding on the gate oxide layer, ensuring the interface quality between the gate oxide layer and the gate electrode, and maintaining the consistency and long-term reliability of the device's electrical parameters.

[0040] Exemplarily, the step of transferring the wafer after plasma nitriding treatment to the second reaction chamber 130 includes: Step S301: The wafer that has completed the in-situ nitriding and passivation treatment is taken out from the first reaction chamber 110 and placed in an empty wafer box, so that the wafer box is in the loading state.

[0041] Step S302: The wafer cassette in the loading state is transferred to the crystal boat loading position 161 outside the second reaction chamber 130 in a closed transport path protected by inert gas.

[0042] In step S303, the wafer that has completed the in-situ nitriding and passivation treatment is removed from the wafer cassette in the loading state and transferred to the wafer boat 140, and the wafer that has completed the in-situ nitriding and passivation treatment is transferred to the second reaction chamber 130 using the wafer boat 140.

[0043] Here, step S302 refers to first transferring the wafer cassette in the loading state to the Standard Mechanical Interface (SMIF) compartment 150 for temporary storage, and then transferring the wafer cassette in the loading state from the Standard Mechanical Interface 150 to the wafer transfer compartment 160 outside the second reaction chamber 130 when the wafer boat 140 in the second reaction chamber 130 is in an empty state, while the wafer boat loading position 161 is located inside the wafer transfer compartment 160.

[0044] The standard mechanical interface chamber 150 is a standard cleanroom transfer unit configured at the front end of furnace tube diffusion process equipment, serving as a transition interface between the cleanroom environment and the closed process environment inside the equipment. After being transferred to the standard mechanical interface chamber 150, the wafer cassette in its loaded state can cooperate with the sealed enclosure structure of the chamber to form an independent, controlled clean environment. This isolates the wafers loaded within the cassette from the external environment, preventing contact between suspended particles, moisture, and reactive impurities with the wafer surface. This helps reduce the probability of performance degradation issues such as secondary oxidation of the nitrided gate oxide layer, surface nitrogen loss, and particle contamination.

[0045] Furthermore, the standard mechanical interface chamber 150 is equipped with a controllable closed sealed transmission port, which is connected to the furnace tube diffusion equipment of the second reaction chamber 130.

[0046] Therefore, when the wafer boat 140 in the second reaction chamber 130 is in an unloaded state, the scheduling command of the equipment control system can open the docking port between the standard mechanical interface compartment 150 and the furnace tube diffusion equipment, and directly transfer the wafer cassette in the loading state to the wafer boat loading position 161 in the wafer transfer compartment 160 via the wafer cassette transfer robot, without needing to go through an additional wafer cassette temporary storage node for transfer. For example, it does not need to go through the buffer stocker located in the furnace tube diffusion equipment to which the second reaction chamber 130 belongs, thereby further reducing the inter-process transfer path and total time of the wafer, minimizing the exposure time of the unprotected state of the gate oxide layer after nitriding modification, and reducing the probability of secondary oxidation of the interface, external diffusion of surface nitrogen elements, and environmental particle contamination. At the same time, this step can also streamline the flow links, improve the wafer processing cycle of the equipment, and adapt to the high-efficiency operation requirements of mass production processes.

[0047] Conversely, when the wafer boat 140 in the second reaction chamber 130 is in a loading state and cannot accept a new wafer, the wafer cassette in the loading state can be temporarily stored in the standard mechanical interface chamber 150. Relying on the chamber's sealed enclosure structure, an independent, controlled clean microenvironment is formed. Simultaneously, high-purity inert gas is continuously introduced into the chamber to maintain a slightly positive pressure protective atmosphere, such as high-purity argon (Ar) or high-purity nitrogen (N2). Alternatively, high-purity helium (He) or other chemically stable gaseous protective media can be selected based on process compatibility. In other words, even if the wafer has a process waiting period, it can remain in an inert protective environment isolated from the external atmosphere throughout the process, thereby minimizing the probability of secondary oxidation of the gate oxide layer interface after nitriding modification, external diffusion of surface nitrogen, and environmental particle contamination.

[0048] It should be noted that since the wafers mentioned above need to wait and transfer during the process cycle in the standard mechanical interface chamber 150, the wafer cassette used to carry the wafers in step S301 must be compatible with the internal transfer mechanism and carrying station of the standard mechanical interface chamber 150 in terms of its external dimensions, slot positioning reference and transfer docking structure. This ensures that the controlled clean environment formed by the chamber's sealed enclosure structure and the wafer cassette is stable and effective, avoiding problems such as transfer jams, excessive sealing gaps, and leakage of inert protective atmosphere caused by specification mismatch. This ensures that the wafers are in a stable isolated and protected state throughout the waiting and transfer process after nitriding.

[0049] The Cassette Transfer Buffer (CTB) is a transfer buffer chamber or a Cassette Transfer Stage inside the furnace tube diffusion equipment. It maintains a high cleanliness environment that meets semiconductor manufacturing standards. The chamber integrates a wafer boat loading position 161, a wafer transfer robot, and a wafer positioning and calibration mechanism. It is used to receive and temporarily store wafer cassettes, load and unload wafers between wafer boats 140, and perform pre-processing work before wafer boats 140 are sent into the second reaction chamber 130. It can complete the process flow of wafers between wafer cassettes and wafer boats 140 under the condition of isolating the external environment of the equipment, ensuring the cleanliness of the entire transfer process.

[0050] Furthermore, the wafer transfer chamber 160 is continuously circulated with high-purity inert gas and maintains a slightly positive pressure protective atmosphere, such as high-purity argon (Ar) or high-purity nitrogen (N2). Alternatively, high-purity helium (He) or other chemically stable gaseous protective media can be selected according to process compatibility.

[0051] In addition, the wafer transfer chamber 160 is also provided with a wafer unloading position 162. After step S302, or before step S303, it should also include taking out the wafer with the gate electrode completed in the second reaction chamber 130 and transferring it to the wafer cassette that has been pre-transferred to the wafer unloading position 162 and is in an unloaded state, so that the wafer cassette 140 is in an unloaded state.

[0052] After the crystal boat 140 corresponding to the second reaction chamber 130 is in an unloaded state, the wafer located in the wafer cassette in the loading position 161 and in the loading state is taken out and transferred to the unloaded crystal boat 140 to complete the loading. Then, the crystal boat 140 carries the wafer into the second reaction chamber 130 to carry out the fabrication of the gate electrode.

[0053] In summary, the wafer processing method provided in this application can not only perform in-situ plasma nitriding to passivate and modify the gate oxide layer interface, thereby reducing the interface state density of the gate oxide layer and repairing oxygen vacancy defects inside the gate oxide layer, thus improving the breakdown field strength and long-term electrical reliability of the gate oxide layer, but also strictly control the process thermal budget to avoid adverse effects such as doping impurity diffusion in the functional areas of the wafer and device threshold voltage drift caused by high-temperature long-term processing; it can also eliminate the waiting time of the wafer cassette at the additional transfer and temporary storage node through the direct sealed docking and transfer scheme of the standard mechanical interface chamber 150 and the wafer transfer chamber 160. Combined with the controlled clean environment with inert gas protection throughout the process, the exposure time of the wafer in the non-protected state after nitriding modification is minimized, which helps to avoid the risk of secondary oxidation of the gate oxide layer interface, external diffusion of surface nitrogen elements and environmental particle contamination, etc., and while stabilizing the interface modification effect, it simplifies the process flow links, improves the equipment production cycle, and ensures the inter-wafer consistency of electrical parameters of semiconductor devices and the yield of mass production.

[0054] According to a second aspect of this application, a wafer processing apparatus is also provided.

[0055] Please see Figure 2 and Figure 3 The wafer processing apparatus 100 provided in this application includes a transfer module, a preprocessing module, and a control module. The transfer module transfers a wafer from a first reaction chamber 110 to a second reaction chamber 130 in a sealed transfer path protected by an inert gas. The preprocessing module is connected to the first reaction chamber 110 and performs in-situ plasma nitriding on the wafer with a gate oxide layer formed in the first reaction chamber 110. The control module is signal-connected to both the transfer module and the preprocessing module, and drives the preprocessing module to perform in-situ plasma nitriding on the wafer with the gate oxide layer formed in the first reaction chamber 110. The control module also drives the transfer module to transfer the wafer with the plasma nitriding formed in the first reaction chamber 110 to the second reaction chamber 130.

[0056] Here, the transfer module refers to the wafer transfer module composed of multiple transfer mechanisms working together. Specifically, it includes an overhead hoist transfer (OHT) system for transferring wafer cassettes between different furnace tube diffusion equipment, a wafer cassette transfer robot for transferring wafer cassettes between the standard mechanical interface compartment 150 and the wafer transfer compartment 160 inside the furnace tube equipment, and a wafer transfer robot for picking up and placing wafers between the wafer cassette and the wafer boat 140. The multiple transfer mechanisms are connected in sequence to form a closed transfer path under inert gas protection, thereby completing the closed transfer of the wafer from the first reaction chamber 110 to the second reaction chamber 130.

[0057] The pre-processing module refers to the remote plasma generation module 120 connected to the first reaction chamber 110. It is used to introduce a nitrogen-containing gaseous medium into the first reaction chamber 110 and excite the introduced nitrogen-containing gas into a nitrogen-containing plasma, which is then transported into the first reaction chamber 110 to perform in-situ plasma nitriding on the wafer that has completed the gate oxide layer deposition, thereby completing the passivation of interface defects and the modification of dielectric properties of the gate oxide layer.

[0058] The control module serves as the control center of the device, connecting to both the transfer module and the preprocessing module. On one hand, it outputs process control commands to the preprocessing module, regulating process parameters such as the nitrogen gas flow rate, plasma excitation power, nitriding temperature, and duration, driving the preprocessing module to complete the in-situ plasma nitriding of the wafers in the first reaction chamber 110 according to a preset process. On the other hand, it outputs scheduling control commands to the transfer module, managing the timing nodes and transmission paths of wafer transfer, driving the transfer module to transfer the completed plasma nitriding wafers to the second reaction chamber 130 in a sealed manner according to a preset process, ensuring precise connection of each process step and stable operation of the entire device.

[0059] Furthermore, the control module is also configured to execute the wafer processing method described in any of the embodiments of the first aspect above, thereby ensuring the electrical performance stability of the subsequently formed gate oxide layer.

[0060] It should be noted that the details not shown in the wafer processing apparatus 100 described in the second aspect also apply to the wafer processing method described in the first aspect above, and will not be repeated here.

[0061] Furthermore, the aforementioned wafer processing methods and apparatus refer to the process methods and supporting equipment applied in the fabrication of power semiconductor chips. Power semiconductor chips can be diode devices, transistor devices, or combinations thereof. Diode devices can include, but are not limited to, power diodes, merged PiN Schottky (MPS) diodes, Schottky diodes, metal-oxide-semiconductor gate-controlled diodes, etc. Transistor devices include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), FinFETs, high-electron-mobility transistors (HEMTs), thyristors, etc.

[0062] Alternatively, power semiconductor chips can be made of any semiconductor material suitable for manufacturing semiconductor chips, including but not limited to elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), and binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide (InGaAsP).

[0063] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A wafer processing method, characterized in that, include: The wafer to be processed is transferred to the first reaction chamber, and a gate oxide layer is formed in the first reaction chamber; A nitrogen-containing gas is provided and excited into a nitrogen-containing ion body, which is then introduced into the first reaction chamber to perform in-situ plasma nitriding treatment on a wafer with a gate oxide layer formed thereon within the first reaction chamber.

2. The wafer processing method according to claim 1, characterized in that, The nitrogen-containing gas includes one or a combination of at least two of NO, N2O, N2, and NH3.

3. The wafer processing method according to claim 1, characterized in that, The reaction temperature range for in-situ plasma nitriding of the wafer with the gate oxide layer formed in the first reaction chamber is 400℃~600℃.

4. The wafer processing method according to claim 1, characterized in that, The reaction time range for in-situ plasma nitriding of the wafer with the gate oxide layer in the first reaction chamber is 15s to 45s.

5. The wafer processing method according to any one of claims 1 to 4, characterized in that, After the step of performing in-situ plasma nitriding treatment on the wafer with the gate oxide layer formed in the first reaction chamber, the method further includes: The wafer, after plasma nitriding, is transferred to the second reaction chamber, where a gate electrode is formed.

6. The wafer processing method according to claim 5, characterized in that, The step of transferring the wafer after plasma nitriding to the second reaction chamber includes: The wafer that has completed the in-situ nitriding and passivation treatment is taken out from the first reaction chamber and placed in an empty wafer box, so that the wafer box is in the loading state. The wafer cassette in the loading state is transferred to the crystal boat loading position outside the second reaction chamber in a sealed transport path protected by inert gas. The wafer that has completed the in-situ nitriding and passivation treatment is removed from the wafer cassette in the loading state and transferred to the crystal boat, and the crystal boat is used to transfer the wafer that has completed the in-situ nitriding and passivation treatment to the second reaction chamber.

7. The wafer processing method according to claim 6, characterized in that, The step of transferring the wafer cassette in the loading state to the boat loading position outside the second reaction chamber in a sealed transport path protected by inert gas includes: The wafer cassette in its loaded state is transferred to the standard mechanical interface chamber outside the second reaction chamber, and When the crystal boat is in an unloaded state, the wafer cassette in the loading state is transferred from the standard mechanical interface compartment to the wafer transfer compartment outside the second reaction chamber, and the crystal boat loading position is located inside the wafer transfer compartment; The standard mechanical interface chamber is used for the sealing and temporary storage of the wafer cassette; the wafer transfer chamber is used for the transfer of wafers between the wafer cassette and the wafer boat; and both the standard mechanical interface chamber and the wafer transfer chamber are filled with circulating high-purity nitrogen gas and are maintained at a slight positive pressure.

8. The wafer processing method according to claim 7, characterized in that, The wafer transfer compartment also includes a wafer boat unloading station. After the step of transferring the wafer cassette in the loading state to the standard mechanical interface compartment outside the second reaction chamber, the following steps are also included: The wafer with the gate electrode completed in the second reaction chamber is removed and transferred to a wafer cassette that has been pre-transferred to the unloading position of the crystal boat and is in an unloaded state, so that the crystal boat is in an unloaded state.

9. The wafer processing method according to claim 8, characterized in that, After the step of removing the wafer with the completed gate electrode from the second reaction chamber and transferring it to the empty wafer cassette that has been pre-transferred to the unloading position of the wafer boat, the method further includes: The wafers located in the wafer loading position and in the loaded state in the wafer cassette are removed and transferred to the unloaded wafer boat. The wafer carried in the crystal boat is transferred to the second reaction chamber, and the gate electrode is formed in the second reaction chamber.

10. A wafer processing apparatus, characterized in that, include: A transfer module is used to transfer the wafer from the first reaction chamber to the second reaction chamber in a closed transfer path protected by inert gas. The preprocessing module is connected to the first reaction chamber and is used to perform in-situ plasma nitriding on the wafer in the first reaction chamber that has a gate oxide layer formed thereon. The control module is signal-connected to the transmission module and the pre-processing module respectively, and is used to drive the pre-processing module to perform in-situ plasma nitriding on the wafer with the gate oxide layer completed in the first reaction chamber. And, for driving the transfer module to transfer the wafer that has completed plasma nitriding treatment in the first reaction chamber to the second reaction chamber.

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