Semiconductor module arrangement

Abstract

A semiconductor module device includes: a housing including a first lateral side, a second lateral side opposite to the first lateral side, a third lateral side perpendicular to the first and second lateral sides, and a fourth lateral side opposite to the third lateral side; a first substrate and a second substrate disposed in the housing such that the first substrate is disposed between the second substrate and the third lateral side; a first semiconductor element disposed on the first substrate; and a second semiconductor element disposed on the second substrate. The semiconductor module device further includes a first power supply terminal, a second power supply terminal, and one or more output terminals disposed in a third segment of the housing disposed between the third and fourth lateral sides, wherein the distance between the third segment of the housing and the third lateral side is substantially equal to the distance between the third segment of the housing and the fourth lateral side.

Description

Technical Field

[0001] This disclosure relates to a semiconductor module device. Background Technology

[0002] Semiconductor module devices typically include at least one substrate disposed within a housing. A semiconductor device comprising multiple controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) is disposed on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and (optionally) a second metallization layer deposited on a second side of the substrate layer. Controllable semiconductor elements are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to the substrate. The controllable semiconductor elements are typically mounted to the substrate using soldering or sintering techniques. Wires or electrical connections are used to connect the different semiconductor devices of the semiconductor device to each other. Additionally, terminal elements are provided to contact the semiconductor device from outside the housing. Such terminal elements are typically electrically coupled to the first metallization layer via a first end. A second end of the terminal element protrudes from the housing. The layout of the semiconductor module device (particularly the positioning of the terminal elements) can affect switching characteristics, stray inductance, and losses of the semiconductor device.

[0003] There is a need for semiconductor module devices with improved switching characteristics and reduced stray inductance. Summary of the Invention

[0004] A semiconductor module device includes: a housing including a first lateral side, a second lateral side opposite to the first lateral side, a third lateral side perpendicular to the first and second lateral sides, and a fourth lateral side opposite to the third lateral side; a first substrate and a second substrate disposed in the housing such that the first substrate is disposed between the second substrate and the third lateral side, each of the first and second substrates including a dielectric insulating layer and a first metallization layer disposed on a surface of the dielectric insulating layer, wherein the first metallization layer includes a first segment and a second segment; and a first semiconductor element disposed on the first substrate and a second semiconductor element disposed on the second substrate, wherein each of the first and second semiconductor elements includes a first contact pad and a second contact pad, wherein the second contact pad of the first semiconductor element is electrically coupled to a first contact pad of the first substrate. The semiconductor module device further includes a first power supply terminal electrically coupled to the first section of the first substrate, a second power supply terminal electrically coupled to the second section of the second substrate, and one or more output terminals electrically coupled to the second section of the first substrate and the second semiconductor element, wherein the first power supply terminal, the second power supply terminal and one or more output terminals are arranged in a third section of the housing arranged between a third lateral side and a fourth lateral side, wherein the distance between the third section of the housing and the third lateral side is substantially equal to the distance between the third section of the housing and the fourth lateral side.

[0005] The invention can be better understood by referring to the following figures and description. The components in the figures are not necessarily drawn to scale, but rather the focus is on illustrating the principles of the invention. Furthermore, in the figures, the same reference numerals denote corresponding components in different views. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a semiconductor module device.

[0007] Figure 2 The circuit layout based on an example is illustrated schematically.

[0008] Figure 3 A top view of a semiconductor module device according to an embodiment of the present disclosure is shown schematically.

[0009] Figure 4 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0010] Figure 5 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0011] Figure 6 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0012] Figure 7 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0013] Figure 8 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0014] Figure 9 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0015] Figure 10 A top view of a semiconductor module device according to a further embodiment of the present disclosure is shown schematically.

[0016] Figure 11 A schematic three-dimensional view of the housing of a semiconductor module device according to an embodiment of the present disclosure is shown.

[0017] Figure 12 A three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown.

[0018] Figure 13 A three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown.

[0019] Figure 14 A three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown.

[0020] Figure 15 A three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown.

[0021] Figure 16 A three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown.

[0022] Figure 17 A three-dimensional view of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown. Detailed Implementation

[0023] In the following detailed description, reference is made to the accompanying drawings. The drawings illustrate specific examples in which the invention may be practiced. It should be understood that, unless otherwise specifically stated, the features and principles described with respect to the various examples can be combined with each other. The designation of certain elements as “first element,” “second element,” “third element,” etc., in the specification and in the claims should not be construed as enumeration. Rather, such designation is only used to distinguish different “elements.” That is, for example, the presence of a “third element” does not require the presence of a “first element” and a “second element.” A wire or electrical connection as described herein may be a single conductive element or may comprise at least two separate conductive elements connected in series and / or in parallel. Wires and electrical connections may comprise metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). A semiconductor body as described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included within a semiconductor chip. The semiconductor body has electrical connection pads and includes at least one semiconductor element having electrodes.

[0024] refer to Figure 1 The diagram schematically illustrates a cross-sectional view of a semiconductor module device 300. The semiconductor module device 300 includes a housing 37 and a substrate 310. The substrate 310 includes a dielectric insulating layer 311, a (structured) first metallization layer 3111 attached to the dielectric insulating layer 311, and a (structured) second metallization layer 3112 attached to the dielectric insulating layer 311. The dielectric insulating layer 311 is disposed between the first metallization layer 3111 and the second metallization layer 3112.

[0025] Each of the first metallization layer 3111 and the second metallization layer 3112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 310 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 311 is a ceramic substrate, such as a thin ceramic layer. The ceramic may be composed of or include one of the following materials: alumina; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 310 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal bonding (AMB) substrate. Furthermore, the substrate 310 may be an insulating metal substrate (IMS). For example, an insulating metal substrate typically includes a dielectric insulating layer 311, which comprises (filled) a material (e.g., epoxy resin or polyimide). For example, the material of the dielectric insulating layer 311 may be filled with ceramic particles. Such particles may include, for example, SiO2, Al2O3, AlN, or BN, and may have a diameter between about 1 μm and about 50 μm. The substrate 310 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 311. For example, the non-ceramic dielectric insulating layer 311 may consist of or include a curable resin.

[0026] Substrate 310 is disposed within housing 37. Figure 1 In the example shown, substrate 310 forms the base surface of housing 37, while housing 37 itself only includes sidewalls and a cover. However, this is only an example. It is also possible that housing 37 also includes a base surface, and substrate 310 is disposed on the base surface and within housing 37. According to another example, substrate 310 may be mounted on a substrate (not specifically shown). In some semiconductor module devices 300, more than one substrate 310 is disposed on the base surface of housing 37 or on a single substrate (not shown). For example, substrate may form the base surface of housing 37.

[0027] One or more semiconductor bodies 320 may be disposed on at least one substrate 310. Each semiconductor body 320 disposed on at least one semiconductor substrate 310 may include a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), or any other suitable controllable semiconductor element.

[0028] One or more semiconductor bodies 320 may be formed on the substrate 310 to create a semiconductor device. Figure 1 In the example shown are only two semiconductor bodies 320. Figure 1 The second metallization layer 3112 of the substrate 310 is a continuous layer. Figure 1 In the example shown, the first metallization layer 3111 is a structured layer. "Structured layer" means that the first metallization layer 3111 is not a continuous layer, but rather includes recesses between different segments of the layer. Figure 1 Such a recess is schematically illustrated. In this example, the first metallization layer 3111 comprises three distinct segments. However, this is merely an example. Any other number of segments is generally possible. Different semiconductor bodies 320 may be mounted to the same or different segments of the first metallization layer 3111. The different segments of the first metallization layer 3111 may not be electrically connected, or may be electrically connected to one or more other segments using, for example, bonding wires 33. For example, electrical connections 33 may also include bonding strips, connecting plates, or conductor rails, to name just a few. One or more semiconductor bodies 320 may be electrically and mechanically connected to the substrate 310 via a conductive connection layer 330. For example, such a conductive connection layer may be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

[0029] According to other examples, the second metallization layer 3112 can also be a structured layer. Alternatively, the second metallization layer 3112 can be omitted entirely.

[0030] Figure 1 The illustrated semiconductor module device 300 also includes terminal elements 34. Terminal elements 34 are electrically connected to a first metallization layer 3111 and provide electrical connection between the interior and exterior of the housing 37. Terminal elements 34 can be electrically connected to the first metallization layer 3111 via a first end 341, while a second end 342 of terminal elements 34 protrudes from the housing 37. Terminal elements 34 can be electrically contacted from the outside at their second end 342. A first portion of terminal elements 34 can extend through the interior of the housing 37 in a substantially vertical direction y. The vertical direction y is perpendicular to the top surface of the substrate 310, where the top surface of the substrate 310 is the surface on which at least one semiconductor body 320 is mounted. The second ends 342 of terminal elements 34 can be bent such that they extend in a first horizontal direction x parallel to the top surface of the substrate 310. In this way, for some applications, it is easier to make electrical contact with the second end 342. However, Figure 1 The terminal element 34 shown is merely an example. The terminal element 34 can be implemented in any other manner and can be arranged anywhere within the housing 37. For example, one or more terminal elements 34 can be arranged close to or adjacent to the sidewall of the housing 37. The second end 342 can also extend fully in the vertical direction y, rather than bending in the first horizontal direction x. Any other suitable implementation is possible.

[0031] Each semiconductor body 320 may include a chip pad metallization (not specifically shown), such as a source, drain, anode, cathode, or gate metallization. The chip pad metallization typically provides a contact surface for electrically connecting the semiconductor body 320. For example, the chip pad metallization may electrically contact the interconnect layer 330, terminal element 34, or electrical connection 33. For example, the chip pad metallization may be composed of or include metals such as aluminum, copper, gold, or silver. For example, the electrical connection 33 and terminal element 34 may also be composed of or include metals such as copper, aluminum, gold, or silver.

[0032] Now for reference Figure 2 For example, at least two semiconductor bodies 320 can be arranged in a half-bridge configuration. Figure 2 This is a circuit diagram of an exemplary half-bridge arrangement. The half-bridge arrangement is configured to convert a DC voltage to an AC voltage. The AC voltage can be supplied to, for example, a load (not shown). The half-bridge arrangement is coupled between a first power supply node configured to be operatively coupled to a first potential DC+ and a second power supply node configured to be operatively coupled to a second potential DC-. The first potential DC+ can be a positive potential, and the second potential DC- can be a negative potential that provides the DC voltage via the first and second power supply nodes. The first and second power supply nodes form the input of the half-bridge arrangement.

[0033] A half-bridge may include a high-side switch S1 (first switch) and a low-side switch S2 (second switch) coupled in series between a first power supply node and a second power supply node. The half-bridge arrangement may be configured to drive a load (not specifically shown) at the output node of the half-bridge arrangement. For example, the load may be an inductive load. The output node is electrically connected to a common node between the high-side switch S1 and the low-side switch S2.

[0034] exist Figure 2 In the circuit arrangement, each switch S1, S2 of the half-bridge arrangement is implemented as an IGBT (Insulated Gate Bipolar Transistor). However, this is just an example. For example, switches S1, S2 can also be implemented as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), HEMTs (High Electron Mobility Transistors), BJTs (Bipolar Junction Transistors), or any other type of controllable semiconductor element. Each of switches S1, S2 may include internal or external freewheeling diodes D1, D2. According to another example, each of switches S1, S2 includes two or more separate switching elements (not specifically shown) electrically coupled in parallel with each other.

[0035] Each of the first switch S1 and the second switch S2 includes a control electrode and a controllable load path between the first load electrode and the second load electrode. The load paths of the first switch S1 and the second switch S2 are coupled in series between the first power supply node and the second power supply node.

[0036] For electrical contact according to Figure 2 The example half-bridge arrangement can provide several different connection terminals. According to one example, a first power supply terminal 1 can be electrically coupled to a first power supply node, and a second power supply terminal 4 can be electrically coupled to a second power supply node. A first control terminal 5 can be electrically coupled to the control electrode of a first switch S1, and a second control terminal 6 can be electrically coupled to the control electrode of a second switch S2. A first auxiliary emitter terminal 8 can be electrically coupled to the second load electrode of the first switch S1, and a second auxiliary emitter terminal 10 can be electrically coupled to the second load electrode of the second switch S2. A first collector terminal 7 can be electrically coupled to the first load electrode of the first switch S1, and a second collector terminal 9 can be electrically coupled to the first load electrode of the second switch S2. One or more output terminals 2, 3 can be electrically coupled to the output nodes of the half-bridge arrangement.

[0037] Auxiliary emitter terminals 8 and 10 may be provided, for example, to minimize potential negative feedback effects on the gate-emitter voltage (gate-emitter voltage = voltage between the control electrode and the corresponding emitter terminal (second load electrode) of switches S1 and S2). According to another example, auxiliary emitter terminals 8 and 10 may be provided to detect internal voltage drops between the emitter terminal and the corresponding auxiliary emitter terminal in auxiliary emitter terminals 8 and 10. For example, voltage drops may occur due to stray inductance at the time the corresponding first switch S1 or second switch S2 is turned on or off. For example, the detected voltage drop can be used for error detection.

[0038] Optionally, the device may also include a temperature sensor, such as a negative temperature coefficient thermistor (NTC), including an input electrode and an output electrode. The temperature sensor can be configured to measure the temperature of the semiconductor module device 300. The temperature sensor can be disposed at any suitable location in the device. A first measuring terminal 11 can be electrically coupled to the input electrode of the NTC, and a second measuring terminal 12 can be electrically coupled to the output electrode of the NTC.

[0039] In this way, multiple terminals can be provided for electrical contact with a single half-bridge arrangement. In the semiconductor module device 300, each of the individual terminals 1-10 or 1-12 can be implemented as a terminal element 34, as described above. Figure 1As described, one or more terminals may be electrically coupled to the same segment of the first metallization layer 311. For example, two or more terminals electrically coupled to the same potential may be electrically coupled to the same segment of the first metallization layer 311. However, this is only an example. Two or more terminals electrically coupled to the same potential may also be electrically coupled to two or more different segments of the first metallization layer 311. For example, such segments may be electrically coupled to each other via bonding wires, connecting plates, or conductor rails.

[0040] The layout of the semiconductor module device, particularly the position of the terminal elements 34 within the housing 37, can affect the switching characteristics of the semiconductor device. Therefore, the position of each terminal element 34 within the housing 37 can be selected to meet creepage distance requirements and improve the switching characteristics of the half-bridge arrangement.

[0041] Now for reference Figure 3 The diagram schematically illustrates a semiconductor module device according to an embodiment of the present disclosure. The semiconductor module device includes a housing 37, which includes a first lateral side L1, a second lateral side L2 opposite to the first lateral side L1, a third lateral side L3 perpendicular to the first lateral side L1 and the second lateral side L2, and a fourth lateral side L4 opposite to the third lateral side L3. Figure 3 The housing 37 is not specifically shown. Lateral sides L1, L2, L3, and L4 are formed by... Figure 3 The arrow in the diagram indicates that the semiconductor module device also includes a first substrate 310 disposed in the housing 37. A Second substrate 310 B This makes the first substrate 310 A Arranged on the second substrate 310 B Between the first substrate 310 and the third lateral side L3 A Second substrate 310 B Each of them includes a dielectric insulating layer 311 A 311 B and arranged in dielectric insulating layer 311 A 311 B The first metallization layer 3111 on the surface A 3111 B The first metallization layer 3111 A 3111 B Including the first section 3111 A1 3111 B1 Second section 3111 A2 3111 B2 and the third section 3111 A3 3111 B3 The semiconductor module device also includes a first substrate 310. AThe first controllable semiconductor element 22 A and arranged on the second substrate 310 B The second controllable semiconductor element 22 B The first controllable semiconductor element 22 A Second controllable semiconductor element 22 B Each of them includes a first contact pad 2x1, a second contact pad, and a third contact pad 2x3. First controllable semiconductor element 22 A It can form such as Figure 2 The first switch S1 and the second controllable semiconductor element 22 are shown. B A second switch S2 can be formed. As described above, each of the first switch S1 and the second switch S2 can be formed by one or more controllable semiconductor elements 22 coupled in parallel with each other. Figure 3 The arrangement on the first substrate 310 is schematically shown. A The two controllable semiconductor elements 22 that form the first switch S1 and are disposed on the second substrate 310 are also present. B The two controllable semiconductor elements 22 that form the second switch S2 are then connected.

[0042] Still referencing Figure 3 First controllable semiconductor element 22 A The second contact pad is electrically coupled to the first substrate 310 A First segment 3111 A1 And the second controllable semiconductor element 22 B The second contact pad is electrically coupled to the second substrate 310 B First segment 3111 B1 First controllable semiconductor element 22 A First contact pad 2 A1 Electrically coupled to the first substrate 310 A Second section 3111 A2 And the second controllable semiconductor element 22 B First contact pad 2 B1 Electrically coupled to the second substrate 310 B Second section 3111 B2 First controllable semiconductor element 22 A Third contact pad 2 A3 Electrically coupled to the first substrate 310 A The third section 3111 A3 And the second controllable semiconductor element 22 B Third contact pad 2 B3 Electrically coupled to the second substrate 310 B The third section 3111 B3 .

[0043] exist Figure 3 In the arrangement shown, the controllable semiconductor element 22 A ,twenty two B It is implemented as a so-called vertical device, and consists of two controllable semiconductor elements 22 A ,twenty two B The second contact pad is electrically coupled to the corresponding first segment 3111 through the conductive connection layer. A1 3111 B1 And therefore in Figure 3 It is not visible in the top view. However, the controllable semiconductor element 22 A ,twenty two B Implementing it as a vertical device is merely an example. Conversely, the device can also be implemented as a so-called lateral device. In a lateral device, all contact pads are arranged on the surface of the respective device facing away from the respective substrate 310. If the controllable semiconductor element 22 A ,twenty two B If implemented as a lateral device, then the two controllable semiconductor elements 22 A ,twenty two B The second contact pad can be electrically coupled to the corresponding first segment 3111 via, for example, one or more electrical connection elements 33 (e.g., bonding wires). A1 3111 B1 .

[0044] Still refer to Figure 3 The semiconductor module device 300 also includes components electrically coupled to the first substrate 310. A The third section 3111 A3 The first control terminal 5 is electrically coupled to the first substrate 310. A Second section 3111 A2 The first auxiliary emitter 8, and electrically coupled to the first substrate 310 A First segment 3111 A1 The first collector terminal 7, wherein the first control terminal 5, the first auxiliary emitter terminal 8, and the first collector terminal 7 are arranged in a first section of the housing 37 adjacent to the third lateral side L3. For example, the first collector terminal 7 and the first auxiliary emitter terminal 8 may be arranged on the first substrate 310. A On the additional section. For example, connection to the first substrate 310 can be achieved via electrical connection element 33. A First segment 3111 A1 Second section 3111 A2 The electrical connection is as follows. However, other implementations are also possible. For example, alternatively, the first collector terminal 7 and the first auxiliary emitter terminal 8 can be directly arranged in the first section 3111. A1 Second section 3111A2 Above. The semiconductor module device 300 also includes components electrically coupled to a second substrate 310. B The third section 3111 B3 The second control terminal 6 is electrically coupled to the second substrate 310. B Second section 3111 B2 The second auxiliary emitter 10, and electrically coupled to the second substrate 310 B First segment 3111 B1 The second collector terminal 9, wherein the second control terminal 6, the second auxiliary emitter terminal 10, and the second collector terminal 9 are arranged in a second section of the housing 37 adjacent to the fourth lateral side L4. For example, the second collector terminal 9 and the second auxiliary emitter terminal 10 may be arranged on the second substrate 310. B On the additional section. For example, it can be implemented with the second substrate 310 via electrical connection element 33. B First segment 3111 B1 Second section 3111 B2 The electrical connection is as follows. However, other implementations are also possible. For example, alternatively, the second collector terminal 9 and the second auxiliary emitter terminal 10 can be directly arranged in the first section 3111. B1 Second section 3111 B2 Above. The semiconductor module device 300 also includes components electrically coupled to the first substrate 310. A First segment 3111 A1 The first power supply terminal 1 is electrically coupled to the second substrate 310. B Second section 3111 B2 The second power supply terminal 4 and electrically coupled to the first substrate 310 A Second section 3111 A2 Second substrate 310 B First segment 3111 B1 One or more output terminals 2, 3, wherein the first power supply terminal 1, the second power supply terminal 4 and one or more output terminals 2, 3 are arranged in the third section of the housing 37, the third section being arranged between the first section and the second section.

[0045] In other words, the two substrates 310 carry significant current and voltage. A 310 B The main terminals 1, 2, 3, 4 or power terminals are grouped together, and the first substrate 310 A Any auxiliary terminals and control terminals 5, 7, and 8 are grouped together, and the second substrate 310 B Any auxiliary terminals and control terminals 6, 9, 10 are grouped together, while main terminals 1, 2, 3, 4 are arranged on the first substrate 310.A Auxiliary terminals and control terminals 5, 7, 8 and the second substrate 310 B Between the auxiliary terminals and control terminals 6, 9, and 10.

[0046] This is also Figure 9 The diagram illustrates that, Figure 9 A top view of the housing 37 of the semiconductor module device 300 is shown, wherein the second ends of terminals 1-10 protrude from the housing 37. Figure 9 The arrangement also shows the second ends of the first measuring terminal 11 and the second measuring terminal 12. For example, the first measuring terminal 11 and the second measuring terminal 12 can be connected to the second substrate 310. B The auxiliary terminals and control terminals 6, 9, and 10 are grouped together, or connected to the first substrate 310. A The auxiliary terminals and control terminals 5, 7, and 8 are grouped together.

[0047] According to some embodiments, and as Figure 9 As exemplarily shown, the first control terminal 5 (e.g., at least a second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g., at least a second end of the first auxiliary emitter terminal 8), and the first collector terminal 7 (e.g., at least a second end of the first collector terminal 7) can be arranged in a row and parallel to the third lateral side L3. Similarly, the second control terminal 6 (e.g., at least a second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g., at least a second end of the second auxiliary emitter terminal 10), and the second collector terminal 9 (e.g., at least a second end of the second collector terminal 9) can be arranged in a row and parallel to the fourth lateral side L4.

[0048] According to an alternative embodiment, the first control terminal 5 (e.g., at least a second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g., at least a second end of the first auxiliary emitter terminal 8), and the first collector terminal 7 (e.g., at least a second end of the first collector terminal 7) can be arranged in a row and parallel to the first lateral side L1. Similarly, the second control terminal 6 (e.g., at least a second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g., at least a second end of the second auxiliary emitter terminal 10), and the second collector terminal 9 (e.g., at least a second end of the second collector terminal 9) can be arranged in a row and parallel to the first lateral side L1. According to some embodiments, it is even possible that the first control terminal 5 (e.g., at least a second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g., at least a second end of the first auxiliary emitter terminal 8), the first collector terminal 7 (e.g., at least a second end of the first collector terminal 7), the second control terminal 6 (e.g., at least a second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g., at least a second end of the second auxiliary emitter terminal 10), and the second collector terminal 9 (e.g., at least a second end of the second collector terminal 9) are all arranged in the same row and parallel to, for example, the third lateral side L3 (e.g., see...). Figure 15 Typically, the corresponding terminals can be arranged in any manner with the corresponding sections of the housing 37.

[0049] According to some embodiments, such as Figure 9 As schematically shown, the semiconductor module device 300 includes two output terminals 2 and 3. The second ends of the first power supply terminal 1 and the second power supply terminal 4, both located outside the housing 37, are arranged in a row and parallel to the third lateral side L3 and the fourth lateral side L4. The second ends of the two output terminals 2 and 3, located outside the housing 37, are arranged in a row and parallel to the third lateral side L3 and the fourth lateral side L4. The second ends of the first power supply terminal 1 and the second ends of the second power supply terminal 4 are located between the second ends of the two output terminals 2 and 3 and the fourth lateral side L4. Alternatively, for example, the second ends of the first power supply terminal 1 and the second ends of the second power supply terminal 4 may be located between the second ends of the two output terminals 2 and 3 and the third lateral side L3.

[0050] According to an alternative embodiment, the semiconductor module device 300 includes only one output terminal 2, wherein the second end of the first power supply terminal 1, the second end of the second power supply terminal 4, and the second end of the output terminal 2, located outside the housing 37, are arranged in a row and parallel to the first lateral side L1 and the second lateral side L2. This is in Figure 12 , Figure 13 and Figure 14 It is shown schematically in the diagram.

[0051] According to some embodiments, the second end of the second power supply terminal 4 can be arranged between the second end of the output terminal 2 and the second end of the first power supply terminal 1 (for example, see...). Figure 12 According to an alternative embodiment, the second end of the first power supply terminal 1 may be disposed between the second end of the second power supply terminal 4 and the second end of the output terminal 2 (e.g., see...). Figure 13 According to another alternative embodiment, the second end of the output terminal 2 may be disposed between the second end of the first power supply terminal 1 and the second end of the second power supply terminal 4 (e.g., see...). Figure 14 ).

[0052] For example, a semiconductor module device may include a single half-bridge, such as Figure 3 and Figure 9 As illustrated schematically. However, the semiconductor module device may also include two or even more half-bridges. That is, according to some embodiments, and as shown in the diagram... Figure 4 As schematically shown, the semiconductor module device 300 may further include a third substrate 310 disposed in the housing 37. C and the fourth substrate 310 D This makes the third substrate 310 C Arranged on the fourth substrate 310 D Between the third lateral side L3 and the first substrate 310 A Between the first lateral side L1 and the fourth substrate 310 D Arranged on the second substrate 310 B Between the first lateral side L1, the third substrate 310 C and the fourth substrate 310 D Each of them includes a dielectric insulating layer 311 C 311 D and arranged in dielectric insulating layer 311 C 311 D The first metallization layer 3111 on the surface C 3111 D The first metallization layer 3111 C 3111 D Including the first section 3111 C1 3111 D1 Second section 3111 C2 3111 D2 and the third section 3111 C3 3111 D3 The semiconductor module device may also include components disposed on a third substrate 310. C The third controllable semiconductor element 22 C and arranged on the fourth substrate 310D The fourth controllable semiconductor element 22 D The third controllable semiconductor element 22 C and the fourth controllable semiconductor element 22 D Each of them includes a first contact pad 2x1, a second contact pad, and a third contact pad 2x3.

[0053] Third controllable semiconductor element 22 C The second contact pad is electrically coupled to the third substrate 310 C First segment 3111 C1 And the fourth controllable semiconductor element 22 D The second contact pad is electrically coupled to the fourth substrate 310 D First segment 3111 D1 Third controllable semiconductor element 22 C First contact pad 2 C1 Electrically coupled to the third substrate 310 C Second section 3111 C2 And the fourth controllable semiconductor element 22 D First contact pad 2 D1 Electrically coupled to the fourth substrate 310 D Second section 3111 D2 .

[0054] The semiconductor module device 300 also includes an electrical coupling to a third substrate 310. C First segment 3111 C1 The additional first power supply terminal 1 is electrically coupled to the fourth substrate 310. D Second section 3111 D2 The additional second power supply terminal 4, and electrically coupled to the third substrate 310 C Second section 3111 C2 and the fourth substrate 310 D First segment 3111 D1 One or more additional output terminals 2, 3, wherein an additional first power supply terminal 1, an additional second power supply terminal 4 and one or more additional output terminals 2, 3 are arranged in the third section of the housing 37 and between the first lateral side L1 and the first power supply terminal 1, the second power supply terminal 4 and one or more output terminals 2, 3.

[0055] In other words, the third substrate 310 C and the fourth substrate 310 D The first and second sections 3111 C1 3111 D1 3111 C2 3111 D2Electrical connections are formed outside the housing 37 by electrically coupling a first power supply terminal 1 to an additional first power supply terminal 1, a second power supply terminal 4 to an additional second power supply terminal 4, and one or more output terminals 2 and 3 to one or more additional output terminals 2 and 3, respectively. For example, on the first substrate 310... A First segment 3111 A With the third substrate 310 C First segment 3111 C1 Between, or on the first substrate 310 A Second section 3111 A2 With the third substrate 310 C Second section 3111 C2 There are no internal connections between them (e.g., via bonding line 33). Similarly, in, for example, the second substrate 310 B First segment 3111 B1 With the fourth substrate 310 D First segment 3111 D1 Between, or on the second substrate 310 B Second section 3111 B2 With the fourth substrate 310 D Second section 3111 D2 There is no internal connection between them (e.g., via bonding line 33). Similarly, in the first substrate 310 A Second substrate 310 B No additional electrical connections (e.g., bonding wires) are required between them. First substrate 310 A Second substrate 310 B Any electrical connection between them is provided via a first power supply terminal 1, a second power supply terminal 4, and one or more output terminals 2, 3. The same applies to the third substrate 310. C and the fourth substrate 310 D .

[0056] exist Figure 4 In the example shown, the third substrate 310 C and the fourth substrate 310 D This does not include separate auxiliary terminals and control terminals. For example, the third controllable semiconductor element 22 C Third contact pad 2 C3 It can be electrically coupled to the first substrate 310 A The third section 3111 A3 And the fourth controllable semiconductor element 22 D Third contact pad 2 D3 It can be electrically coupled to the second substrate 310 B The third section 3111 B3That is, an internal connection (e.g., via bonding line 33) can be provided to allow the third substrate 310 to be connected. C and the fourth substrate 310 D Electrically coupled to the first substrate 310 respectively A Second substrate 310 B The corresponding auxiliary terminals and control terminals on it. Figure 4 For clarity, the third substrate 310 is not explicitly shown. C and the fourth substrate 310 D Electrically coupled to the first substrate 310 respectively A Second substrate 310 B Electrical connections to auxiliary terminals 7, 8, 9, and 10. However, refer to... Figure 5 Third substrate 310 C and the fourth substrate 310 D Alternatively, it may include separate control terminals and separate auxiliary terminals. That is, the third substrate 310 C It can (basically) be used with the first substrate 310 A The same, and the fourth substrate 310 D It can (basically) be used with the second substrate 310 B Same. For example, this is also in Figure 16 It is shown schematically in the diagram.

[0057] However, as in, for example Figure 2 , Figures 3 to 5 as well as Figures 7 to 9 The half-bridge arrangement shown is just one example among many. According to alternative embodiments, passive semiconductor elements such as diodes can be used instead of controllable semiconductor elements. This is in... Figure 6 The diagram is schematically shown. That is, according to some embodiments, the semiconductor module device 300 includes a housing 37, which includes a first lateral side L1, a second lateral side L2 opposite to the first lateral side L1, a third lateral side L3 perpendicular to the first lateral side L1 and the second lateral side L2, and a fourth lateral side L4 opposite to the third lateral side L3. The semiconductor module device 300 also includes a first substrate 310 disposed within the housing 37. A Second substrate 310 B This makes the first substrate 310 A Arranged on the second substrate 310 B Between the first substrate 310 and the third lateral side L3 A Second substrate 310 B Each of them includes a dielectric insulating layer 311 A 311 B and arranged in dielectric insulating layer 311 A 311 BThe first metallization layer 3111 on the surface A 3111 B The first metallization layer 3111 A 3111 B Including the first section 3111 A1 3111 B1 Second section 3111 A2 3111 B2 The semiconductor module device 300 also includes a first substrate 310 disposed thereon. A The first semiconductor element 22 A and arranged on the second substrate 310 B The second semiconductor element 22 B The first semiconductor element 22 A Second semiconductor element 22 B Each of them includes a first contact pad 2x1 and a second contact pad. First semiconductor element 22 A The second contact pad is electrically coupled to the first substrate 310 A First segment 3111 A1 And the second semiconductor element 22 B The second contact pad is electrically coupled to the second substrate 310 B First segment 3111 B1 First semiconductor element 22 A First contact pad 2 A1 Electrically coupled to the first substrate 310 A Second section 3111 A2 And the second semiconductor element 22 B First contact pad 2 Bl Electrically coupled to the second substrate 310 B Second section 3111 B2 The semiconductor module device 300 also includes components electrically coupled to the first substrate 310. A First segment 3111 A1 The first power supply terminal 1 is electrically coupled to the second substrate 310. B Second section 3111 B2 The second power supply terminal 4 and electrically coupled to the first substrate 310 A Second section 3111 A2 Second substrate 310 B First segment 3111 B1One or more output terminals 2, 3, wherein the first power supply terminal 1, the second power supply terminal 4 and one or more output terminals 2, 3 are arranged in the third section of the housing 37, the third section being arranged between the third lateral side L3 and the fourth lateral side L4, wherein the distance between the third section of the housing 37 and the third lateral side L3 is substantially equal to the distance between the third section of the housing 37 and the fourth lateral side.

[0058] When passive semiconductor elements, such as diodes, are used instead of controllable semiconductor elements, auxiliary terminals are typically not required. Therefore, in this case, the arrangement may only include the main terminals. In this case, the semiconductor substrate 310 does not necessarily have to include the third segment 31113 of the first metallization layer 3111. However, the substrate 310 can generally be implemented in the same manner, regardless of whether a passive semiconductor element or a controllable semiconductor element is arranged on it. For example, if a passive semiconductor element is arranged on the substrate 310 including the third segment 31113, the third segment 31113 may simply not be electrically contacted. Similarly, other segments, elements, or terminals may not be electrically contacted, even if they are defaulted to being on the substrate 310. For example, such arrangements can typically be combined in a single housing 37. Figure 3 One or more arrangements described and as about Figure 6 One or more arrangements are described.

[0059] like Figure 3 and Figure 6 The arrangement shown is highly symmetrical. In these examples, the first substrate 310 A Second substrate 310 B In particular, the first and second sections 3111 of the corresponding first metallization layer A1 3111 A2 3111 B1 3111 B2 Implemented in a (nearly) symmetrical manner. However, as Figure 3 and Figure 6 The first and second sections 3111 shown A1 3111 A2 3111 B1 3111 B2 The specific shape and arrangement are merely one implementation among several possible methods. (See reference) Figure 7 The first and second sections 3111 are schematically shown. A1 3111 A2 3111 B1 3111 B2 Another possible implementation. It should be noted that the first metallization layer 3111 x A segment can be formed from a single continuous segment. For example, for Figure 3 , Figure 4 , Figure 5 and Figure 6 The first and second segments 3111 in the example shown A1 3111 B1 3111 A2 3111 B2 This is the situation. However, the first metallization layer 3111 x A segment can also be formed by two or more separate segments, however, these two or more separate segments are electrically coupled to each other by one or more electrical connection elements (e.g., bonding wires, bonding strips, connecting plates, or conductor rails). For example, for Figure 7 The second segment 3111 in the example shown A2 3111 B2 That's the case. Many other different implementations (e.g., shape, arrangement, etc.) are often possible. Figure 3 , Figure 6 and Figure 7 In the example shown, the first substrate 310 A Second substrate 310 B The heights are the same. According to some examples, the first substrate 310... A Second substrate 310 B It can be relative to the first substrate 310 A Second substrate 310 B The axes of symmetry extending between and parallel to the third longitudinal side L3 and the fourth longitudinal side L4 are essentially symmetrical.

[0060] However, a first substrate 310 is not necessarily required. A Second substrate 310 B They are symmetrical to each other. (Reference) Figure 8 The first substrate 310 can also be implemented in different ways. A Second substrate 310 B .exist Figure 8 In the illustrated embodiments, for example, according to Figure 3 Example implementation of first substrate 310 A According to Figure 7 Example implementation of second substrate 310 B However, the first substrate 310 A Second substrate 310 B Each of them can be implemented in any other appropriate manner.

[0061] According to some embodiments, the first substrate 310 A First segment 3111 A1 Second section 3111 A2At least a portion of it may be along the first substrate 310 A Facing the second substrate 310 B Extending to one side. Similarly, the second substrate 310 B First segment 3111 B Second section 3111 B At least a portion of it may be along the second substrate 310 B Facing the first substrate 310 A Extending to one side. This allows for the centered arrangement of the first power supply terminal 1, the second power supply terminal 4, and one or more output terminals 2 and 3 between the third longitudinal side L3 and the fourth longitudinal side L4.

[0062] Now for reference Figure 10 The figure schematically illustrates a top view of a semiconductor module device according to a further embodiment of the present disclosure. In this example, the semiconductor module device includes a first substrate, a second substrate, a third substrate, and a fourth substrate as described above, as well as additional fifth and sixth substrates. For clarity, the first metallization layer and the (controllable) semiconductor elements are not specifically shown in the figure. Figure 10 The diagram only schematically illustrates the electrical connections between different substrates (e.g., auxiliary terminals and control terminals respectively connecting the different substrates to the first and second substrates). As described above, no electrical connections are provided between the different substrates relative to the main terminal. That is, each pair of substrates is provided with a separate first power supply terminal 1, a second power supply terminal 4, and output terminals 2 and 3. As described above, the first and second substrates form a pair of substrates, and the third and fourth substrates form a pair of substrates. Similarly, the fifth and sixth substrates form a pair of substrates.

[0063] Figure 11 A schematic three-dimensional view of the housing 37 of a semiconductor module device according to some embodiments of the present disclosure is shown. As described above and as Figure 11 As schematically shown, the semiconductor module device may include two output terminals 2 and 3, wherein the second ends of the first power supply terminal 1 and the second power supply terminal 4, located outside the housing 37, are arranged in a row and parallel to the third lateral side L3 and the fourth lateral side L4. The second ends of the two output terminals 2 and 3, located outside the housing 37, are arranged in a row and parallel to the third lateral side L3 and the fourth lateral side L4. The second ends of the first power supply terminal 1 and the second power supply terminal 4 are located between the second ends of the two output terminals 2 and 3 and the fourth lateral side L4. This arrangement of the second ends of the corresponding main terminals may be identical for each pair of substrates included in the semiconductor module device.

[0064] As described above, according to an alternative embodiment, the semiconductor module device may include only one output terminal 2, wherein the second end of the first power supply terminal 1 arranged outside the housing 37, the second end of the second power supply terminal 4 arranged outside the housing 37, and the second end of the output terminal 2 arranged outside the housing 37 are arranged in a row and parallel to the first lateral side L1 and the second lateral side L2.

[0065] Figure 12 A schematic three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is shown. In this embodiment, the second end of the second power supply terminal 4 may be arranged between the second end of the output terminal 2 and the second end of the first power supply terminal 1. This arrangement of the second ends of the corresponding main terminals may be the same for each pair of substrates included in the semiconductor module device. Figure 13 A schematic three-dimensional view of a housing of a semiconductor module device according to a further embodiment of the present disclosure is shown. In this embodiment, the second end of the first power supply terminal 1 may be arranged between the second end of the second power supply terminal 4 and the second end of the output terminal 2. This arrangement of the second ends of the corresponding main terminals may be the same for each pair of substrates included in the semiconductor module device. Figure 14 A schematic three-dimensional view of the housing of a semiconductor module device according to a further embodiment of the present disclosure is shown. In this embodiment, the second end of the output terminal 2 may be arranged between the second end of the first power supply terminal 1 and the second end of the second power supply terminal 4. This arrangement of the second ends of the corresponding main terminals may be the same for each pair of substrates included in the semiconductor module device.

[0066] Figure 15 A schematic three-dimensional view of a housing 37 of a semiconductor module device according to a further embodiment of the present disclosure is shown. In this embodiment, all auxiliary terminals are arranged in the same row along the third longitudinal side L3 of the housing 37. Figure 16 A schematic three-dimensional view of a housing 37 of a semiconductor module device according to a further embodiment of the present disclosure is shown. In this embodiment, auxiliary terminals are provided for each pair of substrates, similar to those regarding... Figure 5 The situation described.

[0067] Figure 17 A three-dimensional view of a semiconductor module device according to a further embodiment of the present disclosure is schematically shown. In this example, possible implementations of different terminals are schematically illustrated. Different substrates and corresponding first metallization layers and different segments of the controllable semiconductor elements are shown. Figure 17 As can be seen in the image. For clarity, in... Figure 17 No connection wires or other internal electrical connections are shown.

[0068] The semiconductor module devices according to the various embodiments described herein meet several different requirements. For example, the semiconductor module devices according to the various examples described herein have relatively low stray inductance. For example, stray inductance is reduced by centrally arranging one or more output terminals 2, 3 and the first power supply terminal 1 and the second power supply terminal 4 between the third longitudinal side L3 and the fourth longitudinal side L4. Furthermore, highly symmetrical switching characteristics between the low and high sides can be achieved by the semiconductor module devices described herein. The overall losses in the semiconductor module devices described herein are also quite low.

Claims

1. A semiconductor module device (300), comprising: The housing (37) includes a first lateral side (L1), a second lateral side (L2) opposite to the first lateral side (L1), a third lateral side (L3) perpendicular to the first lateral side (L1) and the second lateral side (L2), and a fourth lateral side (L4) opposite to the third lateral side (L3). First substrate (310) A ) and second substrate (310) B ), arranged in the housing (37) such that the first substrate (310) A ) arranged on the second substrate (310) B Between the first substrate (310) and the third lateral side (L3), A ) and the second substrate (310) B Each of these includes a dielectric insulating layer (311) A 311 B ) and arranged in the dielectric insulating layer (311) A 311 B The first metallization layer (3111) on the surface of the surface A 3111 B ), wherein the first metallization layer (3111) A 3111 B ) including the first section (3111) A1 3111 B1 ) and the second section (3111) A2 3111 B2 ),as well as Arranged on the first substrate (310) A The first semiconductor element (22) on the ) A ) and arranged on the second substrate (310) B The second semiconductor element (22) on B ), wherein the first semiconductor element (22) A ) and the second semiconductor element (22) B Each of the following includes a first contact pad (2x1) and a second contact pad, wherein, The first semiconductor element (22) A The second contact pad is electrically coupled to the first substrate (310). A The first segment (3111) A1 ), and the second semiconductor element (22) B The second contact pad is electrically coupled to the second substrate (310). B The first segment (3111) B1 ), The first semiconductor element (22) A The first contact pad (2) A1 ) electrically coupled to the first substrate (310) A The second section (3111) A2 ), and the second semiconductor element (22) B The first contact pad (2) B1 ) electrically coupled to the second substrate (310) B The second section (3111) B2 ), The semiconductor module device (300) also includes Electrically coupled to the first substrate (310) A The first segment (3111) A1 The first power supply terminal (1) of the second substrate (310) is electrically coupled to the second substrate (310). B The second section (3111) B2 The second power supply terminal (4) and electrically coupled to the first substrate (310) A The second section (3111) A2 ) and the second substrate (310) B The first segment (3111) B1 One or more output terminals (2, 3) of the housing (37), wherein the first power supply terminal (1), the second power supply terminal (4) and the one or more output terminals (2, 3) are arranged in a third section of the housing (37) between the third lateral side (L3) and the fourth lateral side (L4), wherein the distance between the third section of the housing (37) and the third lateral side (L3) is substantially equal to the distance between the third section of the housing (37) and the fourth lateral side.

2. The semiconductor module device (300) according to claim 1, wherein, The first substrate (310) A ) and the second substrate (310) B The first metallization layer (3111) of each of them A 3111 B It also includes the third section (3111) A3 3111 B3 ); The first semiconductor element (22) A ) is a controllable semiconductor element, and also includes a third contact pad (2 A3 ); The second semiconductor element (22) B ) is a controllable semiconductor element, and also includes a third contact pad (2 B3 ); The first controllable semiconductor element (22) A The third contact pad (2) A3 ) electrically coupled to the first substrate (310) A The third segment (3111) of the above A3 ), and the second controllable semiconductor element (22) B The third contact pad (2) B3 ) electrically coupled to the second substrate (310) B The third segment (3111) of the above B3 );and The semiconductor module device (300) further includes: Electrically coupled to the first substrate (310) A The third segment (3111) of the above A3 The first control terminal (5) is electrically coupled to the first substrate (310). A The second section (3111) A2 The first auxiliary emitter tip (8), and electrically coupled to the first substrate (310) A The first segment (3111) A1 The first collector terminal (7) of the housing (37) is arranged in the first section between the third section and the third lateral side (L3) of the housing (37). Electrically coupled to the second substrate (310) B The third segment (3111) of the above B3 The second control terminal (6) is electrically coupled to the second substrate (310). B The second section (3111) B2 The second auxiliary emitter tip (10) and electrically coupled to the second substrate (310) B The first segment (3111) B1 The second collector terminal (9) of the housing (37) is arranged in the first section of the housing (37) or in the second section of the housing (37) between the third section and the fourth lateral side (L4).

3. The semiconductor module device (300) according to claim 2, wherein, The first control terminal (5), the first auxiliary transmitter terminal (8), and the first collector terminal (7) are arranged in a row and parallel to the third lateral side (L3).

4. The semiconductor module device (300) according to claim 2 or 3, wherein, The second control terminal (6), the second auxiliary transmitter terminal (10), and the second collector terminal (9) are arranged in a row and parallel to the fourth lateral side (L4).

5. The semiconductor module device (300) according to any one of claims 1-4, comprising two output terminals (2, 3), wherein, The second end of the first power supply terminal (1) outside the housing (37) and the second end of the second power supply terminal (4) outside the housing (37) are arranged in a row and parallel to the third lateral side (L3) and the fourth lateral side (L4). The two output terminals (2, 3) are arranged in a row outside the housing (37) at their second ends, parallel to the third lateral side (L3) and the fourth lateral side (L4). The second end of the first power supply terminal (1) and the second end of the second power supply terminal (4) are arranged between the second ends of the two output terminals (2, 3) and the fourth lateral side (L4).

6. The semiconductor module device (300) according to any one of claims 1-4, comprising an output terminal (2), wherein, The second end of the first power supply terminal (1) outside the housing (37), the second end of the second power supply terminal (4) outside the housing (37), and the second end of the output terminal (2) outside the housing (37) are arranged in a row and parallel to the first lateral side (L1) and the second lateral side (L2).

7. The semiconductor module device (300) according to claim 6, wherein, The second end of the second power supply terminal (4) is arranged between the second end of the output terminal (2) and the second end of the first power supply terminal (1).

8. The semiconductor module device (300) according to claim 6, wherein, The second end of the first power supply terminal (1) is arranged between the second end of the second power supply terminal (4) and the second end of the output terminal (2).

9. The semiconductor module device (300) according to claim 6, wherein, The second end of the output terminal (2) is arranged between the second end of the first power supply terminal (1) and the second end of the second power supply terminal (4).

10. The semiconductor module device (300) according to any one of the preceding claims further includes: Third substrate (310) C ) and the fourth substrate (310) D The third substrate (310) C ) and the fourth substrate (310) D The third substrate (310) is arranged in the housing (37) such that the third substrate (310) C ) arranged on the fourth substrate (310) D Between the first substrate (310) and the third lateral side (L3) and the first substrate (310) A Between the first lateral side (L1) and the fourth substrate (310) D ) arranged on the second substrate (310) B Between the third substrate (310) and the first lateral side (L1), C ) and the fourth substrate (310) D Each of these includes a dielectric insulating layer (311) C 311 D ) and arranged in the dielectric insulating layer (311) C 311 D The first metallization layer (3111) on the surface of the surface C 3111 D ), wherein the first metallization layer (3111) C 3111 D ) including the first section (3111) C1 3111 D1 ) and the second section (3111) C2 3111 D2 ),as well as Arranged on the third substrate (310) C The third semiconductor element (22) on C ) and arranged on the fourth substrate (310) D The fourth semiconductor element (22) on D ), wherein the third semiconductor element (22) C ) and the fourth semiconductor element (22) D Each of the following includes a first contact pad (2x1) and a second contact pad, wherein, The third semiconductor element (22) C The second contact pad is electrically coupled to the third substrate (310). C The first segment (3111) C1 ), and the fourth semiconductor element (22) D The second contact pad is electrically coupled to the fourth substrate (310). D The first segment (3111) D1 ), The third semiconductor element (22) C The first contact pad (2) C1 Electrically coupled to the third substrate (310) C The second section (3111) C2 ), and the fourth semiconductor element (22) D The first contact pad (2) D1 Electrically coupled to the fourth substrate (310) D The second section (3111) D2 ), The semiconductor module device (300) also includes Electrically coupled to the third substrate (310) C The first segment (3111) C1 The additional first power supply terminal (1) is electrically coupled to the fourth substrate (310). D The second section (3111) D2 The additional second power supply terminal (4), and electrically coupled to the third substrate (310) C The second section (3111) C2 ) and the fourth substrate (310) D The first segment (3111) D1 One or more additional output terminals (2, 3) of the housing (37), wherein the additional first power supply terminal (1), the additional second power supply terminal (4) and the one or more additional output terminals (2, 3) are arranged in the third section of the housing (37) and between the first lateral side (L1) and the first power supply terminal (1), the second power supply terminal (4) and the one or more output terminals (2, 3).

11. The semiconductor module device (300) according to claim 10, wherein, The third semiconductor element (22) C ) is a controllable semiconductor element, and also includes a third contact pad (2 C3 ); The fourth semiconductor element (22) D ) is a controllable semiconductor element, and also includes a third contact pad (2 D3 );and The third controllable semiconductor element (22) C The third contact pad (2) C3 ) electrically coupled to the first substrate (310) A The third segment (3111) of the above A3 ), and the fourth controllable semiconductor element (22) D The third contact pad (2) D3 ) electrically coupled to the second substrate (310) B The third segment (3111) of the above B3 ).

12. The semiconductor module device (300) according to any one of the preceding claims, wherein, The first semiconductor element (22) A ) and the second semiconductor element (22) B Each of the following includes at least one diode, at least one IGBT, at least one MOSFET, at least one JFET, or at least one HEMT.

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