Method of manufacturing a semiconductor structure
Patent Information
- Application Number
- CN202510361031.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-09-29
AI Technical Summary
[0005]鉴于以上所述现有技术的缺点，本发明的目的在于提供一种半导体结构的制备方法，用于解决现有技术中因基底表面活性位点密度差异造成其上形成的材料层厚度差异的问题
[0030]如上所述，本发明的半导体结构的制备方法，对半导体基底的I/O区及Core区进行选择性处理，包括对Core区进行硅基化处理以钝化Core区的-OH活性位点形成钝化层，及进行UV/O3处理去除钝化层恢复Core区的-OH活性位点，可根据需要改变半导体基底表面的-OH活性位点的密度，且结合两次高K介电层的沉积，最终可改善高K介电层在半导体基底不同区域上的厚度差异。
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Figure CN122846795A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a method for preparing a semiconductor structure. Background Technology
[0002] In metal-oxide-semiconductor transistors (MOSFETs), the substrate materials corresponding to the HfO2 layer in the core region and the input / output (I / O) region of the device are different. The chemical oxide layer (IL) is more suitable for the core region, where electrical performance requirements are extremely high, due to its high interface quality, which reduces long-range Coulomb scattering and improves carrier mobility. The thermal oxide layer (ISSG), on the other hand, is more suitable for the I / O region, which requires high reliability and high-precision control, and is applicable to high-frequency and high-power applications.
[0003] Currently, the preparation of HfO2 layers commonly employs thermal atomic layer deposition (ALD), using HfCl4 and H2O as precursors. Nucleation strongly depends on the number of active sites on the substrate, i.e., the density of hydroxyl groups (-OH). For example... Figure 1 The diagram illustrates the density distribution of -OH active sites in the Core and I / O regions of existing semiconductor structures, as well as... Figure 2 The diagram illustrates the thickness structure of HfO2 layers formed on the Core and I / O regions of existing semiconductor structures. Specifically, the HfO2 layer is thicker on the Core (IL) region due to the greater number of -OH active sites and the shorter nucleation delay, while the HfO2 layer is thinner on the ISSG region due to the fewer -OH active sites. This results in different incubation characteristics of the HfO2 layer on different substrates, leading to a significant difference in film thickness between the Core and I / O regions. This difference, in turn, affects the equivalent oxide thickness (EOT) and the inverted oxide layer thickness (Tinv).
[0004] Therefore, it is necessary to provide a method for fabricating semiconductor structures. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a semiconductor structure to solve the problem of material layer thickness differences caused by differences in the density of active sites on the substrate surface in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:
[0007] A semiconductor substrate is provided, the semiconductor substrate including an I / O region and a Core region;
[0008] A first dielectric layer is formed in the I / O region of the semiconductor substrate, and a second dielectric layer is formed in the Core region of the semiconductor substrate. The surfaces of the first dielectric layer and the second dielectric layer both have -OH active sites, and the density of -OH active sites in the first dielectric layer is less than the density of -OH active sites in the second dielectric layer.
[0009] The Core region is siliconized to passivate the -OH active sites of the second dielectric layer and form a passivation layer;
[0010] A first deposition of a high-k dielectric layer is performed, forming the high-k dielectric layer with a first thickness on the surface of the first dielectric layer;
[0011] UV / O3 treatment is performed to remove the passivation layer and restore the -OH active sites of the second dielectric layer.
[0012] A second deposition of the high-K dielectric layer is performed, and a high-K dielectric layer with a second thickness is formed on the surface of the first dielectric layer and a high-K dielectric layer with a third thickness is formed on the surface of the second dielectric layer.
[0013] Optionally, the sum of the first thickness and the second thickness is equal to the third thickness or the difference between the first thickness and the second thickness is less than a preset threshold.
[0014] Optionally, the sum of the first thickness and the second thickness is greater than the third thickness.
[0015] Optionally, the silanizing agent used in the silanization process includes HMDS solution, ODTS solution, or OTS solution.
[0016] Optionally, the step of siliconizing the Core region includes:
[0017] A photoresist layer is formed on the surface of the first dielectric layer by photolithography;
[0018] Siliconization process;
[0019] The photoresist layer was removed by wet etching.
[0020] Optionally, the first dielectric layer includes a first silicon oxide layer formed by thermal oxidation, and the second dielectric layer includes a second silicon oxide layer formed by chemical oxidation; wherein the surfaces of both the first dielectric layer and the second dielectric layer have -OH active sites, and the density of -OH active sites in the first dielectric layer is less than the density of -OH active sites in the second dielectric layer.
[0021] Optionally, the steps for preparing the first silicon oxide layer and the second silicon oxide layer include:
[0022] The first silicon oxide layer is formed on the surface of the semiconductor substrate using a thermal oxidation method;
[0023] A photoresist layer is formed on the surface of the first dielectric layer in the I / O region by photolithography.
[0024] Etching is performed to remove the first silicon oxide layer located in the Core region;
[0025] Remove the photoresist layer;
[0026] The second silicon oxide layer is formed on the surface of the semiconductor substrate in the Core region by chemical oxidation.
[0027] Optionally, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
[0028] Optionally, the method for forming the high-k dielectric layer includes PECVD, LPCVD, PEALD, or Thermal ALD.
[0029] Optionally, the high-k dielectric layer formed includes one or a combination of HfO2 layer, TiO2 layer, HfZrO layer, HfSiNO layer, Ta2O5 layer, ZrO2 layer, ZrSiO2 layer, Al2O3 layer, SrTiO3 layer and BaSrTiO layer.
[0030] As described above, the semiconductor structure fabrication method of the present invention selectively processes the I / O region and Core region of the semiconductor substrate, including siliconization of the Core region to passivate the -OH active sites in the Core region to form a passivation layer, and UV / O3 treatment to remove the passivation layer and restore the -OH active sites in the Core region. The density of -OH active sites on the surface of the semiconductor substrate can be changed as needed, and combined with the deposition of two high-k dielectric layers, the thickness difference of the high-k dielectric layer in different regions of the semiconductor substrate can be improved. Attached Figure Description
[0031] Figure 1 This is a density distribution diagram of -OH active sites in the I / O region and Core region of a semiconductor structure in the prior art.
[0032] Figure 2 This diagram shows the thickness structure of the HfO2 layer formed on the I / O and Core regions of a semiconductor structure in the prior art.
[0033] Figure 3 The diagram shows the fabrication process flow of the semiconductor structure in an embodiment of the present invention.
[0034] Figure 4 The diagram shown is a schematic representation of the structure after the formation of the ISSG silicon oxide layer in an embodiment of the present invention.
[0035] Figure 5 The diagram shown is a schematic representation of the structure after the patterned photoresist layer is formed in an embodiment of the present invention.
[0036] Figure 6 The diagram shown is a schematic representation of the structure after removing the ISSG silicon oxide layer located in the Core region in an embodiment of the present invention.
[0037] Figure 7 The diagram shown is a schematic representation of the structure after removing the photoresist layer in an embodiment of the present invention.
[0038] Figure 8 The diagram shows the structure after an IL silicon oxide layer is formed in the Core region according to an embodiment of the present invention.
[0039] Figure 9 This is a schematic diagram of the structure after a photoresist layer is formed on the ISSG silicon oxide layer in the I / O region according to an embodiment of the present invention.
[0040] Figure 10 The diagram shown is a schematic representation of the structure after siliconization treatment to form a passivation layer in an embodiment of the present invention.
[0041] Figure 11 Displayed as Figure 10 A schematic diagram of the interface structure of the Core area.
[0042] Figure 12 The diagram shown is a schematic representation of the structure after removing the photoresist layer in an embodiment of the present invention.
[0043] Figure 13 This is a schematic diagram of the structure after the first deposition of the HfO2 layer in an embodiment of the present invention.
[0044] Figure 14 The diagram shown is a schematic representation of the structure undergoing UV / O3 treatment in an embodiment of the present invention.
[0045] Figure 15 Displayed as Figure 14 A schematic diagram of the interface structure of the Core area.
[0046] Figure 16 This is a schematic diagram of the structure after the second deposition of the HfO2 layer in an embodiment of the present invention.
[0047] Explanation of reference numerals in the attached figures
[0048] 100 Silicon substrate
[0049] 201 ISSG silicon oxide layer
[0050] 202 IL silicon oxide layer
[0051] 300 photoresist layers
[0052] 400 passivation layer
[0053] 501 HfO2 layer of first thickness d1
[0054] 502 HfO2 layer of second thickness d2
[0055] 503 HfO2 layer of third thickness d3 Detailed Implementation
[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0059] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0060] like Figure 3This embodiment provides a method for fabricating a semiconductor structure, including the following steps:
[0061] S1: Provides a semiconductor substrate, the semiconductor substrate including an I / O region and a Core region;
[0062] S2: A first dielectric layer is formed in the I / O region of the semiconductor substrate, and a second dielectric layer is formed in the Core region of the semiconductor substrate, wherein the surfaces of the first dielectric layer and the second dielectric layer both have -OH active sites;
[0063] S3: The Core region is siliconized to passivate the -OH active sites of the second dielectric layer and form a passivation layer;
[0064] S4: Perform the first deposition of the high-k dielectric layer to form the high-k dielectric layer with a first thickness on the surface of the first dielectric layer;
[0065] S5: Perform UV / O3 treatment to remove the passivation layer and restore the -OH active sites of the second dielectric layer;
[0066] S6: Perform a second deposition of the high-K dielectric layer, and continue to form the high-K dielectric layer with a second thickness on the surface of the first dielectric layer and the high-K dielectric layer with a third thickness on the surface of the second dielectric layer.
[0067] This embodiment selectively processes the I / O region and Core region of the semiconductor substrate, including performing siliconization on the Core region to passivate the -OH active sites in the Core region to form the passivation layer, and performing UV / O3 treatment to remove the passivation layer and restore the -OH active sites in the Core region. The density of -OH active sites on the surface of the semiconductor substrate can be changed as needed, and combined with the deposition of the high-k dielectric layer twice, the thickness difference of the high-k dielectric layer in different regions of the semiconductor substrate can be improved.
[0068] The following combination Figures 4 to 16 The fabrication of the semiconductor structure is described below.
[0069] First, refer to Figure 3 and Figure 4 Step S1 is executed to provide a semiconductor substrate, which includes an I / O region and a Core region.
[0070] For details, please refer to Figure 4In this embodiment, the semiconductor substrate is a silicon substrate 100, but the type of semiconductor substrate is not limited to this. For example, the semiconductor substrate can also be a glass substrate, a sapphire substrate, a III-V group semiconductor substrate, etc. The specific type of semiconductor substrate is not excessively limited here.
[0071] To better improve the performance and subsequent applications of the semiconductor structure, this embodiment divides the I / O region and the Core region during the fabrication process of the semiconductor structure.
[0072] Next, refer to Figure 3 and Figures 4-8 Step S2 is executed, in which a first dielectric layer is formed in the I / O region of the semiconductor substrate, and a second dielectric layer is formed in the Core region of the semiconductor substrate. The surfaces of the first dielectric layer and the second dielectric layer both have -OH active sites, and the density of -OH active sites in the first dielectric layer is less than the density of -OH active sites in the second dielectric layer.
[0073] For details, please refer to Figure 4 In this embodiment, the first dielectric layer is a first silicon oxide layer formed by thermal oxidation (OX), namely, the ISSG silicon oxide layer 201 prepared by in-situ steam generation (ISSG). The second dielectric layer is a second silicon oxide layer formed by chemical oxidation (OX), namely, the IL silicon oxide layer 202 serving as an interface layer (IL). This makes the ISSG silicon oxide layer 201 more suitable for I / O areas requiring high reliability and high precision control, and makes the IL silicon oxide layer 202 more suitable for Core areas with extremely high electrical performance requirements.
[0074] The ISSG silicon oxide layer 201 and the IL silicon oxide layer 202 both have -OH active sites on their surfaces, and the density (or number) of -OH active sites on the surface of the ISSG silicon oxide layer 201 is less than the density of -OH active sites on the surface of the IL silicon oxide layer 202 (see [reference]). Figure 1 The difference in the density of these -OH active sites directly affects the nucleation delay of the subsequently deposited material film, resulting in undesirable thickness differences in the prepared film (see...). Figure 2 The technical solution in this application can effectively solve this problem and alleviate the thickness difference of the material layer formed on different regions of the semiconductor substrate.
[0075] The choice of materials for the first dielectric layer and the second dielectric layer is not limited to silicon oxide, and the preparation process is not limited to thermal OX and chemical OX. Other processes can be used to prepare the silicon oxide layer, or other material layers with different -OH active site densities can be used. No excessive restrictions are imposed here.
[0076] The steps for preparing the ISSG silicon oxide layer 201 and the IL silicon oxide layer 202 may include:
[0077] like Figure 4 First, step S2-1 is performed to form the first silicon oxide layer on the surface of the semiconductor substrate using a thermal oxidation method, that is, the ISSG silicon oxide layer 201 is prepared on the surface of the silicon substrate 100 using an ISSG process.
[0078] like Figure 5 Next, step S2-2 is performed, in which a photoresist layer 300 is formed on the surface of the first dielectric layer in the I / O region by photolithography. That is, the patterned photoresist layer 300 is prepared on the surface of the ISSG silicon oxide layer 201 by means of coating or photolithography to cover the surface of the ISSG silicon oxide layer 201 and to protect the surface of the ISSG silicon oxide layer 201 by the photoresist layer 300.
[0079] like Figure 6 Next, step S2-3 is performed to etch and remove the first silicon oxide layer located in the Core region. That is, using the photoresist layer 300 as a mask, the ISSG silicon oxide layer 201 is etched to remove the ISSG silicon oxide layer 201 located in the Core region and expose the silicon substrate 100 in the Core region.
[0080] like Figure 7 Next, proceed to steps S2-4 to remove the photoresist layer 300 to expose the silicon substrate 100 of the I / O area. For example, the photoresist layer 300 can be removed by wet etching.
[0081] like Figure 8 Next, the second silicon oxide layer is formed on the surface of the semiconductor substrate in the Core region by chemical oxidation, that is, the IL silicon oxide layer 202 is formed on the surface of the silicon substrate 100 in the Core region by chemical oxidation.
[0082] Preferably, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, i.e., as shown below. Figure 8In this configuration, the thickness D1 of the ISSG silicon oxide layer 201 located in the I / O region is preferably greater than the thickness D2 of the IL silicon oxide layer 202 located in the Core region, so as to further improve the semiconductor structure's requirements for material layer thickness in different regions and improve performance.
[0083] Next, refer to Figure 3 , Figures 9-12 Step S3 is executed to perform silylation on the Core region to passivate the -OH active sites of the second dielectric layer and form a passivation layer 400.
[0084] The steps involved in siliconization of the Core region may include:
[0085] like Figure 9 First, step S3-1 is performed, in which a photoresist layer is formed on the surface of the first dielectric layer by photolithography. That is, a patterned photoresist layer 300 is prepared on the surface of the ISSG silicon oxide layer 201 in the I / O area by means of coating or photolithography to cover the surface of the ISSG silicon oxide layer 201 and to protect the surface of the ISSG silicon oxide layer 201 by the photoresist layer 300.
[0086] like Figure 10 Next, step S3-2 is performed for silanization. The silanizing agent may include HMDS solution, ODTS solution, or OTS solution, etc. The silanization time is preferably greater than 1 minute to ensure complete passivation of the -OH active sites on the surface of the IL silicon oxide layer 202 located in the Core region, thereby changing the hydrophilicity and chemical reactivity of the IL silicon oxide layer 202 surface. That is, after the silanization treatment, a passivation layer 400 can be considered to have been formed on the surface of the IL silicon oxide layer 202. The interface structure between the passivation layer 400 and the IL silicon oxide layer 202 can be referred to [reference needed]. Figure 11 .
[0087] like Figure 12 Next, step S3-3 is performed, in which wet etching is used to remove the photoresist layer 300 to expose the surface of the ISSG silicon oxide layer 201.
[0088] Next, refer to Figure 3 and Figure 13 Step S4 is executed to perform the first deposition of a high-k dielectric layer, forming the high-k dielectric layer with a first thickness on the surface of the first dielectric layer.
[0089] The methods for preparing the high-k dielectric layer may include plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced atomic layer deposition (PEALD), or thermal atomic layer deposition (TELD), etc.
[0090] like Figure 13 In this embodiment, the high-k dielectric layer is an HfO2 layer, but the type of high-k dielectric layer is not limited to this. It may also include TiO2 layer, HfZrO layer, HfSiNO layer, Ta2O5 layer, ZrO2 layer, ZrSiO2 layer, Al2O3 layer, SrTiO3 layer and BaSrTiO layer, or a combination of HfO2 layer, TiO2 layer, HfZrO layer, HfSiNO layer, Ta2O5 layer, ZrO2 layer, ZrSiO2 layer, Al2O3 layer, SrTiO3 layer and BaSrTiO layer.
[0091] In this embodiment, an HfO2 layer 501 with a first thickness d1 is formed on the surface of the ISSG silicon oxide layer 201 in the I / O region. This first deposition of the HfO2 layer can mitigate the thickness difference of the HfO2 layer finally prepared in the I / O region and the Core region.
[0092] Next, refer to Figure 3 , Figure 14 and Figure 15 Step S5 is executed to perform UV / O3 treatment to remove the passivation layer 400 and restore the -OH active sites of the second dielectric layer. That is, by combining ozone (O3) and ultraviolet radiation (UV) treatment, the passivation layer 400 on the surface of the IL silicon oxide layer 202 located in the Core region is removed to restore the -OH active sites on the surface of the IL silicon oxide layer 202 located in the Core region.
[0093] Both silanization and UV / O3 treatment can effectively treat the substrate, altering the hydrophilicity and chemical reactivity of the material surface without affecting its mechanical, optical, or electrical properties. The duration of the UV / O3 treatment is not limited here; the goal is to restore the -OH active sites on the surface of the IL silicon oxide layer 202. For example... Figure 14 UV / O3 treatment can be applied to the entire area. After UV / O3 treatment, the interface structure of the IL silicon oxide layer 202 can be referred to [reference needed]. Figure 15 .
[0094] Next, refer to Figure 3 and Figure 16 Step S6 is executed to perform a second deposition of the high-K dielectric layer, and to continue forming the high-K dielectric layer with a second thickness on the surface of the first dielectric layer and the high-K dielectric layer with a third thickness on the surface of the second dielectric layer.
[0095] like Figure 16 After UV / O3 treatment, an HfO2 layer 502 with a second thickness d2 is deposited on the surface of the HfO2 layer 501 with a first thickness d1 in the I / O region. At the same time, an HfO2 layer 503 with a third thickness d3 is formed on the surface of the IL silicon oxide layer 202 in the Core region.
[0096] Through process control, the sum of the first thickness d1 and the second thickness d2 can be made equal to the third thickness d3 (or the difference between the first thickness d1 and the second thickness d2 is less than a preset threshold, which is set according to process requirements, such as 5%, 10%, 20%, etc.). Of course, as needed, the sum of the first thickness d1 and the second thickness d2 can be made greater than the third thickness d3 to further improve the semiconductor structure's requirements for the thickness of material layers in different regions and improve performance.
[0097] In summary, the semiconductor structure fabrication method of the present invention selectively processes the I / O region and Core region of the semiconductor substrate, including siliconization of the Core region to passivate the -OH active sites in the Core region to form a passivation layer, and UV / O3 treatment to remove the passivation layer and restore the -OH active sites in the Core region. The density of -OH active sites on the surface of the semiconductor substrate can be changed as needed, and combined with the deposition of two high-k dielectric layers, the thickness difference of the high-k dielectric layer in different regions of the semiconductor substrate can be improved.
[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including an I / O region and a Core region; A first dielectric layer is formed in the I / O region of the semiconductor substrate, and a second dielectric layer is formed in the Core region of the semiconductor substrate; The Core region is siliconized to passivate the -OH active sites of the second dielectric layer and form a passivation layer; A first deposition of a high-k dielectric layer is performed, forming the high-k dielectric layer with a first thickness on the surface of the first dielectric layer; UV / O3 treatment is performed to remove the passivation layer and restore the -OH active sites of the second dielectric layer. A second deposition of the high-K dielectric layer is performed, and a high-K dielectric layer with a second thickness is formed on the surface of the first dielectric layer and a high-K dielectric layer with a third thickness is formed on the surface of the second dielectric layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sum of the first thickness and the second thickness is equal to the third thickness, or the difference between the first thickness and the second thickness is less than a preset threshold.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sum of the first thickness and the second thickness is greater than the third thickness.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The silanizing agents used in the silanization process include HMDS solution, ODTS solution, or OTS solution.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps for siliconizing the Core region include: A photoresist layer is formed on the surface of the first dielectric layer by photolithography; Siliconization process; The photoresist layer was removed by wet etching.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dielectric layer includes a first silicon oxide layer formed by thermal oxidation, and the second dielectric layer includes a second silicon oxide layer formed by chemical oxidation; wherein the surfaces of both the first dielectric layer and the second dielectric layer have -OH active sites, and the density of -OH active sites in the first dielectric layer is less than the density of -OH active sites in the second dielectric layer.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The steps for preparing the first silicon oxide layer and the second silicon oxide layer include: The first silicon oxide layer is formed on the surface of the semiconductor substrate using a thermal oxidation method; A photoresist layer is formed on the surface of the first dielectric layer in the I / O region by photolithography. Etching is performed to remove the first silicon oxide layer located in the Core region; Remove the photoresist layer; The second silicon oxide layer is formed on the surface of the semiconductor substrate in the Core region by chemical oxidation.
8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.
9. The method for preparing a semiconductor structure according to claim 1, characterized in that: Methods for forming the high-k dielectric layer include PECVD, LPCVD, PEALD, or Thermal ALD.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that: The high-k dielectric layer formed includes one or a combination of HfO2 layer, TiO2 layer, HfZrO layer, HfSiNO layer, Ta2O5 layer, ZrO2 layer, ZrSiO2 layer, Al2O3 layer, SrTiO3 layer and BaSrTiO layer.