Semiconductor structure and method of manufacturing the same

Abstract

This application provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes providing a substrate, on which a first dummy gate and a second dummy gate are disposed, and a dielectric layer surrounds the first and second dummy gates; removing at least a portion of the thickness of the first dummy gate; forming a protective layer covering the top surface of the first dummy gate, the second dummy gate, and the dielectric layer; removing a first portion of the second dummy gate and the protective layer to form a second gate trench; wherein the first portion at least covers the second dummy gate; forming a second gate filling the second gate trench; removing a second portion of the first dummy gate and the protective layer to form a first gate trench; wherein the second portion at least covers the first dummy gate; and forming a first gate filling the first gate trench. This application can avoid over-etching the first dummy gate, improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In semiconductor manufacturing processes, especially in the manufacturing of advanced CMOS (Complementary Metal-Oxide-Semiconductor) devices, the introduction of metal gates is crucial for improving device performance and reducing power consumption.

[0003] In related technologies, PMOS and NMOS regions typically require the formation of metal gates in separate steps. During fabrication, one or more metal films are usually deposited in the PMOS region, followed by a CMP (Chemical Metal Processing) step to remove excess metal and planarize the surface. However, due to the process characteristics of CMP, it is often difficult to precisely control the removal of the metal film from the PMOS region without affecting the silicon gate in the NMOS region. This can lead to damage to the gate dielectric layer beneath the NMOS gate when the silicon gate is completely removed, thus reducing the yield of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, the embodiments of this application provide the following technical solutions:

[0005] The first aspect of this application provides a method for fabricating a semiconductor structure, including:

[0006] A substrate is provided, on which a first dummy gate and a second dummy gate are disposed, and a dielectric layer surrounds the first dummy gate and the second dummy gate;

[0007] At least a portion of the thickness of the first dummy gate is removed;

[0008] A protective layer is formed, which covers the first dummy gate, the second dummy gate, and the top surface of the dielectric layer;

[0009] The second dummy gate and a first portion of the protective layer are removed to form a second gate trench; wherein the first portion at least covers the second dummy gate;

[0010] A second gate is formed, and the second gate fills the second gate trench;

[0011] The first dummy gate and a second portion of the protective layer are removed to form a first gate trench; wherein the second portion at least covers the first dummy gate;

[0012] A first gate is formed, and the first gate fills the first gate trench.

[0013] In one possible implementation, the thickness of the protective layer is 25 Å to 80 Å; the material of the protective layer includes at least one of silicon dioxide, silicon carbide, silicon carbonitride, silicon borosilicate glass, and phosphate glass.

[0014] In one possible implementation, the step of removing at least a portion of the thickness of the first dummy gate further includes:

[0015] The thickness of the first dummy gate is 20A to 60A.

[0016] In one possible implementation, the protective layer comprises at least two stacked sub-protective layers.

[0017] In one possible implementation, the step of forming the second gate further includes:

[0018] A second gate material layer is formed, which fills the second gate trench and covers the protective layer;

[0019] A chemical mechanical polishing process is performed to remove the second gate material layer located on the protective layer, and the second gate material layer remaining in the second gate trench constitutes the second gate.

[0020] In one possible implementation, the substrate includes a first region and a second region that are adjacent to each other and insulated from each other, the first region and the second region having different electrical conductivity types;

[0021] The first dummy gate is disposed on the first region, and the second dummy gate is disposed on the second region.

[0022] In one possible implementation, the preparation method further includes:

[0023] A resistor structure is formed, which is disposed in the first region and located on the side of the first gate opposite to the second gate.

[0024] A second aspect of this application provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in the first aspect.

[0025] The semiconductor structure includes:

[0026] Base;

[0027] A first gate structure and a second gate structure are disposed on the substrate at a distance from each other; wherein the first gate structure includes a first gate and the second gate structure includes a second gate.

[0028] A dielectric layer is disposed on the substrate and surrounds the first gate structure and the second gate structure, respectively.

[0029] In one possible implementation, the semiconductor structure further includes a resistor structure disposed on the substrate and located on the side of the first gate structure opposite to the second gate structure.

[0030] The resistor structure includes a functional layer and a protective layer stacked together.

[0031] In one possible implementation, the first gate structure includes at least two, on a cross section perpendicular to the substrate, and in a direction perpendicular to the second gate structure, wherein the size of one of the first gate structures is larger than the size of the other first gate structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the formation of a gate material layer in a semiconductor structure fabrication method provided for related technologies;

[0034] Figure 2 A schematic diagram of forming the gate of a PMOS transistor in a method for fabricating a semiconductor structure provided for related technologies;

[0035] Figure 3 A schematic diagram illustrating the removal of dummy gates in a semiconductor structure fabrication method provided for related technologies;

[0036] Figure 4 A process flow diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0037] Figure 5 A schematic diagram illustrating the formation of a dummy gate in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0038] Figure 6 A schematic diagram illustrating the formation of a dummy gate with a portion of its thickness removed in the fabrication method of the semiconductor structure provided in this application embodiment;

[0039] Figure 7 This is a schematic diagram illustrating the formation of a protective layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0040] Figure 8 This is a schematic diagram of the formation of the first mask layer in the method for fabricating a semiconductor structure provided in the embodiments of this application;

[0041] Figure 9 A schematic diagram illustrating the removal of the second dummy gate in the method for fabricating the semiconductor structure provided in this application embodiment;

[0042] Figure 10 This is a schematic diagram of the formation of the second gate material layer in the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0043] Figure 11 A schematic diagram illustrating the formation of a second gate in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0044] Figure 12 A schematic diagram illustrating the removal of the first dummy gate in the method for fabricating the semiconductor structure provided in this application embodiment;

[0045] Figure 13 This is a schematic diagram illustrating the removal of the second mask layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0046] Figure 14 This is a schematic diagram of the formation of the first gate in the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0047] Figure label:

[0048] 1: Dummy gate structure; 2: Gate material layer; 3: Groove; 4: Gate;

[0049] 100: Substrate; 110: First region; 120: Second region; 130: Shallow trench isolation structure;

[0050] 200: First gate structure; 210: First gate; 220: First gate dielectric layer; 230: First barrier layer; 240: First dummy gate; 250: First gate trench;

[0051] 300: Second gate structure; 310: Second gate; 320: Second gate dielectric layer; 330: Second barrier layer; 340: Second dummy gate; 350: Second gate trench; 360: Second gate material layer;

[0052] 400: Dielectric layer; 410: First dielectric layer; 420: Second dielectric layer;

[0053] 500: Protective layer;

[0054] 600: First mask layer; 610: First mask opening;

[0055] 700: Second mask layer; 710: Second mask opening;

[0056] 800: Resistor structure; 810: Oxide layer; 820: Third dielectric layer; 830: Resistor layer; 840: Polysilicon layer; 850: Fourth dielectric layer. Detailed Implementation

[0057] As described in the background section, semiconductor structures in related technologies have low yields. Please refer to... Figure 1 In the process of fabricating transistors, a dummy gate structure is usually formed on the substrate in advance; then, using the dummy gate structure as a mask, an ion implantation process is performed on the substrate to form source and drain electrodes on the left and right sides of the dummy gate structure, respectively; then, the dummy gate of the dummy gate structure is removed, and the real gate is redeposited.

[0058] However, please refer to Figures 1 to 3 Current transistors typically include NMOS and PMOS transistors. In current manufacturing processes, the dummy gate of the PMOS transistor is usually removed first. Then, a new gate material layer is deposited on top of the NMOS transistor. This gate material layer also covers the top surface of the NMOS transistor. Next, a chemical mechanical polishing (CMP) process is used to remove the gate material layer on the top surface of the NMOS transistor to form the true gate 4 of the PMOS transistor. However, during the removal process, the dummy gate of the NMOS transistor is polished to form a groove 3. This can lead to over-etching during subsequent removal of the dummy gate, resulting in a missing barrier layer in the NMOS transistor and thus reducing the yield of the semiconductor structure.

[0059] To address the aforementioned technical problems, this application provides a semiconductor structure and its fabrication method. By first forming a protective layer covering the first dummy gate, the top surface of the first dummy gate is prevented from being exposed. Thus, when forming the second gate, the protective layer protects the first dummy gate, preventing it from being masked. Consequently, over-etching is prevented during the subsequent formation of the first gate trench, thereby improving the yield of the semiconductor structure.

[0060] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the figures. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0061] Please refer to Figure 4 This application provides a method for preparing a semiconductor structure, including the following steps S100-S700.

[0062] In step S100, refer to Figure 5 A substrate is provided, on which a first dummy gate 240 and a second dummy gate 340 are disposed, and a dielectric layer surrounds the first dummy gate 240 and the second dummy gate 340.

[0063] exist Figure 5 In this embodiment, the substrate 100 serves as a carrier component for the semiconductor structure, supporting the semiconductor structure disposed thereon. The substrate 100 can be made of semiconductor materials such as silicon, germanium, silicon germanide, arsenic germanide, silicon on insulator (SOI), or germanium on insulator (GOI), or other materials, which are not limited in this application embodiment.

[0064] The substrate 100 includes a first region 110 and a second region 120 that are adjacent and insulated from each other, and the first region 110 and the second region 120 have different conductivity types. In one example, the first region 110 is N-type and the second region 120 is P-type. In other words, the first region 110 is an N-type well region to facilitate the formation of an NMOS transistor on the N-type well region. For example, a portion of the N-type well region can be doped to form a P-type channel. The second region 120 is a P-type well region, where PMOS transistors are typically formed in P-type well regions. For example, a portion of the P-type well region can be doped to form an N-type channel.

[0065] To achieve insulation between the first region 110 and the second region 120, a shallow trench isolation structure 130 is provided between adjacent first regions 110 and second regions 120. Exemplarily, shallow trenches are formed in the substrate 100 using a patterned fabrication process, and the shallow trench isolation structure 130 is formed within the shallow trenches, thereby defining multiple first regions 110 and multiple second regions 120 separated by the shallow trench isolation structure 130 on the substrate 100.

[0066] In some embodiments, the shallow trench isolation structure 130 may be made of a single insulating material, and the shallow trench isolation structure 130 may also be supported by multiple insulating materials, so that the shallow trench isolation structure 130 is a layered structure. Exemplarily, the shallow trench isolation structure 130 includes a first isolation layer, a second isolation layer, and a third isolation layer stacked together, wherein the first isolation layer is disposed on the inner wall of the shallow trench, the second isolation layer is disposed on the first isolation layer, and the third isolation layer is disposed on the second isolation layer and fills the area enclosed by the second isolation layer. The materials of the first isolation layer and the third isolation layer may be the same or different. For example, the materials of the first isolation layer and the third isolation layer may both include silicon oxide, and the material of the second isolation layer may include silicon nitride, so that the shallow trench isolation structure 130 is an "ONO" structure. This configuration can improve the isolation effect of the shallow trench isolation structure 130, making each area independent of the others.

[0067] Patterning processes include, but are not limited to, self-aligned multiple (e.g., two or four) patterning processes.

[0068] Next, a first dummy gate 240 and a second dummy gate 340 are formed on the substrate 100 at intervals, wherein the first dummy gate 240 is disposed on the first region 110 and the second dummy gate 340 is disposed on the second region 120. It should be noted that the first dummy gate 240 can be understood as something that needs to be removed in subsequent processes and replaced by the actual gate. The main function of the dummy gate is to provide a temporary mask in the early stages of the process to help define the source and drain regions of the transistor and the subsequent gate location.

[0069] In other embodiments, this step further includes forming structures such as a gate dielectric layer and sidewalls of the gate structure. For example, please refer to [reference needed]. Figure 5 After forming the first region 110 and the second region 120, a gate dielectric material layer, a barrier material layer and a dummy gate material layer are sequentially stacked on the substrate 100 by a deposition process. Then, the above film layers are patterned to form a first gate structure 200 and a second gate structure 300. The first gate structure 200 includes a first gate dielectric layer 220, a first barrier layer 230 and a first dummy gate 240 stacked on top of each other. The second gate structure 300 includes a second gate dielectric layer 320, a second barrier layer 330 and a second dummy gate 340 stacked on top of each other.

[0070] Next, the deposition process continues to form a dielectric layer 400 surrounding the first dummy gate 240 and the second dummy gate 340. It should be understood that when the first dummy gate 240 and the substrate 100 are also separated by the first gate dielectric layer 220 and the first barrier layer 230, the dielectric layer 400 also covers the first gate dielectric layer 220 and the first barrier layer 230; at the same time, the dielectric layer 400 also covers the second gate dielectric layer 320 and the second barrier layer 330.

[0071] In some embodiments, the dielectric layer 400 may include a single film layer, or other alternatives may be used. Exemplarily, the dielectric layer 400 includes a first dielectric layer 410 and a second dielectric layer 420. The first dielectric layer 410 covers the sidewalls of the first gate structure 200 and the second gate structure 300, respectively, and the second dielectric layer 420 is disposed on the substrate 100 and fills the area enclosed by the first dielectric layer 410.

[0072] In step S200, a portion of the thickness of the first dummy gate 240 is removed.

[0073] Please refer to Figure 6 By performing an etching process, a portion of the thickness of the first dummy gate 240 can be removed.

[0074] For example, a portion of the thickness of the first dummy gate 240 and the portion of the thickness of the second dummy gate 340 can also be removed. Exemplarily, a dry etching process or a wet etching process is performed to simultaneously remove a portion of the thickness of the first dummy gate 240 and the portion of the thickness of the second dummy gate 340, thus eliminating the need to prepare a first mask layer and simplifying the semiconductor structure fabrication process.

[0075] In some embodiments, the thickness of the first dummy gate 240 removed is 20 Å to 60 Å. For example, the thickness of the first dummy gate 240 removed is 20 Å, 25 Å, 30 Å, 35 Å, 40 Å, 45 Å, 50 Å, 55 Å, 60 Å, and any two of the above values.

[0076] By appropriately setting the thickness of the first dummy gate 240 to be removed, it is necessary to avoid the first dummy gate 240 being too thin, thus preventing the subsequent protective layer 500 from being too thin and ensuring the protective function of the protective layer 500, thereby preventing the first dummy gate 240 from being over-etched. Conversely, it is also necessary to avoid the first dummy gate 240 being too thick, thus preventing the subsequent protective layer 500 from being too thick. This reduces the difficulty of removing the protective layer 500 and lowers the production cost of the semiconductor structure.

[0077] In step S300, a protective layer is formed, which covers the top surface of the first dummy gate 240, the second dummy gate 340, and the dielectric layer 400.

[0078] Please refer to Figure 7 A deposition process is performed to deposit a protective layer 500 on the top surface of the first dummy gate 240, the second dummy gate 340, and the dielectric layer 400. The deposition process includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0079] The protective layer 500 can be a single film layer or have other structures. For example, the protective layer 500 includes at least two stacked sub-protective layers. This allows for the appropriate selection of the material for each sub-protective layer, providing additional protection or barrier effects for specific process steps.

[0080] In this embodiment, the thickness of the protective layer 500 is 25 Å to 80 Å. It should be noted that when the protective layer 500 includes at least two sub-protective layers, the total thickness of the at least two sub-protective layers is 25 Å to 80 Å.

[0081] Provided that the total thickness of at least two sub-protective layers is between 25A and 80A, the thickness of the at least two sub-protective layers can be the same or different, and can be freely set according to the specific process requirements.

[0082] The protective layer 500 is made of at least one of silicon dioxide (SiO2), silicon carbide (SiC), silicon oxycarbonate (SiOCN), silicon boronitride (SiBCN), borosilicate glass (BSG), and phosphate glass (PSG).

[0083] In step S400, the second dummy gate 340 and the first portion of the protective layer 500 are removed to form the second gate trench 350; wherein the first portion at least covers the second dummy gate.

[0084] For example, please refer to Figure 8A first mask layer 600 is formed, wherein the first mask layer 600 has a first mask opening 610, the first mask opening 610 exposing at least the second dummy gate 340 and a first portion of the guard layer 500. In one example, the first mask opening 610 exposes only the second dummy gate 340. In another example, the first mask opening 610 exposes the second dummy gate 340 and a portion surrounding the second dummy gate 340. In this case, the first portion of the guard layer 500 refers to the portion covering the second dummy gate 340 and the portion surrounding the second dummy gate 340. This allows for better removal of the second dummy gate 340, prevents the second dummy gate 340 from remaining, and improves the performance of the PMOS transistor.

[0085] Next, please refer to Figure 9 An etching process is performed to remove the protective layer 500 and the second dummy gate 340 exposed in the first mask opening 610 to form the second gate trench 350.

[0086] Next, please refer to Figure 10 A cleaning process is used to remove the first mask layer 600 to expose the top surface of the remaining protective layer 500.

[0087] In step S500, a second gate 310 is formed, and the second gate fills the second gate trench 350.

[0088] Please refer to Figure 10 A deposition process is performed to form a second gate material layer 360, which fills the second gate trench 350 and covers the protective layer 500. It should be noted that in this example, the protective layer 500 refers to the remaining protective layer 500.

[0089] Next, please refer to Figure 11 A chemical mechanical polishing process is performed to remove the second gate material layer 360 located on the protective layer 500, and the second gate material layer 360 remaining in the second gate trench 350 constitutes the second gate 310.

[0090] At this time, the top surface of the second gate 310 is flush with the top surface of the remaining protective layer 500 and with the top surface of the dielectric layer 400.

[0091] During the polishing process, given that the top surface of the first dummy gate 240 is covered with a protective layer 500, and that the protective layer 500 is made of a different material than the first dummy gate 240, and that the hardness of the protective layer 500 is greater than that of the first dummy gate 240, the composition of the polishing slurry can be adjusted reasonably according to the materials of the protective layer 500 and the first dummy gate 240. This allows the polishing slurry to act more effectively on the surface of the protective layer 500. Furthermore, after completing the polishing process of the second gate material layer 360, a portion of the protective layer 500 is retained. This prevents the polishing slurry from directly polishing the first dummy gate 240, thus preventing damage to the first dummy gate 240.

[0092] In step S600, the first dummy gate 240 and the second portion of the protective layer 500 are removed to form the first gate trench 250; wherein the second portion at least covers the first dummy gate 240.

[0093] Please refer to Figure 12 A second mask layer 700 is formed, wherein the second mask layer 700 has a second mask opening 710, the second mask opening 710 exposing at least the first dummy gate 240. In one example, the second mask opening 710 exposes only the first dummy gate 240. In another example, the second mask opening 710 exposes both the first dummy gate 240 and a portion surrounding the first dummy gate 240. In this case, the second portion of the protective layer 500 refers to the portion covering the first dummy gate 240 and the portion surrounding the first dummy gate 240. This allows for better removal of the first dummy gate 240.

[0094] Next, an etching process is performed to remove the protective layer 500 and the first dummy gate 240 exposed in the second mask opening 710 to form the first gate trench 250.

[0095] Next, please refer to Figure 13 A cleaning process is used to remove the second mask layer 700 to expose the top surface of the remaining protective layer 500.

[0096] In step S700, a first gate 210 is formed, and the first gate 210 fills the first gate trench 250.

[0097] Please refer to Figure 14 A deposition process is performed to form a first gate 210 within the first gate trench 250. It should be noted that the fabrication process of the first gate 210 is the same as that of the second gate 310, and will not be described further in this embodiment.

[0098] In this embodiment, given the protective layer 500, when removing the first dummy gate 240, it effectively prevents the direct erosion or mechanical damage to the gate dielectric layer and barrier layer by polishing fluid, etchant or other chemicals during the removal of the first dummy gate 240, thereby ensuring the integrity and performance of these critical layers; thus, the subsequently formed first gate 210 can be built on a more stable and reliable foundation, which helps to improve the electrical contact performance between the first gate 210 and the channel, reduce leakage current, and improve the switching speed and overall performance of the semiconductor structure.

[0099] In one possible implementation, the method for fabricating the semiconductor structure further includes:

[0100] Please refer to Figure 13 and Figure 14 A resistor structure 800 is formed, which is disposed in the first region and located on the side of the first gate away from the second gate.

[0101] Among them, the resistor structure 800 is used in high-resistance devices. The introduction of the resistor structure 800 can precisely adjust the electrical parameters of the semiconductor structure, such as capacitance and inductance, thereby optimizing the key performance of the semiconductor structure, such as frequency response, noise suppression and signal integrity.

[0102] The resistor structure 800 includes a stacked oxide layer 810, a third dielectric layer 820, a resistive layer 830, a polysilicon layer 840, and a fourth dielectric layer 850. The oxide layer 810 is made of, but is not limited to, silicon oxide. The third dielectric layer 820 may have a high dielectric constant, and its material may be the same as that of the first gate dielectric layer 220 and the second gate dielectric layer 320. The resistive layer 830 is made of, but is not limited to, titanium nitride. The fourth dielectric layer 850 is made of at least one of silicon dioxide (SiO2), silicon carbide (SiC), silicon carbonitride oxynitride (SiOCN), silicon borosilicate glass (SiBCN), borosilicate glass (BSG), and phosphate glass (PSG).

[0103] It should be noted that the resistor structure 800 can be formed simultaneously during the formation of the first gate structure 200 and the second gate structure 300. At this time, the fourth dielectric layer 850 is formed by the protective layer retained after step S600. This simplifies the fabrication process of the resistor structure 800 and reduces the production cost of the semiconductor structure.

[0104] This application also provides a semiconductor structure, which is prepared by the preparation method described in any of the above embodiments.

[0105] Please refer to Figure 14 The semiconductor structure includes: a substrate 100;

[0106] A first gate structure 200 and a second gate structure 300 are disposed on a substrate 100 at a distance from each other; wherein the first gate structure 200 includes a first gate 210 and the second gate structure 300 includes a second gate 310.

[0107] The first gate structure 200 provided in this application embodiment further includes a first gate dielectric layer 220 and a first barrier layer 230. The first gate dielectric layer 220 is disposed on the substrate 100, the first barrier layer 230 is disposed on the first gate dielectric layer 220, and the first gate 210 is disposed on the first barrier layer 230.

[0108] Meanwhile, the second gate structure 300 also includes a second gate dielectric layer 320 and a second barrier layer 330. The second gate dielectric layer 320 is disposed on the substrate 100, the second barrier layer 330 is disposed on the second gate dielectric layer 320, and the second gate 310 is disposed on the second barrier layer 330.

[0109] The first gate dielectric layer 220 and the second gate dielectric layer 320 are made of the same material. Exemplarily, both the first gate dielectric layer 220 and the second gate dielectric layer 320 include an oxide layer and a high-k dielectric layer. The oxide layer is made of silicon oxide, and the high-k dielectric layer is made of hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0110] The high-k dielectric layer can effectively prevent electrons from directly tunneling through the gate dielectric layer and generating gate leakage current. It is beneficial to reduce the thickness of the gate dielectric layer, meet the requirements of process size reduction, and provide a guarantee for the development of semiconductor structure towards integration.

[0111] Furthermore, the first barrier layer 230 is made of the same material as the second barrier layer 330. For example, the first barrier layer 230 is made of titanium nitride.

[0112] A dielectric layer 400 is disposed on a substrate 100 and surrounds the first gate structure 200 and the second gate structure 300, respectively.

[0113] The semiconductor structure provided in this application embodiment can ensure the integrity of the gate dielectric layer, thereby enabling the subsequent formation of the first gate 210 to be based on a more stable and reliable foundation. This helps to improve the electrical contact performance between the first gate 210 and the channel, reduce leakage current, and improve the switching speed and overall performance of the semiconductor structure.

[0114] In one possible implementation, the semiconductor structure further includes a resistor structure 800 disposed on the substrate 100 and located on the side of the first gate structure 200 opposite to the second gate structure 300. The resistor structure 800 includes a stacked oxide layer 810, a third dielectric layer 820, a resistive layer 830, a polysilicon layer 840, and a fourth dielectric layer 850. The oxide layer 810 is made of, but is not limited to, silicon oxide. The third dielectric layer 820 may have a high dielectric constant, and its material may be the same as that of the first gate dielectric layer 220 and the second gate dielectric layer 320. The resistive layer 830 is made of, but is not limited to, titanium nitride. The fourth dielectric layer 850 is made of at least one of silicon dioxide (SiO2), silicon carbide (SiC), silicon carbonitride oxynitride (SiOCN), silicon borosilicate glass (SiBCN), borosilicate glass (BSG), and phosphate glass (PSG).

[0115] In this embodiment, the resistor structure 800 has a high resistivity, which can improve the performance of the semiconductor structure.

[0116] It should be noted that the first gate structure 200 includes at least two, wherein the dimensions of the at least two first gate structures 200 may be the same or different.

[0117] For example, in a cross section perpendicular to the substrate 100, and in a direction perpendicular to the first gate structure 200 pointing to the second gate structure 300, the size of one of the first gate structures 200 is larger than the size of the other first gate structure 200.

[0118] Different sizes of first gate structures 200 can support different circuit functions and performance requirements. For example, a larger gate structure may be used in circuit sections that require higher drive current, while a smaller gate structure may be used in applications that require lower power consumption or higher switching speed.

[0119] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0120] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application.

[0121] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a first dummy gate and a second dummy gate are disposed, and a dielectric layer surrounds the first dummy gate and the second dummy gate; Remove a portion of the thickness of the first dummy gate; A protective layer is formed, which covers the first dummy gate, the second dummy gate, and the top surface of the dielectric layer; The second dummy gate and a first portion of the protective layer are removed to form a second gate trench; wherein the first portion at least covers the second dummy gate; A second gate is formed, and the second gate fills the second gate trench; The first dummy gate and a second portion of the protective layer are removed to form a first gate trench; wherein the second portion at least covers the first dummy gate; A first gate is formed, and the first gate fills the first gate trench.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the protective layer is 25A to 80A; the material of the protective layer includes at least one of silicon dioxide, silicon carbide, silicon carbonitride, silicon carboronitride, borosilicate glass, and phosphate glass.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of removing at least a portion of the thickness of the first dummy gate further includes: The thickness of the first dummy gate is 20A to 60A.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The protective layer comprises at least two stacked sub-protective layers.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The step of forming the second gate further includes: A second gate material layer is formed, which fills the second gate trench and covers the protective layer; A chemical mechanical polishing process is performed to remove the second gate material layer located on the protective layer, and the second gate material layer remaining in the second gate trench constitutes the second gate.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The substrate includes a first region and a second region that are adjacent to each other and insulated from each other, and the first region and the second region have different conductivity types. The first dummy gate is disposed on the first region, and the second dummy gate is disposed on the second region.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The preparation method further includes: A resistor structure is formed, which is disposed in the first region and located on the side of the first gate opposite to the second gate.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1-7; The semiconductor structure includes: Base; A first gate structure and a second gate structure are disposed on the substrate at a distance from each other; wherein the first gate structure includes a first gate and the second gate structure includes a second gate. A dielectric layer is disposed on the substrate and surrounds the first gate structure and the second gate structure, respectively.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes a resistor structure disposed on the substrate and located on the side of the first gate structure opposite to the second gate structure. The resistor structure includes a functional layer and a protective layer stacked together.

10. The semiconductor structure according to claim 9, characterized in that, The first gate structure includes at least two, on a cross section perpendicular to the substrate, and in a direction perpendicular to the second gate structure, wherein the size of one of the first gate structures is larger than the size of the other first gate structure.

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