Chip, preparation method thereof, and electronic device

Abstract

The application provides a chip and a preparation method thereof and an electronic device, relates to the field of semiconductors, and can simplify the preparation process of a P-channel field effect transistor. The chip comprises a substrate, a buffer layer, an N-channel field effect transistor and a P-channel field effect transistor. The buffer layer is arranged on the substrate, the forbidden band width of the buffer layer is greater than the forbidden band width of gallium nitride, and the buffer layer comprises a piezoelectric material. The N-channel field effect transistor and the P-channel field effect transistor are arranged on the buffer layer in a spaced manner; in the direction of the substrate pointing to the buffer layer, the N-channel field effect transistor comprises a p-GaN layer, an i-GaN channel layer, a barrier layer, a gate cap layer and a first gate electrode which are arranged on the buffer layer in a stacked manner. The P-channel field effect transistor comprises a p-GaN channel layer, a gate dielectric and a second gate electrode which are arranged in a stacked manner. The N-channel field effect transistor further comprises a first electrode and a second electrode which are arranged on the barrier layer. The P-channel field effect transistor further comprises a third electrode and a fourth electrode which are arranged on the p-GaN channel layer. The material of the p-GaN layer is the same as that of the p-GaN channel layer.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a chip, its fabrication method, and an electronic device. Background Technology

[0002] Gallium nitride (GaN), a typical representative of third-generation semiconductors, possesses advantages such as high electron mobility, good thermal stability, and high breakdown electric field, making it highly suitable for core electronic devices in high-voltage, high-power, and high-frequency applications. Compared to power electronic systems composed of discrete GaN devices, power electronic systems composed of monolithic GaN integrated devices offer performance and cost advantages. Furthermore, monolithic GaN integrated devices can suppress parasitic capacitance and conductance issues, which helps improve the efficiency and reliability of power electronic systems.

[0003] like Figure 1a As shown, GaN monolithic integrated devices can include N-channel field-effect transistors and P-channel field-effect transistors. Both P-channel and N-channel field-effect transistors include an n-GaN layer and an aluminum gallium nitride (AlGaN) layer disposed on the n-GaN layer. The fabrication process of P-channel field-effect transistors is more complex. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip and its fabrication method, as well as an electronic device, which can simplify the fabrication process of P-channel field-effect transistors.

[0005] In a first aspect, this application provides a chip comprising a substrate, a buffer layer, an N-channel field-effect transistor (FET), and a P-channel FET. The buffer layer is disposed on the substrate, the buffer layer material having a bandgap greater than that of gallium nitride (GaN), and the buffer layer material comprising a piezoelectric material. The N-channel FET and the P-channel FET are spaced apart on the side of the buffer layer facing away from the substrate. Along the direction from the substrate to the buffer layer, the N-channel FET includes a p-GaN layer, an i-GaN channel layer, a barrier layer, a gate cap layer, and a first gate, stacked on the buffer layer. The P-channel FET includes a p-GaN channel layer, a gate dielectric, and a second gate, stacked on top of each other. The N-channel FET further includes a first electrode and a second electrode disposed on the barrier layer, the first electrode and the second electrode being disposed on opposite sides of the gate cap layer. The P-channel FET further includes a third electrode and a fourth electrode disposed on the p-GaN channel layer, the third electrode and the fourth electrode being disposed on opposite sides of the second gate. The material of the p-GaN layer is the same as the material of the p-GaN channel layer.

[0006] In this application, the p-GaN channel layer of the P-channel field-effect transistor can be directly disposed on the buffer layer, eliminating the need for the n-GaN and AlGaN layers located on the Si substrate in related technologies. This simplifies the fabrication process of the P-channel field-effect transistor, shortens its growth time, and thus reduces its fabrication cost. Although the presence of the p-GaN channel layer in the P-channel field-effect transistor necessitates the inclusion of a p-GaN layer in the N-channel field-effect transistor, both the p-GaN layer and the p-GaN channel layer can be fabricated using the same semiconductor process. Therefore, the p-GaN layer in this application does not complicate the fabrication process of the N-channel field-effect transistor.

[0007] Furthermore, related technologies typically use gallium nitride (GaN) as the buffer layer material. Undoped GaN is an N-type semiconductor; therefore, when GaN is used as the buffer layer, the buffer layer limits the hole mobility of the P-channel MOSFET. Moreover, both heavy and light holes in GaN have high effective mass, and the heavier the hole, the slower its movement, which also leads to a decrease in the hole mobility of the P-channel MOSFET. The hole mobility of a P-channel MOSFET using GaN as the buffer layer material is 10–15 cm⁻¹. 2 / (V·s) hindered the development of P-channel field-effect transistors.

[0008] In this application, the bandgap of the buffer layer material is larger than that of gallium nitride, which is more convergent for two-dimensional electron gas and has no negative impact on two-dimensional hole gas. Therefore, compared with the prior art using gallium nitride as the buffer layer material, the solution of this application can not only further improve the two-dimensional electron gas concentration and electron mobility of N-channel field-effect transistors, but also improve the two-dimensional hole gas and hole mobility of P-channel field-effect transistors.

[0009] In some possible implementations, a first groove is formed on the surface of the buffer layer facing away from the substrate, and the orthographic projection of the first groove onto the substrate lies between the orthographic projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate. Alternatively, the buffer layer has a first opening, and the orthographic projection of the first opening onto the substrate lies between the orthographic projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate.

[0010] After forming a first semiconductor layer on the buffer layer, the first semiconductor layer is etched to obtain a p-GaN layer and a p-GaN channel layer. However, if etching residue remains after etching the first semiconductor layer, leakage current will occur in the p-GaN layer and p-GaN channel layer due to the residual portion. Therefore, the first semiconductor layer can be over-etched to obtain an electrically isolated p-GaN layer and p-GaN channel layer. In the case of over-etching the first semiconductor layer, the buffer layer is also at least partially etched, thereby forming a first groove or a first opening on the surface of the buffer layer facing away from the substrate.

[0011] In some possible implementations, the chip includes multiple transistor groups, each including an N-channel field-effect transistor and a P-channel field-effect transistor. A second groove is formed on the surface of the buffer layer facing away from the substrate, and the orthographic projection of the second groove on the substrate is located between the orthographic projections of adjacent transistor groups on the substrate; or, the buffer layer has a second opening, and the orthographic projection of the second opening on the substrate is located between the orthographic projections of adjacent transistor groups on the substrate.

[0012] The chip includes multiple transistor groups, each including N-channel field-effect transistors and P-channel field-effect transistors. In this case, the portion of the first semiconductor layer located between adjacent transistor groups can also be etched. If etching residue remains after etching the first semiconductor layer, leakage will occur in the p-GaN layer and p-GaN channel layer of one transistor group, and in the p-GaN layer and p-GaN channel layer of the adjacent transistor group. Based on this, the first semiconductor layer can be over-etched to obtain multiple electrically isolated transistor groups. When the first semiconductor layer is over-etched, the buffer layer is also at least partially etched, thereby forming a second groove or a second opening on the surface of the buffer layer facing away from the substrate.

[0013] In some possible implementations, a third groove is formed on the surface of the p-GaN channel layer facing away from the substrate, and at least a portion of the second gate and the gate dielectric are disposed in the third groove. Since the gate dielectric is disposed on the side of the p-GaN channel layer facing away from the substrate, and the gate dielectric is conformally grown with the p-GaN channel layer, the gate dielectric also has a groove at the location of the third groove, and at least a portion of the second gate and the gate dielectric are disposed in the third groove. This reduces the spacing between the second gate and the two-dimensional hole gas (located at the interface between the p-GaN channel layer and the buffer layer), thereby improving the gate control capability of the second gate.

[0014] In some possible implementations, the buffer layer material includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x The values ​​of N and x range from [0.5, 1]. This is because aluminum nitride or aluminum gallium nitride (Al) x Ga1-x The large bandgap of nitrogen (AlN) results in a high breakdown field strength for the buffer layer; furthermore, aluminum nitride (AlN) exhibits excellent thermal conductivity, making it a suitable material for applications such as aluminum gallium nitride (AlN) or aluminum gallium nitride (AlN). x Ga 1-x As a buffer layer material, nitrogen can also improve the chip's breakdown resistance and heat dissipation performance.

[0015] In some possible implementations, the material of the buffer layer includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x When using materials with large band gaps, such as N-channel MOSFETs, and substrates including silicon (Si), a thick buffer layer in the first direction can easily lead to multiple cracks forming within the buffer layer during deposition, making it impossible to fabricate properly functioning N-channel and P-channel MOSFETs. Therefore, the buffer layer is typically thin. However, even with a thin buffer layer, process defects can still easily cause leakage between N-channel and P-channel MOSFETs through the buffer layer.

[0016] Based on this, the embodiments of this application reduce the full width at half maximum (FWHM) of the diffraction peaks of the AlN buffer layer by changing the substrate material and the process parameters for preparing the AlN buffer layer. A narrower FWHM (less than or equal to 1000 arcseconds) results in better film quality for the AlN buffer layer. This allows for the formation of a thicker AlN buffer layer on the substrate while mitigating the problem of cracks within the AlN buffer layer. Furthermore, since aluminum nitride is an insulating material, leakage between the N-channel and P-channel field-effect transistors through the buffer layer is avoided. Moreover, because the solution obtained in this application improves the leakage problem of the buffer layer, deep etching isolation between the N-channel and P-channel field-effect transistors is unnecessary, thereby reducing chip power consumption and improving operating efficiency.

[0017] Optionally, since the stress on the aluminum nitride buffer layer is relatively small due to the silicon carbide (SiC) substrate, the substrate material can include silicon carbide (AlN), and the buffer layer material can include aluminum nitride (AlN). By optimizing the process parameters, the film quality of the aluminum nitride buffer layer formed on the silicon carbide substrate can be improved while increasing the thickness of the aluminum nitride buffer layer (e.g., 200 nm to 800 nm).

[0018] Furthermore, in related technologies employing gallium nitride (GaN) buffer layers, the thickness of the GaN buffer layer in the first direction exceeds 1 μm. In this application, however, the lattice mismatch between the silicon carbide substrate and the aluminum nitride buffer layer is smaller, resulting in lower stress on the aluminum nitride buffer layer. Consequently, the thickness of the buffer layer in the first direction in this embodiment is smaller (e.g., 200 nm to 800 nm), thereby reducing parasitic inductance in the chip.

[0019] In some possible implementations, the gate dielectric extends from the side of the first electrode, barrier layer, p-GaN layer, first gate, second electrode, third electrode, and fourth electrode away from the substrate to between the p-GaN channel layer and the second gate. This allows the gate dielectric to be reused as an interlayer dielectric, eliminating the need for interlayer dielectrics disposed on the substrate-away side of N-channel and P-channel field-effect transistors.

[0020] In some possible implementations, where an inverter is implemented using an N-channel MOSFET and a P-channel MOSFET interconnected, the gate dielectric includes a first trench, a second trench, a third trench, a fourth trench, and a fifth trench. The chip also includes a first wiring layer disposed on the side of the gate dielectric and the second gate facing away from the substrate. The first wiring layer includes an input terminal, an output terminal, a ground terminal, and a voltage terminal. The input terminal is electrically connected to the first gate through the first trench and is also electrically connected to the second gate. The output terminal is electrically connected to the second gate through the second trench and is also electrically connected to the fourth gate through the third trench. The ground terminal is electrically connected to the first gate through the fourth trench. The voltage terminal is electrically connected to the third gate through the fifth trench. The chip also includes a dielectric layer and a second wiring layer disposed on the side of the first wiring layer facing away from the substrate. The dielectric layer includes a sixth via, a seventh via, an eighth via, and a ninth via. The second wiring layer includes a first conductive structure and a second conductive structure. The first conductive structure is electrically connected to the input terminal through the sixth and seventh vias, and the second conductive structure is electrically connected to the output terminal through the eighth and ninth vias.

[0021] Secondly, this application provides an electronic device, which includes a circuit board and the chip described in the first aspect, the chip being disposed on the circuit board.

[0022] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0023] Thirdly, this application provides a method for fabricating a chip, comprising: forming a buffer layer on a substrate, wherein the bandgap of the buffer layer material is greater than the bandgap of gallium nitride, and the buffer layer material includes a piezoelectric material; sequentially forming a channel layer, and an i-GaN channel layer, a barrier layer, and a gate cap layer of an N-channel field-effect transistor on the side of the buffer layer away from the substrate; the channel layer includes a p-GaN layer of an N-channel field-effect transistor and a p-GaN channel layer of a P-channel field-effect transistor; forming a first electrode and a second electrode of the N-channel field-effect transistor on the side of the barrier layer away from the substrate, the first electrode and the second electrode being disposed on opposite sides of the gate cap layer; forming a third electrode and a fourth electrode of the P-channel field-effect transistor on the side of the p-GaN channel layer away from the substrate; forming a first gate of the N-channel field-effect transistor on the side of the gate cap layer away from the substrate; and sequentially forming a gate dielectric and a second gate on the side of the p-GaN channel layer away from the substrate, the third electrode and the fourth electrode being disposed on opposite sides of the second gate.

[0024] In some possible implementations, a channel layer, an i-GaN channel layer, a barrier layer, and a gate cap layer of an N-channel field-effect transistor are sequentially formed on the side of the buffer layer away from the substrate. This includes: sequentially forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the side of the buffer layer away from the substrate. Partial removal of the fourth semiconductor layer yields the gate cap layer. A third opening is formed in the third, second, and first semiconductor layers to obtain a barrier layer, an i-GaN channel layer, a p-GaN layer, a p-GaN channel layer, a first semiconductor intermediate pattern, and a second semiconductor intermediate pattern. The first and second semiconductor intermediate patterns are located on the side of the p-GaN channel layer away from the substrate. The orthogonal projection of the third opening onto the substrate lies between the orthogonal projections of the N-channel and P-channel field-effect transistors onto the substrate. The first and second semiconductor intermediate patterns are then removed.

[0025] In some possible implementations, after forming the third opening in the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, and before removing the first semiconductor intermediate pattern and the second semiconductor intermediate pattern, the chip fabrication method further includes: partially removing the buffer layer to form a first groove on the surface of the buffer layer away from the substrate, or forming a first opening in the buffer layer; wherein the orthogonal projection of the first groove or the first opening on the substrate is located between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor on the substrate.

[0026] In some possible implementations, the chip includes multiple groups of transistors, each group including both N-channel and P-channel field-effect transistors. The chip fabrication method further includes, simultaneously with or after partially removing the buffer layer, forming a second groove or a second opening in the buffer layer on a surface opposite to the substrate; wherein the orthographic projection of the second groove or the second opening onto the substrate lies between the orthographic projections of adjacent transistor groups onto the substrate.

[0027] In some possible implementations, after forming the third and fourth electrodes of the P-channel field-effect transistor on the side of the p-GaN channel layer away from the substrate, and before sequentially forming the gate dielectric and the second gate on the side of the p-GaN channel layer away from the substrate, the chip fabrication method further includes: forming a third groove on the surface of the p-GaN channel layer away from the substrate, wherein at least a portion of the second gate and the gate dielectric are disposed in the third groove.

[0028] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0029] Figure 1a Structural diagrams of N-channel and P-channel field-effect transistors provided for related technologies;

[0030] Figure 1b This is a schematic diagram of the structure of a memory in an electronic device provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0032] Figure 3a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0033] Figure 3b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0034] Figure 4a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0035] Figure 4b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0036] Figure 5 A schematic diagram of the third groove in the chip provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0038] Figure 7a A layout of an inverter is provided for embodiments of this application;

[0039] Figure 7b A circuit diagram of an inverter is provided for an embodiment of this application;

[0040] Figure 8 This is a flowchart illustrating the fabrication process of the chip provided in an embodiment of this application.

[0041] Figure 9 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0042] Figures 10a-10g This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0043] Figure 11a and Figure 11b This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0044] Figures 12a-12d This is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0047] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0048] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0049] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0050] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes a memory.

[0051] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, storage devices, radar, and base stations.

[0052] Figure 1b This application provides a schematic diagram of the structure of a memory in an electronic device. The electronic device includes a circuit board, a memory, and other chips or independent devices. The other chips or independent devices may include a processor. The memory and other chips or independent devices are disposed on the circuit board.

[0053] Memory, processor, and other chips or devices contain logic circuits, and inverters are widely used in logic circuits. For example, inverters are widely used in circuits containing logic circuits, such as static random-access memory (SRAM), ferroelectric random access memory (FeRAM or FRAM), central processing unit (CPU), system on chip (SOC), and electronic control unit (ECU).

[0054] An inverter is a basic electronic device that receives an input signal and outputs a signal that is the inverse of the input signal. For example, if the input signal is high, the output signal is low; or, if the input signal is low, the output signal is high.

[0055] In this application, an inverter can be implemented by interconnecting an N-channel field-effect transistor (N-FET) and a P-channel field-effect transistor (P-FET).

[0056] like Figure 1a As shown, a GaN monolithic integrated device can include an N-channel field-effect transistor (FET) and a P-channel FET. Both P-channel and N-channel FETs include an n-GaN layer and an aluminum gallium nitride (AlGaN) layer disposed on the n-GaN layer. The thickness of the n-GaN layer is typically large, for example, ranging from 1 μm to 5 μm, resulting in a large overall chip thickness. Furthermore, the fabrication process of the P-channel FET is more complex.

[0057] Based on this, embodiments of this application provide a chip, such as... Figure 2 As shown, the chip includes a substrate 10, a buffer layer 11 disposed on the substrate 10, and a novel N-channel field-effect transistor and a P-channel field-effect transistor, which are spaced apart on the side of the buffer layer 11 facing away from the substrate 10. The buffer layer 11 has a bandgap greater than that of gallium nitride (GaN), and the material of the buffer layer 11 includes a piezoelectric material. The chip of this embodiment can be applied to inverters and other electronic devices; this embodiment does not limit its application.

[0058] Along a first direction from the substrate 10 to the buffer layer 11, the N-channel field-effect transistor includes a p-GaN layer 121, an i-GaN channel layer 131, a barrier layer 141, a gate cap layer 151, and a first gate 181 stacked on the buffer layer 11. The N-channel field-effect transistor also includes a first electrode 161 and a second electrode 162 disposed on the barrier layer 141, with the first electrode 161 and the second electrode 171 respectively located on opposite sides of the gate cap layer 151. A two-dimensional electron gas can be formed at the interface between the i-GaN channel layer 131 and the barrier layer 141. When the N-channel field-effect transistor is turned on, the two-dimensional electron gas acts as a channel, enabling the first electrode 161 and the second electrode 162 to conduct.

[0059] It should be understood that the gate cap layer 151 is disposed on the side of the barrier layer 141 facing away from the substrate 10, and the first electrode 161 and the second electrode 171 are disposed on opposite sides of the gate cap layer 151. Therefore, the first electrode 161 and the second electrode 162 are also disposed on the side of the barrier layer 141 facing away from the substrate 10. Furthermore, p-GaN refers to P-type gallium nitride, and i-GaN refers to intrinsic gallium nitride; these will not be elaborated further below.

[0060] Along the first direction, the P-channel field-effect transistor includes a p-GaN channel layer 122, a gate dielectric 19, and a second gate 182 stacked together. The P-channel field-effect transistor also includes a third electrode 162 and a fourth electrode 172 disposed on the p-GaN channel layer 122, with the third electrode 162 and the fourth electrode 172 respectively located on both sides of the second gate 182. Furthermore, the material of the p-GaN layer 121 is the same as the material of the p-GaN channel layer 122; that is, the materials of the p-GaN layer 121 and the p-GaN channel layer 122 can be fabricated using the same semiconductor process. Since the material of the buffer layer 11 includes a piezoelectric material, and the bandgap of the buffer layer 11 is greater than the bandgap of gallium nitride, a two-dimensional hole gas can be formed at the interface between the buffer layer 11 and the p-GaN channel layer 122 under the polarization effect of the buffer layer 11. When a conduction voltage is applied to the second gate 182, the two-dimensional hole gas moves under the electric field, which enables the third electrode 162 and the fourth electrode 172 to conduct.

[0061] As mentioned earlier, the large thickness of the n-GaN layer results in a large chip thickness, and the fabrication process of the P-channel field-effect transistor is relatively complex.

[0062] In this application, the p-GaN channel layer 122 of the P-channel field-effect transistor can be directly disposed on the buffer layer 11, eliminating the need for the n-GaN layer and AlGaN layer located on the Si substrate in related technologies. This simplifies the fabrication process of the P-channel field-effect transistor, shortens its growth time, and thus saves on the fabrication cost. Although the presence of the p-GaN channel layer 122 in the P-channel field-effect transistor means that the N-channel field-effect transistor also includes a p-GaN layer 121, the p-GaN layer 121 and the p-GaN channel layer 122 can be fabricated in the same semiconductor process. Therefore, the fabrication process of the N-channel field-effect transistor is not complicated by the p-GaN layer 121 in this embodiment.

[0063] In related technologies, the thickness of the n-GaN layer in the first direction is usually large. For example, the thickness of the n-GaN layer in the first direction ranges from 1 μm to 5 μm. However, neither the N-channel field-effect transistor nor the P-channel field-effect transistor of this application includes an n-GaN layer. Furthermore, the thickness of the buffer layer 11 in the embodiments of this application is usually less than the thickness of the n-GaN layer. Therefore, the embodiments of this application can also reduce the overall thickness of the chip.

[0064] In some possible implementations, the material of the buffer layer 11 is not limited, as long as the bandgap of the material of the buffer layer 11 is greater than the bandgap of gallium nitride, and the material of the buffer layer 11 includes piezoelectric materials.

[0065] Optionally, the material of the buffer layer 11 includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x N. Furthermore, in order to adjust the bandgap of the buffer layer, the material of the buffer layer 11 can be AlGaNi (Al1) with a higher aluminum content. x Ga 1-x N or aluminum nitride (AlN). For example, the material of the buffer layer 11 is Al gallium nitride (AlN) with a high aluminum content. x Ga 1-x In the case of N, the range of x is [0.5, 1].

[0066] In related technologies, gallium nitride (GaN) is typically used as the material for the buffer layer 11. Undoped GaN is an N-type semiconductor; therefore, when GaN is used as the buffer layer 11, the buffer layer 11 restricts the hole mobility of the P-channel field-effect transistor. Furthermore, both heavy and light holes in GaN have high effective mass, and the heavier the hole, the slower its movement speed, which also leads to a decrease in the hole mobility of the P-channel field-effect transistor. The hole mobility of the P-channel field-effect transistor using GaN as the buffer layer 11 is 10–15 cm⁻¹. 2 / (V·s) hindered the development of P-channel field-effect transistors.

[0067] In this application, the material of the buffer layer 11 is (aluminum nitride AlN or aluminum gallium nitride AlN). x Ga 1-x The band gap of N-channel field-effect transistors is larger than that of gallium nitride, resulting in better convergence of two-dimensional electron gas and no negative impact on two-dimensional hole gas. Therefore, compared with the existing technology that uses gallium nitride as the buffer layer material, the solution of this application can not only further improve the two-dimensional electron gas concentration and electron mobility of N-channel field-effect transistors, but also improve the two-dimensional hole gas and hole mobility of P-channel field-effect transistors.

[0068] Furthermore, due to aluminum nitride or aluminum gallium nitride (Al) x Ga 1-x The large bandgap of N results in a high breakdown field strength for the buffer layer 11; furthermore, aluminum nitride (AlN) material exhibits excellent thermal conductivity, thus, aluminum nitride (AlN) or aluminum gallium nitride (AlN) is employed. x Ga 1-x As a buffer layer material, N can also improve the chip's breakdown resistance and heat dissipation performance.

[0069] Furthermore, the material of the buffer layer 11 includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x When the substrate 10 is made of silicon (Si) and the material has a large bandgap (e.g., N-channel MOSFETs), if the buffer layer 11 is thick in the first direction, multiple cracks can easily form in the buffer layer 11 during deposition on the substrate 10, making it impossible to fabricate properly functioning N-channel and P-channel MOSFETs. Therefore, the buffer layer 11 is usually thin. However, even with a thin buffer layer 11, if there are process defects, leakage between the N-channel and P-channel MOSFETs through the buffer layer 11 can still easily occur.

[0070] Based on this, this embodiment of the application changes the material of the substrate 10 and the process parameters for preparing the AlN buffer layer 11, thereby reducing the full width at half maximum (FWHM) of the diffraction peaks of the AlN buffer layer 11. A narrower FWHM indicates better film quality in the AlN buffer layer 11. This allows for the formation of a thicker AlN buffer layer 11 on the substrate 10 while simultaneously mitigating the problem of cracks within the AlN buffer layer 11. Furthermore, since aluminum nitride is an insulating material, leakage between the N-channel and P-channel field-effect transistors through the buffer layer 11 can be avoided. Moreover, because the solution obtained in this embodiment improves the leakage problem of the buffer layer 11, deep etching isolation between the N-channel and P-channel field-effect transistors is unnecessary, thereby reducing chip power consumption and improving operating efficiency.

[0071] Optionally, since the silicon carbide (SiC) substrate 10 exerts relatively low stress on the aluminum nitride buffer layer 11, the material of the substrate 10 may include materials such as silicon carbide (SiC), and the material of the buffer layer 11 may include aluminum nitride (AlN). By optimizing the process parameters, the film quality of the aluminum nitride buffer layer 11 formed on the silicon carbide substrate 10 can be improved, while the thickness of the aluminum nitride buffer layer 11 in the first direction can be increased.

[0072] Furthermore, in related technologies employing gallium nitride (GaN) buffer layers, the thickness of the GaN buffer layer in the first direction exceeds 1 μm. In this application, however, the lattice mismatch between the silicon carbide substrate 10 and the aluminum nitride buffer layer 11 is smaller, resulting in lower stress on the aluminum nitride buffer layer 11. Consequently, the thickness of the buffer layer 11 in the first direction in this embodiment is smaller (e.g., 200 nm to 800 nm), thereby reducing parasitic inductance in the chip.

[0073] Of course, the material of the substrate 10 in this application embodiment may also include sapphire, silicon, etc., and this application embodiment does not limit it.

[0074] In some possible implementations, the embodiments of this application do not limit the thickness of the substrate 10, p-GaN layer 121 and p-GaN channel layer 122, i-GaN channel layer 131, barrier layer 141, and gate cap layer 151 in the first direction. Optionally, the thickness of the substrate 10 in the first direction ranges from 300 μm to 1000 μm, the thickness of the p-GaN layer 121 and p-GaN channel layer 122 in the first direction ranges from 100 nm to 150 nm, the thickness of the i-GaN channel layer 131 in the first direction ranges from 100 nm to 300 nm, the thickness of the barrier layer 141 in the first direction ranges from 15 nm to 30 nm, and the thickness of the gate cap layer 151 in the first direction ranges from 70 nm to 120 nm.

[0075] Optionally, the material of the buffer layer 11 may include aluminum nitride (AlN), and the material of the substrate 10 may include silicon carbide (SiC). The full width at half maximum (FWHM) of the XRD diffraction peaks in the buffer layer 11 can be less than or equal to 1000 arcseconds (arcsec). In some possible implementations, high-resolution X-ray diffraction (HRXRD) can be used to determine the FWHM of the diffraction peaks in the buffer layer 11.

[0076] In some possible implementations, the material of the barrier layer 141 is not limited in this application embodiment, and the material of the barrier layer 141 includes aluminum gallium nitride.

[0077] In some possible implementations, the material of the gate cap layer 151 is not limited, as long as the gate cap layer 151 can deplete the two-dimensional electron gas located on the side of the barrier layer 141 facing the substrate 10, so that the N-channel field-effect transistor can realize an enhancement-mode device. Optionally, the material of the gate cap layer 151 includes P-GaN.

[0078] In some possible implementations, the first electrode 161 is the source and the second electrode 171 is the drain; or, the first electrode 161 is the drain and the second electrode 171 is the source. The third electrode 162 is the source and the fourth electrode 172 is the drain; or, the third electrode 162 is the drain and the fourth electrode 172 is the source.

[0079] In some possible implementations, the materials of the first electrode 161, second electrode 171, third electrode 162, and fourth electrode 172 are not limited. Optionally, along the first direction, both the first electrode 161 and the second electrode 171 include a stacked titanium layer, an aluminum layer, a nickel layer, and a gold layer, and both the first electrode 161 and the second electrode 171 form an ohmic contact with the barrier layer 141. Along the first direction, both the third electrode 162 and the fourth electrode 172 include a stacked nickel layer and a gold layer, and both the third electrode 162 and the fourth electrode 172 form an ohmic contact with the p-GaN channel layer 122.

[0080] In some possible implementations, the embodiments of this application do not limit the thickness of the first electrode 161, the second electrode 171, the third electrode 162, and the fourth electrode 172 in the first direction. Optionally, the thickness range of the first electrode 161, the second electrode 171, the third electrode 162, and the fourth electrode 172 in the first direction is 120nm to 250nm.

[0081] In some possible implementations, the materials of the gate dielectric 19, the first gate 181, and the second gate 182 are not limited. Optionally, the material of the gate dielectric 19 includes dielectric materials such as aluminum oxide (Al2O3). Along the first direction, both the first gate 181 and the second gate 182 include a nickel layer and a gold layer stacked together.

[0082] In some possible implementations, the embodiments of this application do not limit the thickness of the gate dielectric 19, the first gate 181, and the second gate 182 in the first direction. Optionally, the thickness of the gate dielectric layer in the first direction is in the range of 15nm to 20nm, and the thickness of the first gate 181 and the second gate 182 in the first direction is in the range of 100nm to 300nm.

[0083] In some embodiments, after forming a first semiconductor layer on the buffer layer 11, the first semiconductor layer is etched to obtain a p-GaN layer 121 and a p-GaN channel layer 122. However, if etching residue remains after etching the first semiconductor layer, leakage current will occur in the p-GaN layer 121 and p-GaN channel layer 122 due to the residual portion. Therefore, the first semiconductor layer can be over-etched to obtain electrically isolated p-GaN layers 121 and 122. In the case of over-etching the first semiconductor layer, the buffer layer 11 is also at least partially etched, thereby obtaining... Figure 3a and Figure 3b The structure shown.

[0084] like Figure 3a As shown, a first groove is formed on the surface of the buffer layer 11 facing away from the substrate 10. The orthogonal projection of the first groove onto the substrate 10 is located between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate 10. Alternatively, as... Figure 3b As shown, the buffer layer 11 has a first opening that extends through the buffer layer 11. The orthographic projection of the first opening onto the substrate 10 lies between the orthographic projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate 10. Other openings mentioned below also extend through the film layer containing these openings, and will not be described further below.

[0085] In some embodiments, the chip includes multiple transistor groups, each transistor group including N-channel field-effect transistors and P-channel field-effect transistors. In this case, the portion of the first semiconductor layer located between adjacent transistor groups can also be etched. If etching residue remains after etching the first semiconductor layer, leakage will occur in the p-GaN layer 121 and p-GaN channel layer 122 of one transistor group, and in the p-GaN layer 121 and p-GaN channel layer 122 of the adjacent transistor group. Based on this, the first semiconductor layer can be over-etched to obtain multiple electrically isolated transistor groups. In the case of over-etching the first semiconductor layer, the buffer layer 11 is also at least partially etched, thereby obtaining... Figure 4a and Figure 4b The structure shown.

[0086] like Figure 4a As shown, a second groove is formed on the surface of the buffer layer 11 facing away from the substrate 10. The orthogonal projection of the second groove on the substrate 10 is located between the orthogonal projections of adjacent transistor groups on the substrate 10.

[0087] Or, such as Figure 4b As shown, the buffer layer 11 has a second opening, the orthographic projection of which onto the substrate 10 is located between the orthographic projections of adjacent transistor groups onto the substrate 10.

[0088] In some possible implementations, the first semiconductor layer can be over-etched once, simultaneously obtaining... Figure 3a and Figure 4a The first and second grooves shown, or both simultaneously obtained Figure 3b and Figure 4b The first and second openings are shown. Alternatively, the first semiconductor can be etched in two stages. After the first etching of the first semiconductor layer, the desired result is obtained. Figure 3a The first groove shown or Figure 3b The first opening shown is used to perform a second over-etch on the first semiconductor layer to obtain... Figure 4a The second groove shown Figure 4b The second opening shown; or, after the first over-etching of the first semiconductor layer, the following is obtained: Figure 4a The second groove shown Figure 4b The second opening shown is used to perform a second over-etch on the first semiconductor layer, resulting in... Figure 3a The first groove shown or Figure 3b The first opening is shown.

[0089] In some embodiments, such as Figure 5As shown, a third groove is formed on the surface of the p-GaN channel layer 122 facing away from the substrate 10. Since the gate dielectric 19 is disposed on the side of the p-GaN channel layer 122 facing away from the substrate 10, and the gate dielectric 19 is conformally grown with the p-GaN channel layer 122, the gate dielectric 19 also has a groove at the location of the third groove. At least a portion of the second gate 182 and the gate dielectric 19 are disposed in the third groove. In this way, the distance between the second gate 182 and the two-dimensional hole gas (the two-dimensional hole gas is located at the interface between the p-GaN channel layer 122 and the buffer layer 11) can be reduced, thereby improving the gate control capability of the second gate 182.

[0090] Optionally, the depth of the third groove in the first direction is not limited in the embodiments of this application. The depth of the third groove in the first direction is related to the thickness of the p-GaN channel layer 122 in the first direction. Optionally, the depth range of the third groove is 20nm to 50nm.

[0091] In some possible ways of implementation, such as Figure 6 As shown, the gate dielectric 19 extends from the side of the first electrode 161, barrier layer 141, p-GaN layer 121, first gate 181, second electrode 171, third electrode 162, and fourth electrode 172 away from the substrate 10, to the space between the p-GaN channel layer 122 and the second gate 182. In this way, the gate dielectric 19 can also be reused as an interlayer dielectric (ILD), eliminating the need for interlayer dielectrics disposed on the side of the N-channel and P-channel field-effect transistors away from the substrate 10.

[0092] In some embodiments, when an inverter is implemented using an N-channel field-effect transistor and a P-channel field-effect transistor interconnected, such as Figure 6 As shown, the gate medium 19 includes a perforated first through-hole groove, a second groove, a third groove, a fourth groove, and a fifth groove. The perforated first, second, third, fourth, and fifth grooves in the gate medium 19 refer to the first, second, third, fourth, and fifth grooves penetrating the gate medium 19.

[0093] Furthermore, such as Figure 7a As shown, the chip also includes a first wiring layer disposed on the side of the gate dielectric 19 and the second gate 182 facing away from the substrate 10. The first wiring layer includes an input terminal Vin, an output terminal Vout, a ground terminal GND, and a voltage terminal VDD. Figure 7bAs shown, the input terminal Vin is electrically connected to the first gate through the first trench, and is also electrically connected to the second gate. The output terminal Vout is electrically connected to the second gate through the second trench, and is also electrically connected to the fourth gate through the third trench. The ground terminal GND is electrically connected to the first gate through the fourth trench. The voltage terminal VDD is electrically connected to the third gate through the fifth trench.

[0094] like Figure 7a As shown, the chip also includes a dielectric layer and a second wiring layer disposed on the side of the first wiring layer opposite to the substrate 10. The dielectric layer includes a sixth via, a seventh via, an eighth via, and a ninth via. The second wiring layer includes a first conductive structure 21 and a second conductive structure 22. The first conductive structure 21 is electrically connected to the input terminal Vin through the sixth and seventh vias, and the second conductive structure 22 is electrically connected to the output terminal Vout through the eighth and ninth vias.

[0095] In another embodiment, this application also provides a method for fabricating a chip, such as... Figure 8 As shown, this can be achieved in the following way:

[0096] S110, such as Figure 9 As shown, a buffer layer 11 is formed on the substrate 10. The bandgap of the material of the buffer layer 11 is greater than that of gallium nitride, and the material of the buffer layer 11 includes a piezoelectric material.

[0097] In some possible implementations, the buffer layer 11 can be deposited using metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) processes.

[0098] In some possible implementations, the material of the buffer layer 11 is not limited, as long as the bandgap of the material of the buffer layer 11 is greater than the bandgap of gallium nitride, and the material of the buffer layer 11 includes piezoelectric materials.

[0099] Optionally, the material of the buffer layer 11 includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x N. Furthermore, in order to adjust the bandgap of the buffer layer 11, the material of the buffer layer 11 can be AlGaNi (Al1) with a high aluminum content. x Ga 1-x N or aluminum nitride (AlN). For example, the material of the buffer layer 11 is Al gallium nitride (AlN) with a high aluminum content. x Ga 1-x In the case of N, the range of x is [0.5, 1].

[0100] In related technologies, gallium nitride (GaN) is typically used as the material for the buffer layer 11. Undoped GaN is an N-type semiconductor; therefore, when GaN is used as the buffer layer 11, the buffer layer 11 restricts the hole mobility of the P-channel field-effect transistor. Furthermore, both heavy and light holes in GaN have high effective mass, and the heavier the hole, the slower its movement speed, which also leads to a decrease in the hole mobility of the P-channel field-effect transistor. The hole mobility of the P-channel field-effect transistor using GaN as the buffer layer 11 is 10–15 cm⁻¹. 2 / (V·s) hindered the development of P-channel field-effect transistors.

[0101] In this application, the material of the buffer layer 11 is (aluminum nitride AlN or aluminum gallium nitride AlN). x Ga 1-x The bandgap of N-channel field-effect transistors is greater than that of gallium nitride (GaN). In particular, the two-dimensional electron gas is more convergent, which has no negative impact on the two-dimensional hole gas. Therefore, compared with the existing technology that uses GaN as the buffer layer material, the solution of this application can not only further improve the electron mobility of N-channel field-effect transistors, but also improve the hole mobility of P-channel field-effect transistors.

[0102] Furthermore, due to aluminum nitride or aluminum gallium nitride (Al) x Ga 1-x The large bandgap of N results in a high breakdown field strength for the buffer layer 11; furthermore, aluminum nitride (AlN) material exhibits excellent thermal conductivity, thus, aluminum nitride (AlN) or aluminum gallium nitride (AlN) is employed. x Ga 1-x As a buffer layer material, N can also improve the chip's breakdown resistance and heat dissipation performance.

[0103] Furthermore, the material of the buffer layer 11 includes aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x When the substrate 10 is made of silicon (Si) and the material has a large bandgap (e.g., N-channel MOSFETs), if the buffer layer 11 is thick in the first direction, multiple cracks can easily form in the buffer layer 11 during deposition on the substrate 10, making it impossible to fabricate properly functioning N-channel and P-channel MOSFETs. Therefore, the buffer layer 11 is usually thin. However, even with a thin buffer layer 11, if there are process defects, leakage between the N-channel and P-channel MOSFETs through the buffer layer 11 can still easily occur.

[0104] Based on this, the embodiments of this application change the material of the substrate 10 and the process parameters for preparing the buffer layer 11, so that the full width at half maximum (FWHM) of the diffraction peak of the buffer layer 11 is reduced. The narrower the FWHM of the diffraction peak of the buffer layer 11, the better the crystal quality of the buffer layer 11.

[0105] Improving the crystal quality of the buffer layer 11 effectively enhances its film quality. This allows for the formation of a thicker buffer layer 11 on the substrate 10 while mitigating the problem of cracks within the buffer layer 11. Furthermore, when the buffer layer 11 is made of aluminum nitride, its insulating properties prevent leakage between the N-channel and P-channel field-effect transistors through the buffer layer 11. Moreover, since the solution obtained in this embodiment improves the leakage problem of the buffer layer 11, additional isolation between the N-channel and P-channel field-effect transistors is unnecessary, thereby reducing chip power consumption and improving operating efficiency.

[0106] Optionally, the full width at half maximum (FWHM) of the diffraction peaks of the buffer layer 11 can be less than or equal to 1000 arcseconds (arcsec). In some possible implementations, high-resolution X-ray diffraction (HRXRD) can be used to determine the FWHM of the diffraction peaks of the buffer layer 11.

[0107] Optionally, since the silicon carbide (SiC) substrate 10 exerts relatively low stress on the aluminum nitride buffer layer 11, the material of the substrate 10 may include silicon carbide, and the material of the buffer layer 11 may include aluminum nitride. By adjusting the process parameters, the film quality of the aluminum nitride buffer layer 11 formed on the silicon carbide substrate 10 can be improved, while the thickness of the aluminum nitride buffer layer 11 in the first direction can be increased.

[0108] Furthermore, in related technologies employing gallium nitride (GaN) buffer layers, the thickness of the GaN buffer layer in the first direction exceeds 1 μm. In this application, however, the lattice mismatch between the silicon carbide substrate 10 and the aluminum nitride buffer layer 11 is smaller, resulting in lower stress on the aluminum nitride buffer layer 11. Consequently, the thickness of the buffer layer 11 in the first direction in this embodiment is smaller (e.g., 200 nm to 800 nm), thereby reducing parasitic inductance in the chip.

[0109] Of course, the material of the substrate 10 in this application embodiment may also include sapphire, silicon, etc., and this application embodiment does not limit it.

[0110] S120, such as Figure 10a As shown, a first semiconductor layer 12, a second semiconductor layer 13, a third semiconductor layer 14, and a fourth semiconductor layer 15 are sequentially formed on the side of the buffer layer 11 away from the substrate 10.

[0111] In some possible implementation methods, metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) processes can be used to epitaxially grow a first semiconductor layer 12 on the buffer layer 11, a second semiconductor layer 13 on the first semiconductor layer 12, a third semiconductor layer 14 on the second semiconductor layer 13, and a fourth semiconductor layer 15 on the third semiconductor layer 14.

[0112] S130, such as Figure 10b As shown, the fourth semiconductor layer 15 is partially removed to obtain the gate cap layer 151.

[0113] In some possible implementations, photolithography and inductively coupled plasma etching processes can be used to partially etch the fourth semiconductor layer 15 to obtain the gate cap layer 151.

[0114] S140, such as Figure 10c As shown, a third opening is formed in the third semiconductor layer 14, the second semiconductor layer 13, and the first semiconductor layer 11, resulting in a barrier layer 141, an i-GaN channel layer 131, a p-GaN layer 121, a p-GaN channel layer 122, a first semiconductor intermediate pattern 132, and a second semiconductor intermediate pattern 142. The first semiconductor intermediate pattern 132 and the second semiconductor intermediate pattern 142 are located on the side of the p-GaN channel layer 122 facing away from the substrate 10. The orthogonal projection of the third opening onto the substrate 10 lies between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate 10.

[0115] In some possible implementations, the material of the barrier layer 141 is not limited in this application embodiment, and the material of the barrier layer 141 includes aluminum gallium nitride.

[0116] In some possible implementations, when the first semiconductor layer 12 is over-etched, the chip fabrication method further includes, after step S140 and before step S150, the following steps: Figure 10c As shown, the buffer layer is partially removed to form a first groove in the buffer layer 11 on the surface opposite to the substrate 10; or, as... Figure 10d As shown, the buffer layer is partially removed to form a first opening in the buffer layer 11. The orthogonal projection of the first groove or the first opening onto the substrate lies between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate 10. If the first groove is formed in the buffer layer 11 away from the surface of the substrate 10, the depth of the first groove in the first direction can be 300 nm to 400 nm.

[0117] In this way, after etching the first semiconductor layer, an electrically isolated p-GaN layer 121 and p-GaN channel layer 122 can be obtained, preventing leakage of current through the p-GaN layer 121 and p-GaN channel layer 122 through the residual portion in the first semiconductor layer.

[0118] In some possible implementations, the chip includes multiple groups of transistors, each group comprising both N-channel and P-channel field-effect transistors. In this case, the chip fabrication method further includes, while, after, or before partially removing the buffer layer, the process of partially removing the buffer layer: Figure 10e As shown, the buffer layer 11 is partially removed to form a second groove in the buffer layer 11 on the surface opposite to the substrate 10; or, as... Figure 10f As shown, the buffer layer 11 is partially removed to form a second opening in the buffer layer 11. The orthogonal projection of the second groove or the second opening onto the substrate 10 lies between the orthogonal projections of adjacent transistor groups onto the substrate. If the second groove is formed in the buffer layer 11 away from the surface of the substrate 10, the depth of the second groove in the first direction can be in the range of 300nm-400nm.

[0119] In this way, after etching the first semiconductor layer 12, multiple electrically isolated transistor groups can be obtained, preventing leakage of current through the residual portion in the first semiconductor layer.

[0120] S150, such as Figure 10g As shown, the first semiconductor intermediate pattern 132 and the second semiconductor intermediate pattern 142 are removed.

[0121] Thus, a channel layer, an i-GaN channel layer 131 for an N-channel field-effect transistor, a barrier layer 141, and a gate cap layer 151 are sequentially formed on the side of the buffer layer 11 facing away from the substrate 10. The channel layer includes a p-GaN layer 121 for an N-channel field-effect transistor and a p-GaN channel layer 122 for a P-channel field-effect transistor.

[0122] In some possible implementations, the embodiments of this application do not limit the thickness of the substrate 10, p-GaN layer 121 and p-GaN channel layer 122, i-GaN channel layer 131, barrier layer 141, and gate cap layer 151 in the first direction. Optionally, the thickness of the substrate 10 in the first direction ranges from 300 μm to 1000 μm, the thickness of the p-GaN layer 121 and p-GaN channel layer 122 in the first direction ranges from 100 nm to 150 nm, the thickness of the i-GaN channel layer 131 in the first direction ranges from 100 nm to 300 nm, the thickness of the barrier layer 141 in the first direction ranges from 15 nm to 30 nm, and the thickness of the gate cap layer 151 in the first direction ranges from 70 nm to 120 nm.

[0123] In some possible implementations, the material of the gate cap layer 151 is not limited, as long as the gate cap layer 151 can deplete the two-dimensional electron gas located on the side of the barrier layer 141 facing the substrate 10, so that the N-channel field-effect transistor can realize an enhancement-mode device. Optionally, the material of the gate cap layer 151 includes P-GaN.

[0124] S160, such as Figure 11a and Figure 11b As shown, the first electrode 161 and the second electrode 171 of an N-channel field-effect transistor are formed on the side of the barrier layer 141 away from the substrate 10. The first electrode 161 and the second electrode 171 are respectively disposed on both sides of the gate cap layer 151. The third electrode 162 and the fourth electrode 172 of a P-channel field-effect transistor are formed on the side of the p-GaN channel layer 122 away from the substrate 10.

[0125] In some possible implementations, the embodiments of this application do not limit the order in which the first electrode 161 and the second electrode 171 are formed and the third electrode 162 and the fourth electrode 172 are formed. Optionally, the first electrode 161 and the second electrode 171 may be formed first, and then the third electrode 162 and the fourth electrode 172 may be formed; or the third electrode 162 and the fourth electrode 172 may be formed first, and then the first electrode 161 and the second electrode 171 may be formed.

[0126] In some possible implementations, the first electrode 161 is the source and the second electrode 171 is the drain; or, the first electrode 161 is the drain and the second electrode 171 is the source. The third electrode 162 is the source and the fourth electrode 172 is the drain; or, the third electrode 162 is the drain and the fourth electrode 172 is the source.

[0127] In some possible implementations, the materials of the first electrode 161, the second electrode 171, the third electrode 162, and the fourth electrode 172 are not limited in the embodiments of this application.

[0128] Optionally, forming the first electrode 161 and the second electrode 171 may involve using an electron beam evaporation process to sequentially stack a 20nm-30nm thick titanium layer, a 110nm-130nm thick aluminum layer, a 30nm-50nm thick nickel layer, and a 40nm-60nm thick gold layer along a first direction, and then annealing the layers in a nitrogen atmosphere at 850°C for 30s, so that both the first electrode 161 and the second electrode 171 form ohmic contacts with the barrier layer 141. For example, the thickness of the titanium layer is 20nm, the thickness of the aluminum layer is 120nm, the thickness of the nickel layer is 40nm, and the thickness of the gold layer is 50nm.

[0129] Optionally, forming the third electrode 162 and the fourth electrode 172 includes: using an electron beam evaporation process, sequentially stacking a nickel layer with a thickness of 30 nm to 50 nm and a gold layer with a thickness of 40 nm to 60 nm along a first direction, and annealing in a nitrogen atmosphere at a temperature of 500 °C for 30 s, so that both the third electrode 162 and the fourth electrode 172 form ohmic contacts with the p-GaN channel layer 122. For example, the thickness of the nickel layer is 40 nm and the thickness of the gold layer is 50 nm.

[0130] In some possible implementations, the embodiments of this application do not limit the total thickness of the first electrode 161, the second electrode 171, the third electrode 162, and the fourth electrode 172 in the first direction. Optionally, the thickness range of the first electrode 161, the second electrode 171, the third electrode 162, and the fourth electrode 172 in the first direction is 120nm to 250nm.

[0131] S170, such as Figure 12a As shown, the first gate 181 of an N-channel field-effect transistor is formed on the side of the gate cap layer 151 opposite to the substrate 10.

[0132] In some possible implementations, an electron beam evaporation process can be used to form a nickel layer with a thickness of 40 nm to 50 nm and a gold layer with a thickness of 100 nm to 200 nm on the side of the gate cap layer 151 facing away from the substrate 10, serving as the first gate 181. For example, the thickness of the nickel layer is 45 nm and the thickness of the gold layer is 150 nm.

[0133] S180, such as Figure 12c and Figure 12d As shown, a gate dielectric 19 and a second gate 182 are sequentially formed on the side of the p-GaN channel layer 122 away from the substrate 10, and a third electrode 162 and a fourth electrode 172 are respectively disposed on both sides of the second gate 182.

[0134] In some possible ways of implementation, such as Figure 12cAs shown, an atomic layer deposition process can be used to sequentially form 15nm to 20nm thick aluminum oxide on the side of the p-GaN channel layer 122 away from the substrate 10 under a temperature condition of 300℃ and a nitrogen atmosphere, as the gate dielectric 19.

[0135] In some possible ways of implementation, such as Figure 12c As shown, the gate dielectric 19 extends from the side of the first electrode 161, barrier layer 141, p-GaN layer 121, first gate 181, second electrode 171, third electrode 162, and fourth electrode 172 away from the substrate 10, to the space between the p-GaN channel layer 122 and the second gate 182. In this way, the gate dielectric 19 can be reused as an interlayer dielectric, eliminating the need for interlayer dielectrics disposed on the side of the N-channel and P-channel field-effect transistors away from the substrate 10.

[0136] In some possible ways of implementation, such as Figure 12d As shown, an electron beam evaporation process can be used to form a nickel layer with a thickness of 40 nm to 50 nm and a gold layer with a thickness of 100 to 200 nm on the side of the gate dielectric 19 facing away from the substrate 10, as the second gate 182. For example, the thickness of the nickel layer is 45 nm and the thickness of the gold layer is 150 nm.

[0137] In some embodiments, such as Figure 12b As shown, after removing the first semiconductor intermediate pattern 132 and the second semiconductor intermediate pattern 142 in step S150 and before forming the gate dielectric 19 in step S180, the chip fabrication method further includes: forming a third groove on the surface of the p-GaN channel layer 122 away from the substrate 10, wherein at least a portion of the second gate 182 and the gate dielectric 19 are disposed in the third groove.

[0138] Since the gate dielectric 19 is disposed on the side of the p-GaN channel layer 122 facing away from the substrate 10, and the gate dielectric 19 is conformally grown with the p-GaN channel layer 122, the gate dielectric 19 also has a groove at the third groove location, and at least a portion of the second gate 182 and the gate dielectric 19 are disposed in the third groove. In this way, the spacing between the second gate 182 and the two-dimensional hole gas (located at the interface between the p-GaN channel layer 122 and the buffer layer 11) can be reduced, thereby improving the gate control capability of the second gate 182.

[0139] Optionally, the depth of the third groove in the first direction is not limited in the embodiments of this application. The depth of the third groove in the first direction is related to the thickness of the p-GaN channel layer 122 in the first direction. Optionally, the depth range of the third groove is 20nm to 50nm.

[0140] As mentioned earlier, the large thickness of the n-GaN layer results in a large chip thickness, and the fabrication process of the P-channel field-effect transistor is relatively complex.

[0141] In this application, the p-GaN channel layer 122 of the P-channel field-effect transistor can be directly disposed on the buffer layer 11, eliminating the need for the n-GaN layer and AlGaN layer located on the S substrate in related technologies. This simplifies the fabrication process of the P-channel field-effect transistor, shortens its growth time, and thus saves on its fabrication cost. Although the presence of the p-GaN channel layer 122 in the P-channel field-effect transistor means that the N-channel field-effect transistor also includes a p-GaN layer 121, the p-GaN layer 121 and the p-GaN channel layer 122 can be fabricated in the same semiconductor process. Therefore, the embodiment of this application does not complicate the fabrication process of the N-channel field-effect transistor due to the p-GaN layer 121.

[0142] In related technologies, the thickness of the n-GaN layer in the first direction is usually large. For example, the thickness of the n-GaN layer in the first direction ranges from 1 μm to 5 μm. However, neither the N-channel field-effect transistor nor the P-channel field-effect transistor of this application includes an n-GaN layer. Furthermore, the thickness of the buffer layer 11 in the embodiments of this application is usually less than the thickness of the n-GaN layer. Therefore, the embodiments of this application can also reduce the overall thickness of the chip.

[0143] In some embodiments, when an inverter is implemented using an N-channel field-effect transistor and a P-channel field-effect transistor interconnected, such as Figure 6 As shown, after step S180, a first trench, a second trench, a third trench, a fourth trench, and a fifth trench may be formed in the gate medium 19.

[0144] In some possible implementations, a wet etching process can be used, for example, by using a 5% hydrofluoric acid (HF) solution to partially etch the gate dielectric 19, thereby forming a first trench, a second trench, a third trench, a fourth trench, and a fifth trench in the gate dielectric 19, exposing the first electrode 161, the second electrode 171, the first gate electrode 181, the third electrode 162, and the fourth electrode 172. The first trench, second trench, third trench, fourth trench, and fifth trench in the gate dielectric 19 refer to trenches that penetrate the gate dielectric 19.

[0145] Next, as Figure 7a As shown, a first wiring layer is formed on the side of the gate dielectric 19 and the second gate 182 facing away from the substrate 10. The first wiring layer includes an input terminal Vin, an output terminal Vout, a ground terminal GND, and a voltage terminal VDD. Figure 7bAs shown, the input terminal Vin is electrically connected to the first gate through the first trench, and is also electrically connected to the second gate. The output terminal Vout is electrically connected to the second gate through the second trench, and is also electrically connected to the fourth gate through the third trench. The ground terminal GND is electrically connected to the first gate through the fourth trench. The voltage terminal VDD is electrically connected to the third gate through the fifth trench.

[0146] Next, as Figure 7a As shown, a dielectric layer and a second wiring layer are formed on the side of the first wiring layer opposite to the substrate 10. The dielectric layer includes a sixth via, a seventh via, an eighth via, and a ninth via. The second wiring layer includes a first conductive structure 21 and a second conductive structure 22. The first conductive structure 21 is electrically connected to the input terminal Vin through the sixth and seventh vias, and the second conductive structure 22 is electrically connected to the output terminal Vout through the eighth and ninth vias.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: Substrate; A buffer layer; the buffer layer is disposed on the substrate, the material of the buffer layer has a bandgap wider than the bandgap of gallium nitride, and the material of the buffer layer includes a piezoelectric material; An N-channel field-effect transistor and a P-channel field-effect transistor are provided; the N-channel and P-channel field-effect transistors are spaced apart on the side of the buffer layer away from the substrate; along the direction from the substrate to the buffer layer, the N-channel field-effect transistor includes a p-GaN layer, an i-GaN channel layer, a barrier layer, a gate cap layer, and a first gate layer stacked on the buffer layer; the P-channel field-effect transistor includes a p-GaN channel layer, a gate dielectric, and a second gate layer stacked on the buffer layer; the N-channel field-effect transistor further includes a first electrode and a second electrode disposed on the barrier layer, the first electrode and the second electrode being disposed on opposite sides of the gate cap layer; the P-channel field-effect transistor further includes a third electrode and a fourth electrode disposed on the p-GaN channel layer, the third electrode and the fourth electrode being disposed on opposite sides of the second gate layer; wherein, the material of the p-GaN layer is the same as the material of the p-GaN channel layer.

2. The chip according to claim 1, characterized in that, A first groove is formed on the surface of the buffer layer facing away from the substrate. The orthogonal projection of the first groove on the substrate is located between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor on the substrate. or, The buffer layer has a first opening, the orthographic projection of which onto the substrate is located between the orthographic projections of the N-channel field-effect transistor and the P-channel field-effect transistor onto the substrate.

3. The chip according to claim 1 or 2, characterized in that, The chip includes multiple transistor groups, and each transistor group includes an N-channel field-effect transistor and a P-channel field-effect transistor. A second groove is formed on the surface of the buffer layer facing away from the substrate, and the orthographic projection of the second groove on the substrate is located between the orthographic projections of the adjacent transistor groups on the substrate; or, The buffer layer has a second opening, the orthographic projection of which is located between the orthographic projections of adjacent transistor groups on the substrate.

4. The chip according to any one of claims 1-3, characterized in that, A third groove is formed on the surface of the p-GaN channel layer away from the substrate, and at least a portion of the second gate and the gate dielectric are disposed in the third groove.

5. The chip according to any one of claims 1-4, characterized in that, The buffer layer is made of aluminum nitride (AlN) or aluminum gallium nitride (Al). x Ga 1-x The values ​​of N and x range from [0.5, 1].

6. The chip according to claim 5, characterized in that, The buffer layer is made of aluminum nitride, and the substrate is made of silicon carbide.

7. The chip according to claim 6, characterized in that, The full width at half maximum (FWHM) of the diffraction peaks of the buffer layer is less than or equal to 1000 arcseconds.

8. The chip according to any one of claims 1-7, characterized in that, The gate dielectric extends from the side of the first electrode, the barrier layer, the p-GaN layer, the first gate, the second electrode, the third electrode, and the fourth electrode away from the substrate to the space between the p-GaN channel layer and the second gate.

9. The chip according to claim 8, characterized in that, The grid medium includes a perforated first groove, a second groove, a third groove, a fourth groove, and a fifth groove; The chip further includes a first wiring layer disposed on the side of the gate dielectric and the second gate facing away from the substrate. The first wiring layer includes an input terminal, an output terminal, a ground terminal, and a voltage terminal. The input terminal is electrically connected to the first gate through the first trench and is also electrically connected to the second gate. The output terminal is electrically connected to the second electrode through the second trench and is also electrically connected to the fourth electrode through the third trench. The ground terminal is electrically connected to the first electrode through the fourth trench. The voltage terminal is electrically connected to the third electrode through the fifth trench. The chip further includes a dielectric layer and a second wiring layer disposed on the side of the first wiring layer opposite to the substrate. The dielectric layer includes a sixth via, a seventh via, an eighth via, and a ninth via. The second wiring layer includes a first conductive structure and a second conductive structure. The first conductive structure is electrically connected to the input terminal through the sixth via and the seventh via, and the second conductive structure is electrically connected to the output terminal through the eighth via and the ninth via.

10. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-9, the chip being disposed on the circuit board.

11. A method for fabricating a chip, characterized in that, include: A buffer layer is formed on the substrate, wherein the bandgap of the material of the buffer layer is greater than the bandgap of gallium nitride, and the material of the buffer layer includes a piezoelectric material; A channel layer, an i-GaN channel layer, a barrier layer, and a gate cap layer of the N-channel field-effect transistor are sequentially formed on the side of the buffer layer away from the substrate; the channel layer includes a p-GaN layer of the N-channel field-effect transistor and a p-GaN channel layer of the P-channel field-effect transistor. The first and second electrodes of the N-channel field-effect transistor are formed on the side of the barrier layer away from the substrate, and the first and second electrodes are respectively disposed on both sides of the gate cap layer; The third and fourth electrodes of the P-channel field-effect transistor are formed on the side of the p-GaN channel layer away from the substrate; The first gate of the N-channel field-effect transistor is formed on the side of the gate cap layer opposite to the substrate; A gate dielectric and a second gate are sequentially formed on the side of the p-GaN channel layer away from the substrate; the third and fourth electrodes are respectively disposed on both sides of the second gate.

12. The method for fabricating a chip according to claim 11, characterized in that, The method involves sequentially forming a channel layer on the side of the buffer layer opposite to the substrate, and the i-GaN channel layer, barrier layer, and gate cap layer of the N-channel field-effect transistor, including: A first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer are sequentially formed on the side of the buffer layer opposite to the substrate; The fourth semiconductor layer is partially removed to obtain the gate cap layer; A third opening is formed in the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer to obtain the barrier layer, the i-GaN channel layer, the p-GaN layer, the p-GaN channel layer, the first semiconductor intermediate pattern, and the second semiconductor intermediate pattern. The first semiconductor intermediate pattern and the second semiconductor intermediate pattern are located on the side of the p-GaN channel layer facing away from the substrate. The orthogonal projection of the third opening on the substrate is located between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor on the substrate. Remove the intermediate pattern of the first semiconductor and the intermediate pattern of the second semiconductor.

13. The method for fabricating a chip according to claim 12, characterized in that, After forming the third opening in the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, and before removing the intermediate pattern of the first semiconductor layer and the intermediate pattern of the second semiconductor layer, the chip fabrication method further includes: The buffer layer is partially removed to form a first groove on the surface of the buffer layer opposite to the substrate, or to form a first opening in the buffer layer; wherein the orthogonal projection of the first groove or the first opening on the substrate is located between the orthogonal projections of the N-channel field-effect transistor and the P-channel field-effect transistor on the substrate.

14. The method for fabricating a chip according to claim 13, characterized in that, The chip includes multiple transistor groups, and each transistor group includes an N-channel field-effect transistor and a P-channel field-effect transistor. The chip fabrication method further includes, simultaneously with or after partially removing the buffer layer: The buffer layer is partially removed to form a second groove on the surface of the buffer layer opposite to the substrate, or to form a second opening in the buffer layer; wherein the orthogonal projection of the second groove or the second opening on the substrate is located between the orthogonal projections of adjacent transistor groups on the substrate.

15. The method for fabricating a chip according to any one of claims 11-14, characterized in that, After forming the third and fourth electrodes of the P-channel field-effect transistor on the side of the p-GaN channel layer away from the substrate, and before sequentially forming the gate dielectric and the second gate on the side of the p-GaN channel layer away from the substrate, the chip fabrication method further includes: A third groove is formed on the surface of the p-GaN channel layer away from the substrate, and at least a portion of the second gate and the gate dielectric are disposed in the third groove.

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