Semiconductor device

Abstract

A semiconductor device includes: an active region extending in a first direction; a plurality of gate structures including a first gate structure and a second gate structure; a plurality of channel layers including a first channel layer and a second channel layer; a plurality of source / drain regions including a first source / drain region, a second source / drain region, and a third source / drain region; a first inner spacer layer between the first gate structure and the first source / drain region; a second inner spacer layer between the first gate structure and the second source / drain region; a third inner spacer layer between the second gate structure and the second source / drain region; and a fourth inner spacer layer between the second gate structure and the third source / drain region. A center thickness of each of the second inner spacer layers is greater than a center thickness of each of the first inner spacer layers.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for forming the semiconductor devices. Background Technology

[0002] As the demand for high performance, high speed, and / or versatility in semiconductor devices increases, the integration density of semiconductor devices is also increasing. In responding to this trend towards higher integration, the fabrication of semiconductor devices with finely patterned designs necessitates the realization of patterns with fine widths or fine spacing. Furthermore, efforts are underway to develop semiconductor devices, including transistors with three-dimensional channel structures, to overcome the limitations in operating characteristics caused by the miniaturization of planar metal-oxide-semiconductor FETs (MOSFETs). Summary of the Invention

[0003] One of the technical problems this disclosure aims to solve is to provide semiconductor devices that can improve their integration.

[0004] One of the technical problems this disclosure aims to solve is to provide semiconductor devices with improved performance.

[0005] One of the technical problems this disclosure aims to solve is to provide a method for forming the semiconductor device.

[0006] As a means to solve the above problems, a semiconductor device can be provided, the semiconductor device comprising: a substrate, the substrate including an active region extending in a first direction; a plurality of gate structures, the plurality of gate structures extending on the substrate along a second direction and intersecting the active region, and including a first gate structure and a second gate structure disposed spaced apart from each other in the first direction; a plurality of channel layers, the plurality of channel layers disposed on the active region in a third direction perpendicular to the upper surface of the substrate and spaced apart from each other, and including a first channel layer surrounded by the first gate structure and a second channel layer surrounded by the second gate structure; a plurality of source / drain regions, the plurality of source / drain regions disposed in a region where the active region is recessed, located on one side of each of the plurality of gate structures, and including a first source / drain region connected to the first channel layer, a second source / drain region connected to the first channel layer and the second channel layer, and a third source / drain region connected to the second channel layer; a first internal spacer layer, the first internal spacer... A second internal spacer layer is disposed between the first gate structure and the first source / drain region, and is located below each of the first channel layers on the active region; a second internal spacer layer is disposed between the first gate structure and the second source / drain region, and is located below each of the first channel layers on the active region; a third internal spacer layer is disposed between the second gate structure and the second source / drain region, and is located below each of the second channel layers on the active region; and a fourth internal spacer layer is disposed between the second gate structure and the third source / drain region, and is located below each of the second channel layers on the active region, wherein the center thickness of each of the second internal spacers in the first direction is greater than the center thickness of each of the first internal spacers in the first direction, and the center thickness of each of the third internal spacers in the first direction is greater than the center thickness of each of the fourth internal spacers in the first direction.

[0007] Alternatively, a semiconductor device can be provided, comprising: a first source / drain region and a second source / drain region; a plurality of channel layers stacked spaced apart from each other in a vertical direction and connected to the first source / drain region and the second source / drain region in a first direction intersecting the vertical direction; a gate electrode surrounding each of the plurality of channel layers in a second direction intersecting the first direction and the vertical direction; a gate dielectric layer disposed between the gate electrode and the plurality of channel layers, and between the gate electrode and the first source / drain region and the second source / drain region; a first internal spacer layer disposed between the gate dielectric layer and the first source / drain region; and a second internal spacer layer disposed between the gate dielectric layer and the second source / drain region. Wherein, the minimum thickness of each second internal spacer layer in the first direction is greater than the minimum thickness of each first internal spacer layer in the first direction.

[0008] Alternatively, a semiconductor device may be provided, comprising: a first source / drain region and a second source / drain region; a plurality of channel layers stacked spaced apart from each other in a vertical direction and connected to the first source / drain region and the second source / drain region in a first direction intersecting the vertical direction; a gate electrode surrounding each of the plurality of channel layers in a second direction intersecting the first direction and the vertical direction; a gate dielectric layer disposed between the gate electrode and the plurality of channel layers, and between the gate electrode and the first source / drain region and the second source / drain region; a first internal spacer layer disposed between the gate dielectric layer and the first source / drain region; and a second internal spacer layer disposed between the gate dielectric layer and the second source / drain region, wherein the thickness of the second internal spacer layer in the first direction is about 1.1 times to about 5 times the thickness of the first internal spacer layer in the first direction.

[0009] As a means to solve the above problems, a method for manufacturing a semiconductor device can be provided, the method comprising: alternately stacking a sacrificial layer and a channel layer on a substrate; forming an active structure including an active region by partially removing the sacrificial layer, the channel layer, and the substrate; forming a sacrificial gate structure intersecting the active structure on the active structure; forming a recessed region by partially removing the active structure on at least one side of the sacrificial gate structure; forming a photoresist pattern between the sacrificial gate structures and on a portion of the upper surface of the sacrificial gate structure; depositing a sacrificial pad layer conformally covering the photoresist pattern, the sacrificial gate structure, and the active region; exposing the upper surface of the photoresist pattern by partially removing the upper surface of the sacrificial pad layer using non-selective etching; removing the exposed photoresist pattern; removing a portion of the sacrificial layer and the sacrificial pad layer by a wet etching process; depositing an insulating material layer conformally covering the sacrificial gate structure and a portion of the active region; and forming an internal spacer layer by removing a portion of the insulating material layer.

[0010] In this context, a method for manufacturing a semiconductor device can be provided, wherein the sacrificial pad layer comprises a material having etch selectivity relative to each of the channel layers.

[0011] In this context, a method for manufacturing a semiconductor device can be provided, wherein the sacrificial pad layer comprises a semiconductor material containing at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge), and comprises a material different from that of the channel layer.

[0012] In this context, a method for manufacturing a semiconductor device may be provided, wherein exposing the upper surface of the photoresist pattern by partially removing the upper surface of the sacrificial pad layer using non-selective etching comprises: partially removing the upper surface of the sacrificial pad layer using anisotropic etching.

[0013] In this context, a method for manufacturing a semiconductor device may be provided, wherein removing portions of the sacrificial layer and the sacrificial pad layer by a wet etching process comprises: selectively etching the sacrificial pad layer relative to the channel layer by a wet etching process.

[0014] In this context, a method for manufacturing a semiconductor device may be provided, wherein removing portions of the sacrificial layer and the sacrificial pad layer by a wet etching process comprises: selectively etching portions of the sacrificial layer relative to the channel layer by a wet etching process.

[0015] In this context, a method for manufacturing a semiconductor device can be provided, wherein the insulating material layer comprises silicon nitride or silicon oxynitride.

[0016] In this context, a method for manufacturing a semiconductor device can be provided, wherein the internal spacer layer includes a first internal spacer layer, a second internal spacer layer, a third internal spacer layer, and a fourth internal spacer layer, and the center thickness of each second internal spacer layer in a first direction is greater than the center thickness of each first internal spacer layer in the first direction, and the center thickness of each third internal spacer layer in the first direction is greater than the center thickness of each fourth internal spacer layer in the first direction.

[0017] In this context, a method for manufacturing a semiconductor device can be provided, wherein the internal spacer layer comprises a first internal spacer layer, a second internal spacer layer, a third internal spacer layer, and a fourth internal spacer layer, and the thickness of each second internal spacer layer in the first direction is in the range of about 1.1 times to about 5 times the thickness of each first internal spacer layer in the first direction.

[0018] In this context, a method for manufacturing a semiconductor device can be provided, wherein the internal spacer layer includes a first internal spacer layer, a second internal spacer layer, a third internal spacer layer, and a fourth internal spacer layer, and the center thickness of each second internal spacer layer is equal to the center thickness of each third internal spacer layer. Attached Figure Description

[0019] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 This is a top view showing a semiconductor device according to some embodiments.

[0021] Figure 2 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0022] Figure 3 This is a partially enlarged view showing a semiconductor device according to some embodiments.

[0023] Figure 4 This is a partially enlarged view showing a semiconductor device according to some embodiments.

[0024] Figure 5 This is a partially enlarged view showing a semiconductor device according to some embodiments.

[0025] Figure 6This is a partially enlarged view showing a semiconductor device according to some embodiments.

[0026] Figure 7 This is a schematic cross-sectional view showing a semiconductor device according to some embodiments.

[0027] Figure 8 This is a schematic cross-sectional view showing a semiconductor device according to some embodiments.

[0028] Figures 9A to 9K This is a view showing a method for manufacturing a semiconductor device according to an example embodiment, arranged in the order of the manufacturing process. Detailed Implementation

[0029] In the following description, preferred embodiments will be illustrated with reference to the accompanying drawings. Unless otherwise specified, terms such as 'on', 'upper', 'upper surface', 'below', 'lower', 'lower surface', 'side surface', etc., in this specification may be based on the drawings and may actually vary depending on the orientation in which the components are positioned.

[0030] Furthermore, ordinal numbers such as "first," "second," and "third" can be used as labels for specific elements, operations, directions, etc., to distinguish various elements, operations, directions, etc. Terms such as "first" and "second," which may not be used in the specification, may still be referred to as "first" or "second" in the claims. Additionally, a term referenced by a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or other claims).

[0031] Figure 1 This is a top view showing a semiconductor device 100A according to some embodiments. For ease of explanation, in Figure 1 Only some components of the semiconductor device 100A are shown in the image.

[0032] Figure 2 A schematic cross-sectional view of a semiconductor device 100A according to some embodiments is shown. Figure 2 schematically shown Figure 1 The cross sections of semiconductor device 100A taken along lines I-I' and II-II'.

[0033] Figure 3 This is a partially enlarged view showing a semiconductor device 100A according to some embodiments. Figure 3 It shows Figure 2 A magnified view of region 'A' of semiconductor device 100A.

[0034] refer to Figure 1 , Figure 2 and Figure 3 Semiconductor device 100A may include: a substrate 101 including an active region 105; a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 disposed on the active region 105 and spaced vertically from each other; a gate structure 160 extending to intersect the active region 105 and including a gate electrode 165; a source / drain region 130 contacting the channel structure 140; an internal spacer layer 150 disposed between the gate structure 160 and the source / drain region 130 and located below each of the channel layers 141, 142, 143, and 144; and a contact structure 180 connected to the source / drain region 130. The internal spacer layer 150 may include first to fourth internal spacer layers 150a, 150b, 150c, and 150d. The semiconductor device 100A may also include a device isolation layer 110 and an interlayer insulating layer 170.

[0035] According to this disclosure, the thickness of each second inner spacer layer 150b in the first direction (e.g., the X direction) may be greater than the thickness of each first inner spacer layer 150a in the first direction (e.g., the X direction), and the thickness of each third inner spacer layer 150c in the first direction (e.g., the X direction) may be greater than the thickness of each fourth inner spacer layer 150d in the first direction (e.g., the X direction).

[0036] According to this disclosure, the gate-drain capacitance (Cgd) can be effectively reduced by forming a thicker internal spacer layer on the drain side than on the source side to increase the separation distance between the gate and the drain.

[0037] When the internal spacer layer on the drain side is designed to be thicker while maintaining the gate length, the thickness of the spacer on the source side may become slightly thinner, thereby increasing the gate-source capacitance (Cgs). Due to the relatively small or constant voltage fluctuation range on the source side, the impact on switching current and power consumption on the source side may be weaker than on the drain side. Therefore, the total effective capacitance (Ceff) may actually decrease.

[0038] Furthermore, the device disclosed herein can reduce the total effective capacitance without increasing the gate length (or channel length), but by changing only the thickness of the internal spacer layer while maintaining the gate length (or channel length). As a result, the transistor performance can be effectively improved.

[0039] Furthermore, according to this disclosure, by forming a thicker internal spacer layer on the drain side than on the source side to increase the separation distance between the gate and the drain, leakage current caused by gate-induced drain leakage (GIDL) can be prevented or minimized. Therefore, the reliability of the transistor can be increased, and its performance can be improved.

[0040] The following text will describe each component of the semiconductor device 100A in detail.

[0041] In semiconductor device 100A, the active region 105 may have a finned structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. Therefore, semiconductor device 100A may include an MBCFET. TM (Multi-bridge channel FET) structure transistor (which can be a full-ring gate field-effect transistor).

[0042] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0043] Substrate 101 may include an active region 105 disposed thereon. The active region 105 may be defined within substrate 101 by device isolation layer 110 and may be configured to extend in a first direction (e.g., the X direction). Depending on the manner of description, the active region 105 may also be described as being configured separately from substrate 101. The active region 105 may partially protrude above device isolation layer 110, such that the upper surface of the active region 105 may be at a higher height than the upper surface of device isolation layer 110. The active region 105 may be formed as part of substrate 101, or may include an epitaxial layer grown from substrate 101. On both sides of gate structure 160, the active region 105 may be partially recessed to form recessed regions, and a plurality of source / drain regions 130 may be disposed in these recessed regions.

[0044] In an example implementation, the active region 105 may or may not include a well region containing impurities. For example, in a p-type transistor (pFET), the well region may include n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb); and in an n-type transistor (nFET), the well region may include p-type impurities such as boron (B), gallium (Ga), or indium (In). The well region may, for example, be located at a predetermined depth from the upper surface of the active region 105.

[0045] Device isolation layer 110 may define active region 105 in substrate 101. Device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. Device isolation layer 110 may expose the upper surface of active region 105, and may also partially expose the upper portion of active region 105. In some embodiments, device isolation layer 110 may have a curved upper surface to provide a greater height toward active region 105. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0046] Gate structure 160 may be configured to extend in a second direction (e.g., the Y direction) to intersect with active region 105 and a plurality of channel layers 141, 142, 143, and 144 (hereinafter referred to as "channel structures"). Functional channel regions of transistors may be formed in active region 105 and / or channel structure 140 intersecting with gate electrode 165 of gate structure 160. Each gate structure 160 may include gate electrode 165, gate dielectric layer 162 between gate electrode 165 and first to fourth channel layers 141, 142, 143, and 144, and gate spacer layer 164 located on side surface of gate electrode 165. Gate structure 160 may include first gate structure 160a and second gate structure 160b, which intersect active region 105 to extend in a second direction (e.g., the Y direction) and are spaced apart from each other in a first direction (e.g., the X direction).

[0047] A gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be configured to surround all surfaces of the gate electrode 165 except for the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may contact an inner spacer layer 150 located beneath each of the plurality of channel layers 141, 142, 143, and 144, and may be spaced apart from the source / drain region 130 by the inner spacer layer 150. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but is not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. High-k materials may refer to dielectric materials having a higher dielectric constant than silicon oxide (SiO2). This high-κ material can be, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or zirconium silicon oxide (ZrSi). x O yHafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y It is one of praseodymium oxide (Pr2O3) or praseodymium oxide. According to some embodiments, the gate dielectric layer 162 can be formed as a multilayer film.

[0048] The gate electrode 165 may be disposed on the active region 105 to fill the space between the first to fourth channel layers 141, 142, 143, and 144, and extend onto the channel structure 140. The gate electrode 165 may be separated from the first to fourth channel layers 141, 142, 143, and 144 by a gate dielectric layer 162. The gate electrode 165 may include a conductive material and may include, for example, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or metallic materials (such as aluminum (Al), tungsten (W), or molybdenum (Mo)) or semiconductor materials (such as doped polysilicon). According to some embodiments, the gate electrode 165 may be formed as two or more multilayer structures.

[0049] A gate spacer layer 164 may be disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 130 from the gate electrode 165. According to some embodiments, the gate spacer layer 164 may be formed as a multilayer structure. The gate spacer layer 164 may be formed of at least one of oxide, nitride, or oxynitride, and may be formed as, for example, a low-k film.

[0050] The gate structure 160 may further include a gate capping layer 166 located on the gate electrode 165. The gate capping layer 166 may extend along the gate electrode 165 in the Y direction. The gate capping layer 166 may include at least one of SiON, SiCN, SiCON, or SiN.

[0051] A channel structure 140 may be disposed on the active region 105 in the region where the active region 105 intersects with the gate structure 160. Each channel structure 140 may include first to fourth channel layers 141, 142, 143, and 144, which may be multiple channel layers disposed spaced apart from each other in the Z direction. The first to fourth channel layers 141, 142, 143, and 144 may be disposed sequentially from the top, and the first channel layer 141 may be the bottommost channel layer. The channel structure 140 may be connected to the source / drain region 130. The channel structure 140 may have a width equal to or similar to that of the gate structure 160 in the X direction, and may have a width equal to or smaller than that of the active region 105 in the Y direction. In a cross-section in the Y direction, among the first to fourth channel layers 141, 142, 143, and 144, the lower channel layer may have a width equal to or greater than that of the upper channel layer. In some embodiments, the number and shape of the channel layers forming a single channel structure 140 can vary. For example, a channel structure 140 may include three channel layers, or it may include two channel layers, or five or more channel layers. The channel structure 140 may include a first channel structure 140a configured to be surrounded by a first gate structure 160a, and a second channel structure 140b configured to be surrounded by a second gate structure 160b.

[0052] The channel structure 140 may be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge). The channel structure 140 may be formed of, for example, the same material as the active region 105. In some embodiments, the channel structure 140 may also include an impurity region located in a region adjacent to the source / drain region 130.

[0053] Source / drain regions 130 may be disposed on both sides of the gate structure 160 in recessed regions formed by partially recessing the upper portion of the active region 105. These recessed regions may extend along the side surfaces of the channel structure 140 and the gate dielectric layer 162. The source / drain regions 130 may be configured to cover the side surfaces in the X direction of each of the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140. The upper surface of the source / drain regions 130 may be at a height equal to or higher than the lower surface of the gate electrode 165 on the channel structure 140, and this height may vary in some embodiments. The side surfaces of the source / drain regions 130 may have curvature depending on the first to fourth channel layers 141, 142, 143, and 144 and the internal spacer layer 150. For example, the side surface of the source / drain region 130 contacting the channel structure 140 can be flat or concave in the inward direction. The specific shape of the side surface of the source / drain region 130 is not fixed and can vary depending on some implementations. The source / drain region 130 can be an epitaxially grown region and can include multiple epitaxial layers. The epitaxially grown surface of the source / drain region 130 can contact the channel structure 140, the internal spacer layer 150, and the interlayer insulating layer 170. The source / drain region 130 can be disposed in the recessed region of the active region 105 on one side of each gate structure 160, and can include a first source / drain region 130a connected to the first channel structure 140a, a second source / drain region 130b connected to the first channel structure 140a and the second channel structure 140b, and a third source / drain region 130c connected to the second channel structure 140b. The first source / drain region 130a, the second source / drain region 130b, and the third source / drain region 130c can be configured to be spaced apart from each other in a first direction (e.g., the X direction). The first source / drain region 130a can be connected to the first channel structure 140a, the second source / drain region 130b can be connected to the first channel structure 140a and the second channel structure 140b, and the third source / drain region 130c can be connected to the second channel structure 140b.

[0054] The source / drain region 130 may include a semiconductor material, such as at least one of silicon (Si) or germanium (Ge), and may also include a dopant. For example, when the semiconductor device 100A is an nFET, the dopant may be at least one of phosphorus (P), arsenic (As), or antimony (Sb). For example, when the semiconductor device 100A is a pFET, the dopant may be at least one of boron (B), gallium (Ga), or indium (In). According to some embodiments, the source / drain region 130 may be formed as a plurality of epitaxial layers.

[0055] The internal spacer layer 150 can be configured to be parallel to the gate electrode 165 along the Z-direction between the first to fourth channel layers 141, 142, 143 and 144. The gate electrode 165 can be stably spaced apart from and electrically isolated from the source / drain region 130 by the internal spacer layer 150.

[0056] The internal spacer layer 150 may include a first internal spacer layer 150a, a second internal spacer layer 150b, a third internal spacer layer 150c, and a fourth internal spacer layer 150d. The first internal spacer layer 150a may be disposed on the active region 105 below each of the channel layers of the first channel structure 140a, and between the first gate structure 160a and the first source / drain region 130a. The second internal spacer layer 150b may be disposed on the active region 105 below each of the channel layers of the first channel structure 140a, and between the first gate structure 160a and the second source / drain region 130b. The third internal spacer layer 150c may be disposed on the active region 105 below each of the channel layers of the second channel structure 140b, and between the second gate structure 160b and the second source / drain region 130b. The fourth internal spacer layer 150d may be disposed on the active region 105 below each of the channel layers of the second channel structure 140b and between the second gate structure 160b and the third source / drain region 130c.

[0057] The center thickness of each second inner spacer layer 150b in the first direction (e.g., the X direction) may be greater than the center thickness of each first inner spacer layer 150a in the first direction (e.g., the X direction). The center thickness of each third inner spacer layer 150c in the first direction (e.g., the X direction) may be greater than the center thickness of each fourth inner spacer layer 150d in the first direction (e.g., the X direction).

[0058] The internal spacer layer 150 may include the outer surface of the contact source / drain region 130 and the inner surface of the gate dielectric layer 162 of the contact gate structure 160. The internal spacer layer 150 may be in a shape in which the outer surface facing the source / drain region 130 is recessed and rounded toward the gate electrode 165, but the shape is not limited thereto.

[0059] The inner spacer layer 150 may have a shape in which the inner surface facing the gate dielectric layer 162 is relatively less rounded than the outer surface. Therefore, the inner surface of the inner spacer layer 150 may appear perpendicular to the upper surface of the substrate 101, but its shape is not limited to this. The shape of the inner spacer layer 150 can be modified in various ways depending on the shape of the source / drain regions 130, the fabrication method and sequence of the inner spacer layer 150, etc.

[0060] The internal spacer layer 150 may include at least one of oxide, nitride, or oxynitride, and may be formed as, for example, a low-k film. In some embodiments, the internal spacer layer 150 may include silicon nitride or silicon oxynitride.

[0061] like Figure 3 As shown, referring primarily to an internal spacer layer 150, an internal spacer layer may include: a middle portion located at the center of the internal spacer layer; a lower portion extending downward from the middle portion and having a maximum thickness greater than the thickness of the middle portion; and an upper portion extending upward from the middle portion and having a maximum thickness greater than the thickness of the middle portion.

[0062] In the internal spacer layer 150, the thickness of each portion of the internal spacer layer can refer to the thickness in a direction perpendicular to the surface of the gate dielectric layer 162. In this disclosure, the center thickness D1 can refer to the thickness of the middle portion of the internal spacer layer 150, the upper thickness D2 can refer to the thickness of the upper portion of the internal spacer layer 150, and the lower thickness D3 can refer to the thickness of the lower portion of the internal spacer layer 150.

[0063] In a first direction (e.g., the X direction), the center thickness D1 of each inner spacer layer 150 may be less than the upper thickness D2 and lower thickness D3 of each inner spacer layer 150. The center thickness D1 of each inner spacer layer 150 may be the minimum thickness, and the upper thickness D2 and lower thickness D3 may be the maximum thickness. The thickness of each second inner spacer layer 150b in the first direction (e.g., the X direction) may be greater than the thickness of each first inner spacer layer 150a. The thickness of each third inner spacer layer 150c in the first direction (e.g., the X direction) may be greater than the thickness of each fourth inner spacer layer 150d in the first direction (e.g., the X direction). This thickness may refer to the center thickness D1 of the inner spacer layer 150, or it may refer to the minimum thickness.

[0064] According to this disclosure, the thickness of each second inner spacer layer 150b in a first direction (e.g., the X direction) may be greater than the thickness of each first inner spacer layer 150a in the first direction (e.g., the X direction), and the thickness of each third inner spacer layer 150c in the first direction (e.g., the X direction) may be greater than the thickness of each fourth inner spacer layer 150d in the first direction (e.g., the X direction). In some embodiments (or for example), the center thickness D1 (or "minimum thickness") of the second inner spacer layer 150b and the third inner spacer layer 150c may be in the range of about 5 nm to about 9 nm. The center thickness D1 (or "minimum thickness") of the first inner spacer layer 150a and the fourth inner spacer layer 150d may be in the range of about 1 nm to about 5 nm.

[0065] The thicknesses of the second internal spacer layer 150b and the third internal spacer layer 150c in the first direction (e.g., the X direction) can be in the range of approximately 1.1 to approximately 5 times the thicknesses of the first internal spacer layer 150a and the fourth internal spacer layer 150d in the first direction (e.g., the X direction). When the thicknesses of the second internal spacer layer 150b and the third internal spacer layer 150c in the first direction (e.g., the X direction) are less than the aforementioned ratio range, the effect of forming a thicker internal spacer layer on one side to reduce gate-drain capacitance and leakage current may be relatively small. When the thicknesses of the second internal spacer layer 150b and the third internal spacer layer 150c in the first direction (e.g., the X direction) are greater than the aforementioned ratio range, the internal spacer layer on one side may become excessively thick, thereby actually degrading the performance of the semiconductor device.

[0066] This disclosure covers reducing the total effective capacitance without degrading the device's integration density or channel characteristics by making the internal spacer layer on the first side of the gate thicker than the internal spacer layer on the opposite second side of the gate. In other words, the reduction in total effective capacitance does not require changing the gate length. In this disclosure, the channel length may refer to the gap between the first source / drain region 130a and the second source / drain region 130b, and the gate length may refer to the gap between the first gate structure 160a and the second gate structure 160b.

[0067] In this configuration, the gate length can be, for example, in the range of about 20 nm to about 25 nm, but is not limited thereto, and can be varied depending on the device design. Similarly, the channel length can be, for example, in the range of about 10 nm to about 15 nm, but is not limited thereto, and can be varied depending on the device design. In this configuration, the sum of the thickness of the second internal spacer layer 150b and the thickness of the first internal spacer layer 150a can be in the range of about 1% to about 50% of the channel length. Likewise, the sum of the thickness of the third internal spacer layer 150c and the thickness of the fourth internal spacer layer 150d can be in the range of about 1% to about 50% of the channel length.

[0068] Based on the second source / drain region 130b, the first internal spacer layer 150a and the second internal spacer layer 150b can be symmetrical in shape with respect to the third internal spacer layer 150c and the fourth internal spacer layer 150d. In this case, the second source / drain region 130b can be the drain side of an NMOS transistor, but the region is not limited to this and can be source-side depending on the design of the semiconductor device.

[0069] For example, the thickness of each second internal spacer layer 150b in the first direction may be equal to the thickness of each third internal spacer layer 150c in the first direction, and the thickness of each first internal spacer layer 150a in the first direction may be equal to the thickness of each fourth internal spacer layer 150d in the first direction. Specifically, the center thickness of each second internal spacer layer 150b may be equal to the center thickness of each third internal spacer layer 150c, and the center thickness of each first internal spacer layer 150a may be equal to the center thickness of each fourth internal spacer layer 150d. The distance in the first direction (e.g., the X direction) between the inner surface of the first internal spacer layer 150a that contacts the first gate structure 160a and the second source / drain region 130b may be equal to the distance in the first direction (e.g., the X direction) between the inner surface of the fourth internal spacer layer 150d that contacts the second gate structure 160b and the second source / drain region 130b. The distance between the inner surface of the second internal spacer layer 150b that contacts the first gate structure 160a and the second source / drain region 130b in the first direction (e.g., the X direction) can be equal to the distance between the inner surface of the third internal spacer layer 150c that contacts the second gate structure 160b and the second source / drain region 130b in the first direction (e.g., the X direction).

[0070] Interlayer insulating layer 170 may be configured to cover source / drain region 130 and gate structure 160, and may be configured to cover device isolation layer 110. Interlayer insulating layer 170 may include at least one of oxide, nitride, or oxynitride, and may include, for example, a low-k material. According to some embodiments, interlayer insulating layer 170 may include multiple insulating layers.

[0071] The contact plug 180 can penetrate the interlayer insulation layer 170 to connect to the source / drain region 130 and can apply an electrical signal to the source / drain region 130. The contact plug 180 may have a sloped side surface that depends on the aspect ratio, in which the lower part of the sloped side surface is narrower than the upper part, but its shape is not limited thereto. The contact plug 180 may extend from the top, for example, to below the lower surface of the fourth channel layer 144, which may serve as the uppermost channel structure 140, but is not limited thereto.

[0072] Each contact plug 180 may include a metal silicide layer located at its lower end (including a lower surface), and may also include a barrier layer forming a side surface of the contact plug 180 and extending to the upper surface of the metal silicide layer. The barrier layer may include a metal nitride, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The contact plug 180 may include a metallic material, such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), etc. In the example embodiment, the number and arrangement of the conductive layers constituting the contact plug 180 may be varied.

[0073] Interconnection structures such as contact plugs can also be disposed on the gate electrode 165, and interconnection structures connected to the contact plug 180 can also be disposed on the contact plug 180.

[0074] This disclosure can be implemented in various ways. For example, the shape and thickness conditions of the internal spacer layer can be varied depending on the degree of etching performed in the process. In the following description of the embodiments, references to the foregoing will be omitted. Figures 1 to 3 Any description that overlaps with the description.

[0075] Figure 4 This is a partially enlarged view showing a semiconductor device 100B according to some embodiments. Figure 4 It shows the relationship with Figure 2 The region corresponding to region 'A' is shown. Figure 3 Example of modification.

[0076] refer to Figure 4 According to some embodiments, the semiconductor device 100B may have the same characteristics as the reference. Figure 1 , Figure 2 and Figure 3The same or similar features are described, except that the degree of rounding of the outer surface of the inner spacer layer 150 is changed.

[0077] refer to Figure 4 The internal spacer layer 150 of the semiconductor device 100B may include the outer surface of the contact source / drain region 130 and the inner surface of the gate dielectric layer 162 of the contact gate structure 160.

[0078] The inner spacer layer 150 may have a shape in which the outer surface facing the source / drain region 130 has a relatively low degree of roundness. Therefore, the outer surface of the inner spacer layer 150 may have a shape perpendicular to the upper surface of the substrate 101. The inner surface of the inner spacer layer 150 facing the gate dielectric layer 162 may have a shape in which the inner surface has a relatively low degree of roundness. Therefore, the inner surface of the inner spacer layer 150 may have a shape perpendicular to the upper surface of the substrate 101.

[0079] The outer surface of the first internal spacer layer 150a that contacts the first source / drain region 130a can be substantially coplanar with the side surface of the first channel structure 140a, and the outer surface of the second internal spacer layer 150b that contacts the second source / drain region 130b can be substantially coplanar with the side surface of the first channel structure 140a.

[0080] like Figure 4 As shown, referring primarily to one of the internal spacer layers 150, it may include: a middle portion located at the center of the middle portion; a lower portion extending downward from the middle portion and having a thickness equal to that of the middle portion; and an upper portion extending upward from the middle portion and having a thickness equal to that of the middle portion.

[0081] In the internal spacer layer 150, the thickness of each portion of the internal spacer layer can refer to the thickness in a direction perpendicular to the surface of the gate dielectric layer 162. In some embodiments, the thickness of the upper, middle, and lower portions of the internal spacer layer 150 can be constant in the Z direction.

[0082] The above reference will be omitted. Figures 1 to 3 The description concerns the comparison of thicknesses.

[0083] Figure 5 This is a partially enlarged view showing a semiconductor device 100C according to some embodiments. Figure 5 It shows the relationship with Figure 2 The region corresponding to region 'A' is shown. Figure 3 Example of modification.

[0084] refer to Figure 5According to some embodiments, the semiconductor device 100C may have the same characteristics as the reference. Figure 1 , Figure 2 and Figure 3 The same or similar features are described, except that the degree of rounding of the inner surface of the internal spacer layer 150 is changed.

[0085] refer to Figure 5 The internal spacer layer 150 of the semiconductor device 100C may include the outer surface of the contact source / drain region 130 and the inner surface of the gate dielectric layer 162 of the contact gate structure 160.

[0086] The internal spacer layer 150 may have a shape in which the outer surface facing the source / drain region 130 is recessed and rounded toward the gate electrode 165, and may have a shape in which the inner surface facing the gate dielectric layer 162 is recessed and rounded toward the gate electrode 165, but is not limited thereto.

[0087] In a first direction (e.g., the X direction), the center thickness D1 of each internal spacer layer 150 may be less than the upper thickness D2 and the lower thickness D3 of each internal spacer layer 150. The center thickness D1 of each internal spacer layer 150 may be the minimum thickness, and the upper thickness D2 and the lower thickness D3 may be the maximum thickness.

[0088] The shape, such as the degree of rounding and curvature of the side surfaces of the internal spacer layers, can be varied depending on the degree of etching performed in the process. Therefore, the center thickness D1 of each internal spacer layer 150 can be greater than the upper thickness D2 and lower thickness D3 of each internal spacer layer 150. Furthermore, the center thickness D1 of each internal spacer layer 150 can be the maximum thickness, and the upper thickness D2 and lower thickness D3 can be the minimum thickness.

[0089] The references above will be omitted in the following text. Figures 1 to 3 The description concerns the comparison of thicknesses.

[0090] Figure 6 This is a partially enlarged view showing a semiconductor device 100D according to some embodiments. Figure 6 It shows the relationship with Figure 2 The region corresponding to region 'A' is shown. Figure 3 Example of modification.

[0091] refer to Figure 6 According to some embodiments, the semiconductor device 100D may have the same characteristics as the reference. Figure 1 , Figure 2 and Figure 3 The same or similar features are described, except that the width of the channel portion gradually increases towards the lower end in the X direction.

[0092] In the gate structure 160 described above, the gate electrode ( Figure 2 165) can be transformed into a gate electrode 165' with increased width in a first direction (e.g., the X direction).

[0093] The gate electrode 165' may include an upper gate portion 165'_3, a middle gate portion 165'_2, and a lower gate portion 165'_1. In the gate electrode 165', the middle gate portion 165'_2 may have a larger diameter than the portion corresponding to it. Figure 3 The width of the middle portion of the gate electrode 165 is greater than the width of the lower gate portion 165'_1. Figure 3 The lower portion of the gate electrode 165 has a larger width. Therefore, as the overall size of the gate electrode 165' increases, the electrical characteristics of the gate electrode of the transistor including the gate electrode 165' can be improved.

[0094] In some embodiments of the semiconductor device 100D, even if the width of the channel portion in the X direction increases, only the width of the gate electrode 165' increases, while the thickness and ratio of the internal spacer layer 150 remain unchanged. (The references above will be omitted below.) Figures 1 to 3 The description concerns the comparison of thicknesses.

[0095] Figure 7 This is a schematic cross-sectional view showing a semiconductor device 100E according to some embodiments. Figure 7 It shows the intercept along line I-I' Figure 2 The region corresponding to the cross section.

[0096] refer to Figure 7 According to some embodiments, the semiconductor device 100E may have the same characteristics as the reference. Figure 1 , Figure 2 and Figure 3 The same or similar features are described, except that the first internal spacer layer 150a and the fourth internal spacer layer 150d are omitted.

[0097] refer to Figure 7 According to some embodiments, the semiconductor device 100E may have a structure in which the first internal spacer layer 150a and the fourth internal spacer layer 150d are omitted, so that the internal spacer layers are formed only on one side of the gate structure of the transistor. The side surface of the gate dielectric layer 162 facing the source / drain region 130 may be substantially coplanar with the side surface of the channel structure 140.

[0098] Such as Figure 7 The structure of the semiconductor device 100E can be Figure 9FThe thickness of the sacrificial pad SL to be formed is equal to Figure 9I The sacrificial layer 120 is formed when the thickness of the sacrificial layer 120 to be etched and removed is reached. In this case, one side surface of the sacrificial layer 120 may not be removed further inward, and the side surface of the channel structure 140 may be substantially coplanar with the side surface of the sacrificial layer 120.

[0099] Figure 8 This is a schematic cross-sectional view showing a semiconductor device 100F according to some embodiments. Figure 8 It shows the intercept along line I-I' Figure 2 The region corresponding to the cross section.

[0100] refer to Figure 8 Second source / drain region 130b ( Figure 2 ) can be replaced with the second source / drain region 130b'. Figure 2 The substrate 101 and active region 105 described herein may be replaced by an insulator body 101'. The insulator body 101' may include one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0101] The semiconductor device 100F may further include: a first rear insulating layer 810 located below an insulator body 101'; a rear interconnect structure 820 disposed below the first rear insulating layer 810; and a second rear insulating layer 830 covering the rear interconnect structure 820 below the first rear insulating layer 810. The rear interconnect structure 820 may include ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), copper-containing alloys, etc. The first rear insulating layer 810 and the second rear insulating layer 830 may include at least one of, for example, oxides, nitrides, oxynitrides, or low-k dielectrics. The insulator body 101' may include a device isolation layer 110 (… Figure 2 The device isolation layer 110 is made of the same material as at least one of the first rear insulating layer 810. In this case, the device isolation layer 110 ( Figure 2 The boundary between the first rear insulating layer 810 and the layer containing the same material as the insulator body 101' may not be identifiable. Therefore, the insulator body 101' and the device isolation layer 110 may be collectively referred to as the lower insulating layer, and the insulator body 101' and the first rear insulating layer 810 may be collectively referred to as the lower insulating layer.

[0102] At least one contact plug 180 described above is connected to the source / drain region 130. Figure 2 This can be replaced by a rear contact structure 840 that penetrates the first rear insulating layer 810 and the insulator body 101'. For example, a contact plug 180 can be electrically connected to the first source / drain region 130a and the third source / drain region 130c, with... Figure 2The same applies to the others, but another contact plug 180 can be replaced by a rear contact structure 840 that penetrates the first rear insulating layer 810 and the insulator body 101' and extends into the second source / drain region 130b'. The rear contact structure 840 can be electrically connected to the rear interconnect structure 820.

[0103] Each back contact structure 840 may include a metal silicide layer located at its upper end (including the upper surface), and may also include a barrier layer extending to the lower surface of the metal silicide layer and forming the side surface of the back contact structure 840. The barrier layer may include a metal nitride, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The back contact structure 840 may include a metallic material, such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), etc. In the example embodiment, the number and arrangement of the conductive layers constituting the back contact structure 840 may vary.

[0104] Figures 9A to 9K This is a view showing a method for manufacturing a semiconductor device according to an example embodiment, arranged in the order of the manufacturing process. Figures 9A to 9K Manufacturing process is shown Figure 2 Some implementation methods of semiconductor devices.

[0105] refer to Figure 9A The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143 and 144 can be alternately stacked on the substrate 101.

[0106] The sacrificial layer 120 can be replaced by a gate dielectric layer 162 and a gate electrode 165 located below the fourth channel layer 144 through a subsequent process (e.g., Figure 2 The sacrificial layer 120 may be formed of a material having etch selectivity relative to the first to fourth channel layers 141, 142, 143, and 144. The first to fourth channel layers 141, 142, 143, and 144 may include materials different from those of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may include a semiconductor material comprising at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), while the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0107] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143 and 144 can be formed by performing an epitaxial growth process from this stacked structure. The number of channel layers stacked alternately with the sacrificial layer 120 can be varied in the implementation.

[0108] refer to Figure 9B The sacrificial layer 120, the first to fourth channel layers 141, 142, 143 and 144 and the substrate 101 can be partially removed to form an active structure AS including an active region 105, and a device isolation layer 110 can be formed.

[0109] The active structure AS may include an active region 105, a sacrificial layer 120, and first to fourth channel layers 141, 142, 143, and 144. The active structure AS may be formed as a linear shape extending in one direction (e.g., the X direction) and may be formed as being spaced apart from adjacent active structures in the Y direction. The side surfaces of the active structure AS in the Y direction may be coplanar with each other and may be located on a straight line.

[0110] An insulating material can be filled in the regions where the active region 105, the sacrificial layer 120, and each of the first to fourth channel layers 141, 142, 143, and 144 are partially removed, and the active region 105 can then be made to protrude by removing a portion of the insulating material, thereby forming a device isolation layer 110. The upper surface of the device isolation layer 110 can be formed to be lower than the upper surface of the active region 105.

[0111] refer to Figure 9C A sacrificial gate structure 200 and a gate spacer layer 164 can be formed on the active structure AS.

[0112] Each sacrificial gate structure 200 may be a sacrificial structure formed in a region where a gate dielectric layer 162 and a gate electrode 165 are subsequently disposed on the channel structure 140, such as... Figure 2 As shown. The sacrificial gate structure 200 may have a linear shape that extends in one direction while intersecting with the active structure. The sacrificial gate structure 200 may extend, for example, in the Y direction. Each sacrificial gate structure 200 may include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 stacked sequentially, as well as a mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask patterning layer 206.

[0113] The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, while the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0114] The gate spacer layer 164 may be formed on both sidewalls of the sacrificial gate structure 200. The gate spacer layer 164 may be formed of a low-k material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON or SiOCN.

[0115] refer to Figure 9D The active structure AS exposed from the sacrificial gate structure 200 can be partially removed to form the recessed region RC.

[0116] Using the sacrificial gate structure 200 and the gate spacer layer 164 as a mask, a portion of the exposed sacrificial layer 120 and portions of the first to fourth channel layers 141, 142, 143, and 144 can be removed to form a recessed region RC. Thus, the first to fourth channel layers 141, 142, 143, and 144 can form a channel structure 140 having a defined length in the X direction.

[0117] refer to Figure 9E A photoresist pattern PR can be formed between the sacrificial gate structures 200 and on a portion of the upper surface of the sacrificial gate structure 200.

[0118] Photoresist can be applied to the sacrificial gate structure 200 and the active region 105, and a photoresist pattern PR can be formed using photolithography. The photoresist pattern PR can be formed in a recessed region RC, where a second source / drain region 130b is formed via a subsequent process. The photoresist pattern PR can prevent the sacrificial pad layer SL from depositing on one side surface of the sacrificial layer 120 by covering it. The photoresist pattern PR can also be formed on the upper surface of the sacrificial gate structure 200.

[0119] exist Figure 9E In the image, the photoresist pattern PR is shown as a single layer, but this may be for illustrative purposes only and is not limited to this.

[0120] The photoresist pattern PR may include an antireflective layer to prevent light reflection caused by the underlying film during the photolithography process. This antireflective layer may include, for example, a bottom antireflective coating (BARC) or a developable bottom antireflective coating (dBARC), but is not limited to these.

[0121] refer to Figure 9F It can deposit a conformally covering photoresist pattern PR, sacrificial gate structure 200 and active region 105 sacrificial pad layer SL.

[0122] Specifically, the sacrificial liner layer SL can be deposited on a portion of the upper and side surfaces of the photoresist pattern PR, a portion of the upper and side surfaces of the sacrificial gate structure 200, and a portion of the active region 105.

[0123] The sacrificial pad layer SL may be formed of a material having etch selectivity relative to each of the first to fourth channel layers 141, 142, 143, and 144. The first to fourth channel layers 141, 142, 143, and 144 may include materials different from those of the sacrificial pad layer SL. The sacrificial pad layer SL and the first to fourth channel layers 141, 142, 143, and 144 may include a semiconductor material comprising at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial pad layer SL may include silicon germanium (SiGe), while the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0124] The thickness of the sacrificial liner layer SL to be deposited can be 150b for each second internal spacer layer formed by subsequent processes. Figure 2 The thickness of ) and each first internal spacer layer 150a ( Figure 2 The difference between the thicknesses of the deposited sacrificial liner layer SL. When the thickness of the deposited sacrificial liner layer SL is relatively thick, each second inner spacer layer 150b ( Figure 2 The thickness of ) and each first internal spacer layer 150a ( Figure 2 The difference in thickness between the two layers will increase. When the thickness of the deposited sacrificial liner layer SL is relatively thin, the thickness of each second inner spacer layer 150b ( Figure 2 The thickness of ) and each first internal spacer layer 150a ( Figure 2 The difference in thickness between the two layers will become smaller. By controlling the thickness of the deposited sacrificial liner layer SL, the thickness of the second internal spacer layer 150b can be controlled. Figure 2 The thickness of ) and the first internal spacer layer 150a ( Figure 2 The difference between the thicknesses of ).

[0125] Similarly, the thickness of the deposited sacrificial liner layer SL can be 150 cm for each third internal spacer layer formed by subsequent processes. Figure 2 The thickness of each fourth internal spacer layer is 150d ( Figure 2 The difference between the thicknesses of the three inner spacer layers (SL) can be controlled by controlling the thickness of the deposited sacrificial liner layer SL. Figure 2 The thickness of each fourth internal spacer layer is 150d ( Figure 2 The difference between the thicknesses of ).

[0126] When the thickness of the deposited sacrificial liner layer SL is equal to the thickness of each sacrificial layer 120 after a predetermined depth has been removed from the side surface in the X direction by a subsequent process, spacers may not be formed on one side, such as... Figure 7 The semiconductor device 100E is shown.

[0127] refer to Figure 9G Non-selective etching can be used to remove a portion of the upper surface of the sacrificial pad layer SL, thereby exposing the upper surface of the photoresist pattern PR.

[0128] Specifically, the portions of the sacrificial pad layer SL deposited on the photoresist pattern PR and extending in the X direction, the portions of the sacrificial pad layer SL deposited on the sacrificial gate structure 200 and extending in the X direction, and the portions of the sacrificial pad layer SL located on the active region 105 can be removed by etching. The portions of the sacrificial pad layer SL deposited on the side surface of the photoresist pattern PR and extending in the Z direction, and the portions of the sacrificial pad layer SL deposited on one side surface of the sacrificial gate structure 200 and extending in the Z direction, can be left unremoved. Therefore, the upper surface of the photoresist pattern PR can be exposed.

[0129] exist Figure 9G The etching used can be, for example, anisotropic etching, but is not limited to this.

[0130] refer to Figure 9H It can remove exposed photoresist patterns (PR).

[0131] To remove exposed photoresist patterns (PR), ashing and stripping processes can be used, but are not limited to these.

[0132] The exposed photoresist pattern PR can be removed to re-form the recessed region RC. A second source / drain region 130b can then be formed in the re-formed recessed region RC through subsequent processes. Figure 2 The exposed photoresist pattern PR can be removed to expose a side surface of the sacrificial layer 120 that is not covered by the sacrificial pad layer SL.

[0133] refer to Figure 9I A portion of the sacrificial layer 120 and the sacrificial liner layer SL can be removed by a wet etching process.

[0134] The sacrificial pad layer SL can be selectively etched relative to the channel structure 140, for example, using a wet etching process. The sacrificial layer 120 can be selectively etched relative to the channel structure 140, for example, using a wet etching process, and can be removed from the side surface in the X direction to a predetermined depth. The portion of the side surface of the sacrificial layer 120 covered by the sacrificial pad layer SL can be etched relatively less than the portion of the side surface of the sacrificial layer 120 not covered by the sacrificial pad layer SL. A first recessed region RC1 represents the area where the sacrificial layer 120 on the side not covered by the sacrificial pad layer SL can be removed, while a second recessed region RC2 represents the area where the sacrificial layer 120 on the side to which the sacrificial pad layer SL is applied can be removed. The first recessed region RC1 can have a relatively larger volume removed by the etching process compared to the second recessed region RC2. In this case, the difference in the X-direction width of the etched areas of the two opposing side surfaces of the sacrificial layer 120 can be equal to the thickness of the sacrificial pad layer SL.

[0135] The side surface of the sacrificial layer 120 can be made perpendicular to the upper surface of the substrate 101 by lateral etching as described above, but is not limited thereto, and the degree of rounding can vary depending on the degree of etching. In other embodiments, the sacrificial layer 120 can have an inwardly recessed side surface by lateral etching as described above.

[0136] refer to Figure 9J An insulating material layer IS can be deposited to conformally cover a portion of the sacrificial gate structure 200 and a portion of the active region 105.

[0137] An insulating material layer IS can be deposited to fill the areas where the sacrificial layer 120 is partially removed. The insulating material layer IS may include at least one of oxide, nitride, or oxynitride, and may be formed, for example, as a low-k film. In some embodiments, the insulating material layer IS may include silicon nitride or silicon oxynitride.

[0138] refer to Figure 9K A portion of the insulating material layer IS can be removed to form the internal spacer layer 150.

[0139] The insulating material layer IS can be removed to a predetermined thickness by, for example, an etching process. Therefore, the side surfaces of the inner spacer layer 150 can be etched to have an inwardly recessed shape. In other embodiments, the outer surfaces of the inner spacer layer 150 can be etched to have a shape perpendicular to the upper surface of the substrate 101.

[0140] Next, refer to Figure 2Source / drain regions 130 can be formed in the recessed region RC. Subsequently, an interlayer insulating layer 170 can be formed, and the sacrificial gate structure 200 and sacrificial layer 120 can be removed. Then, a gate structure 160 can be formed. An interlayer insulating layer 170 can also be formed on the gate structure 160. Then, a contact plug 180 can be formed. The interlayer insulating layer 170 can be patterned to form contact holes exposing the source / drain regions 130. Next, conductive material can be filled into the contact holes to form the contact plug 180. Specifically, a material forming a barrier layer can be deposited in the contact holes, and then a silicide process can be performed to form a metal-semiconductor compound layer, such as a silicide layer, at the lower end. Next, conductive material can be deposited to fill the contact holes, thereby forming the contact plug 180. Thus, a device can be manufactured... Figures 1 to 3 Semiconductor device 100A.

[0141] According to embodiments of this disclosure, the gate-drain capacitance (Cgd) can be effectively reduced by forming a thicker internal spacer layer on the drain side than on the source side to increase the separation distance between the gate and the drain.

[0142] According to some embodiments of this disclosure, by forming a thicker internal spacer layer on the drain side than on the source side to increase the separation distance between the gate and drain, leakage current caused by the GIDL phenomenon can be prevented or minimized. Therefore, the reliability of the transistor can be increased, and its performance can be improved.

[0143] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as features that may be specific to particular embodiments of the invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from that combination in certain circumstances, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0144] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, the substrate including an active region extending in a first direction; A plurality of gate structures, the plurality of gate structures extending on the substrate along a second direction and intersecting the active region, and including a first gate structure and a second gate structure spaced apart from each other in the first direction; A channel structure comprising a first channel structure surrounded by a first gate structure and a second channel structure surrounded by a second gate structure, each of the first channel structure and the second channel structure comprising a plurality of channel layers located on the active region and spaced apart from each other in a third direction perpendicular to the upper surface of the substrate. A plurality of source / drain regions are located in the region where the active region is recessed and on a first side of each of the plurality of gate structures, wherein the plurality of source / drain regions include: a first source / drain region connected to the first channel structure; a second source / drain region connected to both the first channel structure and the second channel structure; and a third source / drain region connected to the second channel structure. A first internal spacer layer is located between the first gate structure and the first source / drain region, wherein the first internal spacer layer is located on the active region below each of the plurality of channel layers in the first channel structure. A second internal spacer layer is located between the first gate structure and the second source / drain region, wherein the second internal spacer layer is located on the active region below each of the plurality of channel layers in the first channel structure. A third internal spacer layer is located between the second gate structure and the second source / drain region, wherein the third internal spacer layer is situated below each of the plurality of channel layers in the second channel structure on the active region; and A fourth internal spacer layer is located between the second gate structure and the third source / drain region, wherein the fourth internal spacer layer is situated on the active region below each of the plurality of channel layers in the second channel structure. Wherein, the center thickness of each second inner spacer layer in the first direction is greater than the center thickness of each first inner spacer layer in the first direction, and The center thickness of each of the third inner spacer layers in the first direction is greater than the center thickness of each of the fourth inner spacer layers in the first direction.

2. The semiconductor device according to claim 1, wherein, The center thickness of each of the second inner spacer layers is equal to the center thickness of each of the third inner spacer layers.

3. The semiconductor device according to claim 1, wherein, The center thickness of each of the first inner spacer layers is equal to the center thickness of each of the fourth inner spacer layers.

4. The semiconductor device according to claim 1, wherein, The distance in the first direction between the inner surface of the first internal spacer layer in contact with the first gate structure and the second source / drain region is equal to the distance in the first direction between the inner surface of the fourth internal spacer layer in contact with the second gate structure and the second source / drain region.

5. The semiconductor device according to claim 1, wherein, The center thickness of each second inner spacer layer is in the range of about 1.1 times to about 5 times the center thickness of each first inner spacer layer.

6. The semiconductor device according to claim 1, wherein, The center thickness of each of the third inner spacer layers is in the range of about 1.1 times to about 5 times the center thickness of each of the fourth inner spacer layers.

7. The semiconductor device according to claim 1, wherein, The gap between the first gate structure and the second gate structure is about 20 nm to about 25 nm.

8. The semiconductor device according to claim 1, wherein, The center thickness of each of the first inner spacer layers and the center thickness of each of the fourth inner spacer layers are approximately 1 nm to approximately 5 nm.

9. A semiconductor device, the semiconductor device comprising: First source / drain region and second source / drain region; Multiple channel layers are stacked in a vertical direction and spaced apart from each other, and connected to the first source / drain region and the second source / drain region in a first direction intersecting the vertical direction; A gate electrode that surrounds each of the plurality of channel layers in a second direction intersecting the first direction and the perpendicular direction; A gate dielectric layer, the gate dielectric layer being between the gate electrode and the plurality of channel layers and between the gate electrode and the first source / drain region and the second source / drain region; A first internal spacer layer is located between the gate dielectric layer and the first source / drain region. as well as A second internal spacer layer is provided between the gate dielectric layer and the second source / drain region. The minimum thickness of each second inner spacer layer in the first direction is greater than the minimum thickness of each first inner spacer layer in the first direction.

10. The semiconductor device according to claim 9, wherein, The minimum thickness of each of the second internal spacer layers in the first direction is about 5 nm to about 9 nm.

11. The semiconductor device according to claim 9, wherein, The minimum thickness of each of the first internal spacer layers in the first direction is about 1 nm to about 5 nm.

12. The semiconductor device according to claim 9, wherein, The gap between the first source / drain region and the second source / drain region is approximately 10 nm to approximately 15 nm.

13. The semiconductor device according to claim 9, wherein, The first internal spacer layer and the second internal spacer layer comprise silicon nitride or silicon oxynitride.

14. The semiconductor device according to claim 9, wherein, The outer surface of the first internal spacer layer that contacts the first source / drain region is concave in the inward direction toward the gate electrode, and The outer surface of the second inner spacer layer that contacts the second source / drain region is concave in the inward direction toward the gate electrode.

15. The semiconductor device according to claim 9, wherein, The outer surface of the first internal spacer layer that contacts the first source / drain region is coplanar with the side surfaces of the plurality of channel layers, and The outer surface of the second internal spacer layer that contacts the second source / drain region is coplanar with the side surfaces of the plurality of channel layers.

16. The semiconductor device according to claim 9, wherein, The inner surface of the first inner spacer layer that contacts the gate dielectric layer is concave in the inward direction toward the gate electrode, and The inner surface of the second inner spacer layer that contacts the gate dielectric layer is concave in the inward direction toward the gate electrode.

17. The semiconductor device according to claim 9, wherein, The first gap between the inner surface of the first internal spacer layer contacting the gate dielectric layer and the first source / drain region is smaller than the second gap between the inner surface of the second internal spacer layer contacting the gate dielectric layer and the second source / drain region.

18. A semiconductor device, the semiconductor device comprising: First source / drain region and second source / drain region; Multiple channel layers are stacked in a vertical direction and spaced apart from each other, and connected to the first source / drain region and the second source / drain region in a first direction intersecting the vertical direction; A gate electrode that surrounds each of the plurality of channel layers in a second direction intersecting the first direction and the perpendicular direction; A gate dielectric layer, the gate dielectric layer being between the gate electrode and the plurality of channel layers and between the gate electrode and the first source / drain region and the second source / drain region; A first internal spacer layer is located between the gate dielectric layer and the first source / drain region. as well as A second internal spacer layer is provided between the gate dielectric layer and the second source / drain region. The thickness of the second internal spacer layer in the first direction is approximately 1.1 to approximately 5 times the thickness of the first internal spacer layer in the first direction.

19. The semiconductor device according to claim 18, wherein, The sum of the thickness of the second internal spacer layer and the thickness of the first internal spacer layer is in the range of about 1% to about 50% of the gap between the first source / drain region and the second source / drain region.

20. The semiconductor device according to claim 18, wherein, Each of the second internal spacer layers has a thickness of about 5 nm to about 9 nm in the first direction.

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