Trench region interdigitated fingers for reduced spacing of complementary transistors and cfet architecture

Abstract

This disclosure relates to a forked slot region and CFET architecture for complementary transistors with reduced spacing. Integrated circuit (IC) devices have forked transistors. IC devices may include adjacent forked transistors having different gate stacks separated by dielectric walls. The dielectric walls may resemble adjacent forked spines and be centered between adjacent forked spines, which are located on and between nanoribbon channel stacks. The gate stacks may include: an inner gate dielectric layer located on the nanoribbon channel; and an outer gate dielectric layer located both on the inner gate dielectric layer and on the dielectric walls of the separated gate dielectric stacks. Either or both of the inner and outer gate dielectric layers of adjacent transistors may have different thicknesses or material compositions. By dividing the nanoribbon channel into separate gate trench regions, the dielectric walls between the gate electrodes and the gate dielectric stacks enable independent processing of the transistor gates.

Description

Background Technology

[0001] In the conventional processing of field-effect transistors (FETs), the gate electrodes and gate insulators of millions of transistors are processed simultaneously with matched characteristics (such as gate dielectric thickness). Even limited modifications to the gate processing (e.g., for complementary transistors or other transistors with differences in transistor processing) can cause surface defects and excessive consumption of channel material. For example, repeated deposition and removal of the masking layer can consume and / or damage the channel material or gate dielectric. For transistors with limited access to the channel material, such as transistors with reduced spacing between devices or only single-sided access (e.g., in forksheet FETs), this deposition and removal can be even more difficult or problematic.

[0002] New technologies, structures, and materials are needed to improve the performance and reliability of integrated circuit (IC) devices, for example by providing multiple transistor gate variants whose characteristics (such as leakage or switching speed) can be matched to specific applications. Attached Figure Description

[0003] In the accompanying drawings, the materials described herein are illustrated by way of example and not limitation. For simplicity and clarity, the elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, reference numerals have been repeated in the drawings where deemed appropriate to indicate corresponding or similar elements, for example, having the same or similar function. This disclosure will be described with further specificity and detail using the accompanying drawings: Figure 1A , 1B The figures 1C are cross-sectional views and plan views of an integrated circuit (IC) device according to some embodiments, the IC device having a transistor structure having different gate stacks in adjacent gate electrodes separated by narrow dielectric walls. Figure 2 The figure shows a cross-sectional view of an IC device according to some embodiments, in a complementary field-effect transistor (CFET) structure between the fork spine and the dielectric wall, having a lower nanoribbon stack located below the upper nanoribbon stack; Figure 3 This is a flowchart of a method for forming different gate stacks in adjacent transistors according to some embodiments; Figure 4A , 4BThe figures 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K and 4L are cross-sectional views of workpieces or devices at various manufacturing stages according to some embodiments. The workpieces or devices have transistor structures with different gate stacks in adjacent gate electrodes separated by narrow dielectric walls. Figure 5 The diagram illustrates an exemplary data server machine that employs an IC device having dielectric walls separating gate electrodes with different gate dielectric stacks; and Figure 6 This is a block diagram of an exemplary computing device according to some embodiments. Detailed Implementation

[0004] In the following detailed description, reference is made to the accompanying drawings, which illustrate specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. While the various embodiments differ, they are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in conjunction with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.

[0005] The reference to "an embodiment" or "an embodiment" in this specification means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one implementation included in this description. Therefore, the use of the phrase "an embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be carried out in a limiting sense, and the scope of the subject matter is defined only by the appended claims as properly interpreted and by the full scope of their equivalents.

[0006] As used herein, the terms “above,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer that is “above another layer,” “on another layer,” or “joined to another layer” may be in direct contact with said other layer, or may have one or more intervening layers. A layer that is “between layers” may be in direct contact with said layer, or may have one or more intervening layers.

[0007] The terms “coupling” and “connection”, and their derivatives, are used herein to describe structural relationships between components. These terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupling” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that the two or more elements cooperate or interact with each other (e.g., as in causal, electrical, functional, etc.).

[0008] The terms "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a intended function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0009] The vertical orientation is along the z-direction, and the descriptions of "top," "bottom," "above," and "below" refer to relative positions in the z-axis with their usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figures.

[0010] The terms “substantially,” “near,” “approximately,” “around,” and “about” generally refer to within + / - 10% of the target value (unless explicitly specified). Unless otherwise specified in a particular context, the term “predominantly” means more than 50% or more than half. For example, a composition in which the first component is predominant means that more than half of the composition is the first component. The term “primarily” means the majority or the largest portion. For example, a composition in which the first component is predominantly present means a composition having more of the first component than any other component. A composition in which the first and second components are predominantly present means a composition having more of the first and second components than any other component.

[0011] Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates different instances of similar objects being referred to, and is not intended to imply that the objects being described must be in a given order, whether in time, space, hierarchy, or any other manner.

[0012] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0013] Views labeled "cross-sectional view," "profile view," and "plan view" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, cross-sectional and profile views are obtained along the x–z and y–z planes, and plan views are obtained along the x–y plane. Typically, a profile view in the x–z plane is a section view. Where appropriate, the figures are labeled with axes to indicate their orientation.

[0014] Technologies, structures, and materials are disclosed to improve integrated circuit (IC) devices with forked metal-oxide-semiconductor (MOS) field-effect transistors (FETs).

[0015] Dielectric walls can separate adjacent nanoribbon stacks into individual processing chambers (“tubs”), thereby enabling independent processing of adjacent gate dielectric stacks within a forked FET. A forked FET may have so-called spines or ridges (e.g., dielectric walls) that separate pairs of nanoribbon stacks within the forked FET. During processing, dielectric walls can be formed between adjacent forked FETs (e.g., centered between two adjacent forked spines) to isolate the nanoribbon stacks within the adjacent forked FETs. Instead of parallel nanoribbon stacks necessarily undergoing the same processing, each nanoribbon stack may have its own gate tub and receive specifically tailored processing. Each gate tub may contain a single nanoribbon stack between the forked spines and a dielectric wall between the forked FETs. Dielectric walls can be formed by etching through a dummy gate and by filling the etched opening with a dielectric, thereby creating isolation between adjacent forked FETs and nanoribbon stacks. By depositing a hard mask layer on the dielectric walls and nanoribbon stack, the openings can be patterned, and through the openings, the dummy gate material can be removed, thereby clearing the selected trench region between the dielectric walls and exposing the nanoribbons in the selected trench region for processing.

[0016] Mask openings can be fabricated to clear multiple sets of trench regions selected for a specific processing operation. For example, all (or at least many) of the gate trench regions of a nanoribbon stack to have a certain gate characteristic (e.g., to receive a certain gate dielectric material or thickness) can be cleared together and then simultaneously received for further processing. After the specific processing operation is completed, the hard mask layer can be removed, a new hard mask layer can be deposited, and new openings can be patterned to clear a new set of trench regions for the next processing operation (e.g., forming a second gate dielectric material or thickness). After gate formation, dielectric walls can be retained as electrical isolation between adjacent metal gate electrodes.

[0017] Deploying dielectric walls between adjacent forked FETs (and clearing gate trench regions, for example, through selective isotropic etching) can offer a beneficial contrast to conventional alternatives. Typically, a hard mask may cover all nanoribbon stacks before a harsh isotropic etching process removes the hard mask material from above the selected nanoribbon stacks to be processed. Once exposed, this etching can damage the nanoribbons (e.g., the upper surface of the nanoribbons), and hard mask removal can be unsatisfactory in several ways, compromising subsequent processing of the nanoribbons. For example, edge placement errors can cause the hard mask edges between adjacent nanoribbon stacks to be processed or to remain covered by the hard mask material too close. This error can result in insufficient processing gaps or inadequate protection of the masked nanoribbons. In addition to edge placement errors, patterned hard mask edges may lack vertical fidelity, for example, having sloping, curved, or rough sidewalls, leading to gap variations of several nanometers.

[0018] Dielectric walls and the resulting gate trench region processing can be particularly beneficial for fork-chip FETs and complementary FETs (CFETs). The conventional negative impact of hard mask patterning errors described may be more severe for fork-chip FETs, which have reduced access to the channel material due to the fork spine blocking access from one side, and fork-chip FETs may have wider nanoribbons, both of which exacerbate the wet etching bias problem of removing the mask or dummy material between nanoribbons. For example, the vertical pattern fidelity problem may also affect CFETs more severely due to the additional processing required for complementary stacks stacked vertically on top of each other and due to the higher aspect ratio of the higher double stacks. Dielectric walls between nanoribbon stacks provide means to overcome these problems in fork-chip FETs and complementary FETs and to process adjacent nanoribbon stacks independently.

[0019] Custom processing implemented via the gate trench region can be used to provide: multiple gate variants, for example, with different threshold voltages V. T And the corresponding leakage and switching speeds. For each of the multiple complementary conductivity types, the IC device can have multiple gate variants. For example, the IC device can have four or more threshold voltages V in an NMOS FET. T The distribution, and has four or more threshold voltages V in the PMOS FET. TThe distribution of the gate dielectric layers is as follows. In many embodiments, adjacent transistors have gate dielectric layers of different thicknesses directly on the channel nanoribbon. In many embodiments, adjacent transistors have gate dielectric layers of different thicknesses (e.g., high permittivity or "high-k" layers) directly on the nanoribbon. For example, in adjacent transistors, the gate dielectric layer thickness may differ by 2 angstroms (or up to 5 angstroms). In many embodiments, adjacent transistors have gate dielectric layers with different high-k materials. In some embodiments, adjacent transistors have gate dielectric layers with different material compositions (e.g., elemental ratios) of the same high-k material.

[0020] Figure 1A , 1B The figures 1C and 1C illustrate cross-sectional views and plan views of an IC device 100 according to some embodiments. The IC device 100 has transistor structures 101A, 101B, 101C, and 101D, each transistor structure having different gate stacks 125A, 125B, 125C, and 125D, the gate stacks being separated by forked spines 130 and narrow dielectric walls 140. Transistor structures 101A, 101B, 101C, and 101D are forked FET structures 101, having channel regions within the stacks 121A, 121B, 121C, and 121D of nanoribbon 120. Figure 1A The y–z observation plane is shown, passing laterally through the nanoribbon 120 and transistor structure 101 in multiple adjacent stacks 121A, 121B, 121C, 121D. Figure 1A Multiple (e.g., magnified) views 102, 103 including exemplary gate stacks 125 (e.g., gate stacks 125A, 125B) on nanoribbon 120. Figure 1B The figure shows the x–z observation plane along the longitudinal direction through the nanoribbons 120 and transistor structure 101 in multiple aligned stacks 121. Figure 1B A (e.g., magnified) view 104 including the gate stack 125 adjacent to the nanoribbon 120. Figure 1C The y-z cross-sectional view 105 and the x-y plan view 106 are shown, both of which pass through a dielectric wall 140, which is located between and in contact with the source or drain bodies 110 in transistor structures 101A and 101B.

[0021] Figure 1ADevice 100 is shown, comprising gate stacks 125A, 125B, 125C, and 125D in transistor structures 101A, 101B, 101C, and 101D, the gate stacks being separated by a forked spine 130 and an isolation wall 140. The isolation wall 140 is a dielectric structure on each of the stacks 125A, 125B, 125C, and 125D (e.g., in contact with each of the stacks 125A, 125B, 125C, and 125D). The spine 130 is also a dielectric wall providing isolation and is located on each of the stacks 125A, 125B, 125C, and 125D (e.g., in contact with each of the stacks 125A, 125B, 125C, and 125D). For example, a wall 140 separating gate stacks 125A and 125B and located between electrodes 126 extends vertically from above the top (e.g., upper surface) of electrodes 126 and below the bottom (e.g., lower surface) of electrodes 126. A spine 130 also separates gate stacks 125 (e.g., stacks 125D, 125A and stacks 125B, 125C) and is located between electrodes 126, extending vertically from above the top (e.g., upper surface) of electrodes 126 and below the bottom (e.g., lower surface) of electrodes 126. The dielectric wall 140 (and the spine 130) provide isolation (e.g., electrical isolation) between the gate electrodes 126 of structures 101A, 101B, 101C, and 101D.

[0022] The thin wall 140 enables tight packing of transistor structures 101A, 101B, 101C, 101D and gate electrode 126 in device 100. For example, the forked spine 130 enables tight packing of transistor structures 101 and gate electrode 126 by providing a minimum distance (e.g., width W3) between stacks 121 of nanoribbons 120 located directly on (e.g., in contact with) spine 130. The dielectric wall 140 and spine 130 also enable independent processing of gate stacks 125A, 125B, 125C, 125D in structures 101A, 101B, 101C, 101D (e.g., as described elsewhere herein, such as in Figure 3 As described in method 300), this allows the stack 125 to have different insulating layers 122, 123, etc., for example, different thicknesses, materials, etc. The gate stack 125 is a gate structure, each gate structure including a gate electrode 126 and a gate dielectric stack 124 (e.g., stacks 124A, 124B, 124C, or 124D) on the electrode 126. Each wall 140 is located between a pair of gate electrodes 126, and each electrode 126 is located between the dielectric wall 140 and the spine 130.

[0023] Transistor structures 101A, 101B, 101C, and 101D may have the same or complementary conductivity types (e.g., PMOS and / or NMOS structures 101A, 101B, 101C, and 101D). For example, transistor structure 101A may be a p-type structure 101A, and transistor structure 101B may be an n-type structure 101B, and vice versa. In some embodiments, all transistor structures 101A, 101B, 101C, and 101D have the same conductivity type (e.g., all PMOS structures 101A, 101B, 101C, and 101D, or all NMOS structures 101A, 101B, 101C, and 101D). In many embodiments, transistor structures 101 on the same spine 130 (e.g., structures 101A, 101D, and structures 101B, 101C) have complementary conductivity types. In many embodiments, adjacent structures 101 separated by wall 140 (e.g., structures 101A, 101B) have the same conductivity type. For example, in many embodiments, adjacent transistor structures 101A, 101B have the same conductivity type (e.g., both are NMOS structures 101), but have different threshold voltages V due to differences in the gate stacks 125A, 125B (e.g., composition or thickness). T .

[0024] Transistor structure 101A includes a stack 121A of nanoribbons 120 extending through gate stack 125A. Transistor structure 101B includes a stack 121B of nanoribbons 120 extending through gate stack 125B. Transistor structure 101C includes a stack 121C of nanoribbons 120 extending through gate stack 125C. Transistor structure 101D includes a stack 121D of nanoribbons 120 extending through gate stack 125D. Like... Figure 1A As in the exemplary embodiments, some of the gate stacks 125A, 125B, 125C, and 125D may have different stack compositions. The differences between the compositions of stacks 125A, 125B, 125C, and 125D may be that stacks 125A, 125B, 125C, and 125D include: different amounts of layers (e.g., more or different layers); similar layers, but with different materials, etc. For example, the difference between the first and second compositions of gate stacks 125A and 125B may be that only one of the stacks 125A and 125B has a high-k dielectric layer 123 on the transition layer 122.

[0025] Some gate stacks (e.g., dielectric layers 123) in gate stacks 125 are illustrated differently in different transistor structures 101 to highlight potential differences between stacks 125, but any stack in stacks 125 may be the same as or different from other (e.g., adjacent) stacks 125. Enlarged views 102, 103 show gate stacks 125A, 125B in more detail, but each of stacks 125A, 125B, 125C, 125D may have the same or different composition as any other stack 125. As shown in view 102, the first gate stack 125A includes a first dielectric stack 124A located on a first nanoribbon 120, and the gate stack 125A includes one or more first metal layers 127 located on the dielectric stack 124A. View 102 shows an embodiment having multiple layers 127 located on stack 124A. The first dielectric stack 124A includes a dielectric layer 122A on the first nanoribbon 120 and an insulating layer 123A on the dielectric layer 122A. The first gate stack 125A may also include a metal (e.g., filler) layer 128 on the inner liner layer 127.

[0026] As shown in View 103, the second gate stack 125B includes a second dielectric stack 124B located on the second nanoribbon 120, and the gate stack 125B includes one or more second metal layers 127 located on the dielectric stack 124B. The second dielectric stack 124B includes a dielectric layer 122B located on the second nanoribbon 120 and an insulating layer 123B located on the dielectric layer 122B. The second gate stack 125B may also include a metal (e.g., filler) layer 128 located on the liner layer 127.

[0027] The dielectric layer 122 (e.g., layers 122A, 122B, 122C, 122D) may comprise any suitable material(s) and may have any suitable thickness(s). Layers 122A, 122B, 122C, 122D are located on the nanoribbon 120 in the transistor structures 101A, 101B, 101C, 101D, respectively, and may provide protection for the nanoribbon 120, for example, during processing. For example, layer 122 may be a passivation layer 122 of a native oxide of the material in the nanoribbon 120. In many embodiments, the dielectric layer 122 comprises silicon and oxygen. Layer 122 may be a transition layer 122 between the nanoribbon 120 and other layers above layer 122 (such as layer 123, etc.). In some embodiments, the dielectric layers 122A, 122B, etc., have thicknesses T1, T2 smaller than the thicknesses of the other layers above layers 122A, 122B. In many embodiments, some dielectric layers 122 (e.g., layer 122A) have a thickness T1 that is larger (or smaller) than the thickness T2 of other dielectric layers 122 (e.g., layer 122B). For example, layer 122A may have a thickness T1 of 1 nm or less, and layer 122B may have a thickness T2 of 1.3 nm or more. In some embodiments, one of layers 122A, 122B, 122C, 122D includes a material not included in another layer of layers 122A, 122B, 122C, 122D. Layer 122 may include other suitable materials. Different thicknesses T1 or T2 (or different material compositions) of layers 122A, 122B, 122C, 122D can provide different threshold voltages V for transistor structures 101A, 101B, 101C, 101D. T Different thicknesses T1 or T2 of layers 122A, 122B, 122C, and 122D can provide different thicknesses of nanoribbon 120 in transistor structures 101A, 101B, 101C, and 101D.

[0028] Insulating layers 123 (e.g., layers 123A, 123B, 123C, 123D) may comprise any suitable material(s) and may have any suitable thickness(s). Layers 123A, 123B, 123C, 123D are located on transition layers 122A, 122B, 122C, 122D in transistor structures 101A, 101B, 101C, 101D, respectively. Layer 123 is located on the corresponding layer 122 and on each nanoribbon 120. Layer 123 is located between each pair of vertically adjacent nanoribbons 120 within stack 121. Layer 123 is located on the wall 140 in each stack 125 and on the spine 130 between each pair of nanoribbons 120 within stack 121. In many embodiments, insulating layers 123 have thicknesses T3 and T4 that are greater than the thicknesses T1 and T2 of layers 122 on nanoribbons 120. Insulating layer 123 may be a high-k dielectric layer 123. For example, layer 123 advantageously includes one or more high-k dielectric materials that, when deployed together with or in place of other materials, provide design flexibility and / or superior properties (such as electrical properties).

[0029] In transistor structures 101A, 101B, 101C, and 101D, layer 123 (e.g., high-k layers 123A, 123B, 123C, and 123D) allows for a larger transconductance g. m (For example, for the same voltage and the same thickness T3 or T4 on the gate electrode 126). The high-k layer 123 allows for a larger total thickness of the dielectric above the nanoribbon 120 (e.g., thickness T1 plus thickness T3 in stack 125A or thickness T2 plus thickness T4 in stack 125B), and thus enables the achievement of low leakage current in structure 101 (e.g., for the same voltage on the gate electrode 126 while maintaining the same transconductance g). m For example, for a lower voltage on the gate electrode 126 and the same thickness T3 or T4, the high-k layer 123 can achieve low leakage current in structure 101. In many embodiments, one or more insulating layers 123 (e.g., layer 123A) have a thickness T3 that is larger (or smaller) than the thickness T4 of other insulating layers 123 (e.g., layer 123B). For example, layer 123A may have a thickness T3 of 1.3 nm or less, and layer 123B may have a thickness T4 of 1.8 nm or more. Different thicknesses T3 or T4 (or different material compositions) of layers 123A, 123B, 123C, and 123D can provide different threshold voltages V for transistor structures 101A, 101B, 101C, and 101D. T .

[0030] Insulating layer 123 may comprise any suitable material(s). In many embodiments, insulating layer 123 comprises hafnium and oxygen. In some embodiments, insulating layer 123 comprises zirconium and oxygen. In some embodiments, insulating layer 123 comprises hafnium, zirconium, and oxygen. In some embodiments, insulating layers 123A, 123B, 123C, and 123D have different material compositions. In some embodiments, for example, insulating layer 123A (or layers 123B, 123C, and 123D) comprises hafnium and zirconium, and insulating layer 123B (or layers 123A, 123C, and 123D) comprises neither hafnium nor zirconium, or comprises only one of hafnium and zirconium (e.g., comprising hafnium but not zirconium, or comprising zirconium but not hafnium). In some embodiments, more than one of layers 123A, 123B, 123C, and 123D comprises hafnium, zirconium, and oxygen (HZO, e.g., in hafnium zirconate or hafnium zirconium oxide), but in different elemental ratios. The material composition of one or more layers 123 (e.g., the hafnium to zirconium ratio) may be modified to increase the relative permittivity of layer(s)(s)(s)(s)(e.g., from approximately 1:1 to approximately 2:1 or greater). In some embodiments, a dopant (e.g., yttrium) is added to one or more layers 123(s) to increase the relative permittivity of layer(s)(s)(s)(e.g., by increasing the proportion of a higher permittivity dielectric phase in layer(s)(s)). Any layer 123 may comprise one or more of a variety of elements such as hafnium, zirconium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Layer 123 may comprise other suitable materials.

[0031] Any of the gate stacks 125A, 125B, 125C, and 125D may include a dipole dopant. In some embodiments, one of the gate stacks 125 includes a dipole dopant present in one or more of the other gate stacks 125 that is not present in the gate stack 125. In some embodiments, gate stacks 125A, 125B, etc., include the same dipole dopant, but the dipole dopant is present at a first height (e.g., the sum of thicknesses T1 and T3) relative to the nanoribbons 120 in one or more stacks 121 (e.g., stack 121A), the first height being greater than (or less than) a second height (e.g., the sum of thicknesses T2 and T4) relative to the nanoribbons 120 in one or more other stacks 121 (e.g., stack 121B). The same dipole dopant may be located within different layers 122 and 123 (or at different interfaces of layers 122 and 123) in different dielectric stacks 124A and 124B.

[0032] The gate electrode 126 (and gate stacks 125A, 125B) may include one or more metal layers 127, 128. The gate electrode 126, together with the dielectric stacks 124A, 124B, 124C, 124D, forms a gate structure for electrostatically controlling the conductivity of transistor structures 101A, 101B, 101C, 101D. For example, layers 127, 128 may be work function metal (WFM) layers 127, 128 to (e.g., independently) influence the threshold voltage V of transistor structures 101A, 101B, 101C, 101D. T Layer 127 may be a conformal liner layer 127 surrounding the nanoribbons 120 and the dielectric stack 124, for example, having: a first metal layer 127 on an insulating layer 123A surrounding each nanoribbon 120 in structure 101A; a second metal layer 127 on an insulating layer 123B surrounding each nanoribbon 120 in structure 101B; a third metal layer 127 on an insulating layer 123C surrounding each nanoribbon 120 in structure 101C; and a fourth metal layer 127 on an insulating layer 123D surrounding each nanoribbon 120 in structure 101D.

[0033] Transistor structure 101A and gate stack 125A may include one or more metal layers 127 located in corresponding electrodes 126. Transistor structure 101B and gate stack 125B may include one or more metal layers 127 located in corresponding electrodes 126. Transistor structure 101C and gate stack 125C may include one or more metal layers 127 located in corresponding electrodes 126. Transistor structure 101D and gate stack 125D may include one or more metal layers 127 located in corresponding electrodes 126. Each metal layer 127 is located between walls 140 and spines 130 within stack 125. Each metal layer 127 is located between vertically adjacent pairs of nanoribbons 120 within stack 121, and a dielectric layer 123 is located between each metal layer 127 and two nanoribbons 120 in each pair of nanoribbons 120 (e.g., upper nanoribbon 120 and lower nanoribbon 120). The corresponding dielectric layer 123 is located between each metal layer 127 and the corresponding dielectric wall 140, and between each metal layer 127 and the corresponding spine 130.

[0034] The inner liner 127 in structure 101 (e.g., structures 101A, 101B, etc.) may have different thicknesses T5, T6, etc. For example, the thickness T5 (or thickness T6) is greater than the thickness T6 (or thickness T5) and affects the threshold voltage V of transistor structure 101A (or structure 101B). TThis has a correspondingly greater impact. Layer 127 in structure 101 may have a different material composition. Filling layer 128 in structure 101 may have a different material composition. Layers 127 and 128 may comprise any suitable material(s), including nonmetals. In many embodiments, layer 127 comprises nitrogen (e.g., in a metal nitride) or carbon (e.g., in a metal carbide). In some such embodiments, layer 127 comprises nitrogen and titanium, molybdenum, or tantalum. In some embodiments, a first layer 127 on dielectric stack 124 comprises titanium and nitrogen, and a second layer 127 on the first layer 127 comprises nitrogen and tantalum or molybdenum. In some embodiments, layer 127 comprises titanium, aluminum, and carbon. In many embodiments, layer 128 comprises tungsten.

[0035] Wall 140 includes opposing first and second sidewalls 141, 142. The width W1 (or width W2) of dielectric wall 140 separates sidewalls 141, 142. Width W1 (or width W2) (respectively) separates gate stacks 125A, 125B, etc., in transistor structures 101A, 101B. Dielectric wall 140 (e.g., sidewalls 141, 142) may be nearly vertical. In many embodiments, dielectric wall 140 has only slightly different widths W1, W2 (e.g., in a tapered profile that narrows slightly upwards or downwards). For example, widths W1, W2 may be within 1 nm. Width W1 is defined as the width of wall 140 at the top of wall 140. Width W2 is defined as the width of wall 140 at the bottom of gate stack 125, for example, where wall 140 intersects substrate 199 at the bottom of stack 125 (e.g., in layer 123). In some embodiments (e.g., a planarized back side with transistor structure 101), the horizontal portion of layer 123 may be absent, and the wall 140 at the bottom of stack 125 intersects the substrate 199 at the vertical portion of layer 123.

[0036] The gate stack 125 on electrode 126 is separated by dielectric wall 140 and a minimum distance or width W2 (or width W1, etc.) between electrode 126 and stack 125. In many embodiments, dielectric wall 140 has a minimum width W2 (or width W1, etc.) of 12 nm or less between electrode 126 and stack 125, which enables a corresponding saving of sufficiently compact packaging and layout area for transistor structure 101. In some embodiments, dielectric wall 140 has a minimum width W2 (or width W1, etc.) of 10 nm or less between electrode 126 (and stack 125), which enables excellent packaging and layout area saving for transistor structure 101. This compact layout (small widths W1, W2, and) of structure 101 can be achieved by fine, high aspect ratio etching (e.g., etching through metal gate electrode 126 and etching between metal gate electrodes 126). In many embodiments, the widths W1 and W2 of the dielectric walls 140 are shorter than (e.g., less than) the width W3 of the dielectric spine 130. In many embodiments, the width W2 (or width W1) of the wall 140 is approximately equal to the distance D between the wall 140 and the stack 121 of the adjacent nanoribbons 120. A (or distance D) B ).

[0037] The tight packing of stack 121 and transistor structure 101 can also be characterized as a small distance D1 between adjacent stacks 121 (e.g., first and second stacks 121A, 121B of nanoribbons 120) on different spines 130. In many embodiments, the distance D1 is less than three times the maximum width W1 of the wall 140 (e.g., the wall 140 is centered between stacks 121 and has a width W1 relative to any stack). In many embodiments, the distance D1 is less than 36 nm.

[0038] The insulating wall 140 comprises any suitable material(s), such as a dielectric material. Advantageously, wall 140 comprises a low-k (low permittivity) dielectric material. Advantageously, wall 140 has etch selectivity with other adjacent structures. In many embodiments, wall 140 comprises silicon and nitrogen (e.g., in a silicon nitride). In some embodiments, wall 140 comprises silicon and oxygen (e.g., in a silicon oxide). In some embodiments, for example, in addition to silicon and oxygen, wall 140 also comprises carbon and / or nitrogen. In many embodiments, wall 140 has a composition similar to or the same as that of the dielectric spine 130.

[0039] The isolation wall 140 (in conjunction with the spine 130) enables independent processing of the gate stacks 125A, 125B, 125C, and 125D in structures 101A, 101B, 101C, and 101D (e.g., as at least in...). Figure 3As described in method 300), this allows for stacks 125 of various components (e.g., layers 122, 123, 127, etc. with different thicknesses T1, T2, T3, T4, T5, T6 and / or comprising different materials).

[0040] Most of the stack 125 of layers surrounding the nanoribbon 120 is also located on, or adjacent to, the sidewalls 141, 142 of the isolation walls 140 and the sidewalls 131, 132 of the dielectric spine 130. Insulating layer 123A is located on the sidewall 141 of the wall 140 and the sidewall 132 of the spine 130. Insulating layer 123B is located on the sidewall 142 of the wall 140 and the sidewall 131 of the spine 130. Insulating layer 123C is located on the sidewall 141 of the wall 140 and the sidewall 132 of the spine 130. Insulating layer 123D is located on the sidewall 142 of the wall 140 and the sidewall 131 of the spine 130. In transistor structures 101A and 101C, the metal layer 127 is located on the insulating layers 123A and 123C on the sidewalls 141 and 132 of the wall 140 and spine 130, respectively. In transistor structures 101B and 101D, the metal layer 127 is located on the insulating layers 123B and 123D on the sidewalls 142 and 131 of the wall 140 and spine 130, respectively. Note that, like Figure 1A As in the exemplary embodiment, the gate dielectric layer 122 on the nanoribbon 120 may not be present on the sidewalls 141, 142 of the isolation wall 140 and the sidewalls 131, 132 of the dielectric spine 130.

[0041] The nanoribbons 120 in stacks 121A, etc., may be the same as or different from the nanoribbons 120 in stacks 121B, 121C, 121D, etc. For example, the nanoribbons 120 in different stacks 121 may have the same or different materials, the same or different thicknesses, etc. The nanoribbons 120 may have any suitable width (and may be, for example, nanowire nanoribbons 120 or nanosheet nanoribbons 120). The nanoribbons 120 may have any suitable (one or more) (e.g., semiconductive) material. In many embodiments, the nanoribbons 120 comprise silicon. In some embodiments, at least some of the nanoribbons 120 comprise germanium.

[0042] The dielectric spine 130 comprises any suitable material(s), such as a dielectric material. Advantageously, the spine 130 comprises a low-k dielectric material. Advantageously, the spine 130 has etch selectivity with other adjacent structures. In many embodiments, the spine 130 comprises silicon and nitrogen (e.g., in a silicon nitride). In some embodiments, the spine 130 comprises silicon and oxygen (e.g., in a silicon oxide). In some embodiments, for example, in addition to silicon and oxygen, the spine 130 also comprises carbon and / or nitrogen. In many embodiments, the spine 130 has a composition similar to or the same as that of the dielectric wall 140.

[0043] Gate via 129 is a metallized structure, for example, coupling (e.g., electrically coupling) the gate electrode 126 to an interconnect network (not shown) above the transistor structure 101. Via 129 may comprise any suitable material(s), including nonmetals. Via 129 may comprise multiple metal layers, for example, an inner liner layer (e.g., a barrier layer or seed layer) surrounding a fill layer. Gate via 129 passes through a dielectric layer 149 above the transistor structure 101. Dielectric layer 149 may have any suitable material, such as a low-k dielectric material.

[0044] Substrate 199 may comprise any suitable one or more materials. Substrate 199 may be an IC substrate, such as an IC die or wafer. In some examples, the substrate may comprise monocrystalline silicon (including silicon-on-insulator (SOI)), polycrystalline silicon, germanium, silicon-germanium, III–V alloy materials (e.g., gallium arsenide), silicon carbide (e.g., SiC), sapphire (e.g., Al2O3), or any combination thereof. Substrate 199 may also comprise semiconductor materials, metals, dielectrics, dopants, and other materials common in semiconductor substrates. Substrate 199 may specifically refer to a base material (e.g., a thick semiconductor material substrate or layer) on which other materials (such as metals and dielectrics) are built. In some cases, substrate 199 may refer to a base material layer and any layers built on top of the substrate. Transistor structure 101 may be located on a dielectric layer above other (e.g., semiconductor) materials.

[0045] Figure 1B The illustration shows one or more gate stacks 125 located on and between nanoribbons 120 in a plurality of aligned stacks 121, and a transistor structure 101 in device 100. The stacks 121 of nanoribbons 120 extend between and couple the source bodies or drain bodies 110. Figure 1B Any transistor structure 101 in the transistor structure 101 can be as follows: Figure 1A Any of the structures 101A, 101B, 101C, and 101D. For example, Figure 1B The gate stack 125 in the middle can be as follows: Figure 1A Any one of the piles 125A, 125B, 125C, and 125D. Dielectric wall 140 and spine 130 ( Figure 1B (Not shown) Located between and in contact with the source and drain bodies 110 in transistor structure 101. Enlarged view 104 shows the gate stack 125 in more detail. The gate stack 125 includes a dielectric layer 122 on nanoribbon 120 and an insulating layer 123 on the dielectric layer 122. The gate stack 125 includes a metal (e.g., filler) layer 128 on the liner layer 127 (on layer 123).

[0046] The source or drain body 110 is electrically and physically coupled to the end of the nanoribbon 120 (e.g., a channel region). The source or drain body 110 can be an impurity-doped region, for example, a semiconductor material region doped with one or more electrically active impurities and having increased charge carrier availability and associated conductivity. Bodies 110 in different transistor structures 101 may be doped with opposite types (e.g., n-type or p-type) or have similar types. The source or drain body 110 may comprise a dominant semiconductor material and one or more n-doped materials (such as phosphorus, arsenic, or antimony) or p-type impurities (such as boron or aluminum). Other dopant materials may be used. Any suitable formation method may be used. The body 110 can be a semiconductor region epitaxially grown from, for example, a group IV semiconductor material (e.g., Si, Ge, SiGe, GeSn alloy). Other semiconductor materials may be employed. The body 110 may be substantially crystalline. The source or drain body 110 may be polycrystalline or substantially monocrystalline, for example, having long-range order at least near the ends of the nanoribbon 120 (e.g., on both sides of the body 110) and being merged or connected into a single whole with few grain boundaries.

[0047] The source or drain body 110 is electrically and physically coupled to the opposite end (e.g., the channel region) of the nanoribbon 120. In many embodiments, the transistor structures 101 are physically symmetrical about the nanoribbon 120 (e.g., the channel region) and the gate electrode 126, and in many cases, the identifiers “drain” and “source” for the body 110 can be interchangeably reversed. However, the classification of the source or drain body 110 can be made by the electrical relationship between the transistor structures 101 and the body 110 and other components in a given circuit (e.g., and the corresponding direction of current flow through the structures 101 and the body 110). Some source or drain bodies 110 may simultaneously be the source body 110 in one transistor structure 101 and the drain body 110 in another transistor structure 101.

[0048] The source and drain contact structure 115 is a metallized structure 115, for example, coupling (e.g., electrically coupling) the body 110 to an interconnect network (not shown) above the transistor structure 101. The contact structure 115 may comprise any suitable material(s), including nonmetals. For example, the contact structure 115 may comprise an interface (e.g., silicide) layer located on the body 110. The structure 115 may comprise multiple metal layers, for example, an inner liner layer (e.g., a barrier layer or seed layer) surrounding a fill layer.

[0049] The contact via 119 is a metallized structure, such as coupling (e.g., electrically coupling) the contact structure 115 to an interconnect network (not shown) above the transistor structure 101. The via 119 may comprise any suitable material(s), including nonmetals. The via 119 may comprise multiple metal layers, such as an inner liner layer (e.g., a barrier layer or seed layer) surrounding a fill layer.

[0050] Separators 147 and 148 are isolation structures made of, for example, an insulating material (such as a low-k dielectric) adjacent to the gate electrode 126. Separator 148 provides isolation between the electrode 126 and the body 110. Separator 147 provides isolation between the electrode 126 and the body 110 and the contact structure 115 above the body 110.

[0051] Figure 1C Dielectric wall 140 and spine 130 are shown, located between and in contact with the source and drain bodies 110 in two transistor structures 101A, 101B, etc. View 105 illustrates a cross-sectional y-z view through the dielectric wall 140 and the source or drain body 110 in transistor structures 101A, 101B. View 106 illustrates a cross-sectional x-y plan view through the dielectric wall 140, spine 130, source or drain body 110, and gate electrode 126 in transistor structures 101A, 101B, etc. Each wall 140 is located between a pair of source or drain bodies 110, and each body 110 is located between the dielectric wall 140 and the spine 130. Each wall 140 and spine 130 has sidewalls 141, 142, 131, 132 located on different source bodies or drain bodies 110, and each body 110 (located on the dielectric sidewalls 141, 142, 131, 132 of the different dielectric walls 140 and spine 130) is located between the dielectric sidewalls 141, 142, 131, 132 of the different dielectric walls 140 and spine 130.

[0052] Figure 2The figure illustrates a cross-sectional view of an IC device 100 according to some embodiments. In a CFET structure 101 between a forked spine 130 and a dielectric wall 140, lower nanoribbon stacks 121A2, 121B2, 121C2, and 121D2 are located below upper nanoribbon stacks 121A1, 121B1, 121C1, and 121D1. High double stacks 121 of nanoribbons 120 with different gate stacks 125 can be implemented through the dielectric wall 140 and the spine 130.

[0053] Device 100 includes: first conductivity type transistor structures 101A1, 101B1, 101C1, 101D1, located above second conductivity type transistor structures 101A2, 101B2, 101C2, 101D2 (e.g., aligned vertically with transistor structures 101A2, 101B2, 101C2, 101D2). Each of the stacks 121A2, 121B2, 121C2, 121D2 is located on the same spine 130 as the corresponding stack 121A1, 121B1, 121C1, 121D1, and is located between the same spine 130 and wall 140. In some embodiments, the lower complementary structure 101 (e.g., structures 101D2, 101C2) shares a gate stack 125 (e.g., stacks 125D, 125C) with the upper structure 101 (e.g., corresponding structures 101D1, 101C1). In other embodiments, the lower complementary structure 101 (e.g., structures 101A2, 101B2) has a gate stack 125 (e.g., stacks 125A1, 125B1) that is distinctly different from the stacks 125 (e.g., stacks 125A1, 125B1) of the upper structure 101 (e.g., corresponding structures 101A1, 101B1). For example, an insulating layer 244 is located between the gate stacks 125A1, 125B1 and the stacks 125A2, 125B2 (and electrically isolates the gate stacks 125A1, 125B1 from the stacks 125A2, 125B2).

[0054] The corresponding upper gate stack 125 and lower gate stack 125 may have the same or different compositions (e.g., the thickness and / or material composition of layers 122, 123, 127). The dielectric separator 224 enables separate processing of the upper stack 121 and lower stack 121 (e.g., different gate dielectric layers 123 on nanoribbons 120 in the upper and lower stacks 121). The separator 224 provides the necessary vertical separation for independent processing of the gate stacks 125 above and below the separator 224.

[0055] The back via 229 passes through the back dielectric layer 249 and may be similar to the gate via 129, for example, a metallized structure that, for example, couples (e.g., electrically couples) the gate electrode 126 to an interconnect network (not shown), but is located below the transistor structure 101. The via 229 may comprise any suitable material(s), including nonmetals. The via 229 may comprise multiple metal layers, for example, an inner liner layer (e.g., a barrier layer or seed layer) surrounding a fill layer. The gate via 229 passes through the dielectric layer 249 below the transistor structure 101. The dielectric layer 249 may be similar to layer 149, for example, any suitable material (such as a low-k dielectric material).

[0056] IC device 100 may include or be coupled to a substrate or other main component 299. Main component 299 may be a package substrate, an inserter, an IC die, etc. For example, substrate 199 may be an IC die including transistor structure 101, substrate 199 may be coupled (e.g., soldered or otherwise bonded) to main component 299, and through main component 299, device 100 and transistor structure 101 may be coupled to a power source (not shown).

[0057] The main component 299 is a planar platform and may include dielectric and metallization structures. The main component 299 mechanically supports and electrically couples one or more IC devices 100. At least one side of the main component 299 includes a substrate interconnect interface for bonding to one or more IC devices 100. IC devices 100 may be directly bonded (e.g., hybrid bonding) to the main component 299, or otherwise bonded, for example, via optional solder bumps. Opposite sides of the main component 299 may include similar interfaces, such as copper pads for socketing and / or solder bumps for bonding devices 100 to a main component (such as a printed circuit board (PCB)). The main component 299 may be any main component with a substrate interconnect interface, such as a packaged main component 299 or an inserter, and the main component 299 may be a die itself. In many embodiments, the main component 299 includes one or more organic dielectrics, such as resins or other polymers, located between metallization layers.

[0058] Figure 3 This is a flowchart of a method 300 for forming different gate stacks in adjacent transistors according to some embodiments. Method 300 includes operations 301–312. Figure 3 Some of the operations shown are optional. Other operations may be included. Figure 3An exemplary sequence is shown, but operations can also be performed in other orders, and some operations can be omitted. Some operations can also be performed multiple times before other operations are executed. For example, multiple layers of the same type can be grown or deposited before the next type of layer is grown or deposited. Some operations can be included within other operations, thereby... Figure 3 The number of operations shown in the diagram is not limited to method 300.

[0059] Figure 4A , 4B The figures 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, and 4L are cross-sectional views of workpieces or devices 100 at various manufacturing stages according to some embodiments. The workpieces or devices 100 have transistor structures 101A, 101B, etc., which have different gate stacks 125A, 125B, etc. in adjacent gate electrodes 126 separated by narrow dielectric walls 140. Figure 4A –4L indicates that in Figure 3 Possible examples of intermediate structures during the implementation of method 300. Although Figure 4A The fabrication of most of the illustrated transistor structures 101A, 101B in –4L (using, for example, gate trench regions 401A, 401B) can be performed, but other transistor structures 101 can be fabricated similarly (e.g., in other gate trench regions 401 between dielectric spine 130 and wall 140).

[0060] Return to Figure 3 In optional operation 301, method 300 begins by growing an interface layer over nanoribbons in adjacent (e.g., first and second) nanoribbon stacks. The interface layer may be located between the nanoribbons and subsequently deposited dummy gates. The interface layer may be a protective layer, for example, shielding the nanoribbons from subsequent processing. For example, the interface layer may be a passivation layer (e.g., of native oxide) protecting the nanoribbons from subsequent deposition (and removal etching) of the dummy gates. Each nanoribbon may be covered by a thin interface (e.g., passivation) layer, which is separate from other nanoribbons and interface layers. In many embodiments, the interface layer comprises oxygen. In many embodiments, the interface layer is located on nanoribbons comprising silicon, and the interface layer comprises oxygen and silicon (e.g., in an oxide of silicon). The interface layer may be grown by any suitable means. In some embodiments, for example, using ozone treatment, the interface layer grows by exposure to oxygen.

[0061] Nanoribbon stacks can be received on or in a substrate, such as an IC die or wafer, for example, similar to... Figure 1A The substrate 199 is described. Nanoribbons and nanoribbon stacks can be similar to those in... Figure 1AThe description of nanoribbons 120 and stacks 121 (e.g., stacks 121A, 121B, 121C, 121D) is provided. For example, each pair of adjacent nanoribbon stacks may be located on and separated by dielectric spines, and adjacent (e.g., first and second) nanoribbon stacks may be located between a pair of adjacent dielectric spines. In some embodiments, adjacent first and second nanoribbon stacks (e.g., located between a pair of adjacent dielectric spines) are located above adjacent third and fourth nanoribbon stacks (e.g., located between the same pair of adjacent dielectric spines), for example, similar to... Figure 2 A pair of adjacent stacks 121A1, 121B1, 121C1, 121D1 are located above a pair of corresponding stacks 121A2, 121B2, 121C2, 121D2. A third nanoribbon stack may be located below the first nanoribbon stack and on the same dielectric spine as the first nanoribbon stack (and on the same side of the dielectric spine). A fourth nanoribbon stack may be located below the second nanoribbon stack and on the same dielectric spine as the second nanoribbon stack (and on the same side of the dielectric spine). In some embodiments, the upper (first and second) nanoribbon stacks are coupled between corresponding semiconductor (source and drain) bodies of a first conductivity type (e.g., n or p type), and the third and fourth nanoribbon stacks are coupled between corresponding semiconductor (source and drain) bodies of a second conductivity type (e.g., p or n type).

[0062] In some embodiments, for example, a wide nanoribbon stack is formed by bisecting it using anisotropic etching. Dielectric spines can then be deposited in the bisected openings, on the remaining portions of the nanoribbons, and between the remaining portions of the nanoribbons. After the source and drain bodies have grown at the ends of the nanoribbons, the nanoribbons can be released from the intervening sacrificial layer.

[0063] Return to Figure 3 Method 300 continues at operation 302: a dummy gate is formed on the nanoribbon stack. The dummy gate can be grown by any suitable means. In many embodiments, the dummy gate is formed by depositing metal on the nanoribbons in the first stack and on the nanoribbons in the second stack, and between the nanoribbons in the first stack and between the nanoribbons in the second stack. In some such embodiments, the metal is deposited on a protective layer on the nanoribbons. In some embodiments, the deposited metal is tungsten. The dummy gate can have any suitable material(s), for example, a material that can be etched through by a high aspect ratio etching process.

[0064] Figure 4AThe diagram illustrates an interface layer 422 on nanoribbons 120 and a dummy gate 426 on layer 422 and above nanoribbons 120 in a workpiece or IC device 100, for example, after performing growth and formation operations 301 and 302, according to some embodiments. Nanoribbons 120 in adjacent stacks 121A, 121B on different spines 130 are separated by a distance D1. Nanoribbons 120 in adjacent stacks 121D, 121A and stacks 121B, 121C are located on the same spine 130 and are separated by a width W3. Figure 4A In an exemplary embodiment, the nanoribbon 120 and the substrate 199 comprise silicon, the interface layer 422 comprises silicon and oxygen, and the dummy gate 426 comprises tungsten.

[0065] Return to Figure 3 In operation 303, method 300 continues by forming a dielectric wall between the first and second nanoribbon stacks. The dielectric wall can be formed by any suitable means. In many embodiments, the dielectric wall is formed between a first portion and a second portion of the dummy gate. For example, the dielectric wall can be formed by etching between the first and second portions of the dummy gate and by depositing dielectric material in the opening etched between the first and second portions. The etching can be dry anisotropic etching or any other suitable etching. The dielectric wall may have opposing first and second sidewalls, with the first portion of the dummy gate located on the first sidewall and the second portion of the dummy gate located on the second sidewall. Multiple dielectric walls can be formed, for example, centered between dielectric spines and between pairs of nanoribbon stacks, each nanoribbon stack located between a dielectric wall and a dielectric spine.

[0066] In many embodiments, forming the dielectric wall creates separate first and second trench regions, with a first nanoribbon stack located in the first trench region and a second nanoribbon stack located in the second trench region; for example, each trench region is located between the dielectric wall and the dielectric spine. In many embodiments, neither the first nor second trench regions includes a third nanoribbon stack; for example, the first nanoribbon stack (and no other nanoribbon stacks) is located in the first trench region, and the second nanoribbon stack (and no other nanoribbon stacks) is located in the second trench region.

[0067] In some embodiments, forming a dielectric wall between the first and second nanoribbon stacks forms a dielectric wall between the third and fourth nanoribbon stacks (e.g., the third nanoribbon stack is located below the first nanoribbon stack and on the same dielectric spine, and the fourth nanoribbon stack is located below the second nanoribbon stack and on the same (second) dielectric spine). In some such embodiments, the upper (first and second) nanoribbon stacks are coupled between semiconductor (source and drain) bodies of a first conductivity type (e.g., n or p type), and the third and fourth nanoribbon stacks are coupled between semiconductor (source and drain) bodies of a second conductivity type (e.g., p or n type).

[0068] The dielectric wall can comprise any suitable material(s), such as a low-k dielectric material. The dielectric wall can be similar to... Figure 1A Description of the dielectric wall 140. In many embodiments, the dielectric wall comprises silicon and nitrogen.

[0069] Figure 4B The illustration shows an isolation wall 140 in a workpiece or device 100, for example, after performing a forming operation 303, according to some embodiments. The isolation wall 140 passes through a dummy gate 426 and is located between adjacent nanoribbon stacks 121A, 121B and gate trench regions 401A, 401B. Figure 4B In an exemplary embodiment, portions of the dummy gate 426 remain located within the gate trench region 401. Other gate trench regions 401D and 401C are located on either side of trench regions 401A and 401B and the dielectric spine 130 (e.g., in the y-direction), between the spine 130 and other walls 140.

[0070] Return to Figure 3 In operation 304, method 300 continues: a first cavity is opened on a first side of the dielectric wall. The first cavity may be a gate trench region for processing the first nanoribbon stack. The first cavity may be opened by any suitable means. In many embodiments, the first cavity is opened by removing a first portion of the dummy gate from the first sidewall and from the first nanoribbon stack. In many embodiments, the dummy gate material is removed by selective isotropic etching. In some embodiments, the dummy gate material is removed by wet etching. In some embodiments, a mask layer is deposited on a substrate (including the dummy gate and the dielectric wall), mask openings are patterned on the first nanoribbon stack, and dummy gate material is removed from the first side of the dielectric wall. The mask openings may be patterned to have an edge placement error (EPE) or greater relative to the dielectric wall, for example, to ensure that the mask openings are always located on the correct trench region.

[0071] In some embodiments, a cavity is opened on a first side of the dielectric wall (e.g., between the dielectric wall and the first dielectric spine) to expose a first nanoribbon stack and a third nanoribbon stack located below the first nanoribbon stack and on the same dielectric spine. The first and third nanoribbon stacks may be processed together (e.g., to receive the same gate stack) or separately.

[0072] Figure 4C The diagram illustrates a mask layer 451, 452 and a first cavity 450A in a workpiece or device 100, for example, after an opening operation 304, according to some embodiments. The mask layers 451, 452 are located above the dummy gate 426, wall 140, spine 130, stack 121, and trench region 401. The first cavity 450A is located below and through layers 451, 452. The material (e.g., metal) of the dummy gate 426 has been removed from the gate trench region 401A, and the nanoribbon stack 121A is located in the cavity 450A within the gate trench region 401A. The interface layer 422 on the nanoribbons 120 of the stack 121A is exposed. The sidewalls 141, 132 of the wall 140 and spine 130 are exposed. Large arrows indicate a large permissible EPE (e.g., tolerance) that will still prevent erroneous opening of the cavity 450A in one of the trench regions 401D or 401B.

[0073] Return to Figure 3 In operation 305, method 300 continues by removing the interface layer from the nanoribbons in the first nanoribbon stack. The interface layer can be removed by any suitable means. In many embodiments, for example, after ozone treatment, the interface layer is removed by etching with hydrofluoric acid (e.g., dilute hydrofluoric acid DHF).

[0074] Return to Figure 3 Method 300 continues in operation 306: forming a first dielectric stack on the nanoribbons in the first nanoribbon stack. The first dielectric stack can be formed by any suitable means. In many embodiments, a dielectric layer is grown on the nanoribbons in the first nanoribbon stack. In many embodiments, an insulating layer is deposited on the dielectric layer grown on the nanoribbons in the first nanoribbon stack. In some embodiments, a dipole dopant is deposited on the dielectric layer on the first nanoribbons or on an insulating layer deposited on the grown dielectric layer.

[0075] In some embodiments, a dielectric stack is formed on a third nanoribbon stack (e.g., in the same cavity and gate trench region) simultaneously with the formation of a first dielectric stack on the nanoribbons in the first nanoribbon stack. In some embodiments, some or all of the dielectric (or metal) stacks formed on the third nanoribbon stack are performed after or before the formation of the first dielectric (or metal) stack on the nanoribbons in the first nanoribbon stack. For example, a carbon (or other) first masking material may be deposited in the gate trench region up to and above the top of the lower nanoribbon stack. A metal (e.g., metal nitride) or other second masking material may then be deposited on the first masking material (e.g., using advantageous non-nucleation (e.g., speckled) growth) and conformally (or semi-conformally) deposited on the upper nanoribbon stack. The first mask material (e.g., carbon) can be removed (e.g., ashed), and the second mask material (metal nitride) deposited on the lateral surface of the first mask material can be removed along with the carbon first mask material, exposing the lower nanoribbon stack, but leaving the upper nanoribbon stack covered by the conformal (or semi-conformal) second mask material.

[0076] Complementary transistors can be organized to minimize processing by simultaneously performing the same gate formation operation on the upper and lower (complementary) nanoribbon stacks. For example, setting the threshold voltage V T An operation that offsets in a certain direction (e.g., in the n or p direction) can be performed simultaneously on an n- or p-type nanoribbon stack to obtain complementary threshold voltages V in opposite directions. T The amplitude. Complementary nanoribbon stacks with similar amplitudes (e.g., for low leakage current or fast switching speed) may not be aligned vertically (e.g., in the same processing tank area), but can be wired together to optimize desired parameters (e.g., low leakage current or fast switching speed).

[0077] The dielectric layer grown on the first nanoribbon stack can be similar to an interface layer, such as a native oxide or passivation layer grown from the nanoribbons. The dielectric layer can be formed by any suitable means and has any suitable material. The dielectric layer on the first nanoribbon stack can be similar to... Figure 1A The description of layer 122A, for example, includes silicon and oxygen, and a thickness T1. While the dielectric layer may resemble the interface layer (e.g., grown in operation 301), the dielectric layer may be grown in a more controlled manner, e.g., grown to a precise and controlled thickness. In some embodiments, the dielectric layer is grown from nanoribbons, and a portion of the thickness of the dielectric layer is consumed from the thickness of the nanoribbons. A thicker dielectric layer may correspond to further thinned nanoribbons. In many embodiments, using ozone treatment, the dielectric layer is grown on a first nanoribbon stack.

[0078] The insulating layer can be deposited on a dielectric layer grown on the first nanoribbon. In many embodiments, the deposited insulating layer is a high-k dielectric layer. The deposited insulating layer can be similar to... Figure 1A The description of layer 123A, for example, includes oxygen and hafnium and / or zirconium, and a thickness T3. The deposited insulating layer can be formed by any suitable method and has any suitable material. In many embodiments, the insulating layer is deposited on a dielectric layer grown on a first nanoribbon by atomic layer deposition (ALD), which conformally deposits the insulating layer in the gate trench region (and deposits outside the entire substrate, deposited on the entire substrate). In many embodiments, the insulating layer is deposited on a first side of the dielectric wall (e.g., a first sidewall). In many embodiments, the insulating layer is deposited on the opposite side of the dielectric spine (e.g., an opposite sidewall). ALD (or another suitable deposition method) can deposit the insulating layer in a highly controlled manner and to a precise and controlled thickness.

[0079] Dipole dopants may be deposited on a dielectric layer grown on a first nanoribbon or on an insulating layer deposited on the grown dielectric layer. In some embodiments, annealing (e.g., at a high temperature) is performed, for example, to drive the dipole dopants into the grown dielectric layer or into the insulating layer deposited on the grown dielectric layer. The dipole dopants may be located in the grown dielectric layer (e.g., at a depth between a first interface between the nanoribbon and the grown dielectric layer and a second interface between the grown dielectric layer and the deposited insulating layer, including both the first and second interfaces), or in or on the deposited insulating layer (e.g., at a depth between a second interface between the grown dielectric layer and the deposited insulating layer and an outer surface of the deposited insulating layer, including both the second interface and the outer surface of the deposited insulating layer). During method 300, annealing (e.g., to drive the dipole dopants into either layer) may be performed at any suitable point, for example, before or after the insulating layer is deposited on the nanoribbons in the second nanoribbon stack. In the first nanoribbon, separate annealing (e.g., performed only on the insulating layer on the nanoribbons in the first nanoribbon stack) can drive the dipole dopant to different depths compared to the second nanoribbon.

[0080] Figure 4D The illustration shows, according to some embodiments, a dielectric layer 122A, a first cavity 450A, and a first gate trench region 401A located on nanoribbons 120 in a first stack 121A in a workpiece or device 100 after performing removal and forming operations 305 and 306. Note that the dielectric layer 122A is located on the nanoribbons 120 in the first nanoribbon stack 121A, but not on the sidewalls 141, 132 of the first cavity 450A and the trench region 401A.

[0081] Figure 4E The illustration shows an insulating layer 123A, a first cavity 450A, and a first gate trench region 401A on a dielectric layer 122A on a nanoribbon 120 in a first stack 121A, in a workpiece or device 100 after performing a forming operation 306, according to some embodiments. Note that the insulating layer 123A is located above the layer 122A and the nanoribbon 120 in the nanoribbon stack 121A, and conformally on the sidewalls 141, 132 of the first cavity 450A and the trench region 401A, as well as on the mask layer 452.

[0082] Return to Figure 3 In operation 307, method 300 continues by depositing a first metal layer onto the first dielectric stack. The first metal layer may be a capping layer, protecting the dielectric stack, for example, from further processing. In many embodiments, the first metal layer is a WFM layer. The first metal layer may be similar to... Figure 1A The description of layer 127 in the first gate stack 125A, for example, has a thickness T5. The first metal layer can be formed by any suitable means and has any suitable material, including non-metallic materials. In many embodiments, the first metal layer comprises nitrogen (e.g., in a metal nitride). In some embodiments, the first metal layer comprises titanium and nitrogen (e.g., in a titanium nitride). In many embodiments, the first metal layer is deposited by CVD (chemical vapor deposition) or ALD.

[0083] The cavity or gate trench region may be filled with a sacrificial material, for example, to cover the deposited gate stack during further processing. The sacrificial material helps retain the deposited layer adjacent to the nanoribbon while allowing the removal of layers elsewhere, such as on a hard mask layer above the gate trench region. In some embodiments, the sacrificial material comprises carbon (e.g., in a carbon hard mask). In some embodiments, the sacrificial material is cured using a nitrogen treatment. In some embodiments, the deposited layer on the hard mask layer above the gate trench region is removed by one or more isotropic etchings and / or CMP (chemical mechanical planarization or polishing).

[0084] Figure 4F The illustration shows, according to some embodiments, a first metal layer 127, a first cavity 450A, and a first gate trench region 401A on an insulating layer 123A on a dielectric layer 122A on a nanoribbon 120 in a first stack 121A, on a workpiece or device 100 after performing deposition operation 307. Note that the metal layer 127 is located on the insulating layer 123A in the nanoribbon stack 121A, and conformally on the insulating layer 123A above the sidewall 141 (and other sidewalls of the first cavity 450A and trench region 401A) and the mask layer 452.

[0085] Return to Figure 3 In operation 308, method 300 continues: a second cavity is opened on the second side of the dielectric wall. For example, except on the opposite side of the dielectric wall, the execution of operation 308 may be similar to the execution of operation 304. The second cavity may be a gate trench region for processing the second nanoribbon stack. The second cavity may be opened by any suitable means. In many embodiments, the second cavity is opened by removing a second portion of the dummy gate from the second sidewall and from the second nanoribbon stack. In many embodiments, the dummy gate material is removed by selective isotropic etching. In some embodiments, the dummy gate material is removed by wet etching. In some embodiments, a mask layer is deposited on the substrate, mask openings are patterned on the second nanoribbon stack, and the dummy gate material is removed from the second side of the dielectric wall. The deposited mask layer may be a second mask layer after the removal (e.g., by CMP) of the first mask layer (e.g., in operation 304, etc.).

[0086] In some embodiments, a second cavity is opened on a second side of the dielectric wall (e.g., between the dielectric wall and the second dielectric spine) to expose a second nanoribbon stack and a fourth nanoribbon stack located below the second nanoribbon stack and on the same dielectric spine. The second and fourth nanoribbon stacks may be processed together (e.g., to receive the same gate stack) or separately.

[0087] Figure 4G The diagram illustrates a mask layer 451, 452 and a second cavity 450B in a workpiece or device 100, for example, after an opening operation 308, according to some embodiments. The mask layers 451, 452 are located above the dummy gate 426, wall 140, stacks 121A, 121B, and trench regions 401A, 401B. The second cavity 450B is located below and through layers 451, 452. Material (e.g., metal) of the dummy gate 426 has been removed from the gate trench region 401B, and the nanoribbon stack 121B is located in the cavity 450B within the gate trench region 401B. Interface layer 422 on the nanoribbons 120 of the stack 121B is exposed. Sidewalls 142, 131 of the wall 140 and spine 130 are exposed. Sacrificial material 446 is located on layer 127 in the first gate trench region 401A. For example, by CMP, the upper horizontal portions of the conformal layers 123A and 127 above the electrode 126 may have been removed, and CMP also removes one or more mask layers 452 above the substrate 199.

[0088] Return to Figure 3In operation 309, method 300 continues by removing the interface layer from the nanoribbons in the second nanoribbon stack. For example, the execution of operation 309 may be similar to the execution of operation 305, except on the second nanoribbon stack. The interface layer can be removed by any suitable means. In many embodiments, the interface layer is removed by hydrofluoric acid etching.

[0089] Return to Figure 3 Method 300 continues with operation 310: forming a second dielectric stack on the nanoribbons in the second nanoribbon stack. For example, except for the second nanoribbon stack, the execution of operation 310 can be similar to the execution of operation 306. Clearly, the execution of operation 310 on the second nanoribbon stack can be carried out using different materials, according to different sizes, etc., and the second dielectric stack can have different characteristics than the first dielectric stack. The second dielectric stack can be formed by any suitable means. In many embodiments, a dielectric layer is grown on the nanoribbons in the second nanoribbon stack. In many embodiments, an insulating layer is deposited on the dielectric layer grown on the nanoribbons in the second nanoribbon stack. In some embodiments, a dipole dopant is deposited on the dielectric layer on the second nanoribbons or deposited on an insulating layer deposited on the grown dielectric layer.

[0090] The dielectric layer can be formed on the second nanoribbon by any suitable means and has any suitable material. The dielectric layer on the second nanoribbon stack can be similar to that on... Figure 1A The description of layer 122B, for example, includes silicon and oxygen, and a thickness T2. Note that the dielectric layer formed on the second nanoribbon may have a different thickness or material composition compared to the dielectric layer formed on the first nanoribbon.

[0091] An insulating layer can be deposited on a dielectric layer grown on a second nanoribbon. In many embodiments, the deposited insulating layer is a high-k dielectric layer. In many embodiments, the deposited insulating layer is deposited on the exposed sidewalls of the gate trench region, on the opposite sidewalls of the dielectric wall and the spine. The deposited insulating layer can be similar to... Figure 1A The layer 123B is described, for example, having oxygen and hafnium and / or zirconium and a thickness T4. The deposited insulating layer can be formed by any suitable means and has any suitable material. Note that the deposited insulating layer formed on the second nanoribbon can have a different thickness or material composition compared to the deposited insulating layer formed on the first nanoribbon.

[0092] Dipole dopants can be deposited on a dielectric layer grown on the second nanoribbon or on an insulating layer deposited on the second nanoribbon. Note that the dipole dopants deposited on the second nanoribbon may have the same or different materials as the dopants deposited on the first nanoribbon, and may be deposited at different concentrations or thicknesses, or driven to different depths in the corresponding dielectric stack, compared to the dopants deposited on the first nanoribbon.

[0093] Figure 4H The illustration shows, according to some embodiments, a dielectric layer 122B, a second cavity 450B, and a second gate trench region 401B located on nanoribbons 120 in a second stack 121B within a workpiece or device 100 after performing removal and forming operations 309 and 310. Note that the dielectric layer 122B is located on the nanoribbons 120 in the second nanoribbon stack 121B, but not on the sidewalls 142, 131 of the second cavity 450B and the trench region 401B.

[0094] Figure 4I The diagram illustrates an insulating layer 123B, a second cavity 450B, and a second gate trench region 401B, on a dielectric layer 122B on a nanoribbon 120 in a second stack 121B, in a workpiece or device 100, for example, after performing formation operation 310, according to some embodiments. Note that the insulating layer 123B is located above layer 122B and the nanoribbon 120 in the nanoribbon stack 121B, and conformally on the sidewalls 142, 131 of the second cavity 450B and the trench region 401B, as well as the mask layer 452.

[0095] Return to Figure 3 In operation 311, method 300 continues by depositing a second metal layer onto the second dielectric stack. For example, except for the deposition on the second dielectric stack, the execution of operation 311 can be similar to the execution of operation 307. Clearly, the execution of operation 311 on the second dielectric stack can be accomplished using different materials, according to different dimensions, etc., and the second gate stack can have different characteristics than the first gate stack. The second metal layer can be a capping layer, protecting the second dielectric stack, for example, from further processing. In many embodiments, the second metal layer is a WFM layer. The second metal layer can be similar to... Figure 1A The description of layer 127 in the second gate stack 125B, for example, has a thickness T6. The second metal layer can be formed by any suitable means and has any suitable material, including non-metallic materials. In many embodiments, the second metal layer comprises nitrogen. In some embodiments, the second metal layer comprises titanium and nitrogen.

[0096] Similar to the processing of the first and second gate stacks and nanoribbons, the processing of the third and fourth gate stacks on the third and fourth nanoribbon stacks can be performed, for example, simultaneously, completely independently, or in some hybrid mode of shared and separate operations.

[0097] Figure 4J The illustration shows, according to some embodiments, a second metal layer 127, a second cavity 450B, and a second gate trench region 401B on an insulating layer 123B on a dielectric layer 122B on a nanoribbon 120 in a second stack 121B, for example, after performing deposition operation 311, in a workpiece or device 100. Note that the metal layer 127 is located on the insulating layer 123B in the nanoribbon stack 121B, and conformally on the insulating layer 123B above the sidewalls 142, 131 of the second cavity 450B and the trench region 401B, and on the mask layer 452.

[0098] Return to Figure 3 In operation 312, method 300 continues by forming a first gate electrode on a first nanoribbon stack and a second gate electrode on a second nanoribbon stack. Dielectric walls may be retained, and the first and second gate electrodes may be separated by the dielectric walls. The first and second gate electrodes may be formed in any suitable manner and have any suitable material, including non-metallic materials. The first and second gate electrodes may be similar to those in… Figure 1A Description of electrode 126 in transistor structures 101A, 101B (e.g., having layers 127, 128). The first and second gate electrodes may be formed of the same or different materials, for example having the same or different layers 127, 128.

[0099] Figure 4K The illustration shows sacrificial material 446 on layer 127 in the first and second gate trench regions 401A, 401B of a workpiece or device 100, for example, during or before performing formation operation 312, according to some embodiments. A mask layer is not present over the dummy gate 426, wall 140, spine 130, stack 121, and trench region 401.

[0100] Figure 4LThe illustration shows an IC device 100 according to some embodiments, for example, after performing formation operation 312. The IC device 100 has transistor structures 101A, 101B, 101C, and 101D, which have different gate stacks 125A, 125B, 125C, and 125D in adjacent gate electrodes 126 separated by a narrow dielectric wall 140. Gate electrodes 126 and transistor structures 101A, 101B, 101C, and 101D are coupled, for example, to an interconnect network (not shown) above structure 101 via gate vias 129 in the dielectric layer 149.

[0101] Figure 5 The illustration shows an exemplary data server machine 506 according to some embodiments. The data server machine 506 employs an IC device having dielectric walls separating forked transistors with different gate stacks. The server machine 506 can be any commercial server, for example, including any number of high-performance computing platforms housed in a rack and networked together for electronic data processing. In an exemplary embodiment, the commercial server includes one or more devices 550 having dielectric walls separating forked transistors with different gate stacks.

[0102] Furthermore, as shown in the figures, server machine 506 includes a battery and / or power supply 515 to power device 550 and provides power delivery functions such as power regulation in some embodiments. Device 550 may be deployed as part of package-level integrated system 510. Integrated system 510 is further illustrated in enlarged view 520. In exemplary embodiments, device 550 (labeled "memory / processor") includes at least one memory chip (e.g., random access memory (RAM)) and / or at least one processor chip (e.g., microprocessor, multi-core microprocessor, or graphics processor, etc.) having the characteristics discussed herein. In embodiments, device 550 is a microprocessor including static RAM (SRAM) cache memory. As shown in the figures, device 550 may be an IC device having dielectric walls separating forked transistors with different gate stacks, as discussed herein. Device 550 may be further coupled (e.g., communicatively coupled to) a board, inserter, or other substrate or main component 299, and one or more of the following devices: a power management IC (PMIC) 530; an RF (wireless) IC (RFIC) 525, including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, and the analog front-end module also including a power amplifier on the transmit path and a low-noise amplifier on the receive path); and its controller 535. In some embodiments, RFIC 525, PMIC 530, controller 535, and device 550 include dielectric walls having forked transistors with discrete gate stacks.

[0103] Figure 6 This is a block diagram of an exemplary computing device 600 according to some embodiments. For example, one or more components of the computing device 600 may include any of the devices or structures discussed herein. Many components are... Figure 6 The components are illustrated as being included in computing device 600, but any one or more of these components may be omitted or doubled depending on the application requirements. In some embodiments, some or all of the components included in computing device 600 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various components of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing device 600 may not include... Figure 6The computing device 600 may include one or more of the components shown in the diagram, but may include interface circuitry systems for coupling to said one or more components. For example, the computing device 600 may not include a display device 603, but may include display device interface circuitry systems (e.g., connector and driver circuitry systems) to which the display device 603 may be coupled. In another set of examples, the computing device 600 may not include an audio output device 604, other output devices 605, a Global Positioning System (GPS) device 609, an audio input device 610, or other input devices 611, but may include audio output device interface circuitry systems, other output device interface circuitry systems, GPS device interface circuitry systems, audio input device interface circuitry systems, and audio input device interface circuitry systems to which the audio output device 604, other output devices 605, GPS device 609, audio input device 610, or other input device 611 may be coupled.

[0104] Computing device 600 may include processing device 601 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" refers to a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 601 may include memory 621, communication device 622, cooling device 623, battery / power regulation device 624, logic 625, interconnects 626 (i.e., optionally including redistribution layer (RDL) or metal-insulator-metal (MIM) devices), thermal regulation device 627, and hardware security device 628.

[0105] Processing device 601 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0106] The computing device 600 may include a memory 602, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drive. In some embodiments, the memory 602 includes memory that shares a die with the processing device 601. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0107] The computing device 600 may include a thermal regulation / cooling device 606. The thermal regulation / cooling device 606 can keep the processing device 601 (and / or other components of the computing device 600) at a predetermined low temperature during operation.

[0108] In some embodiments, computing device 600 may include communication chip 607 (e.g., one or more communication chips). For example, communication chip 607 may be configured to manage wireless communication for transmitting data to and from computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, but in some embodiments they may not contain any wires.

[0109] Communication chip 607 can implement any of many wireless standards or protocols, including but not limited to IEEE standards (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long Term Evolution (LTE) initiatives, and any modifications, updates, and / or revisions (e.g., Advanced LTE initiatives, Ultra Mobile Broadband (UMB) initiatives (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks. WiMAX is an abbreviation for Global Interoperability for Microwave Access, a certification mark of products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication chip 607 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 607 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 607 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, etc. In other embodiments, the communication chip 607 may operate according to other wireless protocols. The computing device 600 may include an antenna 613 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0110] In some embodiments, the communication chip 607 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 607 may include multiple communication chips. For example, a first communication chip 607 may be dedicated to short-range wireless communications (such as Wi-Fi or Bluetooth), and a second communication chip 607 may be dedicated to long-range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others). In some embodiments, the first communication chip 607 may be dedicated to wireless communications, and the second communication chip 607 may be dedicated to wired communications.

[0111] The computing device 600 may include a battery / power circuitry system 608. The battery / power circuitry system 608 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 600 to a separate energy source (e.g., AC line power).

[0112] The computing device 600 may include a display device 603 (or a corresponding interface circuit system, as discussed above). The display device 603 may include any visual indicator, such as, for example, a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0113] The computing device 600 may include an audio output device 604 (or a corresponding interface circuit system, as discussed above). The audio output device 604 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earphones.

[0114] The computing device 600 may include an audio input device 610 (or a corresponding interface circuitry system, as discussed above). The audio input device 610 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0115] The computing device 600 may include a GPS device 609 (or a corresponding interface circuit system, as discussed above). The GPS device 609 may communicate with a satellite-based system and may receive the location of the computing device 600, as is known in the art.

[0116] The computing device 600 may include other output devices 605 (or corresponding interface circuitry, as discussed above). Examples of such other output devices 605 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0117] The computing device 600 may include other input devices 611 (or corresponding interface circuitry systems, as discussed above). Examples of such other input devices 611 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice, styluses, touchpads), barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0118] Computing device 600 may include a security interface device 612. The security interface device 612 may include any device that provides security measures for computing device 600, such as intrusion detection, biometric verification, secure encoding or decoding, access list management, malware detection, or spyware detection.

[0119] The computing device 600 or a subset thereof may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0120] The subject of this description is not limited to... Figure 1A – The specific application illustrated in Figure 6. As those skilled in the art will understand, this subject matter can be applied to other deposition applications and any suitable manufacturing applications.

[0121] The examples below relate to other embodiments, and the details in the examples can be used anywhere in one or more embodiments.

[0122] In one or more first embodiments, a device includes: first, second, and third dielectric walls located in an IC substrate, the third dielectric wall being located between the first and second dielectric walls; a first stack of first nanoribbons located on the first dielectric wall and through a first gate structure in a first transistor structure, the first gate structure including a first dielectric layer located on the first and third dielectric walls and between a pair of first nanoribbons; and a second stack of second nanoribbons located on the second dielectric wall and through a second gate structure in a second transistor structure, the second gate structure including a second dielectric layer located on the second and third dielectric walls and between a pair of second nanoribbons.

[0123] In one or more second embodiments, as a further extension of the first embodiment, the device further includes: fourth and fifth dielectric walls located in the IC substrate, the first dielectric wall located between the third and fourth dielectric walls, and the second dielectric wall located between the third and fifth dielectric walls; a third stack of third nanoribbons located on the first dielectric wall and through a third gate structure in a third transistor structure, the third gate structure including a third dielectric layer located on the first and fourth dielectric walls and between a pair of third nanoribbons; and a fourth stack of fourth nanoribbons located on the second dielectric wall and through a fourth gate structure in a fourth transistor structure, the fourth gate structure including a fourth dielectric layer located on the second and fifth dielectric walls and between a pair of fourth nanoribbons, wherein the composition of the third dielectric layer is different from the composition of the first, second, and fourth dielectric layers, and the composition of the fourth dielectric layer is different from the composition of the first and second dielectric layers.

[0124] In one or more third embodiments, as a further extension of the first or second embodiment, the device further includes: a third stack of third nanoribbons located below a first stack of the first nanoribbons, located on the first dielectric wall, and located within a third transistor structure; and a fourth stack of fourth nanoribbons located below a second stack of the second nanoribbons, located on the second dielectric wall, and located within a fourth transistor structure, the third and fourth stacks of the third and fourth nanoribbons located between the first and second dielectric walls, wherein the first and second transistor structures have a first conductivity type, and the third and fourth transistor structures have a second conductivity type.

[0125] In one or more fourth embodiments, as a further extension of the first to third embodiments, the third stack of the third nanoribbon passes through the third gate structure in the third transistor structure, and the insulating layer is located between the first and third gate structures.

[0126] In one or more fifth embodiments, as a further extension of the first to fourth embodiments, the first gate structure includes a first metal located between the first and third dielectric walls and between the pair of first nanoribbons; a first dielectric layer located between the first metal and the first dielectric wall, between the first metal and the third dielectric wall, between the first metal and the upper first nanoribbon of the pair of first nanoribbons, and between the first metal and the lower first nanoribbon of the pair of first nanoribbons; and the second gate structure includes a second metal located between the second and third dielectric walls and between the pair of second nanoribbons; a second dielectric layer located between the second metal and the second dielectric wall, between the second metal and the third dielectric wall, between the second metal and the upper second nanoribbon of the pair of second nanoribbons, and between the second metal and the lower second nanoribbon of the pair of second nanoribbons.

[0127] In one or more sixth embodiments, as a further extension of the first to fifth embodiments, the first width of the third dielectric wall is smaller than the second width of the first dielectric wall.

[0128] In one or more seventh embodiments, as a further extension of the first to sixth embodiments, the width of the third dielectric wall is less than 12 nm, and the distance between the first stack of the first nanoribbons and the second stack of the second nanoribbons is less than 36 nm.

[0129] In one or more eighth embodiments, as a further extension of the first to seventh embodiments, the width of the third dielectric wall is approximately equal to the distance between the third dielectric wall and the first stack of the first nanoribbons.

[0130] In one or more ninth embodiments, as a further extension of the first to eighth embodiments, the first dielectric layer has a first thickness and a first composition, the second dielectric layer has a second thickness and a second composition, and the second thickness is greater than the first thickness or the second composition is different from the first composition.

[0131] In one or more tenth embodiments, as a further extension of the first to ninth embodiments, the IC substrate is coupled to a main component, and the IC substrate is coupled to a power source through the main component.

[0132] In one or more eleventh embodiments, a device includes: a dielectric spine located between and in contact with a first stack of first nanoribbons and a second stack of second nanoribbons; a first gate structure located between the dielectric spine and a first dielectric wall, the first stack of first nanoribbons passing through the first gate structure in a first transistor structure, the first gate structure including a first dielectric layer located on the dielectric spine and the first dielectric wall and between a pair of first nanoribbons; and a second gate structure located between the dielectric spine and the second dielectric wall, the second stack of second nanoribbons passing through the second gate structure in a second transistor structure, the second gate structure including a second dielectric layer located on the dielectric spine and the second dielectric wall and between a pair of second nanoribbons.

[0133] In one or more twelfth embodiments, as a further extension of the eleventh embodiment, the device further includes: a third stack of third nanoribbons located below a first stack of the first nanoribbons, located on the dielectric spine, and located in a third transistor structure; and a fourth stack of fourth nanoribbons located below a second stack of the second nanoribbons, located on the dielectric spine, and located in a fourth transistor structure, wherein the first and second transistor structures have a first conductivity type, and the third and fourth transistor structures have a second conductivity type.

[0134] In one or more thirteenth embodiments, as a further extension of the eleventh or twelfth embodiment, the dielectric spine is a first dielectric spine, and the device further includes: a second dielectric spine located between and in contact with the third stack of the third nanoribbons and the fourth stack of the fourth nanoribbons; a third gate structure located between the second dielectric spine and the second dielectric wall, the third stack of the third nanoribbons passing through the third gate structure in a third transistor structure, the third gate structure including a third dielectric layer located on the second dielectric spine and the second dielectric wall and between a pair of third nanoribbons; and a fourth gate structure located between the second dielectric spine and the third dielectric wall, the fourth stack of the fourth nanoribbons passing through the fourth gate structure in a fourth transistor structure, the fourth gate structure including a fourth dielectric layer located on the second dielectric spine and the third dielectric wall and between a pair of fourth nanoribbons, wherein the composition of the third dielectric layer is different from the compositions of the first, second, and fourth dielectric layers, and the composition of the fourth dielectric layer is different from the compositions of the first and second dielectric layers.

[0135] In one or more of the fourteenth embodiments, as a further extension of the eleventh to thirteenth embodiments, the device is coupled to a main component, and the device is coupled to a power source through the main component.

[0136] In one or more fifteenth embodiments, a method includes: forming a first dielectric wall between a first stack of first nanoribbons and a second stack of second nanoribbons, the first stack of first nanoribbons being located on a second dielectric wall, the second stack of second nanoribbons being located on a third dielectric wall, the first and second stacks of the first and second nanoribbons being located between the second and third dielectric walls, and the first dielectric wall being located between the first and second stacks of the first and second nanoribbons; opening a cavity between the first and second dielectric walls; forming a dielectric stack on the first nanoribbons; and forming a gate electrode on the first stack of the first nanoribbons.

[0137] In one or more sixteenth embodiments, as a further extension of the fifteenth embodiment, the formation of the first dielectric wall forms separate first and second trench regions, a first stack of the first nanoribbons is located in the first trench region and a second stack of the second nanoribbons is located in the second trench region, neither of the first and second trench regions includes a third nanoribbon stack, the cavity between the first and second dielectric walls is a first cavity in the first trench region, the dielectric stack on the first nanoribbon is a first dielectric stack, and the gate electrode above the first stack of the first nanoribbon is a first gate electrode, and the method further includes: opening a second cavity in the second trench region between the first and third dielectric walls; forming a second dielectric stack on the second nanoribbon; and forming a second gate electrode above the second stack of the second nanoribbon, the first dielectric wall being located between the first and second gate electrodes.

[0138] In one or more of the seventeenth embodiments, as a further extension of the fifteenth or sixteenth embodiments, the formation of the first and second dielectric stacks forms first and second dielectric stacks with different compositions or thicknesses.

[0139] In one or more eighteenth embodiments, as a further extension of the fifteenth to seventeenth embodiments, the formation of the dielectric stack on the first nanoribbon involves depositing a dielectric layer on the sidewall of the first dielectric wall.

[0140] In one or more nineteenth embodiments, as a further extension of the fifteenth to eighteenth embodiments, the method further includes: forming a dummy gate between the second and third dielectric walls by depositing metal on and between the first nanoribbons in the first stack and depositing metal on and between the second nanoribbons in the second stack, wherein forming the first dielectric wall between the first stack of the first nanoribbons and the second stack of the second nanoribbons forms the first dielectric wall through the dummy gate.

[0141] In one or more twentieth embodiments, as a further extension of the fifteenth to nineteenth embodiments, the first dielectric wall is formed between the first stack of the first nanoribbons and the second stack of the second nanoribbons, and the first dielectric wall is formed between the third stack of the third nanoribbons and the fourth stack of the fourth nanoribbons, wherein the third stack of the third nanoribbons is located below the first stack of the first nanoribbons and on the second dielectric wall, and the fourth stack of the fourth nanoribbons is located below the second stack of the second nanoribbons and on the third dielectric wall, wherein the first stack of the first nanoribbons is coupled between the first and second semiconductor bodies of the first conductivity type, and the third stack of the third nanoribbons is coupled between the third and fourth semiconductor bodies of the second conductivity type, and the cavity is opened between the first and second dielectric walls to expose the first stack of the first nanoribbons and the third stack of the third nanoribbons.

[0142] This disclosure can be implemented with modifications and alterations, and the scope of the appended claims is not limited to the embodiments described herein. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this respect, and in various implementations, the above embodiments may include performing only a subset of such features, performing such features in a different order, performing different combinations of such features, and / or performing additional features besides those expressly listed. Therefore, the scope of the patent right should be determined with reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: First, second, and third dielectric walls are located in an integrated circuit (IC) substrate, with the third dielectric wall located between the first and second dielectric walls; A first stack of first nanoribbons is located on the first dielectric wall and through a first gate structure in a first transistor structure, the first gate structure including a first dielectric layer located on the first and third dielectric walls and between a pair of first nanoribbons; and A second stack of second nanoribbons is located on the second dielectric wall and through a second gate structure in a second transistor structure, the second gate structure including a second dielectric layer located on the second and third dielectric walls and between a pair of second nanoribbons.

2. The device as claimed in claim 1, further comprising: The fourth and fifth dielectric walls are located in the IC substrate, the first dielectric wall is located between the third and fourth dielectric walls, and the second dielectric wall is located between the third and fifth dielectric walls; The third stack of the third nanoribbons is located on the first dielectric wall and through the third gate structure in the third transistor structure, the third gate structure including a third dielectric layer located on the first and fourth dielectric walls and between a pair of third nanoribbons; and The fourth stack of the fourth nanoribbon is located on the second dielectric wall and through the fourth gate structure in the fourth transistor structure, the fourth gate structure including a fourth dielectric layer located on the second and fifth dielectric walls and between a pair of fourth nanoribbons, wherein the composition of the third dielectric layer is different from the composition of the first, second and fourth dielectric layers, and the composition of the fourth dielectric layer is different from the composition of the first and second dielectric layers.

3. The device as described in claim 1, further comprising: The third stack of the third nanoribbon is located below the first stack of the first nanoribbon, on the first dielectric wall, and in the third transistor structure; and The fourth stack of the fourth nanoribbon is located below the second stack of the second nanoribbon, on the second dielectric wall, and in the fourth transistor structure. The third and fourth stacks of the third and fourth nanoribbons are located between the first and second dielectric walls. The first and second transistor structures have a first conductivity type, and the third and fourth transistor structures have a second conductivity type.

4. The device of claim 3, wherein the third stack of the third nanoribbon passes through the third gate structure in the third transistor structure, and the insulating layer is located between the first and third gate structures.

5. The device as claimed in any one of claims 1 to 4, wherein: The first gate structure includes a first metal located between the first and third dielectric walls and between the pair of first nanoribbons, wherein the first dielectric layer: Located between the first metal and the first dielectric wall; Located between the first metal and the third dielectric wall; Located between the first metal and the upper first nanoribbon of the pair of first nanoribbons; and It is located between the first metal and the lower first nanoribbon of the pair of first nanoribbons.

6. The device as claimed in claim 5, wherein: The second gate structure includes a second metal located between the second and third dielectric walls and between the pair of second nanoribbons, and the second dielectric layer: Located between the second metal and the second dielectric wall; Located between the second metal and the third dielectric wall; Located between the second metal and the upper second nanoribbon of the pair of second nanoribbons; and It is located between the second metal and the lower second nanoribbon in the pair of second nanoribbons.

7. The device according to any one of claims 1 to 4, wherein the first width of the third dielectric wall is smaller than the second width of the first dielectric wall.

8. The device as claimed in any one of claims 1 to 4, wherein: The width of the third dielectric wall is less than 12 nm; and The distance between the first stack of the first nanoribbon and the second stack of the second nanoribbon is less than 36 nm.

9. The device according to any one of claims 1 to 4, wherein the width of the third dielectric wall is approximately equal to the distance between the third dielectric wall and the first stack of the first nanoribbons.

10. The device as claimed in any one of claims 1 to 4, wherein: The first dielectric layer has a first thickness and a first composition; The second dielectric layer has a second thickness and a second composition; and The second thickness is greater than the first thickness or the second component is different from the first component.

11. The device of any one of claims 1 to 4, wherein the IC substrate is coupled to a main component, and the IC substrate is coupled to a power source through the main component.

12. An apparatus comprising: The dielectric spine is located between the first stack of the first nanoribbons and the second stack of the second nanoribbons and is in contact with the first stack of the first nanoribbons and the second stack of the second nanoribbons. A first gate structure is located between the dielectric spine and the first dielectric wall, and a first stack of the first nanoribbons passes through the first gate structure in the first transistor structure. The first gate structure includes a first dielectric layer, which is located on the dielectric spine and the first dielectric wall and between a pair of first nanoribbons. and A second gate structure is located between the dielectric spine and the second dielectric wall. The second stack of the second nanoribbons passes through the second gate structure in the second transistor structure. The second gate structure includes a second dielectric layer located on the dielectric spine and the second dielectric wall and between a pair of second nanoribbons.

13. The apparatus of claim 12, further comprising: The third stack of the third nanoribbon is located below the first stack of the first nanoribbon, on the dielectric spine, and within the third transistor structure.

14. The apparatus of claim 13, further comprising: The fourth stack of the fourth nanoribbon is located below the second stack of the second nanoribbon, on the dielectric spine, and in the fourth transistor structure, wherein the first and second transistor structures have a first conductivity type, and the third and fourth transistor structures have a second conductivity type.

15. The device of any one of claims 12 to 14, wherein the dielectric spine is a first dielectric spine, and further comprises: The second dielectric spine is located between the third stack of the third nanoribbon and the fourth stack of the fourth nanoribbon and is in contact with the third stack of the third nanoribbon and the fourth stack of the fourth nanoribbon. A third gate structure is located between the second dielectric spine and the second dielectric wall. The third stack of the third nanoribbons passes through the third gate structure in the third transistor structure. The third gate structure includes a third dielectric layer located on the second dielectric spine and the second dielectric wall and between a pair of third nanoribbons. and A fourth gate structure is located between the second dielectric spine and the third dielectric wall, the fourth stack of the fourth nanoribbons is through the fourth gate structure in the fourth transistor structure, the fourth gate structure includes a fourth dielectric layer located on the second dielectric spine and the third dielectric wall and located between a pair of fourth nanoribbons.

16. The device of claim 15, wherein the composition of the third dielectric layer is different from the composition of the first, second, and fourth dielectric layers.

17. The device of claim 16, wherein the composition of the fourth dielectric layer is different from the composition of the first and second dielectric layers.

18. The device of any one of claims 12 to 14, wherein the device is coupled to a main component and the device is coupled to a power source through the main component.

19. A method comprising: A first dielectric wall is formed between a first stack of first nanoribbons and a second stack of second nanoribbons, the first stack of first nanoribbons is located on the second dielectric wall, the second stack of second nanoribbons is located on the third dielectric wall, the first and second stacks of first and second nanoribbons are located between the second and third dielectric walls, and the first dielectric wall is located between the first and second stacks of first and second nanoribbons. A cavity is opened between the first and second dielectric walls; A dielectric stack is formed on the first nanoribbon; and A gate electrode is formed on the first stack of the first nanoribbons.

20. The method of claim 19, wherein: The formation of the first dielectric wall forms separate first and second trench regions, a first pile of the first nanoribbons is located in the first trench region and a second pile of the second nanoribbons is located in the second trench region, neither of the first and second trench regions includes a third nanoribbon pile; The cavity between the first and second dielectric walls is the first cavity in the first trench region; The dielectric stack on the first nanoribbon is a first dielectric stack; and The gate electrode on the first stack of the first nanoribbon is the first gate electrode; and Also includes: A second cavity is opened in the second trench region between the first and third dielectric walls; A second dielectric stack is formed on the second nanoribbon; and A second gate electrode is formed on a second stack of the second nanoribbons, with the first dielectric wall located between the first and second gate electrodes.

21. The method of claim 20, wherein the formation of the first and second dielectric stacks forms first and second dielectric stacks having different compositions or thicknesses.

22. The method of any one of claims 19 to 21, wherein forming the dielectric stack on the first nanoribbon deposits a dielectric layer on the sidewall of the first dielectric wall.

23. The method of any one of claims 19 to 21, further comprising: A dummy gate is formed between the second and third dielectric walls by depositing metal on the first nanoribbons in the first stack and between the first nanoribbons in the first stack, and depositing metal on the second nanoribbons in the second stack and between the second nanoribbons in the second stack, wherein the formation of the first dielectric wall between the first stack of the first nanoribbons and the second stack of the second nanoribbons forms the first dielectric wall through the dummy gate.

24. The method according to any one of claims 19 to 21, wherein: The first dielectric wall is formed between the first stack of the first nanoribbons and the second stack of the second nanoribbons, and between the third stack of the third nanoribbons and the fourth stack of the fourth nanoribbons. The third stack of the third nanoribbons is located below the first stack of the first nanoribbons and on the second dielectric wall, and the fourth stack of the fourth nanoribbons is located below the second stack of the second nanoribbons and on the third dielectric wall. The first stack of the first nanoribbons is coupled between the first and second semiconductor bodies of the first conductivity type, and the third stack of the third nanoribbons is coupled between the third and fourth semiconductor bodies of the second conductivity type. The cavity is opened between the first and second dielectric walls to expose a first stack of the first nanoribbons and a third stack of the third nanoribbons.

Images