Independent trench gate with channel and gate height difference

Abstract

Integrated circuit (IC) devices have gate-all-around (GAA) transistors. The IC devices can include adjacent GAA transistors separated by a dielectric wall and having gate structures with different heights and gate dielectric layers on nanoribbon channels and on the dielectric wall. The stacks of nanoribbons in adjacent transistors can have different heights, compositions, and thicknesses. The gate dielectric layers in adjacent transistors can have different thicknesses or material compositions. The gate metal layers of adjacent transistors can have different thicknesses or material compositions. The dielectric wall between the gate structures can enable independent processing of the transistor gates by dividing the nanoribbon channels into separate gate slots.

Description

Background Technology

[0001] As gate-all-around (GAA) transistors continue to scale, gate geometry shrinks, reducing the space available for gate material patterning. This may necessitate increased patterning precision to improve transistor performance, reduce process variability, and / or prevent reliability issues. For example, using conventional GAA gate patterning schemes, depositing or removing different (e.g., optimized) materials in adjacent (e.g., complementary) transistors, or forming structures of different sizes (e.g., optimized metal gates), may be impractical (or prohibitively expensive).

[0002] New technologies, structures, and materials are needed to improve the metal gate in complementary GAA transistors. Attached Figure Description

[0003] The materials described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be enlarged relative to others for clarity. Furthermore, reference numerals have been repeated in the drawings where deemed appropriate to indicate corresponding or similar elements, such as those having the same or similar functions. This disclosure will be described with additional specificity and detail using the accompanying drawings:

[0004] Figure 1A , Figure 1B and Figure 1C Cross-sectional profiles and plan views of an integrated circuit (IC) device having a transistor structure according to some embodiments are shown, the transistor structure having different gate structures separated by thin dielectric walls;

[0005] Figure 2A , Figure 2B and Figure 2C A cross-sectional profile view of an IC device having a transistor structure according to some embodiments is shown, the transistor structure having gate structures with different gate heights and separated by dielectric walls;

[0006] Figure 3 This is a flowchart of a method for forming nanoribbon channel and gate structures with different heights and compositions over a stack of nanoribbons, according to some embodiments.

[0007] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4HIsometric and plan views of an IC device according to some embodiments are shown, the IC device having gate structures of different heights and compositions on nanoribbons of different heights and compositions at different manufacturing stages;

[0008] Figure 5 A diagram of an example data server machine employing an IC device is shown, the IC device having dielectric walls separating the channel and gate structures with different heights; and

[0009] Figure 6 This is a block diagram of an example computing device according to some embodiments. Detailed Implementation

[0010] In the following detailed description, reference is made to the accompanying drawings, which illustrate by way of description specific embodiments in which the claimed subject matter can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. While the various embodiments differ, they are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in conjunction with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.

[0011] The reference to "an embodiment" or "an embodiment" in this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one implementation covered herein. Therefore, the use of the phrase "an embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, the position or arrangement of various elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be considered limiting, and the scope of the subject matter is defined and properly interpreted only by the appended claims and all their equivalents.

[0012] As used herein, the terms “above,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer “above” or “on top of” another layer, or bonded “to” another layer, may be in direct contact with the other layer or may have one or more intermediate layers. A layer “between” other layers may be in direct contact with the other layers or may have one or more intermediate layers.

[0013] The terms “coupling” and “connection” and their derivatives may be used herein to describe structural relationships between components. These terms are not intended to be synonyms with each other. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupling” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in causal, electrical, functional, etc.).

[0014] The terms “circuit” or “module” can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of “a,” “an,” and “described” include multiple references. The meanings of “in” include “in” and “on”.

[0015] The vertical orientation is in the z-direction, and the terms "top," "bottom," "above," and "below" refer to relative positions with their usual meanings in the z-dimension. However, embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0016] The terms “substantially,” “near,” “approximately,” “near,” and “about” generally refer to within + / -10% of the target value (unless otherwise specified). Unless otherwise specified in the specific context of use, the term “dominant” means more than 50% or more than half. For example, a composition in which the first component is dominant means that more than half of the composition is the first component. The term “primarily” refers to the largest or most abundant portion. For example, a composition in which the first component is primarily dominant means that the composition contains more of the first component than any other component. A composition in which both the first and second components are primarily dominant means that the composition contains more of both the first and second components than any other component.

[0017] Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects indicates only different instances of the similar objects mentioned and is not intended to imply that the objects described must be in a given order in time, space, ranking, or any other way.

[0018] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0019] Views labeled "Cross-section," "Outline," and "Planar" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, cross-sectional and outline views are taken in the xz and yz planes, and planar views are taken in the xy plane. Typically, the outline view in the xz plane is a cross-sectional view. Where appropriate, the figures are labeled with axes to indicate the orientation of the figures.

[0020] The technology, structure, and materials for improving integrated circuit (IC) devices with gate-all-around (GAA) metal-oxide-semiconductor (MOS) field-effect transistors (FETs) are disclosed.

[0021] Dielectric walls can separate adjacent nanoribbon stacks into individual processing chambers (“tubs”), enabling the independent fabrication of nanoribbon stacks, gate dielectric stacks, and metal gates within adjacent GAA FETs. Instead of each channel material layer (e.g., nanoribbon) stack undergoing the same processing in a shared gate trench, each material layer stack can have its own gate tub and receive specially tailored processing. Dielectric walls can be formed by repeatedly etching through long dummy gates in the gate trenches and filling the etched openings with dielectric material, thus creating numerous isolations between the nanoribbon stacks. The openings can be patterned by depositing a hard mask layer over the walls and material layer stacks, and the dummy gate material can be removed through the openings, thereby emptying the selected tubs between the dielectric walls.

[0022] Mask openings can be fabricated to drain groups of trenches selected for a specific processing operation. For example, gate trenches used in all (or at least many) material layer stacks to employ a first (e.g., silicon) material layer group or to receive a specific gate dielectric material or thickness can be drained together and then simultaneously received for further processing. After a specific processing operation is completed, the hard mask layer can be removed, a new hard mask layer can be deposited, and new openings can be patterned to drain new groups of trenches for the next processing operation. For example, the new group of trenches may employ a second (e.g., silicon-germanium) material layer group or receive a second gate dielectric material or thickness. Dielectric walls can be retained after gate formation as electrical isolation between adjacent metal gate electrodes.

[0023] Custom processing enabled by gate trenches can be used to provide multiple channel and gate variants, such as nanoribbon channels with different compositions and heights, and channels with different threshold voltages V. TAnd gate stacks corresponding to leakage and switching speeds. Complementary conductivity type transistors can have nanostrip channels using optimized materials for that type, and different (e.g., optimized) material layers can have different (e.g., staggered) heights in adjacent channel material layer stacks. Transistors can have metal gates of different heights, for example, to minimize parasitic capacitance. Different gate heights can be achieved by selectively recessing the metal gate in selected gate trenches.

[0024] As enabled by separate gate trenches and independent processing, IC devices can have multiple gate variants for each of several complementary conductivity types. For example, an IC device can have four or more threshold voltages V between NMOS FETs. T The distribution, and has four or more threshold voltages V between the PMOS FETs. T The distribution of the gate dielectric layers is as follows. In many embodiments, adjacent transistors have gate dielectric layers of different thicknesses directly on the channel nanoribbon. In many embodiments, adjacent transistors have gate dielectric layers of different thicknesses (e.g., high dielectric constant or "high-k" layers) directly on the nanoribbon. For example, the gate dielectric layer thicknesses may differ by 2 angstroms (or up to 5 angstroms) in adjacent transistors. In many embodiments, adjacent transistors have gate dielectric layers with different high-k materials. In some embodiments, adjacent transistors have gate dielectric layers with different material compositions (e.g., element ratios) of the same high-k material.

[0025] Figure 1A , Figure 1B and Figure 1C Cross-sectional outlines and plan views of an IC device 100 having transistor structures 101A, 101B according to some embodiments are shown. The transistor structures 101A, 101B have different gate structures 125A, 125B separated by thin dielectric walls 140. The gate structures 125A, 125B may have different gate heights (or locations). The transistor structures 101A, 101B are GAA FET structures 101, having channel regions in stacks 121A, 121B through nanoribbons 120 (e.g., nanoribbons 120A, 120B) of the gate structures 125A, 125B, respectively. The nanoribbons 120 in the different stacks 121A, 121B may have different heights (e.g., heights that are interlaced, staggered, etc., relative to another stack 121 (stacks 121A or 121B)) and may have different compositions. Figure 1A A yz view plane is shown that passes laterally through the nanoribbons 120 in the multiple adjacent stacks 121A, 121B and the transistor structure 101. Figure 1AMultiple (e.g., enlarged) views 102, 103 including gate structures 125A, 125B, with gate structures 125A, 125B at different heights H A H B (For example, respectively above height H) Bl H B2 H B3 H B4 Height H A1 H A2 H A3 H A4 The nanoribbon 120 at point 120 has different heights H around it. C H D . Figure 1B A yz contour view 104 and an xy plane view 105 are shown, both passing through a dielectric wall 140, which is between the gate structure 125 and the source or drain body 110 (e.g., body 110A, 110B) in the transistor structures 101A, 101B, and contacts the gate structure 125 and the source or drain body 110. Figure 1C Cross-sectional profiles of the device 100 through gate structures 125A and 125B are shown in diagrams 106, 107, 108, and 109, which have different heights in transistor structures 101A and 101B (and nanoribbons 120 at different heights).

[0026] Figure 1A A device 100 including an isolation wall 140 is shown, which is located between and separates a first gate structure 125A and a second gate structure 125B in transistor structures 101A and 101B, respectively. Gate structures 125A and 125B include at least a gate electrode 126 and a gate dielectric layer 123. Gate structures 125A and 125B may have different dimensions or positions, such that the upper surfaces of structures 125A and 125B are at different heights H. C H D For example, in Figure 1A In the exemplary embodiment shown, one of structures 125A and 125B may have a reduced or lower height H. C or H D And, for example, a correspondingly reduced parasitic capacitance. In some embodiments, such as Figure 1A As shown, the first (vertical position) or height H of the first upper surface of the first gate structure 125A C The second (vertical position or) height H of the second upper surface of the second gate structure 125B is greater than (e.g., higher than) the second gate structure 125B. D In some embodiments, the height H of the upper surface of structure 125AC The height H of the upper surface of structure 125B D 10 nm or larger (e.g., 15 nm). In some embodiments, the height H of the upper surface of the gate structure 125A is... C Less than (e.g., below) the height H of the upper surface of structure 125B D Height H C H D The difference can be achieved through the dielectric wall 140 between the gate structures 125A, 125B and the stack 121A, 121B.

[0027] exist Figure 1A In an exemplary embodiment, the upper surface of the wall 140 between (and on both sides of) the gate structures 125A and 125B is in a vertical position or at a height H. C (height H) C H D (The larger or higher one). In transistor structure 101A, the metal of gate electrode 126 and the dielectric layer 123 in structure 125A (e.g., on sidewalls 141, 142) extend upward to a height H. C In transistor structure 101B, the metal of gate electrode 126 and the dielectric layer 123 in structure 125B (e.g., on sidewalls 141, 142) extend upward to a height H. D On side walls 141 and 142, above height H D The dielectric layer 123 in structure 125B is absent. The gate insulating layer 144 is above structure 125B at a height H. C H D Between, and having a height equal to H C H D The height difference. Gate via 129 passes through the gate insulating layer 144 above structure 125B.

[0028] The height H of structures 125A and 125B C H D The difference can be compared with the height H of nanoribbons 120A and 120B, respectively. A H B The difference is related. For example, nanoribbons 120A in stack 121A and structure 101A can have a height H from nanoribbons 120B in stack 121B and structure 101B. B offset height H A And height H C H D The same vertical span can be achieved by offsetting nanoribbons 120A and 120B. Height H CThe uppermost nanoribbon of nanoribbon 120A is offset by a vertical (span or distance or) height H3, and the height H D The uppermost nanoribbon of nanoribbon 120B is offset by a vertical (span or distance or) height H4. Figure 1A In an exemplary embodiment, the vertical spans or heights H3 and H4 are equal; for example, there are corresponding gate structures 125 of the same thickness between the uppermost nanoribbons 120A and 120B and the corresponding gate vias 129. In some embodiments, height H3 is greater than height H4; for example, there is a gate electrode 126 of minimum thickness in the gate structure 125B on the nanoribbon 120B. In some embodiments, height H3 (e.g., the thickness of the gate electrode 126 in the gate structure 125A) is less than or shorter than height H4.

[0029] As in Figure 1A In the exemplary embodiment shown, the first height H of the first nanoribbon 120A A1 -H A4 It can be used with the second height H of the second nanoband 120B. B1 -H B4 Offset and interleaving. For example, the topmost nanoribbon 120A has a first height H. A1 Greater than (e.g., higher than) the uppermost second height H of the uppermost nanoribbon 120B Bl Each adjacent pair of second nanoribbons 120B includes an upper nanoribbon 120B and a lower nanoribbon 120B, wherein the upper nanoribbon 120B has a first height H. BX The first axis (e.g., the center line) is higher than the second height H of the adjacent first nanoribbon 120A. A（X+1） The second axis at the location, and the lower second nanoribbon 120B has a third height H. B（X+1） The third axis is lower than the second axis of the adjacent nanoribbon 120A. Each adjacent pair of first nanoribbons 120A includes an upper nanoribbon 120A and a lower nanoribbon 120A, wherein the upper nanoribbon 120A has a first height H. AX The first axis is located above the second height H of the adjacent second nanoribbon 120B. BX The second axis at the location, and the lower nanoribbon 120A has a third height H. A（X+1） The third axis is located below the second axis of the adjacent first nanoribbon 120A.

[0030] The stacks 121A and 121B can have any suitable number of nanoribbons 120A and 120B. Figure 1AIn exemplary embodiments, stacks 121A and 121B each have four nanoribbons 120A and 120B, but stacks 121A and 121B may have more or fewer nanoribbons 120A and 120B. In some embodiments, stacks 121A and 121B each have three (or fewer) nanoribbons 120A or 120B. In other embodiments, stacks 121A and 121B each have five (or more) nanoribbons 120A or 120B. In some embodiments, stack 121A has more (or fewer) nanoribbons 120A than stack 121B has nanoribbons 120B.

[0031] exist Figure 1A In an exemplary embodiment, nanoribbons 120A and 120B are uniformly spaced in an alternating manner, wherein each of the first nanoribbons 120A is adjacent to a corresponding second nanoribbon 120B (e.g., at a lower height H). B At constant intervals above (e.g., at a higher height H) A At the location of the second nanoribbon 120B, which is at a constant interval above the next nanoribbon 120A, the second nanoribbon 120B is located. In many embodiments, such as Figure 1A As shown, stacks 121A and 121B have equal and constant spacing H. P H Pb The vertical spacing H between the nanoribbons 120A in the stack 121A Pa (height H) A1 H A2 Between, height H A2 H A3 Between and height H A3 H A4 The difference between them is equal to the vertical spacing H between the nanoribbons 120B in the stack 121B. Pb (height H) B1 H B2 Between, height H B2 H B3 Between and height H B3 H B4 The same difference between them). In the context of the spacing, height (whether vertical or span), thickness, etc. of nanoribbons 120, if the dimensions (e.g., height, etc.) are within 1 nm, the dimensions are considered approximately equal. Nanoribbons 120B (except for the lowest nanoribbon 120B) are vertically centered between the nearest adjacent nanoribbons 120A (e.g., half a spacing above and below the nearest adjacent nanoribbon 120A). Nanoribbons 120A (except for the highest nanoribbon 120A) are vertically centered between the nearest adjacent nanoribbons 120B (e.g., half a spacing above and below the nearest adjacent nanoribbon 120B).

[0032] Height H A1 -H A4 H B1 -H B4 The reference point is the vertical position of nanoribbons 120A and 120B relative to the axis or centerline of nanoribbons 120A and 120B, but nanoribbons 120A and 120B can be referenced in other ways (e.g., the upper or lower surface of nanoribbons 120A and 120B), having a height H. A1 -H A4 H B1 -H B4 The same resulting interlacing (e.g., sorting). In some embodiments, the lower surface of each of the nanoribbons 120A, 120B in stacks 121A, 121B is coplanar with the upper surface of the next nearest neighbor nanoribbon 120B, 120A in another stack 121B, 121A. For example, the nanoribbons 120A, 120B in stacks 121A, 121B may come from the same stack of alternating layers (e.g., where each type of nanoribbon 120A or 120B has a different layer composition), and the next nearest neighbor nanoribbons 120A, 120B in opposing stacks 121A, 121B may come from previously adjacent layers. In some other embodiments (e.g., having thinner nanoribbons 120A and / or 120B), the lower surface of each of the nanoribbons 120A and 120B in the stacks 121A and 121B is above the upper surface of the next nearest adjacent nanoribbon 120B or 120A in the other stacks 121B and 121A. As in many embodiments, the nanoribbon 120A has a thickness T similar to that of the nanoribbon 120B. B Equal thickness T A .

[0033] In many embodiments, the vertical spans or heights H1 and H2 of the stacks 121A and 121B are equal. Figure 1A In an exemplary embodiment, the vertical spans or heights H1 and H2 extend from the lower surfaces of the lowest nanoribbons 120A and 120B in the stacks 121A and 121B to the upper surfaces of the highest nanoribbons 120A and 120B, respectively.

[0034] Transistor structures 101A and 101B can have the same or complementary conductivity types (e.g., NMOS and / or PMOS structures 101A and 101B). Figure 1AIn an exemplary embodiment, transistor structure 101A is an n-type structure 101A, and transistor structure 101B is a p-type structure 101B. In other embodiments, transistor structure 101A is a p-type structure 101A, and transistor structure 101B is an n-type structure 101B. In other embodiments, transistor structures 101A and 101B have the same conductivity type (e.g., both are PMOS structures 101A and 101B, or both are NMOS structures 101A and 101B).

[0035] The dielectric wall 140 enables the independent processing of stacks 121A, 121B of nanoribbons 120A, 120B in transistor structures 101A, 101B, allowing for structures 101A, 101B with nanoribbons 120A, 120B having different heights, thicknesses, compositions, etc. For example, the nanoribbon 120 can have any suitable width (e.g., in the y-axis) and can be, for example, a nanowire nanoribbon 120 or a nanosheet nanoribbon 120. Deploying nanoribbons 120A, 120B with different material compositions can improve performance by allowing for the use of optimal materials for different transistor structures 101. In many embodiments, transistor structures 101A, 101B have complementary conductivity types (e.g., n-type and p-type). In many embodiments, structure 101A is an n-type transistor structure 101A. In many embodiments, the first nanoribbon 120A is primarily silicon. In many embodiments, structure 101B is a p-type transistor structure 101B. In many embodiments, the second nanoribbon 120B comprises silicon and germanium. The nanoribbon 120 provides a channel region for the transistor structure 101 and can be any (e.g., semiconductor) material suitable for use as a channel region. The nanoribbon 120A in the stack 121A can be the same as or different from the nanoribbon 120B in the stack 121B.

[0036] The isolation wall 140 is a dielectric structure on (e.g., in contact with) both structures 125A and 125B. The wall 140, separating the gate structures 125A and 125B, extends vertically from above the top (e.g., upper surface) of the gate electrode 126 to below the bottom (e.g., lower surface) of the electrode 126. The dielectric wall 140 provides isolation (e.g., electrical isolation) between the gate electrodes 126 of structures 101A and 101B. The thin wall 140 enables a close stacking of the transistor structures 101A and 101B and the gate electrode 126 in device 100. The dielectric wall 140 also allows for the independent processing of the gate structures 125A and 125B in structures 101A and 101B (e.g., as described elsewhere herein, such as in…). Figure 3(and method 300), which allows structures 125 with different insulating layers 122, 123, etc., for example, with different thicknesses, materials, etc. Each wall 140 is located between a pair of gate electrodes 126, and each electrode 126 is located between a pair of dielectric walls 140.

[0037] In some embodiments, such as in Figure 1A In an exemplary embodiment, transistor structures 101A and 101B have different gate stacks in adjacent gate structures 125A and 125B separated by a thin dielectric wall 140. For example, structures 125A and 125B may have different gate dielectric layers 123A and 123B or metal layers 127 and 128 (e.g., to advantageously provide different threshold voltages V for transistor structures 101A and 101B). T The different gate stacks in gate structures 125A and 125B and transistor structures 101A and 101B are shown in more detail in views 102 and 103, respectively.

[0038] Transistor structure 101A includes a first stack 121A extending through a first nanoribbon 120 of a first gate structure 125A. Transistor structure 101B includes a second stack 121B extending through a second nanoribbon 120 of a second gate structure 125B. Structures 125A and 125B have different first and second gate stack compositions. The difference between the first and second compositions of structures 125A and 125B can be that structures 125A and 125B include different numbers of layers (e.g., more or different layers), similar layers but different materials, etc. Gate structures 125A and 125B can have different dielectric stacks 124 (e.g., stacks 124A and 124B). For example, the difference between the first and second compositions of gate structures 125A and 125B can be that only one of structures 125A and 125B has a high-k dielectric layer 123 on the conversion layer 122.

[0039] The first gate structure 125A includes a first dielectric stack 124A on the first nanoribbon 120, and the gate structure 125A includes one or more first metal layers 127 on the dielectric stack 124A. View 102 illustrates an embodiment having multiple layers 127 on the stack 124A. The first dielectric stack 124A includes a dielectric layer 122A on the first nanoribbon 120A and an insulating layer 123A surrounding the nanoribbon 120A on the dielectric layer 122A. The first gate structure 125A may also include a metal (e.g., filler) layer 128 on the pad layer 127.

[0040] The second gate structure 125B includes a second dielectric stack 124B on the second nanoribbon 120 (as shown in view 103), and the gate structure 125B includes one or more second metal layers 127 on the dielectric stack 124B. The second dielectric stack 124B includes a dielectric layer 122B on the second nanoribbon 120B and an insulating layer 123B surrounding the nanoribbon 120B on the dielectric layer 122B. The second gate structure 125B may also include a metal (e.g., filler) layer 128 on the pad layer 127.

[0041] The dielectric layer 122 (e.g., layers 122A, 122B) may comprise any suitable material and may have any suitable thickness. Layers 122A, 122B are located on the nanoribbon 120 in transistor structures 101A, 101B, respectively, and may provide protection for the nanoribbon 120, for example, during processing. For example, layers 122A, 122B may be passivation layers 122A, 122B of a native oxide of, for example, the material in the nanoribbon 120. In many embodiments, the dielectric layer 122 comprises silicon and oxygen. Layers 122A, 122B may be transition layers 122 between the nanoribbon 120 and other layers on layer 122, such as layer 123, etc. In some embodiments, the dielectric layers 122A, 122B have thicknesses T1, T2 smaller than the thicknesses of other layers above layers 122A, 122B. In many embodiments, the dielectric layer 122A has a thickness T1 greater than (or less than) the thickness T2 of the dielectric layer 122B. In some embodiments, one of layers 122A and 122B includes a material not included in the other of layers 122A and 122B. Layer 122 may include other suitable materials. Different thicknesses T1 or T2 (or different material compositions) of layers 122A and 122B can provide different threshold voltages V for transistor structures 101A and 101B. T Different thicknesses T1 or T2 of layers 122A and 122B can provide nanoribbons 120 of different thicknesses in transistor structures 101A and 101B.

[0042] Insulating layer 123 (e.g., layers 123A, 123B) may comprise any suitable material and may have any suitable thickness. Layers 123A, 123B are located on conversion layers 122A, 122B in transistor structures 101A, 101B, respectively. In many embodiments, insulating layers 123A, 123B have thicknesses T1, T2, T3, T4 greater than those of layers 122A, 122B on nanoribbon 120. Insulating layer 123 may be dielectric layer 123. For example, layers 123A, 123B advantageously comprise one or more high-k dielectric materials, which can provide design flexibility and / or superior properties (such as electrical properties) when deployed or replaced by other materials.

[0043] Layer 123 (e.g., high-k layers 123A, 123B) can allow for larger transconductance g in transistor structures 101A, 101B. m (For example, for the same voltage and the same thickness T3 or T4 on the gate electrode 126). The high-k layer 123 can allow for a larger total thickness of the dielectric above the nanoribbon 120 (e.g., thickness T1 plus thickness T3 in stack 124A or thickness T2 plus thickness T4 in stack 124B), and thus can achieve low leakage current in structures 101A, 101B (e.g., for the same voltage on the gate electrode 126, while maintaining the same transconductance g). m High-k layers 123A and 123B can achieve low leakage current in structures 101A and 101B, for example, by having a lower voltage on the gate electrode 126 and the same thickness T3 or T4. In many embodiments, insulating layer 123A has a thickness T3 that is greater than (or less than) the thickness T4 of insulating layer 123B. Different thicknesses T3 or T4 (or different material compositions) of layers 123A and 123B can provide different threshold voltages V for transistor structures 101A and 101B. T .

[0044] Insulating layer 123 may comprise any suitable material. In many embodiments, insulating layer 123 comprises hafnium and oxygen. In some embodiments, insulating layer 123 comprises zirconium and oxygen. In some embodiments, insulating layer 123 comprises hafnium, zirconium, and oxygen. In some embodiments, insulating layers 123A and 123B have different material compositions. In some embodiments, for example, insulating layer 123A (or layer 123B) comprises hafnium and zirconium, and insulating layer 123B (or layer 123A) comprises neither hafnium nor zirconium, or comprises only one of hafnium and zirconium (e.g., comprising hafnium without zirconium, or comprising zirconium without hafnium). In some embodiments, layers 123A and 123B both comprise hafnium, zirconium, and oxygen (HZO, e.g., in hafnium zirconate or zirconium hafnium oxide), but in different elemental ratios. The material composition of one or both of layers 123A and 123B (e.g., the ratio of hafnium to zirconium) can be altered to increase the relative permittivity of layers 123A and / or 123B (e.g., from about 1:1 to about 2:1 or higher). In some embodiments, a dopant (e.g., yttrium) is added to one or both of layers 123A and 123B to increase the relative permittivity of layers 123A and / or 123B (e.g., by increasing the proportion of the dielectric phase with a higher permittivity in layer 123). Either or both of layers 123A and 123B may comprise one or more of a variety of elements, such as hafnium, zirconium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, barium, strontium, yttrium, scandium, niobium, and zinc. Layer 123 may comprise other suitable materials.

[0045] The first gate structure 125A and the second gate structure 125B may include a dipole dopant. In some embodiments, one of the first gate structure 125A and the second gate structure 125B includes a dipole dopant that is not present in the other of the gate structures 125A and 125B. In some embodiments, the first gate structure 125A and the second gate structure 125B include the same dipole dopant, but the dipole dopant is present at a first height (e.g., the sum of thicknesses T1 and T3) of the nanoribbons 120 from the stack 121A, which is greater than (or less than) a second height (e.g., the sum of thicknesses T2 and T4) of the nanoribbons 120 from the stack 121B. The same dipole dopant may be present in different layers 122 and 123 of different dielectric stacks 124A and 124B (or at different interfaces of layers 122 and 123).

[0046] Gate electrode 126 (and gate structures 125A, 125B) may include one or more metal layers 127, 128. Gate electrode 126, together with first dielectric stack 124A and second dielectric stack 124B, forms a first gate structure 125A and a second gate structure 125B for conduction of electrostatically controlled transistor structures 101A, 101B. Layers 127, 128 may be work function metal (WFM) layers 127, 128, for example, to (e.g., independently) influence the threshold voltage V of transistor structures 101A, 101B. T Layer 127 may be a conformal padding layer 127 surrounding the nanoribbons 120 and the dielectric stack 124. For example, a first metal layer 127 may be present on an insulating layer 123A surrounding each of the nanoribbons 120 in structure 101A, and a second metal layer 127 may be present on an insulating layer 123B surrounding each of the nanoribbons 120 in structure 101B. Transistor structure 101A and gate structure 125A may include one or more metal layers 127 in the electrodes 126. Transistor structure 101B and gate structure 125B may include one or more metal layers 127 in the electrodes 126.

[0047] The pad layers 127 in structures 101A and 101B can have different thicknesses T5 and T6, respectively. For example, the thickness T5 (or thickness T6) is greater than the thickness T6 (or thickness T5) and affects the threshold voltage V of transistor structure 101A (or structure 101B). TThis has a correspondingly greater impact. Layers 127 in structures 101A and 101B can have the same or different material compositions. Filler layers 128 in structures 101A and 101B can have different material compositions. Layers 127 and 128 can include any suitable material, including nonmetals. In many embodiments, layer 127 includes nitrogen (e.g., in a metal nitride) or carbon (e.g., in a metal carbide). In some such embodiments, layer 127 includes nitrogen and titanium, molybdenum, or tantalum. In some embodiments, a first layer 127 on the dielectric stack 124 includes titanium and nitrogen, and a second layer 127 on the first layer 127 includes nitrogen and tantalum or molybdenum. In some embodiments, layer 127 includes titanium, aluminum, and carbon. In many embodiments, layer 128 includes tungsten.

[0048] Wall 140 includes opposing first sidewalls or sidewalls 141 and second sidewalls or sidewalls 142. Width W1 (or width W2) of dielectric wall 140 separates sidewalls 141 and 142. Width W1 (or width W2) separates gate structures 125A and 125B in transistor structures 101A and 101B, respectively. Dielectric wall 140 (e.g., sidewalls 141 and 142) may be nearly vertical. In many embodiments, dielectric wall 140 has only slightly different widths W1 and W2 (e.g., in a tapered profile that gradually narrows upwards or downwards). For example, widths W1 and W2 may be within 1 nm. Width W1 is defined as the width of wall 140 at the top of wall 140. Width W2 is defined as the width of wall 140 at the bottom of structure 125, for example, where wall 140 contacts substrate 199 at the bottom of gate structure 125.

[0049] Gate structures 125 are separated by dielectric walls 140, and structures 125 have a minimum distance or width W2 (or width W1, etc.) between them. In many embodiments, the dielectric walls 140 have a minimum width W2 (or width W1, etc.) of 12 nm or less between structures 125, which allows for sufficiently compact packaging of transistor structures 101A, 101B and subsequent savings in layout area. In some embodiments, the dielectric walls 140 have a minimum W2 (or width W1, etc.) of 10 nm or less between structures 125, which allows for excellent packaging of transistor structures 101A, 101B and savings in layout area. This compact layout of structures 101 (with small widths W1, W2, and) can be achieved by fine, high aspect ratio etching (e.g., through and between the metal gate electrodes 126).

[0050] The close stacking of the stacks 121 and the transistor structure 101 can also be characterized by a small distance D separating the first stack 121A and the second stack 121B of the nanoribbons 120. In many embodiments, the distance D is less than three times the maximum width W1 of the wall 140. For example, if the wall 140 is centered between the stacks 121 and within the distance D, then the wall 140 is less than the width W1 from either stack.

[0051] The isolation wall 140 comprises any suitable material, such as a dielectric material. Advantageously, wall 140 comprises a low-k (low dielectric constant) dielectric material. Advantageously, wall 140 has etch selectivity compared to other adjacent structures. In many embodiments, wall 140 comprises silicon and nitrogen (e.g., in a silicon nitride). In some embodiments, wall 140 comprises silicon and oxygen (e.g., in a silicon oxide). In some embodiments, for example, in addition to silicon and oxygen, wall 140 also comprises carbon and / or nitrogen.

[0052] The isolation wall 140 enables independent processing of the gate structures 125A and 125B in structures 101A and 101B (e.g., as at least in...). Figure 3 (as described in Method 300), which allows for various compositions 125 (e.g., having different thicknesses T1, T2, T3, T4, T5, T6 and / or including layers 122, 123, 127, etc., of different materials).

[0053] At least some of the layers of structures 125A and 125B surrounding the nanoribbon 120 are also on the sidewalls 141 and 142 of the isolation wall 140. Insulator layer 123A is on sidewall 141. Insulator layer 123B is on sidewall 142. In transistor structure 101A, metal layer 127 is on insulating layer 123A on sidewall 141. In transistor structure 101B, metal layer 127 is on insulating layer 123B on sidewall 142. It is noteworthy that gate dielectric layers 122A and 122B on the nanoribbon 120 may not be present on the sidewalls 141 and 142 of the isolation wall 140, such as... Figure 1A As in exemplary embodiments. In many embodiments, for any given gate structure 125, the layer 123 on the sidewalls 141, 142 is continuous with the layer 123 surrounding the nanoribbon 120 that runs through the given structure 125. For example, the layer 123 may be a single layer continuous around the corresponding gate electrode 126 or connected to both x-directions of the observation plane.

[0054] Gate via 129 is a metallized structure that couples (e.g., electrically couples) a gate electrode 126 to an interconnect network (not shown) above transistor structure 101. Via 129 may comprise any suitable material, including non-metallic materials. Via 129 may comprise multiple layers of metal, such as a pad (e.g., barrier or seed) layer surrounding a fill layer. Gate via 129 passes through dielectric layer 149 above transistor structures 101A, 101B. Dielectric layer 149 may be any suitable material, such as a low-k dielectric material.

[0055] Substrate 199 may comprise one or more of any suitable materials. Substrate 199 may be an IC substrate, such as an IC die or wafer. In some examples, the substrate may comprise monocrystalline silicon (including silicon-on-insulator (SOI)), polycrystalline silicon, germanium, silicon-germanium, III-V alloy materials (e.g., gallium arsenide), silicon carbide (e.g., SiC), sapphire (e.g., Al2O3), or any combination thereof. Substrate 199 may also comprise semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Substrate 199 may specifically refer to a base material (e.g., a thick substrate or semiconductor material layer) on which other materials (such as metals and dielectrics) are constructed. In some contexts, substrate 199 may refer to a base material layer on a substrate and any stacked layers, etc. Transistor structure 101 may be on top of a dielectric layer over other materials (e.g., semiconductors).

[0056] Figure 1B Cross-sectional plan view 104 and outline view 105 of an IC device 100 according to some embodiments are shown, including dielectric walls 140 separating adjacent source or drain bodies 110A, 110B and gate structures 125A, 125B in transistor structures 101A, 101B. Outline view 104 (similar to...) Figure 1A (Most of the content is for reference only) has a cross-sectional yz observation plane passing through the gate structures 125A, 125B of transistor structures 101A, 101B. Plan view 105 has a cross-sectional xy observation plane passing through the source or drain bodies 110A, 110B and gate electrode 126 (e.g., below the upper surface of structures 125A, 125B, and below dielectric layer 144) of the gate and transistor structures 125A, 125B, 101A, 101B. Nanoribbons 120 (e.g., nanoribbons 120A, 120B) not in the observation plane are shown with dashed lines (e.g., for reference).

[0057] IC device 100 includes source or drain bodies 110A, 110B located before or after (e.g., in the x-direction) the gate electrode 126 of structures 125A, 125B shown in outline view 104. In plan view 105, dies 110A, 110B are located in the x-direction of the gate electrode 126. A first transistor structure 101A includes a first source or drain body 110A coupled to a stack 121A of a first nanoribbon 120A. A second transistor structure 101B includes a second source or drain body 110B coupled to a stack 121B of a second nanoribbon 120B.

[0058] As shown in view 105, the source or drain body 110 is electrically and physically coupled to the opposite end of the channel region nanoribbon 120. In many embodiments, the transistor structure 101 is physically symmetrical about the nanoribbon 120 (e.g., the channel region) and the gate electrode 126, and the identifiers “drain” and “source” of the body 110 can be interchanged in many contexts. However, the source or drain body 110 can be classified according to the electrical relationship between the transistor structure 101 and the body 110 and other components in a given circuit (e.g., and the direction of the current flowing subsequently through the structure 101 and the body 110). Some source or drain bodies 110 may be a source body 110 in one transistor structure 101 and a drain body 110 in another transistor structure 101.

[0059] The source or drain body 110 can be an impurity-doped region, such as a semiconductor material region doped with one or more electroactive impurities and having increased charge carrier availability and associated conductivity. Dies 110 in different transistor structures 101 can be doped with opposite types (e.g., n-type or p-type) or similar types. The source or drain body 110 can include a primary semiconductor material and one or more n-dopers (e.g., phosphorus, arsenic, or antimony) or p-type impurities (e.g., boron or aluminum). Other dopant materials can be used. Any suitable formation method can be used. The die 110 can be an epitaxially grown semiconductor region, such as a group IV semiconductor material (e.g., Si, Ge, SiGe, GeSn alloy). Other semiconductor materials can be employed. The body 110 can be substantially crystalline. The source or drain body 110 can be polycrystalline or substantially single-crystal, for example, having long-range order at at least adjacent ends of the nanoribbon 120 and merging or connecting into a single body with few grain boundaries.

[0060] The source or drain bodies 110A and 110B can be made of different materials, for example, to improve the performance of the complementary transistor structures 101A and 101B. In many embodiments, structure 101A is an n-type transistor structure 101A, and body 110A is primarily silicon. In many embodiments, structure 101B is a p-type transistor structure 101B, and body 110B comprises silicon and germanium.

[0061] As shown in View 105, a dielectric wall 140 is located between source or drain bodies 110A, 110B. The wall 140 includes opposing first sidewalls 141 and second sidewalls 142, and the dielectric wall 140 is in direct contact with the bodies 110A, 110B at the sidewalls 141, 142. As shown in View 105, the dielectric wall 140 is located between the stacks 121A, 121B of the first nanoribbon 120A and the second nanoribbon 120B, the gate electrode 126, and the source or drain bodies 110A, 110B. The dielectric wall 140 extends through a spacer 147. A gate dielectric layer 123 is located on the electrode 126 (e.g., in a gate stack or structure 125 having the gate electrode 126) and on the dielectric wall 140 (e.g., at the sidewalls 141, 142) and on the spacer 147. The dielectric wall 140 is an isolation structure, providing electrical isolation, for example, between the electrodes 126 and between the bodies 110A, 110B. Other gate electrodes 126, etc., not shown, are in other transistor structures 101 outside the edge of view 105 (e.g., in the x direction).

[0062] Spacer 147 (as shown in view 105) is an isolation structure between adjacent gate electrode 126 and source or drain body 110, for example, having an insulating material (such as a low-k dielectric). Spacer 147 provides isolation (e.g., electrical isolation) between electrode 126 and body 110.

[0063] Figure 1C Cross-sectional profile views of a device 100 having a dielectric wall 140 between nanoribbons 120A and 120B of different materials and heights in transistor structures 101A and 101B, according to some embodiments, are shown. Views 106 and 107 show a gate structure 125A between the dielectric wall 140 in transistor structure 101A and the source or drain body 110A. Views 108 and 109 show a gate structure 125B between the dielectric wall 140 in transistor structure 101B and the source or drain body 110B. Dielectric wall 140 ( Figure 1C (Not shown in views 107, 109) Between the stacks 121 of nanoribbons 120 in transistor structures 101A, 101B (e.g., 1A and 109) Figure 1B(As shown). Spacers 148 (e.g., spacers 148A, 148B) are located between the gate structure 125 and the source and drain bodies 110.

[0064] Views 106 and 107 are yz and xz cross-sectional profiles of the gate structure 125A, the source or drain body 110A, and the nanoribbon 120A in transistor structure 101A. View 106 shows... Figure 1A A portion (e.g., a portion of transistor structure 101A) and a reference for the xz cross-sectional profile 107 via nanoribbon 120A. Views 106 and 107 are vertically aligned, for example, the height H of nanoribbon 120A. A1 -H A4 Align between views 106 and 107. (As shown) Figure 1A As shown, the height H of the nanoribbon is 120 Å. A1 -H A4 With height H of nanoribbon 120B B1 -H B4 Offset (and staggered). Spacer 147 is located above nanoribbon 120A. Spacer 148A is located between and below nanoribbon 120A. In some embodiments, spacers 147 and 148A have different compositions, such as Figure 1C As shown.

[0065] Views 108 and 109 are yz and xz cross-sectional profiles of the source or drain body 110B and nanoribbon 120B in transistor structure 101B. View 108 shows... Figure 1A A portion (e.g., a portion of transistor structure 101B) and a reference for the xz cross-sectional profile 109 via nanoribbon 120B. Views 108 and 109 are vertically aligned, for example, the height H of nanoribbon 120B. B1 -H B4 Align between views 108 and 109. (As shown) Figure 1A As shown, the height H of the nanoribbon is 120 Å. A1 -H A4 With height H of nanoribbon 120B B1 -H B4 Offset (and staggered). Spacer 147 is located above nanoribbon 120B. Spacer 148B is located between and below nanoribbon 120B. In some embodiments, spacers 147 and 148B have different compositions, such as Figure 1C As shown.

[0066] The first and second gate electrodes 126 in transistor structures 101A and 101B may be different or substantially similar, respectively. Gate electrode 126 may include a metal layer (including layer 127), which may be different or substantially similar in transistor structures 101A and 101B. Gate electrode 126 may be part of gate structure 125, which also includes a dielectric layer 123 on electrode 126 and on spacers 147, 148A, and 148B. Gate dielectric layer 123 insulates the channel regions of nanoribbons 120A and 120B from electrode 126 and may be different or substantially similar in transistor structures 101A and 101B. (Nanoribbon 120 may also have other dielectric layers, such as passivation layers on nanoribbons 120A and 120B, and insulating channel regions between nanoribbons 120A and 120B and electrode 126).

[0067] Spacers 147, 148A, and 148B are isolation structures for adjacent gate electrodes 126, for example, having an insulating material (such as a low-k dielectric material). Spacer 148 provides isolation between electrode 126 and body 110. Spacer 147 provides isolation between electrode 126 and body 110, as well as the contact structure 119 above body 110. Dielectric wall 140 allows for independent processing of spacers 148A and 148B for adjacent stacks 121A and 121B, and thus allows for the use of different (e.g., optimized) materials in spacers 148A and 148B. In many embodiments, the dielectric materials of spacers 148A and 148B have mutual etch selectivity.

[0068] As shown in View 107, a first transistor structure 101A includes a first gate electrode 126, wherein a first cavity spacer 148A is provided between the first gate electrode 126 and the source or drain body 110A and between adjacent nanoribbons 120A in structure 101A. As shown in View 109, a second transistor structure 101B includes a second gate electrode 126, wherein a second cavity spacer 148B is provided between the second gate electrode 126 and the source or drain body 110B and between adjacent nanoribbons 120B in structure 101B. In many embodiments, the first cavity spacer 148A and the second cavity spacer 148B have different compositions. In some embodiments, the spacers 148A and 148B have etch selectivity. In some embodiments, the nanoribbons 120A and 120B have different compositions, and the spacers 148A and 148B have different compositions, for example, optimized to serve as cavity spacers 148 for adjacent nanoribbons 120A and 120B with different compositions. For example, spacers 148A and 148B can each be composed of different dielectric materials, selectively deposited during manufacturing on different sacrificial materials between nanoribbons 120A and 120B. In some embodiments, nanoribbon 120A is primarily silicon, and spacer 148A has a dielectric material deposited on SiGe (e.g., the sacrificial material), which is selective for Si, SiOC, SiOCN, and SiO surfaces. In some embodiments, nanoribbon 120B comprises silicon and germanium, and spacer 148B has a dielectric material deposited on Si (e.g., the sacrificial material), which is selective for SiGe surfaces.

[0069] Gate via 129 contacts gate structures 125A and 125B through dielectric layer 149 above transistor structures 101A and 101B. Gate via 129 above transistor structure 101B passes through dielectric layer 144.

[0070] The source and drain contact structure 119 (e.g., via structure 119) is a metallized structure 119 that couples (e.g., electrically couples) a body 110 to an interconnect network (not shown) above transistor structure 101. Contact structure 119 can comprise any suitable material, including non-metallic materials. For example, contact structure 119 can comprise an interface (e.g., silicide) layer on body 110. Structure 119 can comprise multiple layers of metal, such as a pad (e.g., barrier or seed) layer surrounding a filler layer. Contact structure 119 extends through dielectric layer 149 above transistor structures 101A, 101B and through dielectric layer 114 above body 110 and between body 110 and layer 149. Dielectric layers 114 and 149 can be made of any suitable material, such as a low-k dielectric material.

[0071] Figure 2A , Figure 2B and Figure 2C A cross-sectional profile view of an IC device 100 having transistor structures 101A and 101B according to some embodiments is shown. The transistor structures 101A and 101B have gate structures 125A and 125B, which have different gate heights H. C H D And it is separated by a dielectric wall 140. Figure 2A , Figure 2B and Figure 2C It shows, for example, Figure 1A The embodiments shown are similar to those shown, but with significant differences. Figure 2A One embodiment is shown in which the dielectric layer 123 of the gate structure 125A on the sidewalls 141, 142 is higher than the height H. D It extends beyond the gate electrode 126. Figure 2B An embodiment is shown, wherein the height H C H D The upper surfaces of the gate structures 125A and 125B are lower than the height H. E The upper surface of the dielectric wall 140 at that location. Figure 2C An embodiment is shown, wherein the height H C H D The upper surfaces of the gate structures 125A and 125B are higher than the corresponding nanoribbons 120A and 120B, and the nanoribbons 120A and 120B have different heights H. A H B and thickness T A T B .

[0072] Figure 2A Transistor structure 101A is shown, wherein the metal and dielectric layer 123 of the gate electrode 126 in structure 125A (e.g., on sidewalls 141, 142) extends upward to a height H. C In transistor structure 101B, the metal of the gate electrode 126 in structure 125B extends upward to a height H. D The dielectric layer 123 in structure 125B (e.g., on sidewalls 141, 142) extends upward and above height H. D For example, extending upwards to height H C The dielectric layer 123 in structure 125B exists on the sidewalls 141 and 142 above the height H. D The location. In Figure 2A In an exemplary embodiment, the upper surface of the wall 140 between gate structures 125A and 125B (and on both sides of gate structures 125A and 125B) is in a vertical position or at a height H.C (height H) C H D The larger or higher one in the middle.

[0073] View 202 is shown at a greater magnification and shows the dielectric layer 144 above the gate electrode 126 of the gate structure 125B at the sidewall 141 of the dielectric wall 140. The height H of layer 144 above the gate electrode 126 is... C H D Between, extending upwards to height H D The gate electrode 126 includes layers 127 and 128, both of which extend upwards only to a height H. D The gate dielectric layer 123 of the gate structure 125B reaches a height H on the sidewall 141 of the dielectric wall 140. C until it is above height H D Layer 123 is located between dielectric layer 144 and sidewall 141 of dielectric wall 140 (e.g., at height H). C H D between).

[0074] It is worth noting that stack 121B has fewer nanoribbons 120B than stack 121A has nanoribbons 120A. In some embodiments, stack 121A has fewer nanoribbons 120A than stack 121B has nanoribbons 120B. Figure 2A In an exemplary embodiment, the span height H2 is shorter than the span height H1. The stacked bodies 121A and 121B have equal spacing H. Pa H Pb .

[0075] IC device 100 may include or be coupled to a substrate or other host component 299. Host component 299 may be a package substrate, interposer, IC die, etc. For example, substrate 199 may be an IC die including transistor structure 101, substrate 199 may be coupled (e.g., soldered or otherwise bonded) to host component 299, and device 100 and transistor structure 101 may be coupled to a power source (not shown) through host component 299.

[0076] The host component 299 is a planar platform and may include dielectric and metallization structures. The host component 299 mechanically supports and electrically couples one or more IC devices 100. At least one side of the host component 299 includes a substrate interconnect interface for bonding to one or more IC devices 100. The IC device 100 may be directly bonded (e.g., hybrid bonding) to the host component 299 or otherwise bonded (e.g., via optional solder bumps) to the host component 299. The opposite side of the host component 299 may include similar interfaces, such as copper pads for slots and / or solder bumps for bonding the device 100 to a host component such as a printed circuit board (PCB). The host component 299 may be any host component with a substrate interconnect interface, such as a packaged host component 299 or an interposer. The host component 299 itself may be a die. In many embodiments, the host component 299 includes an organic dielectric, such as a resin or other polymer, located between metallization layers.

[0077] Figure 2B It shows that at a height above H C H D The vertical position or height H of both E The upper surface of the wall 140 located between (and to both sides of) the gate structures 125A and 125B. In the transistor structure 101A, the metal of the gate electrode 126 and the dielectric layer 123 in the structure 125A (e.g., on the sidewalls 141, 142) extend upward to a height H. C Height H C Below height H E And higher than height H C The dielectric layer 123 in structure 125A does not exist above height H on the sidewalls 141 and 142. C The position of the gate insulating layer 144A is above the structure 125A at a height H. C H E Between and the height equals the height H C H E The difference. In transistor structure 101B, the metal of gate electrode 126 and the dielectric layer 123 in structure 125B (e.g., on sidewalls 141, 142) extend upward to a height H. D Height H D Below height H C H E Both. The dielectric layer 123 in structure 125B does not exist above height H on the sidewalls 141 and 142. D The position of the gate insulating layer 144B is above the structure 125B, at a height H. D H E Between and the height equals the height H D HE The difference (greater than the height of floor 144A (which is equal to the height H) C H E difference)).

[0078] In many embodiments, height H3 (e.g., the thickness of gate electrode 126 in gate structure 125A) is equal to height H4 (e.g., the thickness of gate electrode 126 in gate structure 125B), for example, where heights H3 and H4 are respectively equal to the minimum permissible thickness of gate electrode 126 above the respective nanoribbons 120A and 120B. In some embodiments, height H3 (e.g., the thickness of gate electrode 126 in gate structure 125A) is less than or shorter than height H4 (e.g., the thickness of gate electrode 126 in gate structure 125B). In some such embodiments, height H... C H D Approximately equal to or lower than height H E For example, there are substantially similar gate insulating layers 144A and 144B above the gate structures 125A and 125B, and the upper surfaces of the layers 144A and 144B are coplanar with the upper surface of the wall 140.

[0079] Figure 2C Transistor structures 101A and 101B are shown, wherein the metal of the gate electrode 126 in structures 125A and 125B extends upward to a height H, respectively. C H D The height H of electrode 126 in structure 125A C The height H of electrode 126 in structure 125B is greater than that of structure 125B. D And through the nanoribbon 120A of the gate structure 125A at a height H A The height H is greater than the corresponding height H of the nanoribbon 120B that passes through the gate structure 125B. B The nanoribbon 120A passing through the gate structure 125A has a thickness T. A Thickness T A The thickness T is greater than the thickness T of the 120B nanoribbon passing through the 125B gate structure. B In other embodiments, the nanoribbon 120B passing through the gate structure 125B has a thickness T. B Thickness T B The thickness T is greater than the 120 Å thickness of the nanoribbon passing through the 125 Å gate structure. A Height H A H B H C H D and thickness T A T BThe difference can be achieved through the dielectric wall 140 between structures 125A, 125B and stacks 121A, 121B.

[0080] Figure 3 This is a flowchart of a method 300 for forming nanoribbon channel and gate structures with different heights and compositions, according to some embodiments. Method 300 includes operations 310-360. Figure 3 Some of the operations shown are optional. Additional operations may be included. Figure 3 An example sequence is shown, but operations can be performed in other orders, and some operations can be omitted. Some operations can also be performed multiple times before other operations are performed. For example, a stack of many dielectric walls and many nanoribbons can be formed before any gate structure is recessed. Some operations can be included within other operations, making... Figure 3 The number of operations shown is not a limitation of method 300.

[0081] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H A outline diagram of an IC device 100 according to some embodiments is shown, the IC device having gate structures of different heights and compositions on nanoribbons of different heights and compositions at different manufacturing stages. Figures 4A-4H It shows in Figure 3 Possible examples of intermediate structures during the implementation of method 300.

[0082] Figure 4A An IC device 100 according to some embodiments is shown. The IC device 100 has a dummy gate 426 located above a first stack 121A and a second stack 121B of alternating first material layers 420A and second material layers 420B in a substrate 199, for example, before performing a formation operation 310. The substrate 199 may include a sub-fin 499 located below one or both of the stacks 121A and 121B. The first material layers 420A and 420B may each have a thickness T. A T B First stack 121 A Second stack 121 B They can be separated by a distance D.

[0083] In many embodiments, the dummy gate 426 comprises tungsten. In many embodiments, the dummy gate 426 comprises polysilicon. The dummy gate 426 is located above, between, and on either side of the first stack 121A and the second stack 121B.

[0084] In many embodiments, one of the first material layer 420A and the second material layer 420B is primarily silicon, and the other of layers 420A and 420B is silicon-germanium. In many embodiments, the thickness T A T B They are approximately equal.

[0085] return Figure 3 Method 300 begins at operation 310, wherein a dielectric wall is formed between a first stack of first material layers and a second stack of second material layers. The first and second stacks of the first and second material layers may be first and second stacks of nanoribbons with the same or different compositions. In many embodiments, after the dielectric wall is formed between the stacks of material layers, the stacks of nanoribbons are formed from the stacks of material layers.

[0086] A first stack and a second stack, wherein the first material layer and the second material layer can be received on or in a substrate (such as an IC die or wafer), for example, such as Figure 1A The substrate 199 is described. Material layer stacks can be formed by any suitable means and with any suitable materials. In many embodiments, a first material layer and a second material layer are deposited in a single stack of semiconductor material layers having mutual etch selectivity, and the stack is cut (e.g., etched) into a plurality of parallel smaller stacks (e.g., fins) of the first and second material layers. In some such embodiments, the smaller stacks or fins of the first and second material layers are cut (e.g., in orthogonal directions) to form more smaller stacks or fins of the first and second material layers aligned on a shared centerline or axis. In many embodiments, some parallel stacks will have alternating complementary conductivity types (e.g., n-type and p-type), and adjacent aligned (e.g., coaxial) stacks or fins include a channel layer that will share a source or drain body grown in a trench between adjacent fins. In many embodiments, the first material layer is primarily silicon (e.g., for an n-type channel), and the second material layer comprises silicon and germanium (e.g., for a p-type channel). In many embodiments, the first material layer is a channel layer in the first stack and a sacrificial layer in the second stack, and the second material layer is a channel layer in the second stack and a sacrificial layer in the first stack.

[0087] Dielectric walls can be formed by any suitable means and with any suitable materials. In many embodiments, forming dielectric walls involves opening (e.g., etching) cavities through the first dielectric material (e.g., in trenches between pairs of first and second stacks of the first and second layers, e.g., beyond the ends of the first and second stacks of the first and second layers). The etching can be anisotropic etching (e.g., plasma etching on lines parallel to the layers and stacks). The etching can have a minimum width, e.g., 15 nm or less. The etch width can be less than one-third of the height of the layer stack. The etched (and subsequent dielectric wall) sidewalls can be nearly vertical, e.g., separated by only slightly different upper and lower widths (e.g., in a tapered profile that tapers slightly upwards or downwards). For example, the upper and lower widths can be within 1 nm. In many embodiments, the etching has a minimum width of 12 nm or less, which allows for sufficiently tight encapsulation of the material layer stack and savings in subsequent layout area. In some embodiments, the etching has a minimum width of 10 nm or less, which allows for excellent encapsulation of the material layer stack and savings in layout area. Such a small width and tight layout of material layer stacks can be achieved through fine, high aspect ratio etching (e.g., through dummy gates).

[0088] The first dielectric material can be in a plurality of parallel trenches, wherein each pair of adjacent parallel trenches has a pair of stacks (e.g., many, many stacks of the first and second layers). Etching can be performed through the plurality of parallel trenches to open a plurality of cavities, for example, these parallel trenches extending substantially parallel to and beyond the ends of the first and second stacks of the first and second material layers (e.g., having cavities longer than the material layers). A dummy gate can be located above the first and second stacks (e.g., having the first dielectric material to all sides) and can extend in a direction substantially orthogonal to the first and second stacks of the first and second material layers, and can be etched through the dummy gate having the first dielectric material and through the spacer dielectric on the sidewalls of the dummy gate, etching cavities between the dummy gate and the trenches of the first dielectric material.

[0089] Dielectric walls can be formed by depositing a second dielectric material in an etched cavity (parallel to the material layers and stack). These dielectric walls can be formed concurrently with many other dielectric walls, for example, parallel dielectric walls on both sides of many parallel material layers and stacks, all formed by concurrent etching and concurrent dielectric deposition. Concurrent wall formation allows each material layer stack to be tightly surrounded or secured by a pair of dielectric walls. Each dielectric wall can have opposing first and second sidewalls, wherein a first portion of the dummy gate is on the first sidewall, and a second portion of the dummy gate is on the second sidewall.

[0090] Excess deposited second dielectric material (e.g., above the dummy gate, which is now divided into multiple sections by dielectric walls) can be removed by chemical mechanical planarization or polishing (CMP). Such CMP can planarize (or achieve a shared height) the upper surface of the substrate, including the upper surface of the dielectric walls and the dummy gates on both sides of the dielectric walls. Each dielectric wall may have an upper surface between a first sidewall and a second sidewall, which is flush with the upper surfaces of the dummy gates on both sides of the dielectric wall.

[0091] The dielectric wall can comprise any suitable dielectric material, such as a material having etch selectivity with adjacent materials. For example, the deposited second dielectric material advantageously has good etch selectivity with the first dielectric material in the trench at the end of the material layer stack and the sacrificial material of the dummy gate, after which both the first dielectric material and the sacrificial material can be removed while retaining the dielectric wall. Spacer dielectric material can also be retained. Advantageously, the deposited (e.g., second) dielectric material is a low-k dielectric material. In many embodiments, the second dielectric material is deposited, for example, using CVD (chemical vapor deposition) or ALD (atomic layer deposition) to deposit silicon and nitrogen. The deposited second dielectric material can be an isolation structure (e.g., a dielectric wall), such as... Figure 1A The wall 140 is described.

[0092] The processing "slots" can be formed by dielectric walls, wherein each slot contains a material stack and is separated from similar adjacent slots by the dielectric walls. The slots can be independent processing spaces, for example, where a first slot (and material stack) can be processed separately from a second slot (and material stack), for example, the first and second slots are isolated from each other by dielectric walls. In many embodiments, the dielectric walls form separate first and second slots, wherein the first slot has a first material layer stack (e.g., nanoribbons) and the second slot has a second material layer stack (e.g., nanoribbons), for example, where each slot is located between a pair of adjacent dielectric walls. In some embodiments, neither the first nor the second slot includes a third nanoribbon stack (or other material layer stack), for example, the first nanoribbon stack (and no other nanoribbon stacks) is in the first slot, and the second nanoribbon stack (and no other nanoribbon stacks) is in the second slot. The independent processing slots (or groups of slots) can be accessed by (e.g., photolithographically) patterning a mask layer over a substrate, wherein the mask openings are located over the slot to be processed. Dielectric walls (and sufficient spacing between them) enable the individual processing of adjacent material stacks, while allowing for even significant mask edge placement errors. Mask layers can be removed and repatterned as needed to access the same or different processing blocks (e.g., for specific processing operations in slot groups).

[0093] As described, dielectric walls can be formed by a dummy gate over a stack of first and second material layers. The stack of first and second material layers can be between corresponding pairs of dielectric walls and in corresponding first and second trenches, for example, also including corresponding first and second portions of the dummy gate. The dummy gate can be grown by any suitable means. In some embodiments, the stack of first and second material layers is received as a stack of first and second nanoribbons, and the dummy gate is formed by depositing metal (or other material) over and between the nanoribbons in the first stack and between the nanoribbons in the second stack. In some such embodiments, the metal or other material is deposited on and above a protective (e.g., passivation) interface layer over the nanoribbons. In some embodiments, the deposited metal is tungsten. The dummy gate can be any suitable material, for example, a material that can be etched by high aspect ratio etching. In some embodiments, polysilicon is deposited as the dummy gate.

[0094] For example, an interface layer may be formed (e.g., grown) over the nanoribbon before the formation of the dummy gate and, depending on the dummy gate material. The interface layer may be between the nanoribbon and the subsequently deposited dummy gate. The interface layer may be, for example, a protective layer that protects the nanoribbon from subsequent processing. For example, the interface layer may be a passivation layer (e.g., a passivation layer of native oxide) that protects the nanoribbon from subsequent deposition (and removal etching) of the dummy gate. Each nanoribbon may be covered by a thin interface (e.g., passivation) layer separate from the other nanoribbons and the interface layer. In many embodiments, the interface layer comprises oxygen. In many embodiments, the interface layer is on a nanoribbon comprising silicon, and the interface layer comprises oxygen and silicon. The interface layer can be grown by any suitable means. In some embodiments, the interface layer is grown by exposure to oxygen (e.g., using ozone treatment).

[0095] Figure 4B An IC device 100 according to some embodiments is shown, which has a dielectric wall 140 in the material between and on the sides of the stacks 121A, 121B of material layers 420A, 420B and through the dummy gate 426, for example, after performing a formation operation 310. The first upper surface 427A (of the dummy gate 426 above the first stack 121A of the first material layer 420A), the second upper surface 427B (of the dummy gate 426 above the second stack 121B of the second material layer 420B), and the third upper surface 427C (of the dielectric wall 140) are all planarized to the same height H. C .

[0096] The dielectric wall 140 has a width W1 (or width W2) that separates the sidewalls 141 and 142. The dielectric wall 140 (e.g., sidewalls 141 and 142) can be nearly vertical. In many embodiments, the dielectric wall 140 has only slightly different widths W1 and W2 (e.g., in a tapered profile that tapers slightly upwards or downwards). For example, widths W1 and W2 can be within 1 nm. Width W1 is defined as the width of the wall 140 at the top of the wall 140. Width W2 is defined as the width of the wall 140 at the bottom of the gate 426, for example, where the wall 140 contacts the substrate 199 at the bottom of the gate 426. In many embodiments, the dielectric wall 140 has a minimum width W2 (or width W1, etc.) of 12 nm or less, which allows for sufficiently compact packaging of the stack bodies 121A and 121B and subsequent savings in layout area. In some embodiments, the dielectric wall 140 has a minimum width W2 (or width W1, etc.) of 10 nm or less, which enables excellent packaging and layout area savings for the stacks 121A, 121B. This compact layout of the stacks 121A, 121B (with small widths W1, W2, and) can be achieved through fine, high aspect ratio etching (e.g., through and between gates 426).

[0097] The close packing of the stacks 121 can also be characterized by a small distance D separating the first stack 121A and the second stack 121B of the material layers 420A and 420B. In many embodiments, the distance D is less than three times the maximum width W1 of the wall 140. For example, if the wall 140 is centered between the stacks 121 and within the distance D, then the wall 140 is less than the width W1 from either stack.

[0098] return Figure 3 Method 300 continues at operation 320, wherein a stack of first and second nanoribbons is formed. In many embodiments, the stack of nanoribbons is formed (e.g., released) from a stack of material layers, wherein dielectric walls are present between the stacks. In many embodiments, each material layer stack (in a trench) is between a pair of dielectric walls, and the dielectric walls enable the independent processing of the material layer stacks, including the release of nanoribbons from the material layer stacks. The independent processing of the dielectric walls and each material layer stack further enables the release of nanoribbons in adjacent stacks but with different heights, compositions, and / or thicknesses. For example, similar first and second stacks of first and second material layers on a first and second side of the dielectric walls can be processed independently to produce a stack of first nanoribbons from a first material layer on a first side of the dielectric walls and a stack of second nanoribbons from a second material layer on a second side of the dielectric walls.

[0099] In embodiments having a first material layer on a second material layer (e.g., within each pair of alternating first and second material layers), the resulting first nanoribbon in the first stack has a first height higher than the second nanoribbon in the second stack. In many embodiments, the stack forming the first and second nanoribbons forms a first stack or group of first nanoribbons having a first height and a second stack or group of second nanoribbons having second heights interspersed with the first stacks of the first height. For example, each of the first nanoribbon and its corresponding first height is higher (e.g., at a higher height) than each corresponding second nanoribbon and its corresponding second height (e.g., where each second nanoribbon has a second height between a pair of first heights of the first nanoribbons above and below).

[0100] Stacks of the first and second nanoribbons can be formed in a similar manner and by similar means, simultaneously or sequentially (e.g., independently). Although this disclosure describes processing a first material layer stack and then describes processing a second material layer stack, the stacks can be processed together (or in reverse order, or after another operation in a set of operations, etc.). Although this disclosure describes releasing and retaining the first material layer in the first material layer stack and the second material layer in the second material layer stack (as nanoribbon channel layers) (and removing the second material layer in the first material layer stack and the first material layer in the second material layer stack as sacrificial layers), other configurations of the material layers can be retained and further processed.

[0101] The first stack forming the first nanoribbon may include opening a first (e.g., trench) cavity on a first side of the dielectric wall. In many embodiments, opening the first cavity exposes the sidewalls of a first material layer and a second material layer within the first cavity (e.g., in a first material stack). Exposing the sidewalls of the first and second layers in the first stack makes the material layers available for further processing, while the first and second layers in the second stack may retain a mask (e.g., by dummy gate material) on a second side of the dielectric wall.

[0102] The first cavity can be opened by any suitable means, for example, by patterning a rigid mask layer over a substrate using a mask opening over the first material layer stack and by isotropically (e.g., selectively) removing dummy gate material in a trench between a pair of dielectric walls. Exposure etching can expose other first material layer stacks to be processed concurrently (e.g., while leaving the second material layer stack masked).

[0103] The first stack forming the first nanoribbon may include releasing a first material layer in the first material layer stack, for example by selectively removing a second material layer between the first material layers in the first stack. A channel material layer to be retained (e.g., a first or second material layer in a given stack coupled to the corresponding source and drain bodies) may be released by removing a sacrificial material layer adjacent to the channel material layer (e.g., between channel material layers in the same stack as the channel material layer). Separating the dielectric walls of the first and second stacks allows for the individual release of the channel material layer and removal of the sacrificial material layer in different stacks, including retaining the first material and removing the second material in the first stack and retaining the second material and removing the first material in the second stack.

[0104] The sacrificial material layer can be removed by any suitable means, such as selective etching with etch selectivity between the first and second material layers. Removing different material layers on different sides of the dielectric wall can result in offset and staggered heights in the first and second stacks of adjacent channel material layers (e.g., nanoribbons).

[0105] With the first slot open, in some embodiments, further processing of the first stack can continue before processing (e.g., forming) the second stack. In some embodiments, the first nanoribbon in the first stack is thinned before forming the second nanoribbon in the second stack (e.g., at operation 330). In some embodiments, a first gate structure is formed over the first nanoribbon in the first stack before forming the second nanoribbon in the second stack (e.g., at operation 340).

[0106] In some embodiments, the first stack is covered (and the first trench is filled) with a dummy gate or other sacrificial material to, for example, facilitate further processing of the second stack. A dummy gate material (e.g., a metal) may be deposited over and between the first nanoribbons. In some embodiments, an interface layer is formed (e.g., grown) on the first nanoribbons before the dummy gate material is deposited in the first trench. The sacrificial material may protect the deposited layer and the nanoribbons. In some embodiments, the sacrificial material comprises carbon (e.g., in a carbon hard mask). In some embodiments, the sacrificial material is cured with nitrogen.

[0107] A patterned hard mask layer over the substrate (e.g., covering a second stack but having an opening over the first stack) can be removed for subsequent processing. In some embodiments, the hard mask layer over the gate trench is removed by one or more isotropic etching and / or CMP. Such etching or CMP can planarize the upper surface of the substrate (e.g., recess and substantially flush with a single shared height), including the upper surface of the dielectric wall and sacrificial material to both sides of the dielectric wall.

[0108] The second stack forming the second nanoribbon may include opening a second (e.g., a trench) cavity on a second side of the dielectric wall. Opening the second cavity on the second side of the dielectric wall can be very similar to opening the first cavity on the first side of the dielectric wall; for example, exposing the sidewalls of the first and second material layers in the second cavity of the second material stack and making them available for further processing. The second cavity can be opened by any suitable means, such as by patterning a mask opening above the second material layer stack and by selectively removing dummy gate material. Exposure etching can expose other second material layer stacks to be processed concurrently (e.g., while leaving the first material layer stack masked).

[0109] The second stack forming the second nanoribbon may include releasing a second material layer in the second material layer stack, for example, by selectively removing a first material layer between the second material layers in the second stack. The sacrificed (e.g., the first) material layer can be removed by any suitable means, such as selective etching between the first and second material layers (e.g., using different etchants to remove the first material layer and retain the second material layer). Removing different material layers on different sides of the dielectric wall can result in adjacent first and second channel material layer stacks (e.g., nanoribbons) having offset and staggered heights.

[0110] Figure 4C An IC device 100 with a stack 121A having a first nanoribbon 120A in a gate trench 425A according to some embodiments is shown, for example, after performing a formation operation 320. The nanoribbon 120A in the stack 121A is released (e.g., there is no sacrificial material layer 420B on and between the nanoribbon 120A). Access to the stack 121A and the gate trench 425A is possible through patterned openings 410A in the mask layer 450. There is no dummy gate 426 in the trench 425A. The nanoribbon 120A and the sidewalls 141, 142 (of the dielectric wall 140) are exposed in the gate trench 425A, for example, and can be processed.

[0111] Material layers 420A and 420B in stack 121B are kept masked below mask layer 450 and between dummy gate 426 between sidewalls 141 and 142 of dielectric wall 140.

[0112] return Figure 3 Method 300 continues by thinning a first or second (e.g., channel) material layer at operation 330. Separate first and second (e.g., trench) cavities may enable thinning of one or the other of the first or second material layer in only one of the first and second cavities, but layers in both the first and second cavities (and the first and second stacks) may be thinned. The first or second (e.g., channel) material layer may be thinned by any suitable means, such as isotropic etching. In some embodiments, layer thinning may be performed concurrently with the removal of a sacrificial material layer (e.g., by over-etching). In some embodiments, the first nanoribbon is thinned to a first thickness less than the second thickness of the second nanoribbon. In some embodiments, the second nanoribbon is thinned to a first thickness less than the second thickness of the first nanoribbon.

[0113] Method 300 continues by forming a first gate structure and a second gate structure over the stack of the first and second nanoribbons at operation 340. The first gate structure may include a first insulating layer and a first metal electrode, and the stack of the first nanoribbons may extend through the first gate structure. The second gate structure may include a second insulating layer and a second metal electrode, and the stack of the second nanoribbons may extend through the second gate structure. In many embodiments, forming the first gate structure includes depositing a first insulating layer on a first sidewall or sidewall of a dielectric wall and on the stack of the first nanoribbons. In many embodiments, forming the second gate structure includes depositing a second insulating layer on a second sidewall or sidewall of a dielectric wall and on the stack of the second nanoribbons.

[0114] The first and second gate structures can be formed in a similar manner and by similar means, simultaneously or sequentially (e.g., independently). Although this disclosure describes processing the first gate structure and then the second gate structure, the stack can be processed together (or in reverse order, or one after another in multiple sets of operations, etc.). For example, after some gate formation operations in the first (or second) gate trench, the first (or second) gate trench can be filled with sacrificial material for processing the second (or first) gate trench, and then the second (or first) gate trench can be filled with sacrificial material for processing the first (or second) gate trench, etc. Forming the first (or second) gate structure can include removing sacrificial material from the first (or second) gate trench, which can be as described. Different sacrificial materials (and different operations for removing sacrificial material) can be used at different operations within method 300. Although this disclosure may describe certain gate configurations, other configurations (e.g., the number or composition of material layers) can be deployed.

[0115] Forming the first gate structure may include removing an interface (e.g., passivation) layer from the first nanoribbon in the stack. The interface layer can be removed by any suitable means. In many embodiments, the interface layer is removed, for example, by etching with hydrofluoric acid (e.g., dilute hydrofluoric acid (DHF)) after ozone treatment.

[0116] Forming the first gate structure may include forming a first dielectric stack on the first nanoribbon in a stack of first nanoribbons. The first dielectric stack may be formed by any suitable means. In many embodiments, a first dielectric layer is grown on the first nanoribbon in the stack of first nanoribbons. In many embodiments, a first insulating layer is deposited on the first dielectric layer grown on the first nanoribbon in the stack of first nanoribbons. In some embodiments, a dipole dopant is deposited on the first dielectric layer on the first nanoribbon or on the first insulating layer on the first dielectric layer.

[0117] The first dielectric layer grown on the stack of first nanoribbons can resemble an interface layer, such as a native oxide or passivation layer grown from the nanoribbons. The first dielectric layer can be formed by any suitable means and has any suitable material. Figure 1A As described in layer 122A, the first dielectric layer on the stack of the first nanoribbons may, for example, have silicon and oxygen and a thickness T1. Although the first dielectric layer may resemble an interface layer (e.g., as described at operation 310, etc.), the first dielectric layer may be grown in a more controlled manner, for example, with a precise and controlled thickness. In some embodiments, the first dielectric layer is grown from the first nanoribbons, and a portion of the thickness of the first dielectric layer is consumed from the thickness of the first nanoribbons. A thicker first dielectric layer may correspond to a further thinned first nanoribbon. In many embodiments, ozone treatment is used to grow the first dielectric layer on the stack of the first nanoribbons.

[0118] A first insulating layer can be deposited on a first dielectric layer on a first nanoribbon. In many embodiments, the deposited first insulating layer is a high-k dielectric layer. Figure 1A As described in layer 123A, the first insulating layer may, for example, have oxygen and hafnium and / or zirconium, and a thickness T3. The first insulating layer can be formed by any suitable means and has any suitable material. In many embodiments, the first insulating layer is deposited on the first dielectric layer on the first nanoribbon by an ALD, which can conformally deposit the first insulating layer in the first gate trench (and over the entire substrate). In many embodiments, the first insulating layer is deposited on a first side of the dielectric wall (e.g., a first sidewall). The ALD (or another suitable deposition method) can deposit the first insulating layer in a highly controlled manner and to a precise and controlled thickness.

[0119] A dipole dopant can be deposited on a first dielectric layer on the first nanoribbon or on a first insulating layer on the first dielectric layer. In some embodiments, annealing (e.g., at a high temperature) is performed, for example, to drive the dipole dopant into the first dielectric layer or the first insulating layer on the first dielectric layer. The dipole dopant can be in the first dielectric layer (e.g., at a depth between a first interface between the first nanoribbon and the first dielectric layer and a second interface between the first dielectric layer and the first insulating layer, including an endpoint) or in or on the first insulating layer (e.g., at a depth between a second interface between the first dielectric layer and the first insulating layer and an outer surface of the first insulating layer, including an endpoint). Annealing (e.g., driving the dipole dopant into either layer) can be performed at any suitable point during method 300, for example, before or after depositing an insulating layer on the second nanoribbon in a stack of second nanoribbons. Individual annealing (e.g., performed only on the first insulating layer on the first nanoribbon in the stack of first nanoribbons) can drive the dipole dopant into the first dielectric stack of the first nanoribbon at a depth different from that in the dielectric on the second nanoribbon.

[0120] Forming the first gate structure may include depositing a first metal layer on a first dielectric stack. The first metal layer may be, for example, a cover layer to prevent further processing of the dielectric stack. In many embodiments, the first metal layer is a WFM layer. Figure 1A As described in layer 127 of the first gate structure 125A, the first metal layer may, for example, have a thickness T5. The first metal layer can be formed by any suitable means and has any suitable material, including non-metallic materials. In many embodiments, the first metal layer comprises nitrogen (e.g., in a metal nitride). In some embodiments, the first metal layer comprises titanium and nitrogen (e.g., in a titanium nitride). In many embodiments, the first metal layer is deposited by CVD or ALD.

[0121] Forming the first gate structure may include depositing a filler metal layer over a first metal layer on a stack of first nanoribbons, for example, completing the first gate electrode and the first gate structure such that the first stack of first nanoribbons extends through the first gate structure. The filler metal layer may be formed by any suitable means and has any suitable material, including non-metallic materials. The filler metal layer and the first gate electrode may be respectively... Figure 1A The layers 128 and electrodes 126 in the transistor structure 101A are described very similarly.

[0122] The first cavity or gate trench can be filled with a sacrificial material or dummy material, for example, to cover a deposited gate structure layer of the partially formed gate structure during further processing. The sacrificial material can help retain the deposited layer adjacent to the nanoribbon while allowing the layer to be removed elsewhere, such as on a hard mask layer above the gate trench. In some embodiments, the sacrificial material comprises carbon (e.g., in a carbon hard mask). In some embodiments, the sacrificial material is cured with nitrogen. In some embodiments, the sacrificial material is or comprises a metal. In some embodiments, the deposited layer on the hard mask layer above the gate trench is removed by one or more isotropic etchings and / or CMP. Such etching or CMP can planarize the upper surface of the substrate, including the upper surface of the dielectric wall and (e.g., sacrificial) material on either side of the dielectric wall.

[0123] Forming the second gate structure may include removing an interface (e.g., passivation) layer from the second nanoribbon stack, which may be done in any suitable manner and may be similar to removing an interface (e.g., passivation) layer from the first nanoribbon stack, for example, except on the second nanoribbon stack. In many embodiments, the interface layer is removed by hydrofluoric acid etching.

[0124] Forming a second gate structure may include forming a second dielectric stack on the second nanoribbon within a stack of second nanoribbons. Forming the second dielectric stack can be similar to forming the first dielectric stack, for example, except on the stack of second nanoribbons. It is noteworthy that forming the second dielectric stack on the stack of second nanoribbons can be done with different materials, to different sizes, etc., and the second dielectric stack can have different properties than the first dielectric stack. The second dielectric stack can be formed by any suitable method. In many embodiments, a second dielectric layer is grown on the second nanoribbon within a stack of second nanoribbons. In many embodiments, a second insulating layer is deposited on the second dielectric layer on the second nanoribbon within a stack of second nanoribbons. In some embodiments, a dipole dopant is deposited on the second dielectric layer on the second nanoribbon or on the second insulating layer on the second dielectric layer.

[0125] The second dielectric layer can be formed on the second nanoribbon by any suitable means and can be made of any suitable material. For example... Figure 1A As described in layer 122B, the second dielectric layer on the stack of the second nanoribbons can, for example, have silicon and oxygen and a thickness T2. It is noteworthy that the second dielectric layer formed on the second nanoribbon can have a different thickness or material composition than the first dielectric layer formed on the first nanoribbon.

[0126] A second insulating layer can be deposited on the second dielectric layer on the second nanoribbon. In many embodiments, the second insulating layer is a high-k dielectric layer. For example... Figure 1A As described in layer 123B, the second insulating layer may, for example, have oxygen and hafnium and / or zirconium, and a thickness T4. The second insulating layer may be formed by any suitable means and have any suitable material. It is worth noting that the second insulating layer formed over the second nanoribbon may have a different thickness or material composition than the first insulating layer formed over the first nanoribbon.

[0127] Dipole dopants can be deposited on a second dielectric layer grown on or above a second insulating layer of the second nanoribbon. Notably, the dipole dopants deposited above the second nanoribbon can have the same or different material as the dopants deposited above the first nanoribbon, and can be deposited at different concentrations or thicknesses or driven into different depths within the corresponding second dielectric stack.

[0128] Forming the second gate structure may include depositing a second metal layer on the second dielectric stack. Forming the second metal layer can be similar to forming the first metal layer, for example, except that it is on the second dielectric stack. Importantly, the formation of the second metal layer on the second dielectric stack can be done with different materials, to different sizes, etc., and the second gate structure can have different properties than the first gate structure. For example, the second metal layer may be a capping layer protecting the second dielectric stack from further processing. In many embodiments, the second metal layer is a WFM layer. Figure 1A As described in layer 127 of the second gate structure 125B, the second metal layer may, for example, have a thickness T6. The second metal layer can be formed by any suitable means and has any suitable material, including non-metallic materials. In many embodiments, the second metal layer comprises nitrogen. In some embodiments, the second metal layer comprises titanium and nitrogen.

[0129] Forming the second gate structure may include depositing a filler metal layer over a second metal layer on a stack of second nanoribbons, for example, completing the second gate electrode and the second gate structure such that the second stack of second nanoribbons extends through the second gate structure. The filler metal layer may be formed by any suitable means and has any suitable material, including non-metallic materials. The filler metal layer and the second gate electrode may be respectively... Figure 1ALayer 128 and electrode 126 in transistor structure 101B are described very similarly. Dielectric walls can be retained, and the first gate structure and the second gate structure can be separated by the dielectric walls. The first gate electrode and the second gate electrode (including a first fill metal and a second fill metal) can be formed of the same or different materials, for example, having the same or different layers 127, 128. In some embodiments, the fill metal layers in the first gate electrode and the second gate electrode are formed concurrently, for example, deposited on different first WFM pad layers and second WFM pad layers on the first nanoribbon and the second nanoribbon in the open first gate trench and the second gate trench.

[0130] Figure 4D An IC device 100 with a gate structure 125A (including a gate insulating layer 123A on sidewalls 141, 142) located above a nanoribbon 120A is shown, for example, after performing a formation operation 340. The first upper surface 427A (of the structure 125A above the first stack 121A of the channel material layer nanoribbon 120A), the second upper surface 427B (of the dummy gate 426 above the second stack 121B of the second material layer 420B), and the third upper surface 427C (of the dielectric wall 140) are all planarized to a height H. C .

[0131] The first gate structure 125A includes a first dielectric stack 124A on a first nanoribbon 120A, and the structure 125A includes a gate electrode 126, wherein the dielectric stack 124A is located between the electrode 126 and the nanoribbon 120A. The first dielectric stack 124A includes a gate dielectric layer 122A on the nanoribbon 120A and a gate insulating layer 123A surrounding the nanoribbon 120A on layer 122A. The gate electrode 126 includes a metal layer 128 on a pad layer 127 located on layer 123A. The insulating layer 123A is on the sidewalls 141, 142 of the dielectric wall 140 surrounding the structure 125A. In the gate structure 125A, the metal layer 127 is on the insulating layer 123A on the sidewalls 141, 142. Although Figure 4D (or Figures 1A-1C , Figures 2A-2C (etc.) are not shown, but in some embodiments, the sub-fin 499 may be below the gate structure 125A (etc.), and the lower surface of the gate structure 125 may be on either side of the sub-fin 499, for example, wherein the sub-fin 499 forms a notch in the structure 125 between the lower surfaces of the gate structure 125.

[0132] Figure 4EAn IC device 100 is shown according to some embodiments of a stack 121B having a second nanoribbon 120B in a gate trench 425B, for example, after performing formation operations 320 and 340. The nanoribbon 120B in the stack 121B is released (e.g., there is no sacrificial material layer 420A on and between the nanoribbon 120B). Access to the stack 121B and the gate trench 425B is possible through patterned openings 410B in the mask layer 450. A dummy gate 426 is not present in the trench 425B. The nanoribbon 120B and the sidewalls 141, 142 of the dielectric walls 140 are exposed in the gate trench 425B, for example, for processing. The gate structure 125A is above the nanoribbon 120A in the stack 121A, covered by the mask layer 450 and between the dielectric walls 140.

[0133] exist Figure 4E In an exemplary embodiment, the first nanoribbon 120A is primarily silicon, and the second nanoribbon 120B comprises silicon and germanium. The first nanoribbon 120A is coupled to a source and drain body (not shown) that is primarily silicon, and the second nanoribbon 120B is coupled to a source and drain body (not shown) comprising silicon and germanium. The first nanoribbon 120A is at a high H A H A The corresponding height H above the second nanoribbon 120B B For example, the first nanoribbon 120A is at a height of H A1 H A2 H A3 H A4 Each of them is higher than the corresponding height H of the second nanoribbon 120B. B1 H B2 H B3 H B4 The first stack 121A of nanoribbon 120A has a height H1, which is equal to the height H2 of the second stack 121B of the second nanoribbon 120B.

[0134] Figure 4F An IC device 100 with a gate structure 125B (including a gate insulating layer 123B on sidewalls 141, 142) located above a nanoribbon 120B is shown, for example after performing a formation operation 340. The first upper surface 427A (of the structure 125A above the first stack 121A of the channel material layer nanoribbon 120A), the second upper surface 427B (of the structure 125B above the first stack 121B of the channel material layer nanoribbon 120B), and the third upper surface 427C (of the dielectric wall 140) are all at a height H. C The area was flattened.

[0135] The second gate structure 125B includes a second dielectric stack 124B on the second nanoribbon 120B, and the structure 125B includes a gate electrode 126, wherein the dielectric stack 124B is located between the electrode 126 and the nanoribbon 120B. The second dielectric stack 124B includes a gate dielectric layer 122B on the nanoribbon 120B and a gate insulating layer 123B surrounding the nanoribbon 120B on layer 122B. The gate electrode 126 includes a metal layer 128 located on a pad layer 127 located on layer 123B. The gate electrode 126 in the gate structure 125B (e.g., layers 127, 128) may have a different composition than the electrode 126 in the gate structure 125A. The insulating layer 123B is located on the sidewalls 141, 142 of the dielectric wall 140 surrounding the structure 125B. In the gate structure 125B, the metal layer 127 is on the insulating layer 123B on the sidewalls 141 and 142.

[0136] exist Figure 4F In an exemplary embodiment, layers 123A and 123B comprise hafnium, zirconium, and oxygen in different elemental ratios. The pad layer 127 of the gate structures 125A and 125B is a WFM layer 127 with a different composition, for example, to independently influence the threshold voltage V. T In some embodiments, at least some of the corresponding layers (e.g., layers 122, 123, and 127) of structures 125A and 125B have different thicknesses.

[0137] return Figure 3 Method 300 continues at operation 350 by planarizing the surface of the substrate to a first height. For example, planarizing the surface of the substrate to the first height can planarize or flush with the first upper surface above the first stack of the first nanoribbons, the second upper surface above the second stack of the second nanoribbons, and the third upper surface of the dielectric wall to the same height or level. In many embodiments, planarizing the surface of the substrate planarizes the first upper surface of the first gate structure above the stack of the first nanoribbons, the second upper surface of the second gate structure above the stack of the second nanoribbons, and the third upper surface of the dielectric wall. Planarization can flush the first, second, and third surfaces to the same first height above the first and second nanoribbons. In some embodiments, for example, when planarization is performed prior to forming the second gate structure, the upper surfaces of the dielectric wall and the first gate structure are planarized. Planarization can be performed in any suitable manner. In many embodiments, planarization is performed by CMP.

[0138] Method 300 continues at operation 360 by recessing the surface of the first gate structure or the second gate structure downward to a second height below a first height of the upper surface of the dielectric wall. In many embodiments, the upper surface of the second gate structure (e.g., the upper surface of the gate electrode (e.g., the gate metal) of the second gate structure) is recessed to a second height below the first height of the dielectric wall and the upper surface of the first gate structure. In some such embodiments, the recess of the upper surface of the second gate structure causes the second dielectric layer of the second gate structure to be recessed downward to a second height below the first height. In other embodiments, the recess of the upper surface of the second gate structure causes the upper surface of the metal (e.g., the gate electrode) of the second gate structure to be recessed to a second height below the first height, but the second dielectric layer is held on the sidewall or sidewall of the dielectric sidewall surrounding the second gate structure (e.g., on both sides thereon) and in contact with the second gate structure.

[0139] One or both of the first gate structure and the second gate structure may be recessed, for example, independently of the other gate structure, such as by separating the gate structures by dielectric walls. In some embodiments, both the first gate structure and the second gate structure are recessed downward to a second height below a first height of the upper surface of the dielectric wall. In some embodiments, the first gate structure (e.g., the corresponding gate electrode) is recessed downward to a second height below the first height of the upper surface of the dielectric wall, and the second gate structure (e.g., the corresponding gate electrode) is recessed downward to a third height below the second height of the first gate structure.

[0140] The recess in the gate structure can be lowered to any suitable height (e.g., depth) below the first height (e.g., the upper surface of the dielectric wall). In many embodiments, recessing the upper surface of the gate electrode of the second gate structure downwards to a second height below the first height results in the gate electrode of the second gate structure being recessed to the thickness of the uppermost second nanoribbon, which is equal to the thickness of the gate electrode (e.g., gate metal) of the first gate structure above the uppermost first nanoribbon. (If the thickness is within 1 nm, the thicknesses of the gate metal or electrode of the first and second gate structures can be considered equal.) For example, the recess can make the difference between the first thickness (equal to the difference between the height of the uppermost first nanoribbon and the height of the upper surface of the gate electrode of the first gate structure at the first height) and the second thickness (equal to the difference between the height of the uppermost second nanoribbon and the height of the upper surface of the gate electrode of the second gate structure at the second height) zero (or minimize). A recess can reduce parasitic capacitance (e.g., between the second gate structure and adjacent structures such as source or drain epitaxial bodies and other gate electrodes), but the recess can be constrained by a minimum limit on the thickness of the corresponding gate electrode above the corresponding nanoribbon.

[0141] Recessing the gate structure to a second height below the first height can be achieved by any suitable means. The first or second gate structure can be recessed by selective isotropic etching of the respective gate structure. In many embodiments, recessing the first or second gate structure includes depositing a mask layer above the dielectric wall and the planarized upper surface of the first and second gate structures, and forming an opening in the mask layer above the second gate structure. In many embodiments, recessing the first or second gate structure includes wet and / or dry etching the gate electrode of the respective first or second gate structure to the second height. In some embodiments, recessing the first or second gate structure includes multiple etching operations. In some such embodiments, a first etching of the first or second gate structure recesses the gate electrode of the first or second gate structure, and a second etching of the first or second gate structure recesses the respective first or second gate insulating layer, for example, by removing the respective first or second gate insulating layer from the sidewall of the dielectric wall surrounding the respective first or second gate structure (e.g., above the second height).

[0142] An isolation layer of dielectric material can be deposited over one or both gate structures, for example, later contacted via a contact via.

[0143] Figure 4G An IC device 100 with a gate structure 125B according to some embodiments is shown, the gate structure 125B having a height H D The upper surface at point 427B has a height of H. D The height H below the upper surfaces 427A and 427C of the gate structure 125A and dielectric wall 140 C For example, after performing a 360-degree indentation operation.

[0144] Above the nanoribbon 120A, the metal of the gate electrode 126 in the dielectric layer 123A (e.g., on the sidewalls 141, 142) and structure 125A extends upward to a height H. C Above the nanoribbon 120B, the metal of the gate electrode 126 in the dielectric layer 123B (e.g., on the sidewalls 141, 142) and structure 125B extends upward to a height H. D The dielectric layer 123B in structure 125B does not exist above height H on sidewalls 141 and 142. D The position. (The second upper surface 427B of the structure 125A above the first stack 121B of the channel material layer nanoribbon 120B is at a height H.) DThe first upper surface 427A (of the structure 125A above the first stack 121A of the channel material layer nanoribbon 120A) and the third upper surface 427C (of the dielectric wall 140) at height H C The area was flattened.

[0145] Height H C The uppermost nanoribbon in nanoribbon 120A is offset by a vertical (span or distance or) height H3, and the height H D Offset from the uppermost nanoribbon in nanoribbon 120B to a vertical (span or distance or) height H4. Figure 4G In exemplary embodiments, the vertical spans or heights H3 and H4 are equal. For example, the thickness of the gate structure 125A on the uppermost nanoribbon 120A (between the uppermost nanoribbon 120A and the upper surface 427A) is equal to the thickness of the gate structure 125B on the uppermost nanoribbon 120B (between the uppermost nanoribbon 120B and the upper surface 427B). In other embodiments, the height H3 is greater than the height H4. For example, the thickness of the gate electrode 126 in the gate structure 125A is set by CMP, and the thickness of the gate electrode 126 in the gate structure 125B is minimized by trench etching. In some embodiments, the height H3 is less than or shorter than the height H4. For example, the upper surface 427B of the gate electrode 126 in the gate structure 125B is conservatively etched from the height H4. D It is concave downwards.

[0146] Figure 4H An IC device 100 according to some embodiments is shown, the IC device 100 being located above the gate structure 125B at a height H. C H D A dielectric layer 144 is present, for example, after performing a recess operation 360. The upper surface of the dielectric layer 144 is at a height H. C At that location, and the lower surface of layer 144 at height H D Location. Figure 4H In an exemplary embodiment, the dielectric layer 144 is between and in contact with the sidewalls 141 and 142.

[0147] Gate via 129 passes through dielectric layer 149 above transistor structures 101A and 101B to contact gate structures 125A and 125B. Via 129 above transistor structure 101B also passes through dielectric layer 144. Gate via 129 can couple (e.g., electrically couple), for example, gate electrode 126 to an interconnect network (not shown) above transistor structure 101.

[0148] Figure 5A diagram of an example data server machine 506 employing an IC device having dielectric walls separating the channel and gate structures of varying heights is shown. Server machine 506 can be any commercial server, such as any number of high-performance computing platforms housed in a rack and networked together for electronic data processing, which, in an exemplary embodiment, includes one or more devices 550 having dielectric walls separating the channel and gate structures of varying heights.

[0149] As also shown in the figures, server machine 506 includes a battery and / or power supply 515 to provide power to device 550 and, in some embodiments, provides power delivery functions such as power regulation. Device 550 may be deployed as part of package-level integrated system 510. Integrated system 510 is further shown in extended view 520. In an exemplary embodiment, device 550 (labeled “memory / processor”) includes at least one memory chip (e.g., random access memory (RAM)) and / or at least one processor chip (e.g., microprocessor, multi-core microprocessor, or graphics processor, etc.) having the characteristics discussed herein. In an embodiment, device 550 is a microprocessor including static RAM (SRAM) cache memory. As shown in the figures, device 550 may be an IC device having dielectric walls separating channels and gate structures with different heights, as discussed herein. Device 550 may also be coupled (e.g., communication-coupled to) a board, inserter, or other substrate or host assembly 299 together with one or more power management ICs (PMICs) 530, an RF (wireless) IC (RFIC) 525 including a broadband RF (wireless) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband and analog front-end module, and also including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and its controller 535. In some embodiments, RFIC 525, PMIC 530, controller 535, and device 550 include dielectric walls separating the channel and gate structures with different heights.

[0150] Figure 6 This is a block diagram of an example computing device 600 according to some embodiments. For example, one or more components of computing device 600 may include any of the devices or structures discussed herein. Figure 6 The diagram illustrates multiple components included in computing device 600, but any one or more of these components may be omitted or duplicated depending on application requirements. In some embodiments, some or all of the components included in computing device 600 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various components may be fabricated on a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing device 600 may not include... Figure 6 The computing device 600 may include one or more components as shown, but may include interface circuitry for coupling to one or more components. For example, the computing device 600 may not include display device 603, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 603 may be coupled. In another set of examples, the computing device 600 may not include audio output device 604, other output device 605, GPS device 609, audio input device 610, or other input device 611, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, and audio input device interface circuitry to which audio output device 604, other output device 605, GPS device 609, audio input device 610, or other input device 611 may be coupled.

[0151] Computing device 600 may include processing device 601 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" refers to a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 601 may include memory 621, communication device 622, cooling device 623, battery / power regulation device 624, logic 625, interconnect 626 (i.e., optionally including redistribution layer (RDL) or metal-insulator-metal (MIM) devices), thermal regulation device 627, and hardware security device 628.

[0152] Processing device 601 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0153] Computing device 600 may include memory 602, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 602 includes memory that shares a die with processing device 601. The memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0154] The computing device 600 may include a thermal regulation / cooling device 606. The thermal regulation / cooling device 606 can maintain the processing device 601 (and / or other components of the computing device 600) at a predetermined low temperature during operation.

[0155] In some embodiments, computing device 600 may include communication chip 607 (e.g., one or more communication chips). For example, communication chip 607 may be configured to manage wireless communication for transmitting data to and from computing device 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid-state medium. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0156] The communication chip 607 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks; the acronym stands for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 607 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 607 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 607 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, the communication chip 607 can operate according to other wireless protocols. The computing device 600 may include an antenna 613 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0157] In some embodiments, the communication chip 607 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 607 may include multiple communication chips. For example, a first communication chip 607 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 607 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 607 may be dedicated to wireless communications, and the second communication chip 607 may be dedicated to wired communications.

[0158] The computing device 600 may include a battery / power circuit 608. The battery / power circuit 608 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the computing device 600 to an energy source (e.g., AC line power) separate from the computing device 600.

[0159] The computing device 600 may include a display device 603 (or a corresponding interface circuit, as described above). The display device 603 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0160] The computing device 600 may include an audio output device 604 (or a corresponding interface circuit, as described above). The audio output device 604 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0161] The computing device 600 may include an audio input device 610 (or a corresponding interface circuit, as described above). The audio input device 610 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0162] The computing device 600 may include a GPS device 609 (or a corresponding interface circuit, as described above). The GPS device 609 may communicate with a satellite-based system and may receive the location of the computing device 600, as is known in the art.

[0163] The computing device 600 may include other output devices 605 (or corresponding interface circuitry, as described above). Examples of other output devices 605 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0164] The computing device 600 may include other input devices 611 (or corresponding interface circuitry, as described above). Examples of other input devices 611 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0165] Computing device 600 may include a security interface device 612. Security interface device 612 may include any device that provides security measures for computing device 600, such as intrusion detection, biometric authentication, secure encoding or decoding, access list management, malware detection, or spyware detection.

[0166] The computing device 600 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, personal digital assistant (PDA), super mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device.

[0167] The subject matter of this instruction manual is not limited to Figures 1A-6 The specific application shown is illustrated. As those skilled in the art will understand, this subject matter can be applied to other deposition applications as well as any suitable manufacturing applications.

[0168] The following examples relate to other embodiments, and the details in the examples may be used anywhere in one or more embodiments.

[0169] In one or more first embodiments, an apparatus includes: a stack of first nanoribbons extending through a first gate structure in a first transistor structure, the first gate structure including a first metal and a first insulating layer, the first metal extending upward to a first height; a stack of second nanoribbons extending through a second gate structure in a second transistor structure, the second gate structure including a second metal and a second insulating layer, the second metal extending upward to a second height, the first height being greater than the second height; and a dielectric structure between the stack of the first nanoribbons and the stack of the second nanoribbons, the dielectric structure including opposing first and second sidewalls, wherein the first insulating layer is on the first sidewall and the second insulating layer is on the second sidewall.

[0170] In one or more second embodiments, further relating to the first embodiment, the stack of the first nanoribbons includes a plurality of third heights, with a first vertical spacing between adjacent third heights of each first nanoribbon in the first nanoribbon; the stack of the second nanoribbons includes a plurality of fourth heights, with a second vertical spacing between adjacent fourth heights of each second nanoribbon in the second nanoribbon; and each pair of adjacent first nanoribbons in the first nanoribbon includes an upper first nanoribbon and a lower first nanoribbon, the upper first nanoribbon having a corresponding third height higher than the corresponding fourth height of the adjacent second nanoribbon, and the lower first nanoribbon having a corresponding third height lower than the corresponding fourth height of the adjacent second nanoribbon.

[0171] In one or more third embodiments, further for the first or second embodiment, the first vertical distance between the uppermost first nanoribbon in the first nanoribbon and the uppermost surface of the first gate structure is approximately equal to the second vertical distance between the uppermost second nanoribbon in the second nanoribbon and the uppermost surface of the second gate structure.

[0172] In one or more fourth embodiments, further for the first to third embodiments, the upper surface of the dielectric structure is at a third height that is higher than the first height and the second height.

[0173] In one or more fifth embodiments, and further for the first to fourth embodiments, the first nanoribbon has a first composition that is different from the second composition of the second nanoribbon.

[0174] In one or more sixth embodiments, and further for the first to fifth embodiments, the first nanoribbon has a first thickness that is greater than or less than the second thickness of the second nanoribbon.

[0175] In one or more seventh embodiments, further for the first to sixth embodiments, the first insulating layer is located on the first sidewall at a position below the first height, the second insulating layer is located on the second sidewall at a position below the second height, and the second insulating layer is not present on the second sidewall at a position above the second height.

[0176] In one or more eighth embodiments, further for the first to seventh embodiments, the first insulating layer is on or around each nanoribbon in the first nanoribbon, and the second insulating layer is on or around each nanoribbon in the second nanoribbon.

[0177] In one or more ninth embodiments, and further with respect to the first to eighth embodiments, the first insulating layer has a first composition different from the second composition of the second insulating layer, or the first insulating layer has a first thickness greater than or less than the second thickness of the second insulating layer.

[0178] In one or more tenth embodiments, and further for the first to ninth embodiments, the first transistor structure and the second transistor structure are in a first substrate, the first substrate is coupled to a second substrate, and the first transistor structure and the second transistor structure are coupled to a power source through the second substrate.

[0179] In one or more eleventh embodiments, an apparatus includes: a stack of first nanoribbons extending through a first gate structure in a first transistor structure, the first gate structure including a first insulating layer; a stack of second nanoribbons extending through a second gate structure in a second transistor structure, the second gate structure including a metal and a second insulating layer, the second insulating layer being between the metal and the second nanoribbons; and a dielectric wall between the first gate structure and the second gate structure, the dielectric wall including opposing first and second sides, wherein the first insulating layer extends to a first height on the first side, the first insulating layer is around each of the first nanoribbons in the first nanoribbons, the second insulating layer is on the second side and around each of the second nanoribbons in the second nanoribbons, and the metal extends upward to a second height below the first height.

[0180] In one or more twelfth embodiments, and further for an eleventh embodiment, the third height of the uppermost first nanoribbon in the first nanoribbon is higher than the fourth height of the uppermost second nanoribbon in the second nanoribbon.

[0181] In one or more thirteenth embodiments, and further for the eleventh or twelfth embodiment, the first vertical distance between the uppermost first nanoribbon in the first nanoribbon and the first height is approximately equal to the second vertical distance between the uppermost second nanoribbon in the second nanoribbon and the second height.

[0182] In one or more of the fourteenth embodiments, and further for the eleventh to thirteenth embodiments, the first transistor structure and the second transistor structure are in a first substrate, the first substrate is coupled to the second substrate, and the first transistor structure and the second transistor structure are coupled to a power source through the second substrate.

[0183] In one or more fifteenth embodiments, a method includes: planarizing a first surface, a second surface, and a third surface of a substrate to a first height, wherein the first surface is above a stack of first nanoribbons, the second surface is above a stack of second nanoribbons, and a dielectric wall is included on the third surface between the first surface and the second surface; and recessing a first metal of a first gate structure to a second height below the first height, the dielectric wall including opposing first and second sidewalls between the first gate structure and a second gate structure, the first gate structure including a first insulating layer and the first metal, the first insulating layer being on the first sidewall, the stack of first nanoribbons extending through the first gate structure, the second gate structure including a second insulating layer and a second metal, the second insulating layer being on the second sidewall, the stack of second nanoribbons extending through the second gate structure.

[0184] In one or more sixteenth embodiments, and further for a fifteenth embodiment, the first metal is recessed to a second height below the first height, causing the first insulating layer to be recessed downward to the second height.

[0185] In one or more of the seventeenth embodiments, and further for the fifteenth or sixteenth embodiment, the first metal is recessed to a second height below the first height, such that the first metal is recessed above the uppermost first nanoribbon in the first nanoribbon by a first thickness, the first thickness being equal to the second thickness of the second metal above the uppermost second nanoribbon in the second nanoribbon.

[0186] In one or more of the eighteenth embodiments, and further for the fifteenth to seventeenth embodiments, recessing the first metal of the first gate structure to a second height below the first height includes: depositing a mask layer above the planarized first, second, and third surfaces of the substrate; forming an opening in the mask layer above the stack of the first nanoribbons; and wet etching the first metal to the second height.

[0187] In one or more of the nineteenth embodiments, and further for the fifteenth to eighteenth embodiments, the method further includes: forming the first gate structure and the second gate structure, wherein forming the first gate structure includes: depositing the first insulating layer on the first sidewall of the dielectric wall and over the stack of the first nanoribbons, and forming the second gate structure includes: depositing the second insulating layer on the second sidewall of the dielectric wall and over the stack of the second nanoribbons.

[0188] In one or more twentieth embodiments, and further for the fifteenth to nineteenth embodiments, the method further includes: forming a stack of the first nanoribbons and a stack of the second nanoribbons, wherein the stack of the first nanoribbons includes a plurality of third heights, the stack of the second nanoribbons includes a plurality of fourth heights, and the third heights of the first nanoribbons and the fourth heights of the second nanoribbons are interleaved.

[0189] This disclosure may be practiced with modifications and alterations, and the scope of the appended claims is not limited to the described embodiments. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include only a subset of these features, a different order of these features, different combinations of these features, and / or additional features beyond those expressly listed. Therefore, the scope of the patent right should be determined with reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A stack of first nanoribbons extending through a first gate structure in a first transistor structure, the first gate structure including a first metal and a first insulating layer, the first metal extending upward to a first height; A stack of second nanoribbons extending through a second gate structure in a second transistor structure, the second gate structure including a second metal and a second insulating layer, the second metal extending upward to a second height, the first height being greater than the second height; as well as A dielectric structure between a stack of the first nanoribbons and a stack of the second nanoribbons, the dielectric structure including opposing first and second sidewalls, wherein the first insulating layer is on the first sidewall and the second insulating layer is on the second sidewall.

2. The apparatus according to claim 1, wherein: The stack of the first nanoribbons includes a plurality of third heights, and there is a first vertical spacing between adjacent third heights of each of the first nanoribbons. The stack of the second nanoribbons includes multiple fourth heights, and adjacent fourth heights of each second nanoribbon have a second vertical spacing; and Each pair of adjacent first nanoribbons in the first nanoribbon includes an upper first nanoribbon and a lower first nanoribbon, wherein the upper first nanoribbon has a corresponding third height that is higher than the corresponding fourth height of the adjacent second nanoribbon, and the lower first nanoribbon has a corresponding third height that is lower than the corresponding fourth height of the adjacent second nanoribbon.

3. The apparatus according to claim 2, wherein, The first vertical distance between the uppermost first nanoribbon in the first nanoribbon and the uppermost surface of the first gate structure is approximately equal to the second vertical distance between the uppermost second nanoribbon in the second nanoribbon and the uppermost surface of the second gate structure.

4. The apparatus according to claim 1, wherein, The upper surface of the dielectric structure is located at a third height, which is higher than the first height and the second height.

5. The apparatus according to claim 1, wherein, The first nanoribbon has a first composition that is different from the second composition of the second nanoribbon.

6. The apparatus according to claim 1, wherein, The first nanoribbon has a first thickness that is greater than or less than the second thickness of the second nanoribbon.

7. The apparatus according to any one of claims 1 to 6, wherein: The first insulating layer is located on the first sidewall at a position below the first height; The second insulating layer is located on the second sidewall at a position lower than the second height; and The second insulating layer does not exist on the second sidewall at a position higher than the second height.

8. The apparatus according to any one of claims 1 to 6, wherein, The first insulating layer is on or around each nanoribbon in the first nanoribbon, and the second insulating layer is on or around each nanoribbon in the second nanoribbon.

9. The apparatus according to any one of claims 1 to 6, wherein, The first insulating layer has a first composition that is different from the second composition of the second insulating layer.

10. The apparatus of claim 9, wherein the first insulating layer has a first thickness that is greater than or less than the second thickness of the second insulating layer.

11. The apparatus according to any one of claims 1 to 6, wherein: The first transistor structure and the second transistor structure are in the first substrate; The first substrate is coupled to the second substrate; and The first transistor structure and the second transistor structure are coupled to the power supply through the second substrate.

12. An apparatus comprising: A stack of first nanoribbons extending through a first gate structure in a first transistor structure, the first gate structure including a first insulating layer; A stack of second nanoribbons extending through a second gate structure in a second transistor structure, the second gate structure comprising a metal and a second insulating layer, the second insulating layer being between the metal and the second nanoribbon; as well as The dielectric wall between the first gate structure and the second gate structure, the dielectric wall comprising: The first and second sides are opposite, wherein the first insulating layer extends to a first height on the first side, the first insulating layer is around each of the first nanoribbons in the first nanoribbon, the second insulating layer is on the second side and around each of the second nanoribbons in the second nanoribbon, and the metal extends upward to a second height below the first height.

13. The apparatus according to claim 12, wherein, The third height of the uppermost first nanoribbon in the first nanoribbon is higher than the fourth height of the uppermost second nanoribbon in the second nanoribbon.

14. The apparatus according to claim 13, wherein, The first vertical distance between the uppermost first nanoribbon in the first nanoribbon and the first height is substantially equal to the second vertical distance between the uppermost second nanoribbon in the second nanoribbon and the second height.

15. The apparatus according to any one of claims 1 to 14, wherein: The first transistor structure and the second transistor structure are in the first substrate; The first substrate is coupled to the second substrate; and The first transistor structure and the second transistor structure are coupled to the power supply through the second substrate.

16. The apparatus according to any one of claims 1 to 14, wherein, The first nanoribbon has a first composition that is different from the second composition of the second nanoribbon.

17. The apparatus according to any one of claims 1 to 14, wherein, The first nanoribbon has a first thickness that is greater than or less than the second thickness of the second nanoribbon.

18. The apparatus according to any one of claims 1 to 14, wherein, The first insulating layer is on or around each nanoribbon in the first nanoribbon, and the second insulating layer is on or around each nanoribbon in the second nanoribbon.

19. The apparatus according to any one of claims 1 to 14, wherein, The first insulating layer has a first composition that is different from the second composition of the second insulating layer.

20. A method comprising: The first, second, and third surfaces of the substrate are planarized to a first height, wherein the first surface is above a stack of first nanoribbons, the second surface is above a stack of second nanoribbons, and a dielectric wall is included on the third surface between the first and second surfaces; and The first metal of the first gate structure is recessed to a second height below the first height. The dielectric wall includes opposing first and second sidewalls between the first gate structure and the second gate structure. The first gate structure includes a first insulating layer and the first metal. The first insulating layer is on the first sidewall. A stack of the first nanoribbons extends through the first gate structure. The second gate structure includes a second insulating layer and a second metal. The second insulating layer is on the second sidewall. A stack of the second nanoribbons extends through the second gate structure.

21. The method according to claim 20, wherein, The first metal is recessed to a second height below the first height, causing the first insulating layer to be recessed downwards to the second height.

22. The method according to claim 20, wherein, The first metal is recessed to a second height below the first height, and the first metal is recessed to a first thickness above the uppermost first nanoribbon in the first nanoribbon, the first thickness being equal to the second thickness of the second metal above the uppermost second nanoribbon in the second nanoribbon.

23. The method according to any one of claims 20 to 22, wherein, Depressing the first metal of the first gate structure to a second height below the first height includes: A mask layer is deposited above the planarized first, second, and third surfaces of the substrate; An opening is formed in the mask layer above the stack of the first nanoribbons; and The first metal is wet-etched to the second height.

24. The method according to any one of claims 20 to 22, further comprising: Forming the first gate structure and the second gate structure, wherein forming the first gate structure includes depositing the first insulating layer on the first sidewall of the dielectric wall and over the stack of the first nanoribbons, and forming the second gate structure includes depositing the second insulating layer on the second sidewall of the dielectric wall and over the stack of the second nanoribbons.

25. The method according to any one of claims 20 to 22, further comprising: A stack of the first nanoribbons and a stack of the second nanoribbons are formed, wherein: The stack of the first nanoribbons includes multiple third heights; The stack of the second nanoribbons includes multiple fourth heights; and The third height of the first nanoribbon is interleaved with the fourth height of the second nanoribbon.

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