Fabrication of full ring gate integrated circuit structures with gate dielectric having a subtractive delineation transition layer thickness

Abstract

An all-around gate integrated circuit structure with gate dielectric having a subtractive differentiation transition layer thickness is described. For example, an integrated circuit structure includes a first vertically arranged horizontal nanowire or first fin and a second vertically arranged horizontal nanowire or second fin. A first gate stack is over the first vertically arranged horizontal nanowire or first fin, where the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer including silicon and oxygen and having a first thickness. A second gate stack is over the second vertically arranged horizontal nanowire or second fin, where the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer including silicon and oxygen and having a second thickness greater than the first thickness.

Description

Background Technology

[0001] For decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Shrinking features to ever smaller sizes allows for increased density of functional units within the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a single chip, thus facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable a less complex tri-gate fabrication process. On the other hand, maintaining improved mobility and short-channel control is a challenge when microelectronic device dimensions are smaller than the 10-nanometer (nm) node. Nanowires used to fabricate these devices provide improved short-channel control.

[0003] However, scaling up multi-gate and nanowire transistors does not come without consequences. As the size of these basic building blocks of microelectronic circuits decreases, and the number of basic building blocks fabricated in a given area increases, the limitations of the photolithography processes used to pattern these building blocks become increasingly apparent. In particular, there may be a trade-off between the minimum size (critical size) of the features patterned in a semiconductor stack and the spacing between these features. Attached Figure Description

[0004] Figures 1A to 1D Cross-sectional views are shown of various operations in a method of manufacturing an all-gate integrated circuit structure having a gate dielectric with a subtractively differentiated transition layer thickness, according to embodiments of the present disclosure.

[0005] Figure 2 A cross-sectional view is shown of an operation in a method of manufacturing an all-around gate integrated circuit structure with a common metal gate according to an embodiment of the present disclosure.

[0006] Figure 3 A cross-sectional view is shown in a gate stack body representing various operations in a method of manufacturing an integrated circuit structure according to an embodiment of the present disclosure, the integrated circuit structure having a dipole layer for adjusting the threshold voltage of the gate stack body.

[0007] Figures 4A to 4J Cross-sectional views of various operations in a method of manufacturing an all-gate integrated circuit structure according to embodiments of the present disclosure are shown.

[0008] Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0009] Figure 6 Cross-sectional views of nanowires and fins cut through nanowires and fins for a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure are shown.

[0010] Figure 7 Cross-sectional views are shown illustrating various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a full-ring gate device, according to embodiments of the present disclosure.

[0011] Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0012] Figure 8B An embodiment according to this disclosure is shown. Figure 8A The source or drain diagram of a nanowire-based integrated circuit structure taken along the a-a' axis.

[0013] Figure 8C An embodiment according to this disclosure is shown. Figure 8A A cross-sectional channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0014] Figure 9 A computing device according to an embodiment of the present disclosure is shown.

[0015] Figure 10 An intermediary layer including one or more embodiments of the present disclosure is shown. Detailed Implementation

[0016] A full-to-the-loop integrated circuit structure with a gate dielectric having a subtractively distinct transition layer thickness is described. In the following description, numerous specific details (such as specific integration and material schemes) are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known features (such as integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of this disclosure. Furthermore, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0017] Certain terms may also be used in the following description for reference only and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to directions of reference in the accompanying drawings. Terms such as “front,” “rear,” “rear,” and “side” describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, as becomes clear from the text describing the component under discussion and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0018] The embodiments described herein may relate to front-end process (FEOL) semiconductor processing and structure. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything, including (but not limited to) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0019] The embodiments described herein may relate to back-end process (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts for chip-to-package connections, insulating layers (dielectrics), metal layers, and bonding sites. Interconnects, vias, and dielectric structures are formed in the BEOL portion of the contacts (pads) during the manufacturing stage. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0020] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL processing and structure and BEOL processing and structure. In particular, although an exemplary processing scheme can be illustrated using an FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using a BEOL processing scheme, such a method can also be applied to FEOL processing.

[0021] One or more embodiments described herein relate to early direct subtractive patterning of transition layer (TL) oxides for equivalent oxide thickness (EOT) control of various MOS devices. One or more embodiments described herein relate to full-to-all-around gate devices including gate dielectrics with subtractively differentiated transition layer thicknesses. It should be understood that, unless otherwise stated, references to nanowires may indicate nanowires, nanoribbons, or even nanosheets. It should also be understood that the embodiments can be applied to fin FET architectures including gate dielectrics with subtractively differentiated transition layer thicknesses.

[0022] To provide context, in conventional post-gate metallized processes, transition layer (TL) oxides are uniformly grown on all MOS types, such as PMOS / NMOS or devices with different VTs. The embodiments described herein relate to a patterned process to achieve independent tunability of the TL oxide thickness and quality for different MOS devices. For example, PMOS reliability typically benefits from a thicker TL oxide, while the same thickness on an NMOS could lead to undesirable performance losses. The ability to pattern the TL oxide on different devices allows for superior control, which can be fine-tuned to achieve the optimal reliability / performance tradeoff for each PMO / NMOS or any other type of MOS device. With unpatterned TL oxides, there may be no delta between different devices.

[0023] According to one or more embodiments, for a gate-all-around (GAA) architecture (and also applicable to finFET technology), a first TL oxide layer is grown on a Si strip. Gate patterning is then performed using a hard mask (such as a carbon-based hard mask), which can later be selectively removed to turn different MOS devices (such as PMOS / NMOS) on / off. The first TL oxide layer is then removed in the turned-on device using selective etching. The hard mask module (such as a carbon substrate) and the hard mask are then selectively removed. A second TL oxide is then grown on top of the previously patterned first TL oxide to achieve a device-to-device TL oxide delta. This method can be repeated multiple times to distinguish unique combinations of desired numbers of TL oxides and can also be accompanied by nanoribbon trimming using the same hard mask.

[0024] Advantages of implementing the embodiments described herein may include the ability of the patterning process described herein to achieve independent tunability of TL oxide thickness and quality for different MOS devices. The detectability of the embodiments described herein may include oxide thickness measurement using xTEM or other laboratory techniques. Different TL oxide thicknesses on different gate types can be a direct indication of oxide patterning.

[0025] As an example of a process flow Figures 1A to 1D Cross-sectional views of various operations in a method of fabricating an all-around gate integrated circuit structure having a gate dielectric with a subtractively differentiated transition layer thickness, according to embodiments of the present disclosure, are shown. It should be understood that the described and illustrated embodiments are also applicable to fin structures instead of stacks of nanowires, nanoribbons, or nanosheets.

[0026] refer to Figure 1APart (A) shows the initial structure 100 after the gate replacement and nanowire release process and before the main gate patterning. Structure 100 includes a substrate 102 (which may be or include sub-fin regions) having an NMOS region and a PMOS region (shown as a single PMOS / MOS region at this stage). Each NMOS / PMOS region includes a stack of nanowires 104 (such as the silicon nanowires above). An initial transition layer 106B is formed on the nanowires 104, for example, by using a chemical or thermal oxidation process to provide a silicon oxide transition layer through slight nanowire consumption or by using a deposition process. A corresponding layer 106A may also be formed on the substrate 102.

[0027] refer to Figure 1A Part (B) forms a first hard mask layer 108B on the initial transition layer 106B. Alternatively, a corresponding layer 108A can be formed on layer 106A.

[0028] refer to Figure 1A Part (C) forms a second hard mask layer 110 on the first hard mask layer 108B and the corresponding layer 108A.

[0029] refer to Figure 1B Part (D) forms a mask 112 (such as a carbon-based hard mask) to cover the PMOS region and expose the NMOS region.

[0030] refer to Figure 1B In part (E), the second hard mask layer 110, the first hard mask layer 108B, the initial transition layer 106B, and the corresponding layers 108A and 106A are removed from the NMOS region to expose the nanowires 104 in the NMOS region. The patterned second hard mask layer 110A, hard mask layer 108B, initial transition layer 106B, and the corresponding layers 108A and 106A remain on the nanowires in the PMOS region.

[0031] refer to Figure 1C For example, in part (F), the mask 112 is removed from the PMOS region by an ashing and cleaning process. In this stage, additional operations 150 can be performed, wherein nanowire 104 conditioning (e.g., thinning, shaping, narrowing, etc.) is performed while the NMOS nanowire 104 is exposed and the PMOS nanowire 104 is covered.

[0032] refer to Figure 1C In part (G), the patterned second hard mask layer 110A, hard mask layer 108B and corresponding layer 108A are removed from the PMOS region to leave the PMOS nanowire 104 with an initial transition layer 106B thereon (and leave layer 106A), and the NMOS nanowire 104 is exposed.

[0033] refer to Figure 1DA second transition layer 114B is formed on the portion (H), for example, by using a chemical or thermal oxidation process to provide a silicon oxide transition layer through slight nanowire consumption or by using a deposition process. The second transition layer 114B is formed on the initial transition layer 106B in the PMOS region and on the nanowire 104 in the NMOS region. A corresponding layer 114A may also be formed below the nanowire in the PMOS region. The total thickness of the transition layer 106B / 114B on the nanowire 104 in the PMOS region is greater than the total thickness of the transition layer 114B on the nanowire 104 in the NMOS region. In one embodiment, the total thickness of the transition layer 106B / 114B on the nanowire 104 in the PMOS region is at least 10% greater than the total thickness of the transition layer 114B on the nanowire 104 in the NMOS region. In another embodiment, the total thickness of the transition layer 106B / 114B on the nanowire 104 in the PMOS region is at least 50% greater than the total thickness of the transition layer 114B on the nanowire 104 in the NMOS region.

[0034] Figure 1D Subsequent processing of structure 175 may include high-k layer deposition and possible patterning, and gate electrode layer deposition and possible patterning, to form a PMOS gate stack and an NMOS gate stack, respectively, including total transition layers 106B / 114B and total transition layer 114B. In one embodiment, the gate electrode of the NMOS gate stack is an N-type gate electrode, and the gate electrode of the PMOS gate stack is a P-type gate electrode. In another embodiment, the gate electrodes of the NMOS gate stack and the PMOS gate stack are the same and common layer.

[0035] According to embodiments of this disclosure, the vertical thickness of each nanowire 104 in the PMOS region is the same as the vertical thickness of each lateral corresponding nanowire 104 in the NMOS region (or, in the case of fins), and the vertical thickness of the second fin is the same as the vertical thickness of the first fin. In one embodiment, the same horizontal nanowires (formed from the same starting layer) in the NMOS and PMOS regions have the same vertical thickness because both sets of nanowires undergo TL formation operations, rather than preventing one set from undergoing one of the processes, thus resulting in lines of different thicknesses formed from the same layer.

[0036] It should be understood that PMOS and NMOS selective patterning is used as an example, but the processes described in the embodiments herein can be used to pattern any multi-device structure and / or to interchange NMOS and PMOS. It should be understood that flexible results can exist depending on the TL oxide growth process. In one exemplary embodiment, NMOS TL oxide > PMOS TL oxide, where NMOS Tsi = PMOS Tsi. In another exemplary embodiment, NMOS Tsi > PMOS Tsi, where NMOS TL oxide ≥ PMOS TL oxide.

[0037] According to one or more embodiments described herein, the entry structure includes a GAA gate structure or other FET architecture following nanowire release. A first TL oxide is uniformly grown on all device types. The first TL oxide can be of any kind, such as chemically grown using an oxidation wet chemistry, deposited using any type of SiO deposition, oxidatively grown from Si strips using a plasma or thermal oxidation process, etc. Hard mask 1 and hard mask 2 are then deposited. The combination of hard masks 1 and 2 can be tuned to achieve desired selectivity and patterning properties. Hard mask 1 is optional, and examples can be, but are not limited to, TiN, HfO, AlO. Hard mask 2 is selected to have a high etch rate for the removal step and high selectivity for other materials present, such as Si, spacer materials, TL, and other SiO; hard mask 2 can be, but is not limited to, AlO, SiO, etc. Carbon hard mask (CHM) based patterning is then used to selectively protect / block the PMOS (or other selected MOS devices) while turning on the NMOS (or other complementary devices). Etching is then used to remove the hard mask and first TL oxide from the unprotected devices. Because the Si strip is exposed at the end of this step, selective etching in a specific sequence is required to expose Si and other materials such as spacers and SiO. The first etching can, for example, be used to remove AlO as hard mask 2 and TiN as hard mask 1, followed by a mild dilute HF (DHF) to remove the first TL oxide. However, any combination of wet and dry etching is feasible because they exhibit high selectivity and leave no hard mask residue. A CHM-based protection is then applied using ashing and clean stripping. Hard masks 1 and 2 can then be selectively removed without affecting the unprotected or protected devices' first TL oxide. The hard masks can be carefully removed completely without negatively impacting performance due to mobility / roughness loss. This can involve selective dry or wet etching processes. A second TL oxide is then grown on all devices, creating a distinct thickness / quality between the patterned structures. The second TL oxide can be of any kind, such as chemically grown using an oxidation wet chemistry, deposited using any type of SiO deposition, oxidatively grown from the Si strip using plasma or thermal oxidation processes, etc. The main gate patterning can then be performed.

[0038] In one embodiment, as a process variation, the location of the second TL oxide growth can be moved depending on the desired outcome. For example, the second TL oxide can be grown within the CHM opening without affecting the complementary (protected) device. It can also be combined with a hard mask removal process or selectively used with a patterned hard mask as a template for growth. Based on the chemicals involved, the process flow can also introduce variations in Si nanowire thickness (TSi trimming) to further tune the device to device performance, VT, etc. This can be achieved by selecting specific etch chemicals or by including additional chemicals specifically for trimming purposes.

[0039] On the other hand, bimetallic gate stacks can be difficult to integrate with metal gate dicing (MGC) schemes while providing tight polymer endcaps, e.g., <10 nm. Larger NP boundaries may result due to the presence of N-type work function metal (N-WFM) walls in the additional metal gate flow, which can limit library cell height. Previous approaches involved using bimetallic gates where the N-WFM stack differs from the P-WFM stack. Metal gate dicing has different etch rates in different WFMs; for example, MGC may not be uniform in NMOS devices compared to PMOS devices.

[0040] According to one or more embodiments of this disclosure, methods for implementing a common metal gate instead of an additive or subtractive metal gate (SMG) flow approach are described, addressing the problems outlined above. For GAAs, the common metal gate flow avoids the more difficult isotropic wet etch removal of the merged WFM between the NR and the large WEB problem associated with it as part of a standard SMG flow. In embodiments, the common metal gate approach achieves tight NP boundaries and high transistor density in GAA architectures.

[0041] In one embodiment, to address these issues, after completing the patterning process to differentiate the transition layer thickness, a common metal gate process is used as the final operation for the metal gate. The common metal gate process can be used with N-type work function metals (N-WFM) or P-type work function metals (P-WFM), or it can be implemented with an intermediate gap metal gate. After the common metal gate processing is complete, both N-type and P-type gate stacks can be blanket-deposited using gate fill metal.

[0042] To provide further context, dipoles can be used to set the threshold voltage and achieve a relative thinning of the work function metal layer. Embodiments can be implemented to replace the thicker work function metal used in scaled devices in the prior art by using thin-layer dipoles to set the threshold voltage (VT). Embodiments can provide multi-VT solutions.

[0043] As an example intermediate structure in the common metal gate process flow. Figure 2 A cross-sectional view is shown illustrating operations in a method of manufacturing an all-around gate integrated circuit structure having a common metal gate and a polarity-flipping layer according to an embodiment of the present disclosure. It should be understood that such embodiments can be used to implement... Figures 1A to 1D The gate dielectric has a subtractive differentiation in the thickness of the transition layer.

[0044] refer to Figure 2 A method for fabricating an integrated circuit structure includes a start structure 200 comprising a PMOS region 204 and an NMOS region 206 on a substrate 202. The PMOS region 204 includes a first plurality of horizontal nanowires 208 (which may be nanoribbons). The NMOS region 206 includes a second plurality of horizontal nanowires 210 (which may be nanoribbons). A first gate dielectric 209 surrounds the nanowires in the first plurality of horizontal nanowires 208. A second gate dielectric layer 211, also including an N-type polarity reversal layer, surrounds the nanowires in the second plurality of horizontal nanowires 210. The PMOS region 204 and the NMOS region 206 are included in trenches in a dielectric layer 212. A P-type conductive layer 214 is located in both the PMOS region 204 and the NMOS region 206. The P-type conductive layer 214 surrounds the nanowires in the first plurality of horizontal nanowires 208 and also surrounds the nanowires in the second plurality of horizontal nanowires 210. The N-type polarity reversal layer in 211 sets N-type characters in the N-type region 206, even though the conductive layer 214 is P-type. Although not depicted, it can then be seen... Figure 2 A conductive filler is formed on top of the structure. It should be understood that the specified characteristics of PMOS (or P-type) and NMOS (or N-type) can be reversed to the specified characteristics of NMOS (or N-type) and PMOS (or P-type), respectively.

[0045] Refer again Figure 2 According to embodiments of this disclosure, the integrated circuit structure includes a vertical arrangement of a first plurality of horizontal nanowires 208 and a vertical arrangement of a second plurality of horizontal nanowires 210. A first gate stack is disposed on the first vertical arrangement of the first plurality of horizontal nanowires 208 (e.g., in region 204), and the first gate stack includes a PMOS gate stack, which includes a first portion of a P-type conductive layer 214 surrounding the nanowires of the first vertical arrangement of the first plurality of horizontal nanowires 208. A second gate stack is disposed on the second vertical arrangement of the second plurality of horizontal nanowires 210 (e.g., in region 206), and the second gate stack includes an NMOS gate stack, which includes a second portion of a P-type conductive layer 214 surrounding the nanowires of the second vertical arrangement of the second plurality of horizontal nanowires 210.

[0046] In an embodiment, the integrated circuit structure further includes a first epitaxial source or drain structure at a first vertically arranged first end and a second end of a first plurality of horizontal nanowires 208, and a second epitaxial source or drain structure at a second vertically arranged first end and a second end of a second plurality of horizontal nanowires 210, examples of which are described in more detail below. In one embodiment, a first pair of conductive contacts is located on the first epitaxial source or drain structure, and a second pair of conductive contacts is located on the second epitaxial source or drain structure, examples of which are described in more detail below. In one embodiment, the first and second epitaxial source or drain structures are a first pair of non-discrete epitaxial source or drain structures and a second pair of non-discrete epitaxial source or drain structures, examples of which are described in more detail below. In one embodiment, the first and second epitaxial source or drain structures are a first pair of discrete epitaxial source or drain structures and a second pair of discrete epitaxial source or drain structures, examples of which are described in more detail below.

[0047] In another exemplary manufacturing scheme, Figure 3 A cross-sectional view is shown in a gate stack body representing various operations in a method of manufacturing an integrated circuit structure according to embodiments of the present disclosure, the integrated circuit structure having a dipole layer for adjusting the threshold voltage of the gate stack body. It should be understood that such embodiments can be used to implement... Figures 1A to 1D The gate dielectric has a subtractive differentiation in the thickness of the transition layer.

[0048] refer to Figure 3 Part (i) of a method for manufacturing an integrated circuit structure includes: forming a start structure 300 comprising an amorphous oxide layer 304 (such as a SiO2 layer) on a semiconductor channel structure 302. Trench 306 (such as a trench formed during a gate replacement scheme) exposes the amorphous oxide layer 304.

[0049] refer to Figure 3 Part (ii) is formed in trench 306 and on amorphous oxide layer 304, forming a high-k dielectric layer 308.

[0050] refer to Figure 3 Part (iii) forms a material layer 310 in the trench 306 and on the high-k dielectric layer 308.

[0051] refer to Figure 3 In part (iv), the material layer 310 and the high-k dielectric layer 308 are annealed to form a gate dielectric over the semiconductor channel structure 302. The gate dielectric includes a high-k dielectric layer 308 over a dipole material layer 310A. The dipole material layer 310A is different from the high-k dielectric layer 308.

[0052] refer to Figure 3A portion (v) is formed in trench 306 and on high-k dielectric layer 308, forming a work function layer 312. Work function layer 312 comprises metal.

[0053] refer to Figure 3 Part (vi) forms a gate stack by forming a gate stress source layer 314 on the work function layer 312.

[0054] Refer again Figure 3 According to embodiments of this disclosure, a high-k metal gate process begins after spacer formation and epitaxial deposition in the front-end process flow. In the metal gate circuit, a chemical oxide layer 304 is formed during wet cleaning. This layer may also be grown thermally to improve interface quality. A high-k oxide layer 308 with a higher dielectric constant is then deposited on the underlying chemical oxide layer 304. A dipole layer 310 is then deposited using atomic layer deposition. The gate stack is then subjected to a high annealing temperature, during which the dipoles 310 diffuse through the underlying high-dielectric-constant oxide layer 308 to form a net dipole 310A at the high-k 308 / chemical oxide 304 interface. This process is understood to be achieved due to the difference in electronegativity between the high-k and chemical oxide layers. Subsequently, a work function metal 312 is deposited, followed by a gate stress source 314 to increase channel stress.

[0055] Refer again Figure 3 In part (vi), according to an embodiment of the present disclosure, the integrated circuit structure includes a semiconductor channel structure 302, which comprises a single-crystal material. A gate dielectric is located on the semiconductor channel structure 302. The gate dielectric includes a high-k dielectric layer 308 on a dipole material layer 310A. The dipole material layer 310A is different from the high-k dielectric layer 308. The gate electrode has a work function layer 312 on the high-k dielectric layer 308. The work function layer 312 comprises metal. As described in the exemplary embodiments below, a first source or drain structure is located at a first side of the gate electrode, and a second source or drain structure is located at a second side of the gate electrode opposite to the first side.

[0056] In one embodiment, the high-k dielectric layer 308 is an HfO2 layer. In one such embodiment, the gate electrode is an N-type gate electrode, and the dipole layer 310 A comprises a material selected from the group consisting of Al2O3, TiO2, NbO, and ZrO2. In another such embodiment, the gate electrode is a P-type gate electrode, and the dipole layer 310 A comprises a material selected from the group consisting of La2O3, Y2O3, MgO, SrO, and Lu2O3. In one embodiment, the thickness of the dipole layer 310 A is in the range of 1-3 angstroms. In another embodiment, the gate electrode is a Mid-Gap type gate electrode, and the dipole layer 310 A comprises a material selected from the group consisting of Al2O3, TiO2, NbO, ZrO2, HfO2, La2O3, Y2O3, MgO, SrO, and Lu2O3.

[0057] In one embodiment, the gate electrode further includes a gate stress source layer 314 on the work function layer 312. In one such embodiment, the gate electrode is an N-type gate electrode, and the gate stress source layer 314 comprises a metal selected from the group consisting of W, Ti, Mn, Cr, and Al. In another such embodiment, the gate electrode is a P-type gate electrode, and the gate stress source layer 314 comprises a metal selected from the group consisting of Ti, Ta, Sn, and Zr.

[0058] In one embodiment, the gate dielectric further includes an amorphous oxide layer 304 between the dipole material layer 310A and the semiconductor channel structure 302. In one such embodiment, the amorphous oxide layer 304 is a SiO2 layer.

[0059] According to embodiments of this disclosure, dipole layers of varying thicknesses are used to adjust the threshold voltage, thus providing a multi-threshold voltage solution for scaling logic transistors. It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials, including but not limited to Si and SiGe. For example, group III-V materials may be used.

[0060] It should be understood that, in certain embodiments, nanowires or nanoribbons or sacrificial intermediate layers may be composed of silicon. As used throughout, silicon layers can be used to describe silicon materials composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form and may therefore include minute percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Therefore, embodiments involving silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances such as Ge, C, or Sn. It should be understood that silicon layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0061] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial interlayer may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed primarily of both silicon and germanium, for example, at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon-germanium layer comprises about 60% germanium and about 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises about 30% germanium and about 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and therefore may include a small percentage of carbon or tin. Such impurities can be included as unavoidable impurities or components during SiGe deposition, or can “contaminate” SiGe during diffusion during post-deposition processing. Therefore, the embodiments involving silicon germanium layers described herein may include silicon germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances such as carbon or tin. It should be understood that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0062] It should be understood that, in certain embodiments, nanowires, fins, or source or drain structures may be composed of germanium. As used throughout, germanium layers can be used to describe germanium materials composed of a very large amount (if not all) of germanium. However, it should be understood that, in practice, 100% pure Ge may be difficult to form and may therefore contain minute percentages of carbon, silicon, or tin. Such impurities may be included as unavoidable impurities or components during Ge deposition, or may “contaminate” Ge during diffusion during post-deposition processing. Therefore, embodiments involving germanium layers described herein may include germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge atoms or substances such as Si, C, or Sn. It should be understood that germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0063] It should also be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses and / or materials, including but not limited to Si, Ge, SiGe or III-V group materials that can be used as channel materials.

[0064] The following describes various apparatuses and processing methods that can be used to fabricate devices that can be integrated with gate dielectrics having subtractively distinct transition layer thicknesses. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, nanowire release processing can be performed by replacing the gate trench. Examples of such release processes are described below. Additionally, in another aspect, back-side (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein can provide methods for achieving relatively wide interconnect pitches. This can result in improved product performance and reduced patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0065] One or more embodiments described herein relate to biepitaxy (EPI) connections using nanowire or nanoribbon transistors with partial source or drain (SD) and asymmetric trench contact (TCN) depth. In the embodiments, the integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor that is partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. A deep trench is formed on one of the source or drain sides to enable direct contact with the back-side interconnect stage.

[0066] As an example of a process flow for manufacturing all-gate integrated circuit structures, Figures 4A-4J Cross-sectional views of various operations in a method of manufacturing an all-gate integrated circuit structure according to embodiments of the present disclosure are shown.

[0067] refer to Figure 4A A method for fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 404 and nanowires 406 over fins 402 (such as silicon fins). The nanowires 406 may be referred to as vertically arranged nanowires. As depicted, a protective cap 408 may be formed over the alternating sacrificial layers 404 and nanowires 406. Also as depicted, a relaxation buffer layer 452 and a defect modification layer 450 may be formed beneath the alternating sacrificial layers 404 and nanowires 406.

[0068] refer to Figure 4B A gate stack 410 is formed on the vertically arranged horizontal nanowires 406. Then, portions of the vertically arranged horizontal nanowires 406 are released by removing a portion of the sacrificial layer 404 to provide a recessed sacrificial layer 404' and a cavity 412, as shown. Figure 4C What is depicted.

[0069] It should be understood that Figure 4C The structure can be completed without first performing the deep etching and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), in the embodiments, the manufacturing process involves using a process scheme that provides a full-ring gate integrated circuit structure with epitaxial bumps (nub), which can be vertically discrete source or drain structures.

[0070] refer to Figure 4D An upper gate spacer 414 is formed at the sidewall of the gate structure 410. A cavity spacer 416 is formed in the cavity 412 below the upper gate spacer 414. Then, optionally, deep trench contact etching is performed to form a trench 418 and a recessed nanowire 406'. A patterned relaxation buffer layer 452' and a patterned defect modification layer 450' may also be present, as depicted.

[0071] Then, sacrificial material 420 is formed in the trench 418, such as Figure 4E As shown. In other process solutions, an isolated trench bottom or a silicon trench bottom can be used.

[0072] refer to Figure 4F A first epitaxial source or drain structure (e.g., left-side feature 422) is formed at the first end of a vertically arranged horizontal nanowire 406'. A second epitaxial source or drain structure (e.g., right-side feature 422) is formed at the second end of the vertically arranged horizontal nanowire 406'. In embodiments, as depicted, the epitaxial source or drain structure 422 is a vertically discrete source or drain structure and may be referred to as an epitaxial block.

[0073] Then, as Figure 4GAs shown, an interlayer dielectric (ILD) material 424 is formed on the side of the gate electrode 410 and is adjacent to the source or drain structure 422. (Reference) Figure 4H A replacement gate process is used to form the permanent gate dielectric 428 and the permanent gate electrode 426. Then, the ILD material 424 is removed, as shown below. Figure 4I As shown. Then, sacrificial material 420 is removed from one source-drain location (e.g., the right side) to form trench 432, but sacrificial material 420 is not removed from the other source-drain location to form trench 430.

[0074] refer to Figure 4J A first conductive contact structure 434 is formed, coupled to a first epitaxial source or drain structure (e.g., left-side feature 422). A second conductive contact structure 436 is formed, coupled to a second epitaxial source or drain structure (e.g., right-side feature 422). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In the embodiment, although... Figure 4J Not shown, but the method also includes forming an exposed surface of a second conductive contact structure 436 at the bottom of fin 402. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former and W, Ru, Co for the latter).

[0075] In one embodiment, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as depicted. In another such embodiment, not depicted, the first conductive contact structure 434 partially follows the fin 402.

[0076] In one embodiment, the second conductive contact structure 436 extends along the entire fin 402. In another embodiment, although not depicted, the second conductive contact structure 436 has an exposed surface at the bottom of the fin 402 when the bottom of the fin 402 is exposed via a backside substrate removal process.

[0077] In the embodiments, methods such as combination are used. Figures 1A to 1D The gate dielectric is described as having a subtractively differentiated transition layer thickness to form Figure 4J structure or Figures 4A to 4J The related structure.

[0078] On the other hand, in order to access the two conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using back-side exposure using front-side fabrication methods. In some exemplary embodiments, back-side exposure of transistors or other device structures requires wafer-level back-side processing. Compared to conventional TSV-type techniques, back-side exposure of transistors as described herein can be performed at device cell densities and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove all of the donor substrate on which the device layer is disposed during front-side device processing. Therefore, with back-side exposure of transistors, the semiconductor thickness in the device cell may be only tens or hundreds of nanometers, making micrometer-deep TSVs unnecessary.

[0079] The exposure techniques described in this paper enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer that is employed in front-side fabrication, exposed from the back side, and reused in back-side fabrication. When primarily relying on front-side processing, processing both the front and exposed back sides of the device structure can address many challenges associated with 3DIC fabrication.

[0080] For example, backside exposure using a transistor approach can be used to remove at least a portion of the carrier layer and intermediate layer of a donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0081] In some embodiments, prior to the operations described above, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved using any blanket implantation known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a uniform target depth within the desired fracture plane. After such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the absence of fracture, grinding, polishing, and / or etching operations can be employed to remove a carrier layer of greater thickness.

[0082] Next, the exposure of the intermediate layer is detected. A point is detected to identify where the back surface of the donor substrate has advanced to almost the device layer. Any endpoint detection technique known to be suitable for detecting the transition between materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in optical absorption or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in the optical absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary depending on the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the changes in the mass of the material can be associated with different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0083] The detection of the intermediate layer can be enhanced, where the removal process is selective for the carrier layer relative to the intermediate layer because non-uniformity in the carrier removal process can be mitigated by the etch rate increment between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operations remove the intermediate layer at a rate sufficiently lower than that used to remove the carrier layer, detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for etch selectivity. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1 to 10:1 or higher.

[0084] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be uniformly removed by polishing. Alternatively, the thickness of the intermediate layer can be removed using a mask or blanket etching process. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intermediate layer provides an etching stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for removing the intermediate layer compared to removing the device layer. When removing intermediate layer thicknesses of less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, employ a paste that provides very high selectivity (e.g., 100:1-300:1 or higher) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded within the intermediate layer, for example, as electrical isolation between adjacent device regions.

[0085] For embodiments that expose the device layer by completely removing the intermediate layer, the backside processing can begin on the exposed backside of the device layer or on a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and the device regions (such as source or drain regions) previously fabricated in the device layer.

[0086] In some embodiments where the back face of a carrier layer, intermediate layer, or device layer is recessed using wet etching and / or plasma etching, this etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back face surface of the device layer. As further described below, patterning can be within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back face device layer. Therefore, the mask etching process can begin with the corresponding mask device layer etching.

[0087] The above processing scheme can produce a donor-host substrate assembly including an IC device, the IC device having a back side of an interposer, a back side of a device layer and / or a back side of one or more semiconductor regions within the device layer, and / or exposed front-side metallization. Additional back-side processing of any of these exposed regions can then be performed during downstream processing.

[0088] It should be understood that the structure generated by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of the completed device, Figure 5 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0089] refer to Figure 5 The semiconductor structure or device 500 includes a nonplanar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In an embodiment, as shown by dashed lines, the nonplanar active region is divided into nanowires (such as nanowires 504A and 504B) over the sub-fin region 505, rather than solid fins. In either case, for ease of description of the nonplanar integrated circuit structure 500, the nonplanar active region 504 will be referred to hereinafter as the protruding fin portion. In an embodiment, the sub-fin region 505 also includes a relaxation buffer layer 542 and a defect modification layer 540, as depicted.

[0090] Gate line 508 is disposed on a protrusion 504 of the non-planar active region (including, where applicable, surrounding nanowires 504A and 504B), and on a portion of the trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, gate line 508 may also include a dielectric cap layer 554. From this angle, gate contact 514 and the overlying gate contact via 516 and the overlying metal interconnect 560 are also visible, all disposed within an interlayer dielectric stack or layer 570. Figure 5 From this perspective, it can also be seen that in one embodiment, the gate contact 514 is disposed above the trench isolation region 506, but not above the non-planar active region. In another embodiment, the gate contact 514 is disposed above the non-planar active region.

[0091] In this embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 508 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0092] Similarly, Figure 5 As shown, in one embodiment, an interface 580 exists between the protruding fin portion 504 and the sub-fin region 505. Interface 580 may be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is about 10 nanometers wide or narrower, and the sub-fin dopant may optionally be supplied from an adjacent solid-state doped layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0093] Although not in Figure 5As depicted, but it should be understood that the source or drain region of the protruding fin portion 504, or the source or drain region adjacent to the protruding fin portion 504, is on either side of the gate line 508, i.e., in or out of the page. In one embodiment, the material of the protruding fin portion 504 at the source or drain location is removed and replaced with another semiconductor material, for example, by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 580) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, the source and drain regions have associated asymmetric source and drain contact structures, as described above. Figure 4J As stated above.

[0094] Refer again Figure 5 In the embodiments, the fins 504 / 505 (and possibly nanowires 504 A and 504 B) are composed of a crystalline silicon-germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0095] In embodiments, trench isolation region 506 and the trench isolation region (trench isolation structure or trench isolation layer) described throughout the text may be composed of materials suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying bulk substrate, or contributing to such isolation, or isolating active regions (e.g., isolation fin active regions) formed within the underlying bulk substrate. For example, in one embodiment, trench isolation region 506 is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0096] Gate line 508 may be formed of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 552 may include a native oxide layer formed from the top layers of the substrate fin 504. In an embodiment, the gate dielectric layer 552 consists of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 consists of a top hafnium oxide layer and a bottom silicon dioxide or silicon oxynitride layer. In some implementations, a portion of the gate dielectric is a "U"-shaped structure, which includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

[0097] In one embodiment, the gate electrode layer 550 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode layer 550 is composed of a non-work function filling material formed over a metal work function setting layer. The gate electrode layer 550 may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer 550 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0098] The spacers associated with the gate electrode stack can be made of materials suitable for or contributing to the electrical isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0099] Gate contact 514 and the gate contact via 516 thereon may be made of a conductive material. In an embodiment, one or more contacts or vias may be made of a metallic material. The metallic material may be a pure metal (such as tungsten, nickel, or cobalt) or an alloy (such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0100] In an embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while eliminating the use of photolithography steps with extremely tight registration budgets. In the embodiment, the contact pattern is such as bonding Figure 4J The described contact patterns are either vertically symmetrical or asymmetrical. In other embodiments, all contacts are front-connected and asymmetrical. In one such embodiment, the self-aligned method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to create contact openings. In an embodiment, the contact pattern is formed by utilizing existing gate patterns in conjunction with contact plug lithography operations. In one such embodiment, the method eliminates the need for additional critical lithography operations used to generate the contact pattern, as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grating patterning but before gate grating dicing.

[0101] In an embodiment, providing structure 500 involves fabricating a gate stack body structure 508 by a gate replacement process. In this approach, a dummy gate material (such as polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than in an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etching process including the use of an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etching process including an aqueous solution of phosphoric acid.

[0102] Refer again Figure 5 The arrangement of the semiconductor structure or device 500 places the gate contacts above the isolation region. Such an arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above fin 505) and in the same layer as the trench contact via.

[0103] In the embodiments, methods such as combination are used. Figures 1A to 1D The gate dielectric is described as having a subtractively differentiated transition layer thickness to form Figure 5 The structure.

[0104] It should be understood that not all aspects of the above-described processes are required to fall within the spirit and scope of the embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. Semiconductor devices can be transistors or similar devices. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Additionally, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessible dual-gate device, or a fin-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10 nm) technology nodes.

[0105] In one embodiment, as used throughout this specification, the interlayer dielectric (ILD) material comprises or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD)) or by other deposition methods.

[0106] In embodiments, as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including conductive pad layers and filler layers. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnect. In embodiments, the interconnect is made of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0107] In one embodiment, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials may be used in different regions to provide different growth or etching selectivity to each other and the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask layers, capping layers, or plug layers known in the art may be used. The hard mask layer, capping layer, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0108] In one embodiment, as used throughout this specification, lithography is performed using 193nm immersion lithography (i193), EUV, and / or EBDW lithography. Positive or negative resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography mask portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the antireflective coating is a silicon ARC layer.

[0109] On the other hand, one or more embodiments involve adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may involve integrating multiple width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separating them via SAGE walls. In embodiments, the nanowires / nanoribbons are integrated with multiple Wsi within a portion of the SAGE architecture in a front-end process flow. This process flow may involve integrating nanowires and nanoribbons with different Wsi to provide robust functionality for next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0110] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, particularly scaling diffusion to the diffusion spacing. For illustrative comparison, Figure 6 Cross-sectional views of nanowires and fins cut through nanowires and fins for a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure are shown.

[0111] refer to Figure 6On the left side (a), the integrated circuit structure 600 includes a substrate 602 having a fin 604 protruding a certain amount 606 above an isolation structure 608 laterally surrounding the lower portion of the fin. The upper portion of the fin may include a relaxation buffer layer 622 and a defect modification layer 620, as depicted. A corresponding nanowire 605 is located above the fin 604. A gate structure can be formed on the integrated circuit structure 600 to fabricate a device. However, breaks in such a gate structure can be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0112] In comparison, reference Figure 6 On the right side (b), the integrated circuit structure 650 includes a substrate 652 having a fin 654 protruding a certain amount 656 over an isolation structure 658 laterally surrounding the lower portion of the fin. The upper portion of the fin may include a relaxation buffer layer 672 and a defect modification layer 670, as depicted. A corresponding nanowire 655 is located above the fin 654. An isolation SAGE wall 660 (which may include a hard mask thereon, as depicted) is included within the isolation structure 652 and between adjacent fin / nanowire 655 pairs. The distance between the isolation SAGE wall 660 and the nearest fin / nanowire 655 pair defines a gate cap spacing 662. A gate structure can be formed on the integrated circuit structure 600 between the isolation SAGE walls to fabricate a device. Breakage in this gate structure is imposed by the isolation SAGE walls. Due to the self-alignment of the isolation SAGE wall 660, limitations from conventional methods can be minimized to achieve a more aggressive diffusion to diffusion spacing. Furthermore, since the gate structure includes breaks at all locations, individual gate structure portions can be connected via a local interconnect layer formed over the isolation SAGE wall 660. In embodiments, as depicted, each of the SAGE walls 660 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of this disclosure, with Figure 6 The manufacturing process of the associated structure involves using a process scheme that provides an all-around gate integrated circuit structure with epitaxial source or drain structures.

[0113] In the embodiments, methods such as combination are used. Figures 1A to 1D The gate dielectric is described as having a subtractively differentiated transition layer thickness to form Figure 6 The structure of part (b).

[0114] The self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fins, without requiring additional length to account for mask misregistration. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to fabricating a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0115] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, Figure 7 Cross-sectional views are shown of various operations in a method of manufacturing a self-aligned gate end cap (SAGE) structure having a full-ring gate device, according to embodiments of the present disclosure.

[0116] refer to Figure 7 Part (a) of the initial structure includes a nanowire patterned stack 704 on a substrate 702. A photolithographic patterned stack 706 is formed on the nanowire patterned stack 704. The nanowire patterned stack 704 includes alternating sacrificial layers 710 and nanowire layers 712, which may be on a relaxation buffer layer 782 and a defect modification layer 780, as depicted. A protective mask 714 is located between the nanowire patterned stack 704 and the photolithographic patterned stack 706. In one embodiment, the photolithographic patterned stack 706 is a three-layer mask consisting of a topography mask portion 720, an antireflective coating (ARC) layer 722, and a photoresist layer 724. In a particular such embodiment, the topography mask portion 720 is a carbon hard mask (CHM) layer, and the antireflective coating 722 is a silicon ARC layer.

[0117] refer to Figure 7 The stack of part (b) and part (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 702 and trench 730.

[0118] refer to Figure 7 Parts (c) and (b) have an isolation layer 740 and a SAGE material 742 formed in the trench 730. The structure is then planarized to leave a patterned topographic mask layer 720' as the exposed upper layer.

[0119] refer to Figure 7 The portion (d) causes the isolation layer 740 to be recessed below the upper surface of the patterned substrate 702, for example to define the protruding fin portion and provide a trench isolation structure 741 below the SAGE wall 742.

[0120] refer to Figure 7 In part (e), at least in the channel region, the sacrificial layer 710 is removed to release nanowires 712A and 712B. During the formation Figure 7 Following the structure of part (e), a gate stack can be formed around the nanowires 712B or 712A, over the protruding fins of the substrate 702, and between the SAGE walls 742. In one embodiment, the remainder of the protective mask 714 is removed before forming the gate stack. In another embodiment, the remainder of the protective mask 714 is retained as an insulating fin cap as an artifact of the processing scheme.

[0121] Refer again Figure 7 Part (e) should be understood to depict a channel view in which the source or drain regions are positioned in and out of the page. In an embodiment, the channel region including nanowire 712B has a smaller width than the channel region including nanowire 712A. Therefore, in an embodiment, the integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although the structures of 712B and 712A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to herein as nanowires. It should also be understood that references to or descriptions of fin / nanowire pairs throughout the text can refer to a fin and one or more nanowires on it (e.g., Figure 7 The structure of two nanowires (shown in the image) is illustrated. According to embodiments of this disclosure, it is used with... Figure 7 The manufacturing process of the associated structure involves using a process scheme that provides an all-around gate integrated circuit structure with epitaxial source or drain structures.

[0122] In the embodiments, methods such as combination are used. Figures 1A to 1D The gate dielectric is described as having a subtractively differentiated transition layer thickness to form Figure 7 The structure of part (e).

[0123] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may consist of one or more materials suitable for electrically isolating portions of a permanent gate structure from each other or contributing to such isolation. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower layer of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper layer of a material with a higher dielectric constant (such as hafnium oxide).

[0124] To highlight the exemplary integrated circuit structure with three vertically arranged nanowires, Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 8B It shows Figure 8A The source or drain diagram of a nanowire-based integrated circuit structure taken along the a-a' axis. Figure 8C It shows Figure 8A A cross-sectional channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0125] refer to Figure 8AThe integrated circuit structure 800 includes one or more vertically stacked nanowires (groups 804) on a substrate 802. In embodiments, as depicted, a relaxation buffer layer 802C, a defect modification layer 802B, and a lower substrate portion 802A are included in the substrate 802, as depicted. For illustrative purposes, and to emphasize the nanowire portion, optional fins formed by the substrate 802 below the bottommost nanowire are not depicted. The embodiments herein pertain to both single-wire and multi-wire devices. As an example, three nanowire-based devices having nanowires 804A, 804B, and 804C are shown for illustrative purposes. For ease of description, nanowire 804A is used as an example, where the description focuses on one nanowire. It should be understood that, in describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire.

[0126] Each nanowire 804 includes a channel region 806 within the nanowire. The channel region 806 has a length (L). (Reference) Figure 8C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 8A and Figure 8C A gate electrode stack 808 surrounds the entire periphery (Pc) of each channel region 806. The gate electrode stack 808 includes a gate electrode and a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 808 without any intermediate material, such as the underlying substrate material or the upper channel fabrication material. Therefore, in embodiments having multiple nanowires 804, the channel regions 806 of the nanowires are also discrete relative to each other.

[0127] refer to Figure 8A and Figure 8B Both, the integrated circuit structure 800 includes a pair of discrete source or drain regions 810 / 812. This pair of discrete source or drain regions 810 / 812 is located on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. Furthermore, this pair of discrete source or drain regions 810 / 812 is adjacent to the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment (not depicted), the pair of discrete source or drain regions 810 / 812 is directly and perpendicularly adjacent to the channel region 806 because epitaxial growth is performed on and between nanowire portions extending beyond the channel region 806, wherein the nanowire ends are shown within the source or drain structure. In another embodiment, as... Figure 8A As shown, the pair of non-discrete source or drain regions 810 / 812 are indirectly and vertically adjacent to the channel region 806 because they are formed at the ends of the nanowires rather than between the nanowires.

[0128] In the embodiments, as depicted, the source or drain regions 810 / 812 are non-discrete because there is no separate and discrete source or drain region for each channel region 806 of the nanowire 804. Therefore, in embodiments with multiple nanowires 804, for each nanowire, the source or drain region 810 / 812 of the nanowire is a global or uniform source or drain region, rather than discrete. That is, the non-discrete source or drain regions 810 / 812 are global because a single uniform feature is used as the source or drain region for multiple (in this case, 3) nanowires 804, more specifically, for multiple discrete channel regions 806. In one embodiment, from a cross-sectional perspective view orthogonal to the length of the discrete channel region 806, each of the pair of non-discrete source or drain regions 810 / 812 is approximately rectangular in shape, having a bottom tapered portion and a top vertex portion, as shown below. Figure 8B As shown. However, in other embodiments, the source or drain regions 810 / 812 of the nanowire are relatively large but discrete, non-vertically merged epitaxial structures, such as those bonded to... Figures 4A to 4J The described bump.

[0129] According to embodiments of this disclosure, and as Figure 8A and Figure 8B As shown, the integrated circuit structure 800 also includes a pair of contacts 814, each contact 814 on one of the pair of discrete source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds the corresponding discrete source or drain region 810 / 812 in a vertical sense. On the other hand, the entire periphery of the discrete source or drain region 810 / 812 may not be in contact with the contact 814, so the contact 814 only partially surrounds the discrete source or drain region 810 / 812, such as... Figure 8B As shown. In the comparative embodiment (not depicted), the entire periphery of the non-discrete source or drain regions 810 / 812 (e.g., truncated along the a-a' axis) is surrounded by contact 814.

[0130] Refer again Figure 8A In one embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As depicted, the exterior of the pair of spacers 816 may partially overlap with the non-discrete source or drain regions 810 / 812, thereby providing an "embedded" portion of the non-discrete source or drain regions 810 / 812 beneath the pair of spacers 816. As also depicted, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend entirely beneath the pair of spacers 816.

[0131] Substrate 802 may be made of a material suitable for manufacturing integrated circuit structures. In one embodiment, substrate 802 includes a lower body substrate made of a single crystal of a material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or III-V compound semiconductor materials. An upper insulating layer is on the lower body substrate, which may be made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Thus, structure 800 may be fabricated from a starting insulator-on-semiconductor substrate. Alternatively, structure 800 may be formed directly from the body substrate, and localized oxidation may be used to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 800 may be formed directly from the body substrate, and doping may be used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., close to the substrate) has the form of an omega-FET type structure.

[0132] In an embodiment, as described below, the nanowire 804 can be sized as a line or strip and can have square or rounded corners. In an embodiment, the nanowire 804 is made of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 804, the single-crystal nanowire can be based on a (100) global orientation, for example, having […] in the z-direction. <100> Planar. Other orientations may also be considered, as described below. In the embodiments, the dimensions of the nanowire 804, viewed from a cross-sectional perspective, are on the nanoscale. For example, in a particular embodiment, the minimum dimension of the nanowire 804 is less than about 20 nanometers. In the embodiments, the nanowire 804 is made of a strained material, particularly in the channel region 806.

[0133] refer to Figure 8C In the embodiments, each of the channel regions 806 has a width (Wc) and a height (Hc), the width (Wc) and height (Hc) being approximately the same. That is, in both cases, the channel region 806 is square in cross-sectional profile, or circular if the corners are rounded. On the other hand, the width and height of the channel regions do not necessarily have to be the same, as in the case of the nanoribbons described throughout the text.

[0134] In embodiments, as described throughout, the integrated circuit structure includes non-planar devices, such as, but not limited to, fin-FETs or tri-gate devices having corresponding one or more overlying nanowire structures. In such embodiments, the corresponding semiconductor channel region comprises or is formed within a three-dimensional body, wherein one or more discrete nanowire channel portions cover the three-dimensional body. In one such embodiment, the gate structure at least surrounds the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0135] In the embodiments, methods such as combination are used. Figures 1A to 1D The gate dielectric is described as having a subtractively differentiated transition layer thickness to form Figures 8A to 8C The structure.

[0136] In embodiments, as described throughout, the underlying substrate may be composed of a semiconductor material capable of undergoing fabrication processes in which charge can migrate. In embodiments, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (e.g., but not limited to phosphorus, arsenic, boron, gallium, or combinations thereof) to form the active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a different crystalline substrate (e.g., a silicon epitaxial layer grown on a boron-doped bulk silicon single-crystal substrate). The bulk substrate may alternatively be composed of a Group III-V material. In embodiments, the bulk substrate is composed of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a Group III-V material, and the charge carrier dopant impurity atoms may be, such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0137] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art, such as computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processors, memory, and chipsets can potentially be manufactured using the methods disclosed herein.

[0138] Figure 9 A computing device 900 according to one embodiment of the present disclosure is shown. The computing device 900 houses a board 902. The board 902 may include multiple components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some embodiments, at least one communication chip 906 is also physically and electrically coupled to the board 902. In other embodiments, the communication chip 906 is part of the processor 904.

[0139] Depending on its application, computing device 900 may include other components that may be physically and electrically coupled to board 902 or may not be physically and electrically coupled to board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, encryption processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital multifunction discs (DVDs), etc.).

[0140] Communication chip 906 implements wireless communication for transmitting data to and from computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid-state medium. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. Communication chip 906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. Computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 906 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0141] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures constructed according to embodiments of the present disclosure, such as a full-gate all-around integrated circuit structure having a gate dielectric with a subtractively distinct transition layer thickness. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0142] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. The integrated circuit die of the communication chip 906 may include one or more structures constructed according to embodiments of the present disclosure, such as a full-to-the-loop integrated circuit structure having a gate dielectric with a subtractive distinguishing transition layer thickness.

[0143] In another embodiment, another component housed within the computing device 900 may include an integrated circuit die comprising one or more structures constructed according to embodiments of the present disclosure, such as a full-gate-all-around integrated circuit structure having a gate dielectric with a subtractively distinct transition layer thickness.

[0144] In various embodiments, the computing device 900 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In another embodiment, the computing device 900 may be any other electronic device that processes data.

[0145] Figure 10 An interposer 1000, incorporating one or more embodiments of the present disclosure, is illustrated. The interposer 1000 is an interposer substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 1000 is to extend connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that may subsequently be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002 / 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of the interposer 1000. And in yet another embodiment, three or more substrates are interconnected via the interposer 1000.

[0146] Intermediate layer 1000 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In another embodiment, intermediate layer 1000 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other group III-V and IV materials).

[0147] Interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. Interposer 1000 may also include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1000. According to embodiments of this disclosure, the apparatus or processes disclosed herein may be used to manufacture interposer 1000 or to manufacture components included in interposer 1000.

[0148] Therefore, embodiments of this disclosure include a full-gate integrated circuit structure having a gate dielectric with a subtractive differentiation transition layer thickness, and a method for manufacturing a full-gate integrated circuit structure having a gate dielectric with a subtractive differentiation transition layer thickness.

[0149] The description of the illustrated embodiments of this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the detailed description above. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims.

[0150] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even if only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in this disclosure are intended to be illustrative rather than restrictive. The foregoing description is intended to cover alternatives, modifications, and equivalents that will be apparent to those skilled in the art upon which this disclosure benefits.

[0151] The scope of this disclosure includes any feature or combination of features, or any generalization thereof, disclosed herein (explicitly or implicitly), whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from the respective independent claims may be combined in any suitable manner, not just in the specific combinations listed in the appended claims.

[0152] This document describes various embodiments or aspects of this disclosure. In some implementations, different embodiments are implemented separately. However, embodiments are not limited to those implemented in isolation. For example, two or more different embodiments may be combined to be implemented as a single device, process, structure, etc. In some cases, the entirety of various embodiments may be combined. In other cases, a portion of a first embodiment may be combined with portions of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with portions of a second embodiment and a portion of a third embodiment. The following examples relate to further embodiments. Various features of different embodiments may be combined differently, including some features while excluding others, to suit a variety of different applications.

[0153] Example 1: An integrated circuit structure includes: a first vertically arranged horizontal nanowire and a second vertically arranged horizontal nanowire. A first gate stack is located above the first vertically arranged horizontal nanowire, wherein the first gate stack is an NMOS gate stack having a gate electrode above a gate dielectric having a layer comprising silicon and oxygen and having a first thickness. A second gate stack is located above the second vertically arranged horizontal nanowire, wherein the second gate stack is a PMOS gate stack having a gate electrode above a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness. The vertical thickness of each nanowire in the second vertically arranged horizontal nanowire is the same as the vertical thickness of each of the laterally corresponding nanowires in the first vertically arranged horizontal nanowire.

[0154] Example Embodiment 2: The integrated circuit structure according to claim 1, wherein the gate electrode of the NMOS gate stack is an N-type gate electrode, and the gate electrode of the PMOS gate stack is a P-type gate electrode.

[0155] Example 3: The integrated circuit structure according to claim 1, wherein the gate electrode of the NMOS gate stack and the gate electrode of the PMOS gate stack are the same and common layer.

[0156] Example embodiment 4: The integrated circuit structure according to claim 1, 2 or 3, wherein the second thickness is at least 10% greater than the first thickness.

[0157] Example embodiment 5: The integrated circuit structure according to claim 1, 2 or 3, wherein the second thickness is at least 50% greater than the first thickness.

[0158] Example 6: An integrated circuit structure includes a first fin and a second fin. A first gate stack is located on the first fin, wherein the first gate stack is an NMOS gate stack having a gate electrode on a gate dielectric having a layer comprising silicon and oxygen and having a first thickness. A second gate stack is located on the second fin, wherein the second gate stack is a PMOS gate stack having a gate electrode on a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness. The vertical thickness of the second fin is the same as the vertical thickness of the first fin.

[0159] Example embodiment 7: The integrated circuit structure according to claim 6, wherein the gate electrode of the NMOS gate stack is an N-type gate electrode, and the gate electrode of the PMOS gate stack is a P-type gate electrode.

[0160] Example embodiment 8: The integrated circuit structure according to claim 6, wherein the gate electrode of the NMOS gate stack and the gate electrode of the PMOS gate stack are the same and common layer.

[0161] Example embodiment 9, the integrated circuit structure according to claim 6, 7 or 8, wherein the second thickness is at least 10% greater than the first thickness.

[0162] Example embodiment 10: The integrated circuit structure according to claim 6, 7 or 8, wherein the second thickness is at least 50% greater than the first thickness.

[0163] Example 11: A computing device includes a board and an assembly coupled to the board. The assembly includes an integrated circuit structure comprising a first vertically arranged horizontal nanowire or a first fin and a second vertically arranged horizontal nanowire or a second fin. A first gate stack is situated on the first vertically arranged horizontal nanowire or the first fin, wherein the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric having a layer comprising silicon and oxygen and having a first thickness. A second gate stack is situated on the second vertically arranged horizontal nanowire or the second fin, wherein the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness. The vertical thickness of each of the nanowires in the second vertically arranged horizontal nanowire is the same as the vertical thickness of each of the laterally corresponding nanowires in the first vertically arranged horizontal nanowire, or the vertical thickness of the second fin is the same as the vertical thickness of the first fin.

[0164] Example embodiment 12: The computing device according to claim 11, comprising the first vertically arranged horizontal nanowires and the second vertically arranged horizontal nanowires.

[0165] Example embodiment 13: The computing device according to claim 11, comprising the first fin and the second fin.

[0166] Example embodiment 14, the computing device according to claim 11, 12 or 13, further includes a memory coupled to the board.

[0167] Example embodiment 15: The computing device according to claim 11, 12, 13 or 14 further includes a communication chip coupled to the board.

[0168] Example embodiment 16: The computing device according to claim 11, 12, 13, 14 or 15 further includes a camera coupled to the board.

[0169] Example embodiment 17: The computing device according to claim 11, 12, 13, 14, 15 or 16 further includes a display coupled to the board.

[0170] Example embodiment 18, the computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further includes a battery coupled to the plate.

[0171] Example 19: A computing device according to claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0172] Example embodiment 20: A computing device according to claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: First vertically arranged horizontal nanowires; Second vertically arranged horizontal nanowires; A first gate stack is situated on top of a first vertically arranged horizontal nanowire, wherein the first gate stack is an NMOS gate stack having a gate electrode on a gate dielectric having a layer comprising silicon and oxygen and having a first thickness; and A second gate stack is situated on top of the second vertically arranged horizontal nanowires. The second gate stack is a PMOS gate stack having a gate electrode on top of a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness. The vertical thickness of each of the nanowires in the second vertically arranged horizontal nanowires is the same as the vertical thickness of each of the transversely corresponding nanowires in the first vertically arranged horizontal nanowires.

2. The integrated circuit structure according to claim 1, wherein, The gate electrode of the NMOS gate stack is an N-type gate electrode, and the gate electrode of the PMOS gate stack is a P-type gate electrode.

3. The integrated circuit structure according to claim 1, wherein, The gate electrode of the NMOS gate stack and the gate electrode of the PMOS gate stack are the same and share the same layer.

4. The integrated circuit structure according to claim 1, 2, or 3, wherein, The second thickness is at least 10% greater than the first thickness.

5. The integrated circuit structure according to claim 1, 2, or 3, wherein, The second thickness is at least 50% greater than the first thickness.

6. An integrated circuit structure, comprising: First fin; Second fin; A first gate stack, situated above the first fin, wherein the first gate stack is an NMOS gate stack having a gate electrode above a gate dielectric having a layer comprising silicon and oxygen and having a first thickness; and A second gate stack is located on top of the second fin, wherein the second gate stack is a PMOS gate stack having a gate electrode on top of a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness, wherein the vertical thickness of the second fin is the same as the vertical thickness of the first fin.

7. The integrated circuit structure according to claim 6, wherein, The gate electrode of the NMOS gate stack is an N-type gate electrode, and the gate electrode of the PMOS gate stack is a P-type gate electrode.

8. The integrated circuit structure according to claim 6, wherein, The gate electrode of the NMOS gate stack and the gate electrode of the PMOS gate stack are the same and share the same layer.

9. The integrated circuit structure according to claim 6, 7 or 8, wherein, The second thickness is at least 10% greater than the first thickness.

10. The integrated circuit structure according to claim 6, 7 or 8, wherein, The second thickness is at least 50% greater than the first thickness.

11. A computing device, comprising: plate; as well as An assembly coupled to the board, the assembly including an integrated circuit structure, the integrated circuit structure comprising: First vertically arranged horizontal nanowires or first fins; Second vertically arranged horizontal nanowires or second fins; A first gate stack is situated on the first vertically arranged horizontal nanowire or the first fin, wherein the first gate stack is an NMOS gate stack having a gate electrode on a gate dielectric having a layer comprising silicon and oxygen and having a first thickness; and A second gate stack is situated on the second vertically arranged horizontal nanowire or the second fin, wherein the second gate stack is a PMOS gate stack having a gate electrode on a gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness, wherein the vertical thickness of each of the nanowires in the second vertically arranged horizontal nanowire is the same as the vertical thickness of each of the transversely corresponding nanowires in the first vertically arranged horizontal nanowire, or wherein the vertical thickness of the second fin is the same as the vertical thickness of the first fin.

12. The computing device of claim 11, comprising the first vertically arranged horizontal nanowire and the second vertically arranged horizontal nanowire.

13. The computing device of claim 11, comprising the first fin and the second fin.

14. The computing device according to claim 11, 12 or 13, further comprising: A memory coupled to the board.

15. The computing device according to claim 11, 12 or 13, further comprising: A communication chip coupled to the board.

16. The computing device according to claim 11, 12 or 13, further comprising: A camera coupled to the plate.

17. The computing device according to claim 11, 12 or 13, further comprising: A display coupled to the board.

18. The computing device according to claim 11, 12 or 13, further comprising: The battery is coupled to the plate.

19. The computing device according to claim 11, 12 or 13, wherein, The component is a packaged integrated circuit die.

20. The computing device according to claim 11, 12 or 13, wherein, The components are selected from a group consisting of a processor, a communication chip, and a digital signal processor.

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