Array substrate, display panel, electronic device and manufacturing process of array substrate

Abstract

The present disclosure relates to an array substrate, a display panel, an electronic device and a manufacturing process of the array substrate. The array substrate comprises a substrate, a gate insulating layer, an active layer, at least one gate electrode and at least one channel-like region. The gate insulating layer is located on one side of the substrate. The active layer is arranged between the substrate and part of the gate insulating layer, and the active layer comprises at least alternately arranged main doped regions and main channel regions. Each gate electrode is arranged on the side of the gate insulating layer away from the substrate, and the gate electrode is arranged in one-to-one correspondence with the main channel regions. The channel-like region is arranged between the active layer and part of the gate insulating layer, and each channel-like region is arranged in correspondence with a single main channel region. The projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate. In this way, the electric field at the active layer can be reduced to reduce the leakage current, thereby greatly reducing the occurrence of the problem of electric light flicker of the array substrate when used at low frequency or when high / low frequency is switched.

Description

Technical Field

[0001] This disclosure relates to the field of terminal technology, and in particular to an array substrate, a display panel, an electronic device, and a manufacturing process for the array substrate. Background Technology

[0002] With the development of technology, OLED (Organic Light-Emitting Diode) display technology is becoming increasingly mature, and its application in terminal products such as mobile phones, tablets, laptops, and televisions is becoming more and more widespread. However, if OLED terminal products use LTPS (Low Temperature Polycrystalline Silicon) backplane drivers, whether it is 7T1C LTPS or 8T1C LTPS, the leakage current of the two dual gates T3 and T4 is relatively large, which makes it impossible to maintain a good potential. This can cause electro-optical flickering problems when using it at low frequencies or switching between high and low frequencies. Summary of the Invention

[0003] This disclosure provides an array substrate, a display panel, an electronic device, and a manufacturing process for the array substrate to address the shortcomings of related technologies.

[0004] According to a first aspect of the present disclosure, an array substrate is provided, comprising:

[0005] Substrate;

[0006] A gate insulating layer, the gate insulating layer being located on one side of the substrate;

[0007] An active layer is disposed between the substrate and a portion of the gate insulating layer, and the active layer includes at least alternating main doped regions and main channel regions;

[0008] At least one gate, each of the gates being disposed on the side of the gate insulating layer facing away from the substrate, and the gates being disposed in a one-to-one correspondence with the main channel region;

[0009] At least one channel-like region is disposed between the active layer and a portion of the gate insulating layer, each channel-like region is disposed corresponding to a single main channel region, and the projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate.

[0010] Optionally, at least a portion of the projected edge of the channel-like region is recessed inward by a distance no greater than 3 μm relative to the projected edge of the main channel region.

[0011] Optionally, along the thickness direction of the array substrate, the projection of the channel-like region coincides with the projection of the main channel region.

[0012] Optionally, it also includes a doped region, which is stacked on the side of the main doped region away from the substrate, and the doped region is connected to the side of the channel-like region that is flush with the main channel region.

[0013] Optionally, the length L1 of the doped region along the length direction from the main channel region to the main doped region is not greater than 10 μm.

[0014] Optionally, the edge of the doped region does not extend beyond the edge of the corresponding main doped region.

[0015] Optionally, the channel-like region and the doped-like region are set to the same thickness, and the thickness d is not less than 1 nm and not greater than 10 nm.

[0016] Optionally, there are two gates, and at least one set of corresponding gates is provided with a channel-like region between them and the main channel region.

[0017] Optionally, the at least one gate includes a first gate and a second gate;

[0018] The channel-like region includes a first channel-like region and a second channel-like region, wherein the first channel-like region is disposed corresponding to the first gate and the second channel-like region is disposed corresponding to the second gate;

[0019] When the doped region is connected to the side of the first channel region adjacent to and / or away from the second channel region, and the doped region is located on the side of the first channel region adjacent to the second channel region, the doped region is in contact with or spaced apart from the second channel region.

[0020] Optionally, the doped region is also connected to the side of the second channel region that is flush with the main channel region, and the doped region located between the first channel region and the second channel region does not contact each other.

[0021] According to a second aspect of the present disclosure, a display panel is provided, including an array substrate as described above.

[0022] According to a third aspect of the present disclosure, an electronic device is provided, including a display panel as described above.

[0023] According to a fourth aspect of the present disclosure, a manufacturing process for an array substrate is provided, comprising:

[0024] Substrate preparation;

[0025] An active layer is fabricated on one side of the substrate; the active layer includes alternating main doped regions and main channel regions;

[0026] A buffer layer is prepared on the side of the active layer away from the substrate, and the buffer layer is stacked on one side of at least one main channel region. At least a portion of the buffer layer forms a channel-like region, and the projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate.

[0027] A gate insulating layer is formed on the side of the buffer layer opposite to the active layer, such that the active layer and the buffer layer are located between the substrate and a portion of the gate insulating layer;

[0028] At least one gate is formed on the side of the gate insulating layer away from the substrate, and the gate is disposed in a one-to-one correspondence with the main channel region.

[0029] Optionally, the main doped region is doped along the thickness direction of the array substrate and then doped into the buffer layer;

[0030] Wherein, the projection of the buffer layer in the thickness direction of the array substrate exceeds the projection of the main channel region in the thickness direction of the array substrate; the portion of the buffer layer that exceeds the main channel region is doped to form a doped region.

[0031] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0032] As can be seen from the above embodiments, the array substrate of this disclosure has a channel-like region located between the active layer and part of the gate insulating layer. The projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate. In this way, a dual-channel region can be formed in a similar manner, reducing the electric field at the active layer, thereby reducing leakage current and greatly reducing the occurrence of electro-optical flicker problems when the array substrate is used at low frequency or when switching between high and low frequencies.

[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0035] Figure 1 This is a schematic diagram of an array substrate with a single gate structure according to an exemplary embodiment.

[0036] Figure 2 This is a schematic diagram of an array substrate with a single gate structure according to another exemplary embodiment.

[0037] Figure 3This is a schematic diagram of an array substrate with a single gate structure according to another exemplary embodiment.

[0038] Figure 4 This is a schematic diagram of an array substrate with a single gate structure according to another exemplary embodiment.

[0039] Figure 5 This is a schematic diagram of an array substrate with a single gate structure according to another exemplary embodiment.

[0040] Figure 6 This is a schematic diagram of an array substrate with a dual-gate structure according to an exemplary embodiment.

[0041] Figure 7 This is a schematic diagram of an array substrate with a dual-gate structure according to another exemplary embodiment.

[0042] Figure 8 This is a schematic diagram of an array substrate with a dual-gate structure according to another exemplary embodiment.

[0043] Figure 9 This is a schematic diagram of an array substrate with a dual-gate structure according to another exemplary embodiment.

[0044] Figure 10 This is a schematic diagram of an array substrate with a dual-gate structure according to another exemplary embodiment.

[0045] Figure 11 This is a flowchart illustrating a manufacturing process of an array substrate according to an exemplary embodiment.

[0046] Figure 12 yes Figure 11 Another flowchart of the manufacturing process of the array substrate. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0048] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0049] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0050] Figure 1 This is a schematic diagram of an array substrate with a single-gate structure according to an exemplary embodiment. Figure 2 This is a schematic diagram of an array substrate with a dual-gate structure according to an exemplary embodiment. Figure 1 and Figure 2 As shown, the array substrate includes a substrate 1, a gate insulating layer 2, an active layer 3, at least one gate 4, and at least one channel-like region 5. The gate insulating layer 2 is located on one side of the substrate 1, and the active layer 3 is disposed between the substrate 1 and a portion of the gate insulating layer 2. Specifically, the active layer 3 is disposed on one side of the substrate 1, the gate insulating layer 2 covers the active layer 3, and a portion of the gate insulating layer 2 is connected to one side of the substrate 1.

[0051] The active layer 3 includes at least alternating main doped regions 31 and main channel regions 32. For example, in Figure 1 In the array substrate with the single-gate structure shown, there are two main doped regions 31 and one main channel region 32, with the main channel region 32 located between the two main doped regions 31. Figure 2 In the array substrate with the dual-gate structure shown, there are three main doped regions 31 and two main channel regions 32. Each main channel region 32 is connected to two main doped regions 31 on both sides, and the main doped region 31 in the middle is located between the two main channel regions 32.

[0052] Each gate 4 is disposed on the side of the gate insulating layer 2 facing away from the substrate 1, and each gate 4 corresponds to a main channel region 32. A channel-like region 5 is disposed between the active layer 3 and a portion of the gate insulating layer 2, that is, the channel-like region 5 is disposed on the side of the active layer 3 facing away from the substrate 1, and the gate insulating layer 2 covers the channel-like region 5 and connects to the side of the channel-like region 5 facing away from the active layer 3. Each channel-like region 5 corresponds to a single main channel region 32, and the projection of the channel-like region 5 in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region 32 in the thickness direction of the array substrate.

[0053] The array substrate disclosed herein can reduce the electric field at the active layer 3 by designing a channel-like region 5, thereby reducing leakage current and greatly reducing the occurrence of electro-optical flickering problems when the array substrate is used at low frequencies or when switching between high and low frequencies.

[0054] Since array substrates include at least single-gate array substrates and dual-gate array substrates, for ease of description, this paper will first use a single-gate array substrate as an example.

[0055] like Figure 3 and Figure 4 As shown, in the array substrate with a single-gate structure, regarding the design of the channel-like region 5, in some embodiments, the channel-like region 5 is located on the side of the main channel region 32 facing away from the substrate 1. Both the channel-like region 5 and the main channel region 32 are provided and correspondingly arranged. At least a portion of the projected edge of the channel-like region 5 is recessed inwards by a distance no greater than 3 μm relative to the projected edge of the main channel region 32. This improves the manufacturing efficiency of the main channel region 32 while avoiding the channel-like region 5's effect on reducing leakage current being negatively impacted by excessively recessing its projected edge relative to the main channel region 32 to less than 3 μm.

[0056] For ease of description, the main doped region 31 is divided into a first main doped region 311 and a second main doped region 312, and the main channel region 32 connects the first main doped region 311 and the second main doped region 312. The projection of the channel-like region 5 adjacent to the first main doped region 311 is recessed relative to the corresponding projection edge of the main channel region 32, and the recessed distance L2 is no greater than 3 μm. The projection of the channel-like region 5 adjacent to the second main doped region 312 is flush with the corresponding projection edge of the main channel region 32.

[0057] Alternatively, the projection of the channel-like region 5 adjacent to the second main doped region 312 is recessed relative to the corresponding projection edge of the main channel region 32, and the recessed distance L3 is no greater than 3um, while the projection of the channel-like region 5 adjacent to the first main doped region 311 is flush with the corresponding projection edge of the main channel region 32.

[0058] Alternatively, the projection of the channel-like region 5 adjacent to the first main doped region 311 is recessed relative to the corresponding projection edge of the main channel region 32, and the recessed distance L2 is no greater than 3 μm. The projection of the channel-like region 5 adjacent to the second main doped region 312 is also recessed relative to the corresponding projection edge of the main channel region 32, and the recessed distance L3 is no greater than 3 μm.

[0059] In some other embodiments, along the thickness direction of the array substrate, the projection of the channel-like region 5 coincides with the projection of the main channel region 32. That is, the projection of the channel-like region 5 adjacent to the first main doped region 311 is flush with the corresponding projection edge of the main channel region 32, and the projection of the channel-like region 5 adjacent to the second main doped region 312 is flush with the corresponding projection edge of the main channel region 32.

[0060] Further integration Figure 5 and Figure 6 As shown, in some embodiments, the array substrate includes a doped region 6, which is stacked on the side of the main doped region 31 facing away from the substrate 1. The doped region 6 is connected to the side of the channel-like region 5 that is flush with the main channel region 32. The doped region 6 may be connected to one side or opposite sides of the channel-like region 5.

[0061] For example, if only the projection of the side of the channel-like region 5 adjacent to the first main doped region 311 is flush with the corresponding projection edge of the main channel region 32, then the doped region 6 is only connected to the side of the channel-like region 5 adjacent to the first main doped region 311. If only the projection of the side of the channel-like region 5 adjacent to the second main doped region 312 is flush with the corresponding projection edge of the main channel region 32, then the doped region 6 is only connected to the side of the channel-like region 5 adjacent to the second main doped region 312. If the projections of both the side of the channel-like region 5 adjacent to the first main doped region 311 and the side adjacent to the second main doped region 312 are flush with the corresponding projection edge of the main channel region 32, then the doped region 6 is connected to both the side of the channel-like region 5 adjacent to the first main doped region 311 and the side of the channel-like region 5 adjacent to the second main doped region 312.

[0062] To reduce the impact of the doped region 6 on the performance of the array substrate, the length L1 of the doped region 6 is no greater than 10 μm along the length direction from the main channel region 32 to the main doped region 31. It should be noted that the length L1 of the doped region 6 only represents the length of the doped region 6 on one side of the doped region 5. Furthermore, regarding the design of the doped region 6, along the length direction from the main channel region 32 to the main doped region 31, the edge of the doped region 6 does not extend beyond the edge of the corresponding main doped region 31.

[0063] To enhance the performance gain of the channel-like region 5 on the array substrate, the channel-like region 5 and the doped region 6 are set with the same thickness, and their thickness d is not less than 1 nm and not greater than 10 nm. Due to manufacturing process errors, the channel-like region 5 and the doped region 6 are approximately set with the same thickness, but this error range is within the design tolerances.

[0064] like Figure 7 and Figure 8 As shown, for a dual-gate array substrate, the design features of a single-gate array substrate can be fully applied to a dual-gate array substrate. However, the difference is that in a dual-gate array substrate, there are two gates 4, and at least one set of corresponding gates 4 is provided with a channel-like region 5 between it and the main channel region 32.

[0065] For example, only one channel-like region 5 is provided, and it is located in one of the two sets of corresponding gate 4 and main channel region 32. The projected edge of this channel-like region 5 can be recessed inward or flush with the projected edge of its corresponding main channel region 32. It is worth noting that when the projected edge of the channel-like region 5 is flush with the projected edge of its corresponding main channel region 32 on one side, and this side is adjacent to another main channel region 32, the doped region 6 can extend from this side to the projected edge of the other main channel region 32.

[0066] like Figure 9 and Figure 10 As shown, to better reduce leakage current in the dual-gate array substrate, two channel-like regions 5 are provided, each positioned between a corresponding gate 4 and a main channel region 32. It should be emphasized again that, regardless of whether there is one or two channel-like regions 5 in the dual-gate array substrate, the design features of the channel-like region 5 and the doped region 6 in the single-gate array substrate are applicable to the dual-gate array substrate.

[0067] For a dual-gate array substrate, at least one gate 4 includes a first gate 41 and a second gate 42. Two channel-like regions 5 include a first channel-like region 51 and a second channel-like region 52. The first channel-like region 51 is disposed corresponding to the first gate 41, and the second channel-like region 52 is disposed corresponding to the second gate 42. Two main channel regions 32 are included, and are disposed in a one-to-one correspondence with the first channel-like region 51 and the second channel-like region 52, respectively.

[0068] In some embodiments, the projected edges of the first type of channel region 51 and the second type of channel region 52 are both recessed inward relative to the projected edge of their corresponding main channel region 32.

[0069] In some other embodiments, the projected edge of the first type of channel region 51 is recessed inward relative to the projected edge of its corresponding main channel region 32, and the projected edge of the second type of channel region 52 is flush with the projected edge of its corresponding main channel region 32. Alternatively, the projected edge of the first type of channel region 51 is flush with the projected edge of its corresponding main channel region 32, and the projected edge of the second type of channel region 52 is recessed inward relative to the projected edge of its corresponding main channel region 32. Alternatively, the projected edge of the first type of channel region 51 is flush with the projected edge of its corresponding main channel region 32, and the projected edge of the second type of channel region 52 is also flush with the projected edge of its corresponding main channel region 32.

[0070] When the doped region 6 is connected to the side of the first channel region 51 adjacent to and / or away from the second channel region 52, and the doped region 6 is located on the side of the first channel region 51 adjacent to the second channel region 52, the doped region 6 is in contact with or spaced apart from the second channel region 52.

[0071] The doped region 6 can also be connected to the side of the second channel region 52 that is flush with the main channel region 32, and the doped region 6 located between the first channel region 51 and the second channel region 52 does not contact. The doped region 6 is set with the same thickness as the first channel region 51 and the second channel region 52, and the thickness d of the three is not less than 1 nm and not greater than 10 nm.

[0072] In some embodiments, the array substrate includes an upper insulating layer 7, a first electrode 8, and a second electrode 9. The upper insulating layer 7 is disposed on the side of the gate insulating layer 2 facing away from the substrate 1, and the upper insulating layer 7 covers the gate 4. The first electrode 8 and the second electrode 9 are both disposed on the side of the upper insulating layer 7 facing away from the gate insulating layer 2, and both the first electrode 8 and the second electrode 9 penetrate the gate insulating layer 2 and the upper insulating layer 7, respectively connecting to the main doped region 31. When the doped region 6 is too long, the first electrode 8 and the second electrode 9 may also penetrate the doped region 6. The first electrode 8 is the source electrode, and the second electrode 9 is the drain electrode. Of course, the first electrode 8 can also be the drain electrode, and the second electrode 9 can be the source electrode.

[0073] Accordingly, this disclosure also provides a display panel, including the array substrate described in any of the embodiments above. The display panel can be applied to scenarios such as mobile terminals, wearable devices, smart homes, and computer terminals, and this disclosure does not impose any limitations on it.

[0074] Accordingly, this disclosure also provides an electronic device, including the display panel described in any of the embodiments above. This electronic device may include mobile terminals, wearable devices, smart home devices, computer terminals, etc., and this disclosure does not impose any limitations thereon.

[0075] Figure 11This is a flowchart illustrating a manufacturing process of an array substrate according to an exemplary embodiment, such as... Figure 11 As shown, accordingly, based on the aforementioned array substrate, this disclosure also provides a manufacturing process for the array substrate. The manufacturing process for the array substrate includes the following steps:

[0076] Step 111, Prepare substrate 1.

[0077] Step 112: An active layer 3 is fabricated on one side of the substrate 1. The active layer 3 includes alternating main doped regions 31 and main channel regions 32.

[0078] Step 113: A buffer layer is prepared on the side of the active layer 3 away from the substrate 1, and the buffer layer is stacked on one side of at least one main channel region 32. At least a portion of the buffer layer forms a channel-like region 5, and the projection of the channel-like region 5 in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region 32 in the thickness direction of the array substrate.

[0079] When fabricating the buffer layer, it is prepared at least on the side of the main channel region 32 facing away from the substrate 1. To reduce costs, the buffer layer is laid within the projection range of the main channel region 32 along the thickness direction of the array substrate, so that the projection of the channel-like region 5 does not exceed the projection of the corresponding main channel region 32. The buffer layer may be made of, but is not limited to, silicon hydride. The buffer layer is patterned using, but is not limited to, photolithography and dry etching processes.

[0080] Step 114: Prepare a gate insulating layer 2 on the side of the buffer layer away from the active layer 3, so that the active layer 3 and the buffer layer are located between the substrate 1 and part of the gate insulating layer 2.

[0081] Step 115: At least one gate 4 is formed on the side of the gate insulating layer 2 away from the substrate 1, and the gate 4 is disposed in a one-to-one correspondence with the main channel region 32.

[0082] When forming the gate 4 on the side of the gate insulating layer 2 away from the substrate 1, photoresist is first coated on the side of the gate insulating layer 2 away from the substrate 1, and then the photoresist is processed by a photolithography machine to form a groove to accommodate the gate 4. Subsequently, the bottom of the groove is etched to improve the flatness of the bottom of the groove, and then the gate 4 is placed in the groove.

[0083] like Figure 12 As shown, to improve the manufacturing efficiency of the array substrate, sometimes the buffer layer cannot be completely placed within the projection range of the main channel region 32 along the thickness direction of the array substrate during the fabrication of the buffer layer, thus causing the buffer layer to extend beyond the main channel region 32. In this case, the manufacturing process of the array substrate may further include the following steps:

[0084] Step 121: Doping is performed on the main doped region 31 along the thickness direction of the array substrate, extending to the buffer layer. The projection of the buffer layer along the thickness direction of the array substrate exceeds the projection of the main channel region 32 along the thickness direction of the array substrate. The portion of the buffer layer extending beyond the main channel region 32 is doped to form a doped region 6.

[0085] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0086] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A gate insulating layer, the gate insulating layer being located on one side of the substrate; An active layer is disposed between the substrate and a portion of the gate insulating layer, and the active layer includes at least alternating main doped regions and main channel regions; At least one gate, each of the gates being disposed on the side of the gate insulating layer facing away from the substrate, and the gates being disposed in a one-to-one correspondence with the main channel region; At least one channel-like region is disposed between the active layer and a portion of the gate insulating layer, each channel-like region is disposed corresponding to a single main channel region, and the projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate.

2. The array substrate according to claim 1, characterized in that, At least a portion of the projected edge of the channel-like region is recessed inward by a distance no greater than 3 μm relative to the projected edge of the main channel region.

3. The array substrate according to claim 1, characterized in that, Along the thickness direction of the array substrate, the projection of the channel-like region coincides with the projection of the main channel region.

4. The array substrate according to claim 2 or 3, characterized in that, It also includes a doped region, which is stacked on the side of the main doped region away from the substrate, and the doped region is connected to the side of the channel-like region that is flush with the main channel region.

5. The array substrate according to claim 4, characterized in that, In the length direction along the main channel region to the main doped region, the length L1 of the doped region is no greater than 10 μm.

6. The array substrate according to claim 4, characterized in that, The edge of the doped region does not extend beyond the edge of the corresponding main doped region.

7. The array substrate according to claim 4, characterized in that, The channel-like region and the doped-like region are set to the same thickness, and the thickness d is not less than 1 nm and not greater than 10 nm.

8. The array substrate according to claim 1, characterized in that, The gate is provided in two forms, and at least one set of gates is provided with a channel-like region between the gate and the main channel region.

9. The array substrate according to claim 4, characterized in that, The at least one gate includes a first gate and a second gate; The channel-like region includes a first channel-like region and a second channel-like region, wherein the first channel-like region is disposed corresponding to the first gate and the second channel-like region is disposed corresponding to the second gate; When the doped region is connected to the side of the first channel region adjacent to and / or away from the second channel region, and the doped region is located on the side of the first channel region adjacent to the second channel region, the doped region is in contact with or spaced apart from the second channel region.

10. The array substrate according to claim 9, characterized in that, The doped region is also connected to the side of the second channel region that is flush with the main channel region, and the doped region located between the first channel region and the second channel region does not contact the main channel region.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, Includes the display panel as described in claim 11.

13. A manufacturing process for an array substrate, characterized in that, include: Substrate preparation; An active layer is prepared on one side of the substrate; The active layer includes alternating main doped regions and main channel regions; A buffer layer is prepared on the side of the active layer away from the substrate, and the buffer layer is stacked on one side of at least one main channel region. At least a portion of the buffer layer forms a channel-like region, and the projection of the channel-like region in the thickness direction of the array substrate does not exceed the projection of the corresponding main channel region in the thickness direction of the array substrate. A gate insulating layer is formed on the side of the buffer layer opposite to the active layer, such that the active layer and the buffer layer are located between the substrate and a portion of the gate insulating layer; At least one gate is formed on the side of the gate insulating layer away from the substrate, and the gate is disposed in a one-to-one correspondence with the main channel region.

14. The manufacturing process of the array substrate according to claim 13, characterized in that, Also includes: The main doped region is doped along the thickness direction of the array substrate, and the doping extends to the buffer layer; Wherein, the projection of the buffer layer in the thickness direction of the array substrate exceeds the projection of the main channel region in the thickness direction of the array substrate; the portion of the buffer layer that exceeds the main channel region is doped to form a doped region.

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