An InP-based low-noise high-gain APD monolithic integrated chip and a preparation method thereof

Abstract

The application relates to the technical field of optical communication and optoelectronic integration, in particular to an InP-based APD monolithic integrated chip with low noise and high gain, which comprises a semi-insulating InP substrate, a preamplifier circuit structure and a photodetector epitaxial structure. The preamplifier circuit structure and the photodetector epitaxial structure are both formed on the semi-insulating InP substrate. The photodetector epitaxial structure comprises an absorption layer. A quasi-continuous domain bound state micro-nano structure is arranged on a light incident surface of the photodetector epitaxial structure and is used for limiting the vertical incident light field in the absorption layer. The preamplifier circuit structure is provided with an active device. The active device and the photodetector epitaxial structure are monolithically integrated through a metal interconnection line. The application also comprises a preparation method. The application adopts a low-noise multiplication layer to obtain an ultralow-noise characteristic, and high bandwidth and high absorption efficiency coexist, and monolithic integration is utilized to obtain a synergistic improvement of high gain and high-speed performance, so that the demand of a high-sensitivity ultrawideband receiving chip is met.

Description

Technical Field

[0001] This invention relates to the fields of optical communication and optoelectronic integration technology, and in particular to an InP-based low-noise, high-gain APD monolithic integrated chip and its fabrication method. Background Technology

[0002] With the rapid development of big data, cloud computing, and 5G / 6G communication technologies, optical communication systems are evolving towards ultra-high speed performance of 100Gb / s or even 400Gb / s or more per wavelength. As the core component of the system, the performance of the optical receiving front end directly determines the transmission distance and bit error rate of the entire communication link.

[0003] To measure the high-speed signal processing capability of a device, a key physical quantity is considered: the 3dB bandwidth (f 3dB This represents the frequency range at which the device's output power drops to a low frequency or half of the DC reference value, determined by the transit time bandwidth (f). transit ), RC time constant bandwidth (f RC ) and avalanche establishment bandwidth (f avalanche Jointly decided: f transit The finite transit time required for charge carriers to traverse the depletion region of a device (including the absorption layer, charge layer, and multiplication layer) was characterized. A thinner depletion region can effectively improve fo. transit However, this also leads to lower light absorption efficiency and device gain. RC Primarily influenced by the junction capacitance of the device and the resistance of the external circuitry, a smaller photosensitive surface corresponds to a lower junction capacitance and a higher ft. RC However, it is also limited by its relatively low light absorption efficiency. avalanche There is an inherent trade-off with gain: thinning the multiplication layer can shorten the feedback path of a single round trip of the carrier and increase the avalanche establishment bandwidth, but it limits the achievable multiplication gain.

[0004] Current research shows that traditional PIN photodetectors have high bandwidth but lack internal gain, limiting their sensitivity. Avalanche photodetectors (APDs) utilize the carrier collisional ionization effect to provide internal gain, significantly improving receiver sensitivity. However, existing InP-based APDs also face several limiting challenges:

[0005] 1. The contradiction between gain-bandwidth product and noise: The hole ionization rate of traditional InP multiplication layers is relatively high, resulting in a high excess noise factor (i.e. a large effective ionization rate ratio k factor) of the device, which limits the signal-to-noise ratio at high gain.

[0006] 2. The contradiction between bandwidth and efficiency: In order to increase the speed, the light absorption layer needs to be thinned to shorten the carrier transit time, but this will lead to insufficient light absorption and a decrease in quantum efficiency.

[0007] 3. Parasitic parameter limitations: Traditional discrete APD devices are interconnected with the preamplifier (TIA) via gold wire bonding. The parasitic inductance and capacitance introduced will cause severe signal attenuation and reflection at high frequencies, limiting the total bandwidth of the receiver.

[0008] 4. Constraints of high speed and high gain: To achieve high-speed detection of optical signals, the optimal choice is to make it work in linear mode. However, the gain of traditional discrete APD devices in linear mode has not yet been able to meet the requirements of high-performance detection and high-precision communication.

[0009] Therefore, developing a new type of APD chip that combines low noise, high gain, and ultra-wideband characteristics is a key technical path to break through the current performance bottleneck of InP-based APDs, and also a necessary measure to meet the urgent needs of future ultra-high-speed optical communication systems. Summary of the Invention

[0010] The purpose of this invention is to provide an InP-based low-noise, high-gain APD monolithic integrated chip and its fabrication method, mainly addressing the problems existing in the prior art. It selects InAlAs with a low ionization ratio as the low-noise multiplication material (InAlAsSb, AlGaAsSb, and other materials with extremely small k-factors can also be used), overcoming the constraint of high excess noise factor in the InP multiplication layer; and by combining a quasi-BIC optical field enhancement mechanism, the light absorption efficiency is still guaranteed under the premise of thin absorption multiplication layer and small photosensitive surface; finally, through monolithic integration with a III-V low-noise preamplifier, integrated amplification and high-gain performance in linear mode are achieved while minimizing parasitic capacitance and inductance.

[0011] To achieve the above objectives, the technical solution adopted by the present invention is to provide an InP-based low-noise, high-gain APD monolithic integrated chip, characterized in that it includes a semi-insulating InP substrate, a preamplifier circuit structure, and a photodetector epitaxial structure.

[0012] Both the preamplifier circuit structure and the photodetector epitaxial structure are formed on the semi-insulating InP substrate; the photodetector epitaxial structure includes an absorption layer; a quasi-continuous domain bound state micro / nano structure is provided on the light incident surface of the photodetector epitaxial structure to confine the vertically incident light field within the absorption layer; an active device is provided in the preamplifier circuit structure; the active device and the photodetector epitaxial structure are monolithically integrated through metal interconnects.

[0013] Furthermore, the photodetector epitaxial structure sequentially includes an N-type contact layer, a multiplication layer, a charge layer, the absorption layer, and a P-type contact layer along the epitaxial growth direction; the multiplication layer is composed of a lattice-matched or strain-compensated III-V group semiconductor material; the absorption layer is composed of a III-V group semiconductor material.

[0014] Furthermore, the ionization rate ratio k-factor of the multiplication layer is less than 0.3.

[0015] Furthermore, the multiplication layer is made of InAlAs material; the absorption layer is made of InGaAs material.

[0016] Furthermore, transition layers are provided between the absorption layer and the charge layer, and between the absorption layer and the P-type contact layer, respectively, to smooth band discontinuities and suppress carrier accumulation at the heterojunction interface.

[0017] Furthermore, the quasi-continuous bound state micro / nano structure is a two-dimensional photonic crystal grating or metasurface structure disposed above the epitaxial structure of the photodetector, and a metal reflective layer disposed at the bottom of the semi-insulating InP substrate; the quasi-continuous bound state micro / nano structure transforms the non-radiative continuous bound state mode into a quasi-continuous bound state mode with a finite quality factor Q by breaking the lattice symmetry, thereby realizing the resonant coupling of vertically incident light and lateral transmission mode.

[0018] Furthermore, the active device is a III-V group transistor, specifically an InP-based high electron mobility transistor or a double heterojunction bipolar transistor structure, and is configured as a transimpedance amplifier circuit; the output terminal of the APD and the input terminal of the transimpedance amplifier circuit are connected by a metal interconnect and a built-in resistor to achieve monolithic integration.

[0019] This invention also discloses a method for fabricating the above-mentioned InP-based low-noise, high-gain APD monolithic integrated chip, characterized by comprising the following steps:

[0020] Step S100: The preamplifier circuit structure and the photodetector epitaxial structure are sequentially epitaxially grown on the semi-insulating InP substrate;

[0021] Step S200: Using selective etching technology, the area corresponding to the preamplifier circuit structure is selected and preserved, and the remaining part of the structure is etched to expose the epitaxial structure of the photodetector.

[0022] Step S300: Mesa etching is performed on the epitaxial structure of the photodetector, and sidewall passivation protection is applied.

[0023] Step S400: The quasi-continuous domain bound state micro / nano structure is fabricated in the region above the epitaxial structure of the photodetector;

[0024] Step S500: A metal reflective layer and a metal electrode are fabricated on the bottom of the semi-insulating InP substrate.

[0025] Step S600: Prepare the active devices and passive components in the preamplifier circuit structure;

[0026] Step S700: Deposit a passivation layer and open electrode vias to fabricate metal interconnects, thereby realizing the electrical connection between the preamplifier circuit structure and the photodetector epitaxial structure.

[0027] Furthermore, in step S400, the quasi-continuous domain bound state micro / nano structure is formed on a dielectric hard mask or semiconductor top layer by electron beam lithography and dry etching processes.

[0028] Furthermore, in step S100, a one-time epitaxial growth is performed using metal-organic chemical vapor deposition or molecular beam epitaxy, or a two-stage epitaxial growth technique is used to grow the preamplifier circuit structure and the photodetector epitaxial structure, respectively.

[0029] In view of the above technical features, the present invention has the following significant advantages compared with the prior art:

[0030] 1. This invention utilizes the excellent multiplication characteristics and interface control of InAlAs materials to significantly reduce the effective ionization ratio of APD (k-factor ≤ 0.3), and has ultra-low noise, thereby improving the signal-to-noise ratio.

[0031] 2. This invention utilizes Quasi-BIC micro / nano structures to break the traditional bandwidth-efficiency constraint of detectors, achieving enhanced light absorption under thin absorption multiplication layers and small photosensitive surfaces, thus achieving both high bandwidth and high absorption efficiency.

[0032] 3. The monolithic integration technology of this invention breaks through the limitations of packaging parasitic parameters, and has high-speed integration, enabling the chip to have higher-speed (>50GHz) signal processing capabilities for the future.

[0033] 4. This invention utilizes the monolithic integration of InGaAs / InAlAs APD and III-V low-noise preamplifier to achieve both high gain and high speed, greatly enhancing the gain performance in linear mode. Attached Figure Description

[0034] Figure 1 This is a cross-sectional schematic diagram of the photodetector epitaxial structure in a preferred embodiment of the InP-based low-noise, high-gain APD monolithic integrated chip of the present invention.

[0035] Figure 2 This is a cross-sectional schematic diagram of the preamplifier circuit structure in a preferred embodiment of the InP-based low-noise, high-gain APD monolithic integrated chip of the present invention.

[0036] Figure 3This is a schematic diagram of the connection circuit between the photodetector epitaxial structure and the preamplifier circuit structure in a preferred embodiment of the InP-based low-noise high-gain APD monolithic integrated chip of the present invention.

[0037] Figure 4 This is a schematic diagram of the quasi-continuous domain bound state micro / nano structure in a preferred embodiment of the InP-based low-noise high-gain APD monolithic integrated chip of the present invention.

[0038] Figure 5 This is a side view of a quasi-continuous domain bound state micro / nano structure in a preferred embodiment of the InP-based low-noise, high-gain APD monolithic integrated chip of the present invention.

[0039] Figure 6 This is a schematic diagram of the optical field localization enhancement of a quasi-continuous domain bound state micro / nano structure in a preferred embodiment of the InP-based low-noise high-gain APD monolithic integrated chip of the present invention.

[0040] Figure 7 This is a flowchart of a preferred embodiment of the method for fabricating an InP-based low-noise, high-gain APD monolithic integrated chip of the present invention.

[0041] In the figure: 1-substrate, 2-N-type buffer contact layer, 3-N-type buffer layer, 4-multiplication layer, 5-charge layer, 6-first transition layer, 7-absorption layer, 8-second transition layer, 9-P-type contact layer, 10-metal reflective layer, 11-amplifier contact layer, 12-amplifier buffer layer, 13-collector, 14-charge layer, 15-base, 16-emitter, 17-P-type electrode, 18-N-type electrode, 19-quasi-continuous domain bound state micro / nano structure. Detailed Implementation

[0042] The present invention will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0043] Example 1: InP-based low-noise, high-gain APD monolithic integrated chip.

[0044] Please see Figure 1 and Figure 2 This invention discloses an InP-based low-noise, high-gain APD monolithic integrated chip. As shown in the figure, a preferred embodiment includes a preamplifier circuit structure and a photodetector epitaxial structure disposed on a substrate 1. In this embodiment, substrate 1 is a semi-insulating InP substrate. Both the preamplifier circuit structure and the photodetector epitaxial structure are formed on substrate 1.

[0045] In this embodiment, the photodetector epitaxial structure uses a smaller photosensitive surface (e.g., 20 μm in diameter) to reduce junction capacitance and increase the bandwidth limited by the RC time constant (f RC Small photosensitive surface APDs have lower junction capacitance, which is beneficial for high-frequency response, but reduces optical coupling efficiency. This embodiment combines Quasi-BIC optical field enhancement to maintain high quantum efficiency even with a small photosensitive surface.

[0046] The epitaxial structure of the photodetector, starting from the substrate 1, includes, from bottom to top, an N-type buffer contact layer 2, an N-type buffer layer 3, a multiplication layer 4, a charge layer 5, a first transition layer 6, an absorption layer 7, a second transition layer 8, and a P-type contact layer 9.

[0047] The N-type buffer contact layer 2 is an N-type highly doped InP layer with a thickness of 600 nm and a doping concentration of 5 × 10⁻⁶. 18 / cm 3 It is used to provide low-resistance contacts.

[0048] N-type buffer layer 3 is composed of highly doped N-type In. 0.52 Al 0.48 As, with a thickness of 200 nm and a doping concentration of 5 × 10⁻⁶ 17 / cm 3 It serves as an electric field buffer layer below the multiplication layer 4.

[0049] The multiplication layer 4 is composed of a lattice-matched or strain-compensated group III-V semiconductor material (preferably In in this embodiment). 0.52 Al 0.48 As), its ionization ratio k-factor is less than 0.3 (preferably 0.2 to 0.25 in this embodiment). The multiplication layer 4 is an unintentionally doped layer with a thickness not exceeding 300 nm (100 nm in this embodiment) to shorten the carrier transit time and improve the device bandwidth.

[0050] Charge layer 5 is In 0.52 Al 0.48 An As layer, 50 nm thick, with a p-type doping concentration of 9 × 10⁻⁶. 17 / cm 3 It is used to adjust the electric field between the multiplication layer 4 and the absorption layer 7, ensuring that the absorption layer 7 is in the low field region (to avoid carrier multiplication noise), while the multiplication layer 4 is in the high field region (to allow avalanche multiplication to occur).

[0051] The first transition layer 6 is located between the charge layer 5 and the absorption layer 7, and consists of three unintentionally doped InGaAlAs thin layers, each with a thickness of 30 nm. Specifically, from bottom to top, they are: In... 0.52 Ga 0.12 Al 0.36As, In 0.53 Ga 0.23 Al 0.24 As and In 0.53 Ga 0.35 Al 0.12 As. The first transition layer 6 is to achieve a smooth band transition between the charge layer 5 and the absorption layer 7, and to suppress carrier accumulation at the heterojunction interface.

[0052] Absorbing layer 7 is made of In 0.53 Ga 0.47 Composed of As material, with a thickness of 300nm, it is an unintentionally doped layer. 0.53 Ga 0.47 As materials have a high absorption coefficient in the near-infrared band (1310nm to 1550nm), which can fully absorb and convert photons. Choosing a thinner absorption layer 7 (e.g., less than 500nm, 300nm in this embodiment) can effectively shorten the transit time of photogenerated carriers, which is beneficial to achieving high-speed response.

[0053] The second transition layer 8 is located between the absorption layer 7 and the p-type contact layer 9, and consists of three unintentionally doped InGaAsP thin layers, each with a thickness of 10 nm. Specifically, from bottom to top, they are: In... 0.588 Ga 0.412 As 0.886 P 0.114 In 0.714 Ga 0.286 As 0.619 P 0.381 and In 0.851 Ga 0.149 As 0.327 P 0.673 The second transition layer 8 is designed to achieve a smooth band transition between the absorption layer 7 and the P-type contact layer 9, and to suppress carrier accumulation at the heterojunction interface.

[0054] P-type contact layer 9 is a p-type doped InP layer with a thickness of 150 nm and a doping concentration of 1 × 10⁻⁶. 17 / cm 3 It is used to form a good low-resistance ohmic contact with the upper electrode.

[0055] Please see Figures 4 to 6In this embodiment, a quasi-continuous domain bound state micro / nano structure 19 is also disposed on the light incident surface of the photodetector epitaxial structure (i.e., above the P-type contact layer 9), in conjunction with the metal reflective layer 10 at the bottom of the substrate 1, to confine the vertically incident light field within the absorption layer 7. Specifically, a SiNx dielectric layer 11 is deposited above the P-type contact layer 9. A hole array or columnar array with subwavelength periodicity is formed on the SiNx dielectric layer 11 to constitute a two-dimensional photonic crystal grating or metasurface structure, serving as the quasi-continuous domain bound state micro / nano structure 19. Simultaneously, a gold or silver layer with a thickness of 100 nm is deposited at the bottom of the substrate 1 as a metal reflective layer. In this embodiment, the two-dimensional photonic crystal grating or metasurface structure transforms the non-radiative continuous domain bound state mode into a quasi-continuous domain bound state mode with a finite quality factor Q by disrupting lattice symmetry (e.g., changing circular holes to elliptical holes, or introducing defects into the uniform periodic array), thereby achieving resonant coupling between the vertically incident light and the lateral transmission mode. The light field entering the absorption layer oscillates laterally within the absorption layer due to the reflection effect of the bottom metal reflective layer, thus achieving near-perfect absorption within the thin absorption layer 7 (only 300nm).

[0056] The preamplifier circuit structure includes active components and is monolithically integrated with the photodetector epitaxial structure via metal interconnects and built-in resistors. In this embodiment, the active components are III-V group transistors, specifically InP-based double heterojunction bipolar transistors (DHBTs). The built-in resistors have a resistance value of 1KΩ to 5KΩ. In other embodiments, high electron mobility transistors (HEMTs) may also be used.

[0057] Specifically, the preamplifier circuit structure, from bottom to top, includes an amplifier contact layer 11, an amplifier buffer layer 12, a collector 13, a charge layer 14, a base 15, and an emitter 16. Specifically, the amplifier contact layer 11 is made of InP, doped with 5 × 10⁻⁶ ppm. 17 cm -3 The thickness is 500 nm. The amplifier buffer layer 12 is made of InP, doped with 1×10⁻⁶ ppm. 17 cm -3 The thickness is 100 to 200 nm. The collector 13 is made of InP, doped with 1 × 10⁻⁶ ppm. 15 cm -3 The thickness is 1000 nm. The charge layer 14 is made of InP, doped with 1 × 10⁻⁶ ppm. 17 cm -3 The 30nm thick layer is used to adjust the conduction band offset between the collector and base. Base 15 is made of InGaAs with 5×10⁻⁶ P-type doping. 17 cm -3 The thickness is 300 nm. Emitter 16 is made of InP, doped with 1 × 10⁻⁶ particles. 17 cm -3The thickness is 400 to 500 nm.

[0058] The DHBT is configured as a transimpedance amplifier (TIA) circuit. Specifically, the output of the photodetector epitaxial structure and the input of the transimpedance amplifier circuit (i.e., the emitter of the DHBT) are monolithically integrated via metal interconnects. An internal resistor Re (approximately 10 ohms) can also be connected between the output of the photodetector epitaxial structure and the emitter of the DHBT. 3 Ω), used for impedance matching and stability control.

[0059] The preamplifier circuit structure and the photodetector epitaxial structure share the same substrate 1, with an unintentionally doped InP isolation layer (approximately 300 nm thick) between them for electrical isolation. The P-type electrode 17 (anode) of the photodetector epitaxial structure is connected to the emitter of the preamplifier circuit structure via metal interconnects, and the N-type electrode 18 (cathode) of the photodetector epitaxial structure is connected to the bias voltage. The metal interconnects employ a multilayer metallization process (such as Ti / Pt / Au) and are surface planarized using polyimide. Through monolithic integration, the parasitic inductance and capacitance introduced by bonding wires in traditional discrete device packaging are eliminated, significantly improving high-frequency response characteristics.

[0060] Please see Figure 3 In this embodiment, the cascaded circuit of the preamplifier circuit and the photodetector epitaxial structure is shown in the figure. The output current of the photodetector serves as the emitter input of the preamplifier. An internal resistor Re (approximately 10Ω) is connected between the output terminal of the photodetector and the emitter input terminal of the preamplifier. 3 Ω), used for impedance matching and stability control.

[0061] Example 2: Fabrication method of InP-based low-noise, high-gain APD monolithic integrated chip

[0062] This embodiment provides a method for preparing the chip described in Embodiment 1, including the following steps.

[0063] Please see Figure 7 This invention discloses a method for fabricating an InP-based low-noise, high-gain APD monolithic integrated chip. As shown in the figure, a preferred embodiment includes the following steps:

[0064] Step S100, epitaxial growth.

[0065] On a semi-insulating InP substrate, a photodetector epitaxial structure and a preamplifier circuit structure are sequentially epitaxially grown using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques.

[0066] Specifically, a one-step epitaxial growth method is adopted: the photodetector epitaxial structure (including an N-type buffer contact layer, an N-type buffer layer, a multiplication layer, a charge layer, a first transition layer, an absorption layer, a second transition layer, and a P-type contact layer) and the preamplifier circuit structure (including an amplifier contact layer, an amplifier buffer layer, a collector, a charge layer, a base, and an emitter) are continuously epitaxially grown on the substrate. Alternatively, a two-step epitaxial growth technique can be used, i.e., the photodetector epitaxial structure is first epitaxially grown, and then the preamplifier circuit structure is selectively epitaxially grown using a dielectric mask.

[0067] Step S200: Selected area etching.

[0068] Photolithography is used to define the region corresponding to the preamplifier circuit structure, and a photoresist mask is left above this region. Then, selective etching techniques (such as selective wet etching or dry etching) are used to remove the preamplifier circuit structure layer and isolation layer in the areas not protected by the mask, and the remaining part of the structure is etched until the surface of the underlying photodetector epitaxial structure (i.e., the P-type contact layer) is exposed.

[0069] Step S300: Mesa etching and sidewall passivation of the photodetector epitaxial structure.

[0070] Mesa etching is performed on the exposed photodetector epitaxial structure, extending the etching depth to the N-type buffer layer between the multiplication layer and the substrate, forming the mesa structure of the photodetector epitaxial structure. After etching, the heterojunction interface is surface-treated, and the mesa sidewalls are passivated for protection, such as by depositing SiNx or SiO2 passivation layers, to reduce the interface state density, sidewall leakage current, and dark current.

[0071] Step S400: Fabrication of quasi-continuous domain bound state micro / nano structures

[0072] Quasi-continuous bound-state micro / nano structures are fabricated in the region above the epitaxial structure of a photodetector (i.e., above the P-type contact layer). Specifically, a SiNx dielectric hard mask layer is first deposited; then, a subwavelength periodic pattern (hole or columnar array) is defined using electron beam lithography (EBL); finally, the pattern is transferred to the dielectric hard mask or the top semiconductor layer using a dry etching process (such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP)) to form a hole array or columnar array with a subwavelength period.

[0073] Step S500: Prepare the bottom metal reflective layer and metal electrode.

[0074] A metallic reflective layer (such as a gold or silver layer, approximately 100 nm thick) is deposited at the bottom of the substrate to form a resonant cavity together with the quasi-continuous domain bound-state micro / nanostructure at the top. Simultaneously, N-type electrodes and P-type ohmic contact electrodes are fabricated on the N-type buffer contact layer and P-type contact layer of the photodetector epitaxial structure, respectively.

[0075] Step S600: Prepare the preamplifier circuit structure.

[0076] The fabrication of active devices in the preamplifier circuit structure includes, for example, the emitter, base, and collector mesa and metal electrodes of the DHBT, as well as passive components such as resistors and capacitors. The fabrication process of the preamplifier circuit structure specifically includes mesa etching, base metallization, emitter metallization, and collector metallization of the DHBT.

[0077] Step S700: Metal interconnection and planarization.

[0078] A passivation layer (such as SiNx or SiO2) is deposited on the device surface to protect it. Electrode vias are then formed on the passivation layer to expose the electrodes that need to be interconnected (such as the P-type electrode of a photodetector and the emitter of a DHBT). Metal interconnects are then fabricated (such as electroplated gold or evaporated Ti / Pt / Au) to achieve electrical connections between the preamplifier circuit structure and the photodetector epitaxial structure. Finally, polyimide is used for surface planarization to facilitate subsequent processes or packaging.

[0079] By following the above steps, the InP-based low-noise, high-gain APD monolithic integrated chip described in Example 1 is obtained.

[0080] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A low-noise, high-gain APD monolithic integrated chip based on InP, characterized in that, This includes a semi-insulating InP substrate, a preamplifier circuit structure, and a photodetector epitaxial structure. Both the preamplifier circuit structure and the photodetector epitaxial structure are formed on the semi-insulating InP substrate. The photodetector epitaxial structure includes an absorption layer; a quasi-continuous domain bound state micro / nano structure is disposed on the light incident surface of the photodetector epitaxial structure to confine the vertically incident light field within the absorption layer; an active device is disposed in the preamplifier circuit structure; the active device and the photodetector epitaxial structure are monolithically integrated through metal interconnects.

2. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 1, characterized in that, The photodetector epitaxial structure includes, along the epitaxial growth direction, an N-type contact layer, a multiplication layer, a charge layer, the absorption layer, and a P-type contact layer; the multiplication layer is composed of a lattice-matched or strain-compensated III-V group semiconductor material; the absorption layer is composed of a III-V group semiconductor material.

3. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 2, characterized in that, The ionization rate ratio k-factor of the multiplication layer is less than 0.

3.

4. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 3, characterized in that, The multiplication layer is made of InAlAs material; the absorption layer is made of InGaAs material.

5. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 3 or 4, characterized in that, Transition layers are provided between the absorption layer and the charge layer, and between the absorption layer and the P-type contact layer, respectively, to smooth band discontinuities and suppress carrier accumulation at the heterojunction interface.

6. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 1, characterized in that, The quasi-continuous bound-state micro / nano structure is a two-dimensional photonic crystal grating or metasurface structure disposed above the epitaxial structure of the photodetector, and a metal reflective layer disposed at the bottom of the semi-insulating InP substrate. The quasi-continuous bound-state micro / nano structure transforms the non-radiative continuous bound-state mode into a quasi-continuous bound-state mode with a finite quality factor Q by breaking the lattice symmetry, thereby realizing the resonant coupling between the vertically incident light and the lateral transmission mode.

7. The InP-based low-noise, high-gain APD monolithic integrated chip according to claim 1, characterized in that, The active device is a III-V group transistor, specifically an InP-based high electron mobility transistor or a double heterojunction bipolar transistor structure, and is configured as a transimpedance amplifier circuit; the output terminal of the APD and the input terminal of the transimpedance amplifier circuit are connected by a metal interconnect and a built-in resistor to achieve monolithic integration.

8. A method for fabricating an InP-based low-noise, high-gain APD monolithic integrated chip as described in any one of claims 1 to 7, characterized in that, Includes the following steps: Step S100: The photodetector epitaxial structure and the preamplifier circuit structure are sequentially epitaxially grown on the semi-insulating InP substrate; Step S200: Using selective etching technology, a portion of the area corresponding to the preamplifier circuit structure is retained, and the remaining part of the structure is etched to expose the photodetector epitaxial structure. Step S300: Mesa etching is performed on the epitaxial structure of the photodetector, and sidewall passivation protection is applied. Step S400: The quasi-continuous domain bound state micro / nano structure is fabricated in the region above the epitaxial structure of the photodetector; Step S500: A metal reflective layer and a metal electrode are fabricated on the bottom of the semi-insulating InP substrate. Step S600: Prepare the active devices and passive components in the preamplifier circuit structure; Step S700: Deposit a passivation layer and open electrode vias to fabricate metal interconnects, thereby realizing the electrical connection between the preamplifier circuit structure and the photodetector epitaxial structure.

9. The preparation method according to claim 8, characterized in that, In step S400, the quasi-continuous domain bound state micro / nano structure is formed on a dielectric hard mask or semiconductor top layer by electron beam lithography and dry etching processes.

10. The preparation method according to claim 8, characterized in that, In step S100, a one-time epitaxial growth is performed using metal-organic chemical vapor deposition or molecular beam epitaxy, or a two-stage epitaxial growth technique is used to grow the preamplifier circuit structure and the photodetector epitaxial structure, respectively.

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