High-reliability CSP light source packaging positioning system

Abstract

The application belongs to the technical field of semiconductor packaging and is used for solving the problem that the prior art cannot eliminate local geometric distortion caused by reference switching under the double constraints of ensuring absolute positioning accuracy and relative position accuracy, and particularly relates to a high-reliability CSP light source packaging positioning system which comprises a mounting pre-positioning module, a spatial difference analysis module, an influence weight generation module, a mounting position locking module and a mounting execution module; the absolute accuracy constraint and the relative accuracy constraint are transformed from binary opposition into continuous decision-making of weighted fusion, so that the two constraints are smoothly transitioned in space, stress mutation caused by reference switching is eliminated from the root, and the geometric consistency of the chip array is significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically a high-reliability CSP light source packaging and positioning system. Background Technology

[0002] High-density multi-chip integrated packaging technology, such as micro LED display modules and adaptive high beam modules, requires the mounting of dozens to hundreds of chips on a single substrate with micron-level precision. The accuracy of chip mounting position directly determines the optical performance and reliability of the final product. Therefore, the positioning accuracy of die bonding equipment is a core technical indicator in this field.

[0003] In existing technologies, the positioning strategies of die bonding equipment are mainly divided into two categories. The first category is global reference positioning, in which the equipment uses a preset global marker point on the substrate as a reference, identifies the position of the marker point through a vision system, and aligns each chip independently to its design coordinates. This strategy can ensure the positional accuracy of each chip relative to the overall coordinate system of the substrate, but it cannot constrain the relative positional error between adjacent chips. The second category is local reference positioning, in which the equipment uses the actual position of the already mounted chips as a reference and determines the mounting position of subsequent chips in a relay manner. This strategy can ensure the consistency of the spacing between adjacent chips, but it will lead to the cumulative offset of the overall array relative to the design coordinates of the substrate.

[0004] In actual production, equipment typically switches between the two strategies mentioned above based on process requirements, using a global reference in some areas and a local reference in others. This switching mechanism logically assumes that the two strategies can operate independently without interference. However, when the references of the two strategies are spatially adjacent, the switching boundary is constrained by both sets of references simultaneously (one side of the chip is required to align with the global marker point, and the other side is required to maintain consistent spacing with adjacent chips). If there is a slight deviation between the two sets of references, a geometric conflict arises at the boundary, which cannot be resolved by selecting any single reference. This contradiction leads to local geometric distortion in the reference switching area of ​​the chip array, manifesting as an unintended distortion in the relative positions of the chips. This distortion is absorbed by the plastic deformation of the solder layer, becoming a potential cause of fatigue cracking in subsequent reliability testing; on the other hand, it manifests as pixel misalignment or spot shift in the optical array, directly affecting the product's optical performance. Therefore, how to eliminate the local geometric distortion caused by reference switching while ensuring both absolute positioning accuracy and relative position accuracy has become a pressing technical problem in this field. Summary of the Invention

[0005] The purpose of this invention is to provide a highly reliable CSP light source packaging positioning system to solve the problem that existing technologies cannot eliminate local geometric distortion caused by reference switching under the dual constraints of ensuring absolute positioning accuracy and relative position accuracy. The technical problem to be solved by this invention is: how to provide a highly reliable CSP light source packaging positioning system that can eliminate local geometric distortion caused by reference switching under the dual constraints of ensuring absolute positioning accuracy and relative position accuracy.

[0006] The objective of this invention can be achieved through the following technical solutions: A high-reliability CSP light source packaging positioning system, comprising: Mounting prepositioning module: obtains the design position coordinates of the chip to be mounted, the global anchoring target position of the chip to be mounted, and the deviation vector between the actual position coordinates and the design position coordinates of each mounted chip in the set of mounted chips; Spatial difference analysis module: Based on the deviation vector of each mounted chip in the mounted chip set and the preset chip topology connection relationship, calculate the topological stress value of each mounted chip. The topological stress value is used to characterize the degree of spatial difference of the deviation vector between the mounted chip and its adjacent mounted chips. Influence weight generation module: Generates deviation influence weight and topology influence weight based on the dispersion of the deviation vector of the assembled chip set and the topological stress value of the adjacent assembled chips of the chip to be mounted. Mounting position locking module: Based on the deviation influence weight, the topology influence weight, the global anchoring target position of the chip to be mounted, and the deviation vector of the adjacent mounted chips of the chip to be mounted, the module performs weighted fusion processing on the global anchoring target position and the local anchoring reference position of the chip to be mounted to obtain the target mounting position of the chip to be mounted. The local anchoring reference position is determined based on the design position coordinates of the chip to be mounted and the deviation vector of its adjacent mounted chips. Placement execution module: controls the placement execution mechanism to perform placement operations according to the target placement position.

[0007] The present invention has the following beneficial effects: By employing a dual-field weighted fusion mechanism of deviation influence weight and topology influence weight, the geometric conflict at the switching boundary between the global and local references is eliminated. Existing technologies use a "two-choice" reference switching mode, which inevitably creates a contradiction at the switching boundary: one side of the chip is required to align with the substrate marking point, while the other side of the chip is required to maintain consistent spacing with adjacent chips, resulting in local geometric distortion. This invention transforms the absolute precision constraint and relative precision constraint from a binary opposition into a weighted fusion continuous decision, enabling a smooth spatial transition between the two constraints. This fundamentally eliminates the stress abruptness caused by reference switching and significantly improves the geometric consistency of the chip array. By constructing and dynamically feeding back topological stress values, this invention achieves quantitative perception and proactive guidance of the degree of distortion within the chip array. Existing technologies only focus on whether a single chip falls within the allowable range of the pads, failing to perceive the spatial accumulation of deviation gradients between adjacent chips, resulting in local distortions being implicitly solidified within the array. This invention defines topological stress using the sum of the squares of the magnitudes of the spatial gradients of the deviation vectors, and uses it as a driving factor to dynamically adjust the weights of local anchoring constraints. This allows the system to automatically strengthen local constraints in stress-concentrated regions to relax the distortion, and automatically strengthen global constraints in stress-sparse regions to correct the overall offset, thereby achieving adaptive optimization of stress distribution. By deconstructing the deformation mode discrimination factor and the stress field spatial gradient, the mounting result is upgraded from a binary judgment of whether a single chip is qualified to a quantifiable attribution analysis. Existing technologies cannot distinguish the essential difference between overall array offset and local distortion, resulting in a lack of clear direction for process optimization. This invention generates a deformation mode discrimination factor by using the ratio of the deviation direction consistency coefficient to the stress field uniformity index. This factor can accurately identify whether the substrate deformation is an overall rigid deformation or a local distortion deformation, and output the center coordinates of the local distortion region, providing a quantitative basis for targeted adjustment of process parameters. By using deformation modal time-series analysis and adaptive adjustment of weight parameters, real-time monitoring and proactive intervention of the mounting process stability are achieved. Existing technologies lack adaptive mechanisms when process conditions fluctuate, making it difficult to control quality differences between batches. This invention records the switching frequency of deformation modal labels during continuous mounting. When the switching frequency exceeds a preset threshold, the generation parameters of deviation influence weight and topology influence weight are automatically adjusted to enhance the sensitivity of local topological constraints and suppress local distortion diffusion. This proactive intervention when the process condition is unstable improves the process robustness of mass production. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a system block diagram of Embodiment 1 of the present invention; Figure 2 This is a data flow processing flowchart of Embodiment 1 of the present invention. Detailed Implementation

[0010] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] In the field of multi-chip integrated packaging, especially in high-end applications such as micro LED display modules and adaptive high beam modules, the micron-level precision of chip mounting positions directly determines the optical performance and reliability of the final product. From a mechanical perspective, the high-precision mounting process needs to ensure the absolute positional accuracy of each chip relative to the overall coordinate system of the substrate while maintaining a high degree of consistency in the relative positions between adjacent chips. This dual constraint is physically equivalent to the minimum energy state of an elastic system, that is, the final positional distribution of the chip array should be the equilibrium point under the combined action of global anchoring potential energy and local elastic potential energy.

[0012] However, existing die bonding equipment generally treats absolute accuracy and relative accuracy as mutually exclusive optimization goals, and operates by choosing between "global reference" and "local reference" or simply switching according to chip number. This linear logic has a structural blind spot - it assumes that the two references can operate independently and without interference, but ignores the geometric conflict that will inevitably occur at the reference switching boundary: one side of the chip is required to align with the substrate marking point, and the other side of the chip is required to maintain the same spacing with the adjacent chip. The small deviation between the two sets of references forms an irreconcilable contradiction at the boundary.

[0013] For example, in the mass production mounting of automotive-grade micro LED display modules, when the equipment switches from a global reference mode to a local reference mode, the chip array near the switching boundary exhibits unintended local distortions, manifesting as shear deformation in the relative positions of the chips. Existing visual inspection systems can only determine whether each chip falls within the allowable range of its respective pad, but cannot detect the spatial accumulation of deviation gradients between adjacent chips. Furthermore, this local distortion is absorbed by the plastic deformation of the solder layer, becoming a potential cause of early fatigue cracking in subsequent temperature cycling tests; simultaneously, in optical performance testing, it manifests as pixel misalignment or spot shift, directly affecting display uniformity and light distribution accuracy.

[0014] If the above problems are not solved, high-density integrated packaging technology will always be trapped in the dilemma of "absolute accuracy is qualified but relative accuracy fails" or vice versa, resulting in large fluctuations in product yield and significant batch-to-batch reliability differences. Specifically, the failure to identify geometric conflicts at the reference switching boundary will cause uneven stress distribution within the array, causing some chips to be subjected to unintended shear stress for a long time, thus accelerating solder joint failure. At the same time, the regional differences in stress accumulation cannot be captured by traditional single-chip detection methods, resulting in a lack of quantitative basis for process optimization, and ultimately preventing the technological advantages of high-precision packaging from being transformed into stable mass production capabilities.

[0015] Example 1: As Figure 1-2 As shown, a high-reliability CSP light source packaging positioning system includes: Pre-positioning module for mounting: obtains the design position coordinates of the chip to be mounted, the global anchoring target position of the chip to be mounted, and the deviation vector between the actual position coordinates and the design position coordinates of each mounted chip in the set of mounted chips; In the specific implementation process, the mounting pre-positioning module serves as the data entry point and benchmark anchor point for the entire system. Its core function is to provide accurate and traceable initial positioning information for subsequent spatial difference analysis and weight fusion. This embodiment configures this module as follows.

[0016] The placement pre-positioning module first obtains the design position coordinates of the chip to be placed. These coordinates originate from the computer-aided design file of the chip array. In the design file, each chip is assigned a unique identifier and its theoretical position coordinates in the design coordinate system, denoted as . Simultaneously, this module acquires the global anchoring target position of the chip to be mounted. The acquisition of the global anchoring target position relies on the measurement of the substrate's global reference (i.e., the design coordinates and measured coordinates of preset global mark points; global mark points are pre-fabricated positioning marks on the substrate used to establish the substrate's global coordinate system). Specifically, the system first reads the design coordinates of multiple preset global mark points on the substrate. The actual coordinates of these marker points were obtained by measuring them before placement using the die bonder's vision system. Based on these two sets of coordinates, the system uses the least squares method to solve for the rigid body transformation parameters of the entire substrate, including translation parameters. Rotation parameters and scaling parameters During the solution process, the system first calculates the centroids of the two sets of marker point coordinates, centers the coordinates, calculates the covariance matrix, obtains the rotation matrix through singular value decomposition, and then inversely calculates the translation and scaling factors. Subsequently, the design position coordinates of the chip to be mounted are transformed according to the scaling, rotation, and translation parameters, i.e. This yields the global anchoring target position of the chip. This transformation parameter is considered constant during a single batch of mounting. If significant thermal deformation occurs on the substrate during mounting, this step can be re-executed at a preset interval for correction.

[0017] The placement pre-positioning module is also responsible for maintaining the deviation vector between the actual position coordinates and the designed position coordinates of each chip in the placed chip set. Specifically, after each chip is placed, the system measures its actual placement coordinates using the die bonder's vision system. And calculate the chip's deviation vector. This deviation vector records the absolute positioning error of each chip during the mounting process, serving as the basis for all subsequent spatial difference analyses.

[0018] To construct the topological constraints between chips, the system pre-parses the computer-aided design file of the chip array, extracting the design location coordinates of each chip and the adjacency definitions between them. These adjacency relationships can be explicitly defined in the design file, such as the adjacency constraints between pixels in an optical array, or they can be automatically determined based on chip spacing thresholds. The system constructs an undirected graph with each chip as a node and adjacency definitions as edges, and establishes a set of adjacent nodes for each chip. This includes the identifiers of other chips that have adjacency constraints with this chip. This topology remains static during the mounting process.

[0019] During the operation of the placement pre-positioning module, the system needs to obtain the deviation vector of adjacent already placed chips in real time for the chip to be placed. Therefore, for the current chip to be placed... The system starts from its set of adjacent nodes. The chips that have been successfully mounted are selected from the pool and a set of adjacent mounted chips is formed. And read the deviation vectors of these adjacent chips from the stored deviation vector array. These data will serve as the basis for constructing local anchoring reference positions in subsequent weighted fusion processing.

[0020] In addition, the pre-positioning module also needs to obtain the filtered topological stress values ​​of each mounted chip. This data is updated and stored by the spatial difference analysis module after each chip is mounted. The calculation process of the filtered topological stress values ​​will be detailed in subsequent modules, but the pre-positioning module ensures that this data is available before running. All the above data—including the design position coordinates of the chip to be mounted, the global anchoring target position, the deviation vector of adjacent mounted chips, and the filtered topological stress values ​​of each mounted chip—are aggregated in the pre-positioning module, providing a complete set of input data for the subsequent influence weight generation module and mounting position locking module.

[0021] To illustrate the above process, consider a specific example: Suppose a miniature LED display module contains 16 chips arranged in 4 rows and 4 columns. The 7th chip is currently being mounted, and its designed position coordinates are... The system has pre-calculated the rigid body transformation parameters using substrate markers, thus obtaining the global anchoring target position of the chip. The set of adjacent nodes of this chip includes the chip already mounted on the left (the 6th chip) and the chip already mounted above (the 3rd chip), and their offset vectors are respectively and The mounting pre-positioning module then calculates the positions of the two virtual anchor points as follows: and Meanwhile, the system obtains the filtered topological stress values ​​of the 6th and 3rd chips from the spatial difference analysis module, which are 0.8 and 1.2, respectively. These data, along with other weighting parameters, will be passed to subsequent modules for fusion calculation.

[0022] Spatial difference analysis module: Based on the deviation vector of each mounted chip in the mounted chip set and the preset chip topology connection relationship, calculate the topological stress value of each mounted chip. The topological stress value is used to characterize the degree of spatial difference of the deviation vector between the mounted chip and its adjacent mounted chips. The core function of the spatial difference analysis module is to transform the discrete deviation vectors of the mounted chips into a quantifiable topological stress field, thereby revealing the degree of spatial distortion within the chip array. This embodiment configures this module as follows.

[0023] First, the system needs to construct a pre-defined topological connection relationship between chips as the structural basis for spatial difference analysis. Specifically, before mounting begins, the system parses the computer-aided design file of the chip array, extracting the unique identifier and design position coordinates of each chip, and simultaneously extracting the adjacency relationship definition between chips. This adjacency relationship can be an explicit connection relationship defined in the design file, such as row and column adjacency between pixels in a micro LED display module, or it can be an adjacency relationship automatically determined based on a chip spacing threshold. The system constructs an undirected graph with each chip as a node and adjacency relationships defined as edges, and establishes a set of adjacent nodes for each chip. This set of adjacent nodes records the connections to the chip. All other chip markings with optical or mechanical constraints remain static during mounting. This design allows topological constraints to accurately reflect the product's optical design intent, rather than simply relying on spatial distance.

[0024] The core calculation object of the spatial difference analysis module is the topological stress value, which is used to quantitatively characterize the degree of spatial difference in the deviation vector between a mounted chip and its adjacent mounted chips. For any mounted chip... Its deviation vector The pre-positioning module has already calculated and stored this information in the preceding steps. After each placement is completed, the system iterates through the set of placed chips. Perform the following calculation process.

[0025] For each mounted chip The system first obtains the set of adjacent mounted chips. This refers to the subset of chips that have already been mounted within the set of adjacent nodes. If If empty, the chip has not yet formed a constraint with any adjacent mounted chips, and its topological stress value is set to zero. If not empty, then for each adjacent chip... The system calculates the relative deviation gradient between the chip and its neighboring chips. The physical meaning of this relative deviation gradient is that it quantifies the degree of consistency in the direction and magnitude of the deviation generated by two adjacent chips during the mounting process. When the two deviations are completely consistent, the gradient is zero, indicating that only overall translation occurs in the local area without distortion. When there is a difference in the two deviations, the magnitude of the gradient reflects the degree of local shearing or stretching.

[0026] Based on the aforementioned relative deviation gradient, the system further calculates the chip... The original topological stress value It is defined as the sum of the squares of the relative deviation gradient magnitudes between the chip and all its adjacent mounted chips, i.e. The use of a sum of squares instead of a sum of absolute values ​​is intended to amplify the effect of larger gradients, making the system more sensitive to severe local distortions. This original topological stress value directly reflects the chip's... The degree of geometric distortion it experiences within its local neighborhood.

[0027] However, due to inherent noise in vision system measurements, directly using the raw topological stress values ​​may lead to instability in weight calculations. Therefore, the system introduces a neighborhood averaging filter mechanism to smooth the raw topological stress values. Specifically, for each mounted chip... The system obtains its own original topological stress value. and its adjacent set of mounted chips The original topological stress values ​​of each chip are obtained, and the arithmetic mean of these stress values ​​is calculated to obtain the filtered topological stress values. This filtering operation utilizes the spatial correlation of stress values ​​in the neighborhood chip, effectively suppressing interference from isolated noise points while preserving the regional stress distribution trend.

[0028] In continuous chip placement, if the topological stress value of the entire placed array is recalculated after each placement, the computational load will increase quadratically with the number of chips. Therefore, the system employs an incremental update strategy, updating only the localized areas affected by newly placed chips. When the chip... After mounting, its deviation vector It is known that the system obtains its adjacent set of mounted chips. For each adjacent chip in this set The system calculates the new relative deviation gradient. And calculate the new stress contribution value. Subsequently, the system will use the newly added stress contribution value as the chip's... The original topological stress value And this value is accumulated to each adjacent chip. In the original topological stress value, i.e. After completing the above accumulation, the system only processes the chip. and its adjacent chips The original topological stress values ​​are reapplied with neighborhood averaging filtering to obtain updated filtered topological stress values ​​for these chips, while the filtered values ​​for other unaffected chips remain unchanged. This incremental update mechanism ensures that the computational complexity after a single placement is only linearly related to the number of adjacent chips, guaranteeing that the system can still respond in real time in large-scale array placement of hundreds of chips.

[0029] For ease of understanding, let's continue with the example of the miniature LED display module. Assume that the currently mounted chips include the 3rd and 6th chips, and their deviation vectors are respectively... and Furthermore, chips 3 and 6 are adjacent to chip 7 in the topology diagram, but they are not actually adjacent to each other. After mounting chip 7, its deviation vector was measured to be... For the 7th chip, its adjacent set of already mounted chips... The system calculates the relative deviation gradient. and Their modulus squares are respectively and ,therefore For the third chip, its original topological stress value is calculated based on its relationship with other adjacent chips (let's say the first chip). New stress contribution value Therefore, after the update Similarly, after the sixth chip is updated, the original topological stress value changes from the assumed value. Become Subsequently, the system performs neighborhood averaging filtering on chips 3, 6, and 7 respectively. Assume that the adjacent mounted chips of chip 3 include chips 1 and 7, and their original stress values ​​are respectively... , Then after filtering Similarly, the filtered stress values ​​of other chips are calculated to ultimately form an updated topological stress field. These stress values ​​will serve as input to the subsequent influence weight generation module, used to dynamically adjust the local constraint strength in the localization strategy.

[0030] After the spatial difference analysis module completes the topological stress field calculation, this embodiment further configures a substrate deformation mode deconstruction function. Specifically, after obtaining the deviation vector and filtered topological stress value of each chip in the mounted chip set, the system executes the following analysis process.

[0031] The system first calculates the direction angle of each deviation vector. For each mounted chip... Its deviation vector Direction angle Defined as The range of values ​​is The system statistically analyzes the distribution of orientation angles of all mounted chips and calculates the central tendency index of the orientation angle distribution. Specifically, the system uses a circular distribution statistical method to calculate the ratio of the magnitude of the sum of the unit vectors of each orientation angle to the number of chips. The ratio The value range is [0,1]. A value closer to 1 indicates a more concentrated orientation angle, while a value closer to 0 indicates a more dispersed orientation angle. The system will... As the consistency coefficient of the deviation direction, it is denoted as .

[0032] Simultaneously, the system calculates the spatial gradient of the filtered topological stress value on the substrate plane. For each mounted chip... The system obtains its designed position coordinates on the substrate plane. The system calculates the spatial gradient using the stress values ​​of its adjacent chips. Specifically, the system employs a finite difference method for each chip. Calculate the gradient components in the X direction respectively. and gradient components in the Y direction The denominator is the design coordinate difference between adjacent chips; if < ( The value is a preset minimum positive number. At this point, only the Y-axis gradient component is used, or the adjacent edge is skipped; that is, gradient calculation is only performed on adjacent chips with different X-coordinates. Subsequently, the system calculates the magnitude of the spatial gradient for each chip. The system uses the average spatial gradient magnitude of each chip as an index of stress field uniformity. This index reflects the degree of spatial variation in stress—the larger the value, the more uneven the stress field.

[0033] Based on the above two indicators, the system generates a substrate deformation mode discrimination factor. ,in To prevent decimals from being divided by zero, the value is taken as follows: The physical meaning of this discrimination factor is as follows: when the deviation directions are highly consistent and the stress field changes gradually, the discrimination factor is large, indicating that the substrate mainly undergoes overall rigid deformation; when the deviation directions are dispersed and the stress field changes drastically, the discrimination factor is small, indicating that the substrate has local torsional deformation. The system compares the discrimination factor with a preset first threshold. Second threshold Comparison, among which When the discriminant factor is higher than When the system outputs the overall rigid body deformation mode label, it outputs the overall rigid body deformation mode label; when the discriminant factor is lower than 1, the system outputs the overall rigid body deformation mode label. Then, the system further locates the center coordinates of the local distortion region. The specific method is as follows: traverse all chips and select the spatial gradient magnitude. The largest chip is used as the center of the local distortion region, and the designed position coordinates of this chip are output as the center coordinates. Simultaneously, the local distortion deformation mode label is output. The values ​​of the two thresholds are calibrated through offline experiments, based on the manually labeled deformation mode classification results in historical data, selecting the threshold combination that achieves the highest classification accuracy.

[0034] Influence weight generation module: Generates deviation influence weight and topology influence weight based on the dispersion of the deviation vector of the assembled chip set and the topological stress value of the adjacent assembled chips of the chip to be mounted. The core function of the influence weight generation module is to dynamically calculate two weight coefficients based on the deviation distribution characteristics and stress distribution characteristics of the currently mounted area. These coefficients are used to adjust the relative importance of global anchoring constraints and local topological constraints in the positioning decision. This embodiment configures this module as follows.

[0035] The input data for this module comes from the placement pre-positioning module and the spatial difference analysis module. Specifically, before each chip is placed, the system obtains the deviation vector of each chip in the set of already placed chips from the placement pre-positioning module. The filtered topological stress values ​​of each chip are obtained from the spatial difference analysis module. and the set of adjacent already mounted chips to be mounted. The filtered topological stress values ​​of each adjacent chip.

[0036] The process of generating the deviation impact weights is based on the dispersion of the deviation vectors of the mounted chip set. The system first calculates the arithmetic mean of the deviation vectors in the mounted chip set to obtain the mean deviation vector. This mean reflects the overall offset trend of the currently mounted array. Subsequently, the system calculates the standard deviation of each deviation vector relative to this mean, i.e. This standard deviation quantitatively describes the dispersion of the deviation vector; a larger value indicates greater inconsistency in the direction and magnitude of the deviations of each chip. Simultaneously, the system calculates the arithmetic mean of the magnitudes of each deviation vector, i.e. This indicator reflects the average magnitude of the deviation.

[0037] Based on the above statistics, the system generates the bias influence weight. Its calculation logic is as follows: ,in The preset maximum deviation influence weighting coefficient, To prevent the division by zero (taking a value of 0.1 micrometers); if the calculated value is... If the value is less than zero, it is set to zero. The physical meaning of this formula is that when the dispersion (standard deviation) of the deviation vector is small relative to the average deviation magnitude, it indicates that the deviations of each chip have good consistency. In this case, the global anchoring constraint should have a higher weight to pull the overall array back to its design position. Conversely, when the dispersion of the deviation vector is large, the confidence of the global anchoring decreases, and its weight decreases accordingly. The system will calculate the... Clamp to The range is used to ensure that the weight values ​​are within a reasonable range.

[0038] The generation process of topology influence weights is based on the topology stress values ​​of the adjacent already mounted chips of the chip to be mounted. The system first obtains the set of adjacent already mounted chips of the chip to be mounted. The filtered topological stress values ​​of each adjacent chip are used to calculate the arithmetic mean of these stress values, thus obtaining the neighborhood average stress value. This indicator reflects the degree of geometric distortion in the area surrounding the chip—the greater the stress value, the more significant the relative deviation gradient between chips in the neighborhood, and the more severe the local distortion.

[0039] Subsequently, the system generates topology influence weights. Its calculation logic is as follows: ,in The preset maximum topological influence weighting coefficient. This is a preset reference stress threshold; A value greater than zero should be used. If this is detected during system initialization... If the value is ≤0, it will be automatically assigned the preset default value (e.g., 1μm²). The calibration method is as follows: Under stable process conditions, mount a standard array, calculate the filtered topological stress values ​​of all chips, and take the 75th percentile of this distribution as the reference threshold. If the product is sensitive to local distortion, the quantile can be reduced (e.g., to 50%), and vice versa. The physical meaning of this formula is that when the neighborhood average stress value is lower than the reference threshold, the degree of local distortion is relatively mild, and the weight of the local anchoring constraint increases proportionally with the stress value; when the stress value exceeds the reference threshold, the weight reaches the saturation upper limit. This is to prevent excessive local constraints from dominating decision-making due to excessive stress. This saturation characteristic ensures that the system can maintain a reasonable constraint balance even under extreme torsion conditions.

[0040] and The initial values ​​are obtained through simulation optimization, simulating the final deviation of the array under different weight combinations, and selecting the combination that minimizes the overall deviation; in actual production, fine-tuning can be performed based on process experience.

[0041] After calculating the weight of the deviation effect respectively and topological influence weights The system then normalizes the two values ​​until their sum equals 1. The normalization formula is as follows: , If the sum of the total weights is less than 0.01, then a forced setting will be applied. , This ensures that the system has reasonable constraint guidance under any extreme conditions.

[0042] The preset parameters involved in the above calculation process , and The calibration was obtained through offline experiments. The calibration process is as follows: A test substrate with the same array layout and substrate material as the target product was selected, and the entire array was mounted under stable process conditions. During the mounting process, the system iterated through preset parameter combinations, such as... The values ​​are 0.5, 1.0, 1.5, and 2.0. The values ​​are 0.5, 1.0, 1.5, and 2.0. The values ​​are taken as the 30th, 50th, and 70th percentiles of the statistical distribution of the filtered topological stress values ​​of each chip in historical data. For each set of parameters, the system simulates the positioning method of this embodiment and records the overall variance of the deviation vector of each chip after mounting. The parameter set that minimizes the overall variance is selected as the final calibration result. This calibration process is completed in one go during the equipment commissioning phase, and the calibrated parameters are permanently stored in the system configuration.

[0043] For ease of understanding, we will continue using the previous example of a miniature LED display module. Assuming there are currently 10 chips mounted, the calculated mean deviation vector is... Standard deviation Mean deviation modulus The preset maximum deviation affects the weighting coefficient. The bias affects the weight. Meanwhile, assuming the adjacent already mounted chips to be mounted are the 3rd and 6th chips, their filtered topological stress values ​​are respectively... , Neighborhood average stress value Preset reference stress threshold Maximum topological influence weighting coefficient Then the topological influence weight (Since the ratio is greater than 1, the saturation value is taken). At this point, the total weight sum is 0.486 + 1.0 = 1.486, after normalization... , The results indicate that, due to the neighborhood average stress exceeding the reference threshold, local distortion is more pronounced, thus local anchoring constraints receive higher weights, while the weights of global anchoring constraints are correspondingly reduced. This weight combination will be passed to the mounting position locking module for subsequent weighted fusion calculations.

[0044] The calibration experiment should use at least three different batches of test substrates, with each group being repeatedly mounted no less than five times. The intersection or average of the optimal parameters of each group should be taken to enhance the robustness of the calibration results.

[0045] Mounting position locking module: Based on the deviation influence weight, the topology influence weight, the global anchoring target position of the chip to be mounted, and the deviation vector of the adjacent mounted chips of the chip to be mounted, the module performs weighted fusion processing on the global anchoring target position and the local anchoring reference position of the chip to be mounted to obtain the target mounting position of the chip to be mounted. The local anchoring reference position is determined based on the design position coordinates of the chip to be mounted and the deviation vector of its adjacent mounted chips. The core function of the mounting position locking module is to fuse the two weighting coefficients output by the weight generation module with the global anchoring target position and the local anchoring reference position provided by the mounting pre-positioning module. Through weighted optimization, it solves for the optimal mounting position that simultaneously satisfies both absolute and relative accuracy constraints, and outputs executable target coordinates within the hardware constraint boundaries. This embodiment provides the following specific configuration for this module.

[0046] The input data for this module comes from the placement pre-positioning module, the spatial difference analysis module, and the influence weight generation module. Specifically, before each chip is placed, the system obtains the design position coordinates of the chip to be placed from the placement pre-positioning module. Global anchoring of target location and adjacent already mounted chip sets Deviation vector of each adjacent chip Obtain the acceptable mounting area of ​​the pads from the spatial difference analysis module. Obtain the normalized bias influence weights from the influence weight generation module. and topological influence weights These data collectively constitute the input space for location decision-making.

[0047] The placement position locking module first constructs the specific form of the local anchoring reference position. This is for the set of adjacent already placed chips to be placed. Each adjacent chip in The system adds the design position coordinates of the chip to be mounted to the deviation vector of the adjacent chip, i.e. The system obtains the virtual anchor point position corresponding to the adjacent chip. The physical meaning of this virtual anchor point is that it represents the position the current chip should be in if it maintains the same deviation direction and magnitude as the adjacent chip. In this way, the system transforms the actual deviation information of the adjacent chips into a local anchoring reference for the current chip, enabling a quantitative expression of relative position constraints.

[0048] Based on this, the system constructs a dual-field cooperative potential function, incorporating the global anchoring target position and the positions of each virtual anchor point into a unified optimization framework. The global anchoring potential function is defined as follows: Its physical meaning is the current chip position. The degree of deviation from the global anchoring target position. The local topological anchoring potential function is defined as follows: Its physical meaning is the sum of the squares of the distances from the current chip position to each virtual anchor point position, reflecting the degree to which the relative position constraints between the current chip and its adjacent chips are satisfied.

[0049] The system then constructs a total potential function, which sums the two constraints using weighted coefficients provided by the influence weight generation module: .because and All The weighted sum of a quadratic convex function is also a convex quadratic function, therefore it has a unique global minimum point. Taking the derivative of this convex quadratic function and setting the derivative to zero yields an analytical solution for the unconstrained optimal position. Let [the value of the derivative be...]. Given the number of adjacent mounted chips, the condition for the gradient of the total potential function to be zero is: After sorting, we get: ; Therefore, the unconstrained optimal position is in the form of a weighted arithmetic mean: ; The physical meaning of this expression is clear: when Much larger When the unconstrained optimal position approaches the globally anchored target position, the system prioritizes absolute accuracy; when Much larger When the unconstrained optimal position approaches the arithmetic mean of the virtual anchor point positions, the system prioritizes ensuring relative positional consistency with adjacent chips; when the weights of both are equal, the system seeks a balance between the two types of constraints; if Less than the preset minimum value (e.g.) ), then Set as the global anchor target location.

[0050] The above calculation results for the unconstrained optimal position are obtained under ideal conditions, but there are hardware limitations in the actual placement process—the geometric center of the chip must fall within the acceptable placement area of ​​the pads. Otherwise, solder splattering or electrical connection failure may occur. Therefore, the system projects the unconstrained optimal position onto the acceptable mounting area of ​​the pads to obtain the final target mounting position. The acceptable mounting area for the pads is pre-acquired by the mounting pre-positioning module. This acquisition method involves: the die bonder's vision system capturing real-time images of the substrate pads; extracting the actual contour of the pads using an edge detection algorithm; determining the permissible spatial boundary for chip geometric center movement based on this contour; and defining the area within this boundary as the acceptable mounting area. In practical applications, this area is typically rectangular, and its projection calculation degenerates into component-wise clamping: if... If the X-coordinate exceeds the region boundary, the nearest boundary value is taken; the Y-coordinate is handled similarly.

[0051] After completing the above calculations, the mounting position locking module will lock the target mounting position. The chip is sent to the placement execution module, which controls the placement execution mechanism to move the chip to the specified coordinates and complete the placement operation.

[0052] For ease of understanding, we will continue using the previous example of a miniature LED display module. Assume the chip to be mounted is the 7th chip, and its designed position coordinates are... Globally anchor the target position Adjacent set of mounted chips Their deviation vectors are respectively Therefore, the positions of the two virtual anchor points are calculated: The normalized weights are respectively , Substituting into the formula for calculating the unconstrained optimal position: .

[0053] First calculate the first term in the numerator: The second term in the numerator: the sum of all virtual anchor points is... multiplied by have to The sum of the numerators is The denominator is .therefore .

[0054] Assuming the acceptable mounting area for the pads is in the X direction. , Y direction The rectangle contains the unconstrained optimal position, whose X-coordinates (1001.2) and Y-coordinates (500.8) both fall within this region. Therefore, the projection result is the unconstrained optimal position itself, which is the target mounting position. The result is between the global anchored target position. and the average position of virtual anchor points The balance between these values ​​reflects the effectiveness of weight allocation.

[0055] After completing the calculation, the mounting position locking module outputs the target mounting position to the mounting execution module. This position takes into account both the absolute accuracy requirements caused by the overall deformation of the substrate (reflected by the global anchoring target position) and the local geometric constraints of adjacent chips (reflected by the virtual anchor point position), and performs projection constraints within the hardware-acceptable boundaries to ensure the physical realizability of the calculation results.

[0056] Placement execution module: controls the placement execution mechanism to perform placement operations according to the target placement position.

[0057] The core function of the placement execution module is to convert the target placement position output by the placement position locking module into executable mechanical motion commands, control the placement head of the die bonder to accurately move the chip to the specified coordinates and complete the placement operation, and simultaneously feed the actual placement coordinates back to the data update module to achieve closed-loop control. This embodiment provides the following specific configuration for this module.

[0058] The placement execution module first obtains the target placement position of the chip to be placed from the placement position locking module. The coordinates are based on the substrate coordinate system and are in micrometers. The module converts these coordinates into the coordinate system of the placement head motion control system. The conversion process is based on the rigid transformation matrix between the camera coordinate system and the motion coordinate system calibrated at the factory of the die bonder. This transformation matrix is ​​pre-determined and stored in the system configuration file during the equipment calibration stage.

[0059] After coordinate transformation, the placement execution module sends position commands to the X-axis and Y-axis servo drives of the placement head, driving the placement head to move from its current position to directly above the target placement position. During the movement, the module reads the actual position feedback from the encoder in real time and uses a proportional-integral-derivative closed-loop control algorithm for dynamic position correction, ensuring positioning accuracy at the sub-micron level. Specifically, the system reads the encoder feedback value at a frequency of 1 kHz and calculates the position deviation. And according to the formula Calculate the control output, where , , The preset proportional, integral, and derivative coefficients for the servo driver are adjusted during the equipment commissioning phase based on the mass inertia and response characteristics of the placement head.

[0060] Once the placement head reaches the target placement position and the positional deviation is stable within the preset positioning dead zone (typically ±1 micrometer), the placement execution module initiates the Z-axis movement of the placement head. The Z-axis movement consists of four phases: rapid descent, slow contact, pressure control, and holding. During the rapid descent phase, the Z-axis descends at a preset high speed (e.g., 20 mm / s) to a preset safe height (e.g., 100 micrometers) from the substrate surface. It then enters the slow contact phase, continuing to descend at a lower speed (e.g., 2 mm / s) until the force sensor detects that the contact force has reached a preset contact threshold (e.g., 0.1 Newtons). At this point, the system switches to pressure control mode, using a proportional-integral control algorithm to adjust the torque output of the Z-axis motor according to a preset placement pressure target value (e.g., 2.0 Newtons) to maintain a constant placement pressure. The pressure holding time is preset according to the solder type and process requirements, typically 0.2 to 0.5 seconds, to ensure sufficient solder wetting.

[0061] During pressure maintenance, the placement execution module continuously monitors the feedback value of the force sensor. If the deviation between the actual pressure and the target pressure exceeds the preset tolerance range (e.g., ±0.2 Newtons), the system automatically adjusts the motor torque for compensation. If the deviation continues to exceed the tolerance range for more than a preset time (e.g., 0.1 seconds), it is determined to be a placement anomaly, triggering the retry mechanism. The retry mechanism includes lifting the chip, cleaning the placement head, realigning, and attempting placement again. The maximum number of retries is preset to 3. If the placement still fails after 3 retries, the system stops the placement of the current chip, marks the chip as abnormal, and continues to place the next chip. The final report outputs a list of abnormal chips.

[0062] After placement is complete, the placement execution module controls the Z-axis to rise at a preset speed, separating the placement head from the chip. Subsequently, the die bonder's vision system takes in-situ photographs of the placed chip and measures its actual placement position coordinates. The measurement uses an image recognition algorithm to extract the chip's geometric center and compares it with a reference mark on the substrate to obtain the actual coordinate value. Measurement accuracy is limited by the vision system hardware and is typically ±2 micrometers. The placement execution module sends the measured actual position coordinates to the data update module via a communication interface as feedback on the chip's placement result.

[0063] During the placement process, the placement execution module simultaneously records multiple process parameters, including the time from the issuance of the position command to position stabilization, the actual pressure curve during the pressure control phase, and the final placement position deviation. These parameters are stored in the process log database for subsequent process analysis and quality traceability.

[0064] For ease of understanding, we will continue using the previous example of the miniature LED display module. Assume the target mounting position output by the mounting position locking module is... The placement execution module transforms the coordinates and controls the placement head to move. Once it reaches the desired position and stabilizes, the Z-axis descends and a placement pressure of 2.0 Newtons is applied, held for 0.3 seconds. After placement, the vision system takes an image to measure the actual position coordinates. The coordinates are transmitted to the data update module for calculating the deviation vector. This completes the full data loop for the current placement process. The placement execution module then prepares to receive the target location of the next chip to be placed and continues the placement task.

[0065] Data Update Module: This module receives input data from the placement execution module and the placement position locking module. Specifically, after each chip is placed, the placement execution module measures the actual placement position coordinates of the chip using the die bonder's vision system and feeds these coordinates back to the data update module. Simultaneously, the data update module obtains the chip's designed position coordinates from the placement position locking module and retrieves the stored set of placed chips and related deviation vectors from the placement pre-positioning module.

[0066] The data update module first calculates the deviation vector of the newly mounted chip. The system then obtains the actual position coordinates fed back by the mounting execution module. And read the design position coordinates of the chip from the mounting position locking module. Calculate the difference between the two. This deviation vector records the absolute positioning error of the chip during the mounting process. Its value can be positive or negative, representing the positive or negative offset of the actual position relative to the designed position, respectively. After calculation, the system stores the chip's identifier and the corresponding deviation vector in the set of mounted chips. Sum of deviation vector arrays This allows the chip to serve as a reference for subsequent mounting decisions.

[0067] After storing the deviation vector, the data update module triggers the incremental update process of the topological stress field. The system first acquires the newly mounted chip. Adjacent mounted chip sets That is, from its set of adjacent nodes The process filters out a subset of chips that have already been mounted. If this subset is empty, it means that the current chip has not yet formed a topological constraint with any mounted chips, so its original topological stress value is set to zero, and there is no need to update the stress values ​​of other chips. If this subset is not empty, then for... Each adjacent chip in The system will perform the following update operations.

[0068] The system calculates the new relative deviation gradient between the newly mounted chip and the adjacent chip. The physical meaning of this gradient lies in its quantification of the relative deviation between the newly mounted chip and its adjacent chips after mounting. Based on this gradient, the system calculates the contribution value of the added stress. This is the square of the gradient magnitude. The newly added stress contribution value reflects the degree to which the newly formed adjacent edges contribute to the topological stress field.

[0069] Subsequently, the system updates the original topological stress value of the newly mounted chip. Since the chip had no adjacency constraints before mounting, its original topological stress value is directly equal to the sum of all newly added stress contributions, i.e. At the same time, for each adjacent chip The system uses its original topological stress value With the newly added stress contribution value Adding them together yields the updated original topological stress values. The physical basis of this accumulation operation is that when a new chip forms a new adjacent edge with a neighboring chip, the relative deviation gradient corresponding to that edge becomes part of the topological stress of the neighboring chip, and therefore its contribution needs to be accumulated into the original stress value of the chip.

[0070] After updating the original topological stress values, the system performs neighborhood averaging filtering on the affected chips to suppress measurement noise and enhance the spatial continuity of the stress field. Affected chips include newly mounted chips. and all its adjacent chips For newly mounted chips The system obtains its adjacent set of mounted chips. The updated original topological stress values ​​of each chip are calculated. The filtered topological stress value is obtained by taking the arithmetic mean of these stress values. For each adjacent chip The system obtains its own set of adjacent mounted chips. (This collection contains newly mounted chips) (along with other existing adjacent chips), the updated original topological stress values ​​of each chip in this set are compared with... The updated filtered topological stress value is obtained by performing an arithmetic mean. For other chips not affected by this mounting, their filtered topological stress values ​​remain unchanged.

[0071] For ease of understanding, let's continue with the previous example of the miniature LED display module. Assume the newly mounted chip is the 7th one, and its actual position coordinates, as measured, are... Design location coordinates The deviation vector is calculated. The adjacent set of mounted chips of this chip. Their deviation vectors are respectively and The system first calculates the gradient of the newly added relative deviation: , Calculate the contribution value of the newly added stress: , Therefore, the original topological stress value of the newly mounted chip. For the third chip, assume its original topological stress value is... After the update For the 6th chip, assume its original topological stress value is... After the update .

[0072] Then filtering is performed. Assume the adjacent mounted chip set of the 3rd chip includes the 1st and 7th chips, and their original stress values ​​are respectively... , Then after filtering The set of adjacent mounted chips for the 6th chip includes the 2nd and 7th chips, assuming... Then after filtering The set of adjacent mounted chips for the 7th chip is... The updated original stress values ​​are respectively Then after filtering At this point, the filtered topology stress values ​​of chips 3, 6, and 7 have been updated, while the stress values ​​of the remaining chips remain unchanged.

[0073] It is worth noting that the data update module uses an incremental update mechanism instead of a full recalculation. After each placement, the system only updates the topological stress values ​​of the newly placed chip and its adjacent chips, while the stress values ​​of other chips remain unchanged. This design makes the computational complexity after a single placement linearly related to the number of adjacent chips, but independent of the total number of chips already placed, thus maintaining real-time responsiveness in large-scale array placement of hundreds of chips. After completing the above update, the data update module outputs the updated set of placed chips, the deviation vector array, and the topological stress field to the placement prepositioning module and the influence weight generation module for use in the placement decision of the next chip, thereby forming a complete data closed loop; the system uses double-precision floating-point storage to ensure sufficient accuracy.

[0074] Full-array stress monitoring module: After all chips are mounted, a global statistical analysis is performed on the final topological stress field to identify stress concentration areas and output quality evaluation information, providing a quantitative basis for process optimization and reliability screening. This embodiment specifies the following configuration for this module.

[0075] The trigger condition for this module is the set of mounted chips. Includes all Once each chip is assembled, the mounting process is complete. At this point, the data update module has completed the final update of the filtered topological stress value for each chip, and the system obtains the filtered topological stress value for each chip from the data update module. ,in .

[0076] The full array stress monitoring module first performs statistical analysis on the filtered topological stress values ​​of the entire array. The system calculates the arithmetic mean of the filtered topological stress values ​​for all chips. This metric reflects the average degree of distortion of the entire array. The system then calculates the standard deviation. This indicator reflects the high degree of dispersion of stress distribution; a larger standard deviation indicates a more significant difference in the degree of distortion among different regions of the array. Simultaneously, the system iterates through all chips, recording the maximum value of the filtered topological stress. And record the chip identifier corresponding to the maximum value. .

[0077] After completing the statistical calculations, the system will set the maximum value. With preset alarm threshold Compare. Preset alarm thresholds. The value is determined based on process verification experiments. The specific calibration method is as follows: During the equipment debugging phase, multiple standard arrays mounted under different process parameters are selected, and the filtered topological stress value of each chip is measured. Through reliability tests (such as temperature cycling tests and high temperature and humidity aging tests), the stress distribution of early failure chips is statistically analyzed. The filtered topological stress values ​​of the early failure chips are sorted from smallest to largest, and the 25th percentile is taken as the preset alarm threshold. Once calibrated, this threshold is permanently stored in the system configuration file and remains unchanged in subsequent production.

[0078] like Exceeding the preset alarm threshold The system will select the chip corresponding to the maximum value. The core point of the high-stress region is marked. To further identify the extent of the high-stress region, the system executes a region growing algorithm centered on this chip. Specifically, the system initializes an empty set. , chip Add it to the system. Then, the system iterates through the data. For each chip in the process, the adjacent chips, if the filtered topological stress value of a certain adjacent chip... Exceeding the preset alarm threshold If a certain percentage (default value is 0.7, but process engineers are allowed to adjust it within the range of 0.5 to 0.9) is used, then the adjacent chip will also be added. Repeat this process until no new chips are added, and finally... This refers to the set of chips contained in the high-stress area. The system outputs an alarm message containing the identifiers of all chips in this area and highlights the positions of these chips in the array layout diagram in a highlighted color on the device operation interface; the algorithm uses the visited set to avoid duplicate additions and ensures termination.

[0079] like If the preset alarm threshold is not exceeded, the system determines that the current mounting quality is acceptable and outputs a stress distribution statistical report. This report is presented in tabular or chart format, including the filtered topology stress value for each chip, the mean stress value and standard deviation of the entire array, and a stress distribution histogram. The system overlays the stress distribution map with the design topology map, using a color-coding method to represent stress magnitude: low stress areas are represented in green, medium stress areas in yellow, and high stress areas in red. This visual output helps process engineers intuitively identify stress distribution trends within the array.

[0080] For ease of understanding, we will continue using the aforementioned example of a miniature LED display module. Assume the module contains 16 chips. After the entire mounting process, the system obtains the filtered topological stress values ​​for each chip as follows: Chips 1 to 4 are... Chips 5 to 8 are respectively Chips 9 to 12 are respectively Chips 13 to 16 are respectively The system calculates the arithmetic mean. Standard deviation maximum value This corresponds to chip 7. Assume a preset alarm threshold. ,but This triggers an alarm. The system performs region growth centered on chip 7, with adjacent chips including chips 3, 6, 8, and 11. The stress value of chip 3 is... ,Exceed High-stress areas are added; the stress value of chip 6 is... If the stress value is less than the specified value, do not add it; the stress value of chip 8 is... If the stress value is less than the specified value, do not add it; the stress value of chip 11 is... Exceeding this limit, a high-stress area is added. Continue expanding centered on chips 3 and 11. Chip 7, an adjacent chip of chip 3, is already in the set. The stress value of chip 2... The stress value of the chip was not exceeded. Not exceeded; chip 7 is already in the set of adjacent chips of chip 11, and the stress value of chip 10 is not exceeded. The stress value of the chip did not exceed 12. The stress value of the chip did not exceed 15. Not exceeded. The final high-stress area includes chips 7, 3, and 11. The system outputs an alarm message, identifying chips 3, 7, and 11 as high-stress areas, and highlights the positions of these three chips in red in the array layout diagram.

[0081] After an alarm is issued, process engineers can trace the process causes that may lead to stress concentration in the high-stress area based on its location. These causes could include localized warpage of the substrate in that area, differences in solder distribution, or adverse stress accumulation due to the mounting sequence. The monitoring results are simultaneously stored in the process database as a basis for batch quality traceability and for subsequent optimization and adjustment of process parameters.

[0082] Based on the above-described substrate deformation mode deconstruction, this embodiment further includes deformation mode timing analysis and adaptive parameter adjustment functions. This function runs continuously throughout the mounting process, and its specific configuration is as follows.

[0083] After each mounting process, the system records the substrate deformation mode discrimination result calculated for the currently mounted area. Specifically, the system maintains a timing window of fixed length, with the window length preset to [value missing]. (Window length) The frequency threshold can be adaptively set according to the array size, for example, taking 10% of the total number of chips in the array, but not less than 5. This was obtained by collecting switching frequency data from at least 20 batches of normal production data and calculating its 95th percentile. The most recent data was recorded. Deformation mode label sequence after the second application is completed ,in Indicates the first The deformation mode label after each chip is mounted has a value of either "overall rigid body deformation" or "local torsional deformation". This is useful when the number of mounted chips is insufficient. At that time, the switching frequency is calculated using all existing tags.

[0084] After each chip is mounted, the system calculates the switching frequency between different modal tags in the timing sequence. Specifically, the system iterates through adjacent tags in the sequence and counts the number of times the tag changes. That is, satisfying The number of positions. The switching frequency is defined as... This frequency reflects the stability of the deformation mode during the mounting process—a higher frequency indicates more frequent mode switching, suggesting a more unstable process state.

[0085] The system will compare the calculated switching frequency with the preset frequency threshold. Compare. Frequency threshold. The value was determined through process verification experiments, using the upper quartile of the statistical distribution of switching frequencies under normal and stable production conditions as the threshold. When the switching frequency exceeds... When this happens, the system generates a process stability degradation warning signal, which is displayed on the equipment interface and stored in the process log database.

[0086] In response to the warning signal, the system triggers an adaptive adjustment of the generation parameters for the deviation impact weight and topology impact weight. Specifically, the system adjusts the preset maximum deviation impact weight coefficient in the impact weight generation module. Preset maximum topology influence weight coefficient and preset reference stress threshold Incremental adjustments will be made. The adjustment rules are as follows: When a warning signal is triggered, the system will... Decrease by one step (For example ),Will Increase step size (For example ), and at the same time Decrease by one step (For example ); after each adjustment, if in subsequent If no further warning is triggered within a given chip, the parameters remain unchanged to avoid repeated adjustments. As a preset stable observation window, it can be selected =5. The adjustment range of each parameter is limited by the preset upper and lower limits, for example... The range of values ​​is , The range of values ​​is The range of values ​​is When the adjusted parameters reach the boundary, stop adjusting in that direction. The adjusted parameters take effect immediately and are used for weight calculations in subsequent chips.

[0087] This adaptive adjustment mechanism enables the system to automatically increase the weight of local topology constraints when it detects process instability (by increasing...). and decrease And reduce the weight of the global anchoring constraint (by reducing) This allows the system to place greater emphasis on the relative positional consistency between adjacent chips, thus suppressing the further spread of local distortion. Once the process condition stabilizes and the switching frequency falls below the threshold, the system will no longer trigger new adjustments, and the parameters will remain at their current values. If the process engineer manually resets the parameters via the interface, the parameters can be restored to their initial calibration values.

[0088] This embodiment constructs a dual-field collaborative mechanism of deviation influence weight and topology influence weight, transforming the binary opposition of "global benchmark" and "local benchmark" in existing technologies into a weighted and fused continuous decision, fundamentally eliminating geometric conflicts at the benchmark switching boundary. Based on this, by introducing topological stress as a quantitative index of the deviation field spatial gradient, the system can perceive the distortion distribution inside the chip array in real time and dynamically adjust the weight ratio of the two constraints with stress minimization as the guide, thereby achieving a high degree of consistency in the relative positions of adjacent chips while ensuring absolute positioning accuracy. Furthermore, through full-array stress monitoring and deformation mode deconstruction, the mounting result is elevated from a binary judgment of single-chip qualification to a quantifiable evaluation of stress field distribution, providing a clear attribution basis for process optimization. Thus, this embodiment effectively solves the coupling contradiction between absolute and relative accuracy in multi-chip integrated packaging, eliminates local stress abrupt changes caused by benchmark switching, and significantly improves the geometric consistency and solder joint reliability of array mounting.

[0089] The above description is merely an example and illustration of the structure of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the structure of the invention or exceed the scope defined in the claims, all of which should fall within the protection scope of the present invention.

[0090] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0091] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A high-reliability CSP light source packaging and positioning system, characterized in that, include: Mounting prepositioning module: obtains the design position coordinates of the chip to be mounted, the global anchoring target position of the chip to be mounted, and the deviation vector between the actual position coordinates and the design position coordinates of each mounted chip in the set of mounted chips; Spatial difference analysis module: Based on the deviation vector of each mounted chip in the mounted chip set and the preset chip topology connection relationship, calculate the topological stress value of each mounted chip. The topological stress value is used to characterize the degree of spatial difference of the deviation vector between the mounted chip and its adjacent mounted chips. Influence weight generation module: Generates deviation influence weight and topology influence weight based on the dispersion of the deviation vector of the assembled chip set and the topological stress value of the adjacent assembled chips of the chip to be mounted. Mounting position locking module: Based on the deviation influence weight, the topology influence weight, the global anchoring target position of the chip to be mounted, and the deviation vector of the adjacent mounted chips of the chip to be mounted, the module performs weighted fusion processing on the global anchoring target position and the local anchoring reference position of the chip to be mounted to obtain the target mounting position of the chip to be mounted. The local anchoring reference position is determined based on the design position coordinates of the chip to be mounted and the deviation vector of its adjacent mounted chips. Placement execution module: controls the placement execution mechanism to perform placement operations according to the target placement position.

2. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The pre-defined inter-chip topology is constructed through the following process: Analyze the chip array design file to extract the design location coordinates of each chip and the adjacency relationship definition between chips; An undirected graph is constructed using each chip as a node and the adjacency relationship as an edge. Based on the undirected graph, an adjacency node set is established for each chip.

3. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The process of calculating the topological stress value of each mounted chip specifically includes: For each mounted chip, obtain the set of its adjacent mounted chips; Calculate the difference between the deviation vector of the mounted chip and the deviation vector of each adjacent chip in the set of adjacent mounted chips to obtain the relative deviation gradient; Calculate the sum of squares of the moduli of each relative deviation gradient to obtain the original topological stress value of the mounted chip; The original topological stress value of the mounted chip is arithmetically averaged with the original topological stress values ​​of its adjacent chips to obtain the filtered topological stress value of the mounted chip.

4. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The process of generating deviation influence weights based on the dispersion of the deviation vector of the mounted chip set specifically includes: A deviation influence weight is generated by combining the arithmetic mean of the deviation vectors of each mounted chip in the mounted chip set, the standard deviation of each deviation vector relative to the arithmetic mean, and the arithmetic mean of the magnitude of each deviation vector, wherein the deviation influence weight is negatively correlated with the ratio of the standard deviation and the arithmetic mean of the magnitude.

5. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The process of generating topological influence weights based on the topological stress values ​​of adjacent mounted chips of the chip to be mounted specifically includes: The filtered topological stress values ​​of each adjacent chip in the adjacent set of adjacent mounted chips of the chip to be mounted are obtained, and the arithmetic mean of the filtered topological stress values ​​is calculated to obtain the neighborhood average stress value. A topology influence weight is generated by combining the ratio of the neighborhood average stress value to a preset reference stress threshold and a preset maximum topology influence weight coefficient, wherein the topology influence weight is positively correlated with the ratio and does not exceed the preset maximum topology influence weight coefficient.

6. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The target placement location for the chip to be mounted is determined through the following process: For each adjacent chip in the set of adjacent mounted chips of the chip to be mounted, the design position coordinates of the chip to be mounted are added to the deviation vector of the adjacent chip to obtain the virtual anchor point position corresponding to the adjacent chip. The deviation influence weight is used as the weighting coefficient of the global anchoring target position, and the topology influence weight is used as the weighting coefficient of each virtual anchor position. The global anchoring target position and each virtual anchor position are weighted and arithmetically averaged to obtain the unconstrained optimal position of the chip to be mounted. The unconstrained optimal position is projected onto the acceptable mounting area of ​​the pad corresponding to the chip to be mounted to obtain the target mounting position.

7. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, It also includes a data update module: Obtain the actual position coordinates of the chip to be mounted after mounting, and calculate the deviation vector of the chip to be mounted based on the difference between the actual position coordinates and the designed position coordinates of the chip to be mounted; Add the chip to be mounted to the set of mounted chips; Based on the deviation vector of the chip to be mounted and the deviation vector of each adjacent mounted chip, the topological stress value of the chip to be mounted and each adjacent mounted chip is incrementally updated.

8. The high-reliability CSP light source packaging and positioning system according to claim 7, characterized in that, The process of incrementally updating the topological stress values ​​of the chip to be mounted and its adjacent mounted chips specifically includes: For each adjacent chip in the set of adjacent mounted chips of the chip to be mounted, the difference between the deviation vector of the chip to be mounted and the deviation vector of the adjacent chip is calculated to obtain the new relative deviation gradient, and the square of the magnitude of the new relative deviation gradient is calculated to obtain the new stress contribution value. The newly added stress contribution value is used as the original topological stress value of the chip to be mounted; For each adjacent chip, the original topological stress value before the update is added to the newly added stress contribution value to obtain the original topological stress value of the adjacent chip after the update. The updated original topological stress values ​​of the chip to be mounted and its adjacent chips are arithmetically averaged with the original topological stress values ​​of their respective adjacent mounted chips to obtain the updated filtered topological stress values ​​of the chip to be mounted and its adjacent chips.

9. The high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, The global anchor target position is obtained through the following process: Obtain the design coordinates and measured coordinates of the preset global Mark points on the substrate; Based on the design coordinates and the measured coordinates, the rigid body transformation parameters of the substrate are calculated using the least squares method. The rigid body transformation parameters include translation parameters, rotation parameters, and scaling parameters. The design position coordinates of the chip to be mounted are transformed according to the scaling parameters, the rotation parameters, and the translation parameters to obtain the global anchoring target position.

10. A high-reliability CSP light source packaging and positioning system according to claim 1, characterized in that, It also includes a full-array stress monitoring module: After all chips are mounted, obtain the filtered topological stress value of each chip; Calculate the arithmetic mean, standard deviation, and maximum value of the topological stress values ​​after filtering for each chip; The maximum value is compared with a preset alarm threshold. When the maximum value exceeds the preset alarm threshold, the corresponding chip is marked as a high-stress area and an alarm message is output.

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