Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a substrate, a switching transistor, a driving transistor and a first capacitor. The switching transistor comprises a first gate, a first semiconductor and a second gate. The driving transistor comprises a shielding portion, a driving semiconductor and a driving gate. The first capacitor is disposed on the substrate. The first capacitor comprises a first sub-plate and a second sub-plate. The second sub-plate is located on a side of the first sub-plate away from the substrate. The first sub-plate and the second sub-plate at least partially overlap in a direction perpendicular to a plane in which the substrate is located. The second sub-plate is electrically connected to the driving gate. The first sub-plate is electrically connected to the shielding portion. One of the first sub-plate and the second sub-plate is disposed in the same layer as the first gate. The present application can simplify the manufacturing process of the display panel and improve the manufacturing efficiency of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to a display panel and display device. Background Technology

[0002] In Organic Light Emitting Diode (OLED) display products, the display panel includes a driving backplane and light-emitting devices. The driving backplane contains multiple transistors. To achieve faster charging speeds and better circuit compensation, some transistors have larger on-state currents, while others require more precise threshold voltages for better compensation. Achieving both simultaneously necessitates multiple conductive layers to house the gate, increasing the complexity of the manufacturing process and impacting the efficiency of display panel fabrication. Summary of the Invention

[0003] This application provides a display panel and a display device, which are intended to simplify the manufacturing process of the display panel.

[0004] An embodiment of the first aspect of this application provides a display panel, which includes a substrate, a switching transistor, a driving transistor, and a first capacitor. The switching transistor is disposed on the substrate and includes a first gate, a first semiconductor, and a second gate. The first semiconductor is located on the side of the first gate facing away from the substrate, and the second gate is located on the side of the first semiconductor facing away from the substrate. The driving transistor is disposed on the substrate and includes a shielding portion, a driving semiconductor, and a driving gate. The driving semiconductor is located on the side of the shielding portion facing away from the substrate and is electrically connected to the shielding portion. The driving gate is located on the side of the driving semiconductor facing away from the substrate. The first capacitor is disposed on the substrate and includes a first sub-plate and a second sub-plate. The second sub-plate is located on the side of the first sub-plate away from the substrate, and along a direction perpendicular to the plane of the substrate, the first sub-plate and the second sub-plate at least partially overlap. The first sub-plate is electrically connected to the driving gate, and the second sub-plate is electrically connected to the shielding portion. One of the first sub-plate and the second sub-plate is disposed on the same layer as the first gate.

[0005] The second aspect of this application also provides a display device, including the display panel of any of the first aspect embodiments described above.

[0006] In the display panel provided in this application embodiment, the display panel includes a substrate, a switching transistor, a driving transistor, and a first capacitor. The switching transistor includes two gates, a first gate and a second gate, enabling the switching transistor to have a larger on-state current, achieving faster charging speed and better circuit compensation effect. The driving transistor includes a shield, a driving semiconductor, and a driving gate. The shield and the driving semiconductor are electrically connected, enabling the driving transistor to have a more positive threshold voltage and achieve better compensation effect. The first capacitor includes a first sub-plate and a second sub-plate. The first sub-plate is electrically connected to the shield, and the second sub-plate is electrically connected to the driving gate, enabling the first capacitor to maintain the gate voltage of the driving transistor during the data writing stage and maintain a stable gate-source voltage during the light-emitting stage. In this application embodiment, one of the first sub-plate and the second sub-plate is disposed in the same layer as the first gate, allowing one of the first sub-plates and the first gate to be fabricated in the same process step, simplifying the display panel fabrication process and improving the fabrication efficiency of the display panel. Attached Figure Description

[0007] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0008] Figure 1 This is a schematic diagram of the structure of a display panel provided in this application; Figure 2 This is one of the partial cross-sectional views of a display panel provided in this application; Figure 3 This is one of the partial top views of the pixel circuit of a display panel provided in this application; Figure 4 This is a second partial cross-sectional view of a display panel provided in this application; Figure 5 This is a second partial top view of the pixel circuit of a display panel provided in this application; Figure 6 This is a third partial top view of the pixel circuit of a display panel provided in this application; Figure 7 This is a third partial cross-sectional view of a display panel provided in this application; Figure 8 This is an equivalent circuit diagram of the pixel circuit of a display panel provided in this application; Figure 9 This is a graph of Embodiment 1 from a simulation experiment of a display panel provided in this application; Figure 10 This is a graph of Embodiment 2 from a simulation experiment of a display panel provided in this application; Figure 11 This is a graph of embodiment 3 in a simulation experiment of a display panel provided in this application; Figure 12 This is a graph of embodiment 4 in a simulation experiment of a display panel provided in this application; Figure 13 This is a combined curve diagram of an embodiment of a display panel provided in this application during a simulation experiment; Figure 14 This is a schematic diagram of the structure of a display device provided in this application; Figure 15 This is a schematic flowchart of a method for manufacturing a display panel provided in this application; Figure 16 This is a flowchart illustrating one step of a method for manufacturing a display panel provided in this application; Figure 17 and Figure 18 yes Figure 16 A schematic diagram of the preparation process of the preparation method shown; Figure 19 This is a flowchart illustrating one step of a method for manufacturing a display panel according to another embodiment of this application; Figure 20 and Figure 21 yes Figure 19 A schematic diagram of the preparation process of the preparation method shown; Figures 22 to 26 yes Figure 15 The diagram shows the structural structure of the preparation process of the preparation method shown. Detailed Implementation

[0009] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0010] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0011] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0012] To better understand this application, the following will be combined with... Figures 1 to 14 The display panel and display device according to embodiments of this application will be described in detail.

[0013] Figure 1 This is a schematic diagram of the structure of a display panel 10 provided in this application. Figure 2 yes Figure 1 A cross-sectional view in one embodiment.

[0014] like Figure 1 and Figure 2As shown, an embodiment of the first aspect of this application provides a display panel, which includes a substrate 100, a switching transistor 200, a driving transistor 300, and a first capacitor 400. The switching transistor 200 is disposed on the substrate 100 and includes a first gate 210, a first semiconductor 220, and a second gate 230. The first semiconductor 220 is located on the side of the first gate 210 facing away from the substrate 100, and the second gate 230 is located on the side of the first semiconductor 220 facing away from the substrate 100. The driving transistor 300 is disposed on the substrate 100 and includes a shielding portion 310, a driving semiconductor 320, and a driving gate 330. The driving semiconductor 320 is located on the side of the shielding portion 310 facing away from the substrate 100 and is electrically connected to the shielding portion 310. The driving gate 330 is located on the side of the driving semiconductor 320 facing away from the substrate 100. A first capacitor 400 is disposed on a substrate 100. The first capacitor 400 includes a first sub-electrode 410 and a second sub-electrode 420. The second sub-electrode 420 is located on the side of the first sub-electrode 410 away from the substrate 100, and the first sub-electrode 410 and the second sub-electrode 420 overlap at least partially along a direction perpendicular to the plane of the substrate 100. The first sub-electrode 410 is electrically connected to the driving gate 330, and the second sub-electrode 420 is electrically connected to the shielding portion 310. One of the first sub-electrode 410 and the second sub-electrode 420 is disposed on the same layer as the first gate 210.

[0015] In the display panel provided in this embodiment, the display panel includes a substrate 100, a switching transistor 200, a driving transistor 300, and a first capacitor 400. The switching transistor 200 includes two gates, a first gate 210 and a second gate 230, enabling the switching transistor 200 to have a larger on-state current, achieving faster charging speed and better circuit compensation. The driving transistor 300 includes a shield 310, a driving semiconductor 320, and a driving gate 330. The shield 310 and the driving semiconductor 320 are electrically connected, enabling the driving transistor 300 to have a more positive threshold voltage for better compensation. The first capacitor 400 includes a first sub-plate 410 and a second sub-plate 420. The first sub-plate 410 is electrically connected to the shield 310, and the second sub-plate 420 is electrically connected to the driving gate 330. This allows the first capacitor 400 to maintain the gate voltage of the driving transistor 300 during the data writing phase and to maintain a stable gate-source voltage during the light-emitting phase. In this embodiment, one of the first sub-electrode plate 410 and the second sub-electrode plate 420 is disposed in the same layer as the first gate 210, so that one of the first sub-electrode plate 410 and the second sub-electrode plate 420 can be fabricated in the same process step as the first gate 210, which can simplify the fabrication process of the display panel and improve the fabrication efficiency of the display panel.

[0016] Optionally, the shielding portion 310 and the second sub-electrode plate 420 are disposed in the same layer, which facilitates the electrical connection between the shielding portion 310 and the second sub-electrode plate 420. When the shielding portion 310 and the second sub-electrode plate 420 are disposed in the same layer, a conductive layer of the first sub-electrode plate 410 is disposed between the shielding portion 310 and the substrate 100, which simplifies the film layer structure of the display panel.

[0017] The substrate 100 can be a flexible substrate 100 or a rigid substrate 100. For example, the material of the substrate 100 may include flexible materials such as polyimide, or the substrate 100 may include rigid materials such as glass.

[0018] Optional, such as Figure 1 and Figure 3 As shown, the display panel includes multiple sub-pixels 120 and a pixel circuit 500. The pixel circuit 500 can drive the sub-pixels 120 to emit light. The pixel circuit 500 includes the aforementioned switching transistor 200, driving transistor 300, and first capacitor 400. The pixel circuit 500 may also include other transistors or capacitors. The multiple sub-pixels 120 can be arranged in an array.

[0019] In the pixel circuit 500, the driving transistor 300 is responsible for the "current control and maintenance" of light emission, that is, it continuously outputs a constant current to the light-emitting element according to the gate voltage held by the storage capacitor, which directly determines the brightness and grayscale level of the pixel; while the switching transistor 200 is responsible for the "writing and gating" of the voltage signal, that is, it is turned on only when the scan signal is at the enable level to realize the signal transmission, and is turned off when the scan signal is at the de-enable level to cut off the signal transmission path.

[0020] Optionally, the display panel further includes multiple conductive layers disposed on the substrate 100, with an insulating layer disposed between adjacent conductive layers. The first gate 210, the second gate 230, the shielding portion 310, the driving gate 330, the first sub-electrode 410, and the second sub-electrode 420 may be disposed within the multiple conductive layers. The multiple conductive layers may include a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 sequentially stacked along a direction away from the substrate 100, with the first sub-electrode 410 located in the first conductive layer M1 and the second sub-electrode 420 located in the second conductive layer M2. The display panel also includes an active layer, with the first semiconductor 220 and / or the driving semiconductor 320 located in the active layer. Optionally, the active layer is located between the second conductive layer M2 and the third conductive layer M3, with an insulating layer between the second conductive layer M2 and the active layer, and between the active layer and the third conductive layer M3, and the second gate 230 and / or the driving gate 330 located in the third conductive layer M3.

[0021] Please continue reading. Figure 1 and Figure 3Optionally, the display panel also includes multiple signal lines electrically connected to the pixel circuit 500. These signal lines may include, for example, a data signal line (Data), a scan signal line (Scan), a drive power signal line (Vdd), and a reference power signal line (Vref). Optionally, the data signal line (Data), the scan signal line (Scan), and the switching transistor 200 are electrically connected. For example, the switching transistor 200 includes a source and a drain; the data signal line (Data) is electrically connected to the source or drain of the switching transistor 200, and the scan signal line (Scan) is electrically connected to the first gate 210 or the second gate 230 of the switching transistor 200. The data signal can be written to the pixel circuit 500 through the switching transistor 200. Optionally, the drive transistor 300 includes a source and a drain; the drive power signal line (Vdd) is electrically connected to the source or drain of the drive transistor 300, causing the drive signal to drive the sub-pixel 120 to emit light through the drive transistor 300. Optionally, the scan signal line (Scan) extends along a first direction X, and the data signal line (Data) extends along a second direction Y.

[0022] There are various ways to electrically connect the driving semiconductor 320 and the shielding portion 310, as long as electrical signal transmission can be achieved between them. For example, the driving semiconductor 320 and the shielding portion 310 can be directly connected via a via. Alternatively, a conductive portion can be provided on another conductive layer, with one end of the conductive portion connected to the shielding portion 310 via a via, and the other end of the conductive portion connected to the driving semiconductor 320 via a via, allowing the driving semiconductor 320 and the shielding portion 310 to be electrically connected via a conductive portion. Similarly, there are various ways to electrically connect the first sub-electrode plate 410 and the driving gate 330, as long as electrical signal transmission can be achieved between them. For example, the first sub-electrode plate 410 can be directly connected to the driving gate 330 via a via, or the first sub-electrode plate 410 can be electrically connected to the driving gate 330 via a conductive portion located on another conductive layer. There are several ways to electrically connect the second sub-electrode plate 420 to the shielding part 310, as long as electrical signal transmission can be achieved between the second sub-electrode plate 420 and the shielding part 310. For example, the second sub-electrode plate 420 can be on the same layer as the shielding part 310 and directly connected to each other, or the second sub-electrode plate 420 can be electrically connected to the shielding part 310 after being transferred through a conductive part located on another conductive layer.

[0023] The display panel may include one or more active layers, with the first semiconductor 220 and the driving semiconductor 320 located on the same or different active layers. In some alternative embodiments, such as Figure 1 and Figure 2 As shown, both the driving semiconductor 320 and the first semiconductor 220 comprise metal oxide and are disposed in the same layer.

[0024] In these optional embodiments, the driving semiconductor 320 and the first semiconductor 220 are disposed on the same layer, allowing the driving semiconductor 320 and the first semiconductor 220 to be fabricated in the same process step, which further simplifies the fabrication process of the display panel. Furthermore, both the driving semiconductor 320 and the first semiconductor 220 are made of metal oxide, meaning that both the switching transistor 200 and the driving transistor 300 are metal oxide transistors, resulting in good uniformity between the switching transistor 200 and the driving transistor 300.

[0025] For example, referring to the above, the display panel includes an active layer located between the second conductive layer M2 and the third conductive layer M3, and the driving semiconductor 320 and the first semiconductor 220 are located in this active layer. Optionally, the first semiconductor 220 and the driving semiconductor 320 may be spaced apart from each other or integrally disposed according to electrical connection requirements. Optionally, the materials of the first semiconductor 220 and the driving semiconductor 320 may include at least one of indium gallium zinc oxide, indium gallium zinc tin oxide, indium gallium oxide, indium zinc oxide, and indium zinc oxide.

[0026] Optionally, when the pixel circuit 500 includes other transistors, the semiconductors of these other transistors can also include metal oxide and be disposed on the same layer as the first semiconductor 220 and the driving semiconductor 320. This can minimize the number of active layers in the display panel and allow multiple transistors to be fabricated simultaneously in a single process. This not only further simplifies the display panel fabrication process but also ensures that the thickness, interface state density, and defect concentration of the semiconductors of the multiple transistors are highly consistent. The mismatch of key parameters such as threshold voltage Vth, mobility, and subthreshold swing of each transistor is minimal, further improving the uniformity of the multiple transistors in the pixel circuit 500. Furthermore, the semiconductors of the other transistors can also include metal oxide, which can achieve extremely low off-state current, thereby enabling ultra-low refresh rates and significantly reducing dynamic power consumption.

[0027] In some alternative embodiments, such as Figures 1 to 4 As shown, the first semiconductor 220 includes a first channel region 221 and a first source region 222 and a first drain region 223 located on both sides of the first channel region 221 in the first direction X.

[0028] In some optional embodiments, after the second gate 230 is fabricated, the first semiconductor 220 can be ion implanted using the second gate 230 as a mask to form a first channel region 221, a first source region 222, and a first drain region 223. The first channel region 221 is the portion of the first semiconductor 220 that is blocked by the second gate 230; that is, the first channel region 221 is the area where the first semiconductor 220 and the second gate 230 overlap in a direction perpendicular to the plane of the substrate 100. The direction perpendicular to the plane of the substrate 100 is, for example, the thickness direction Z of the display panel.

[0029] Optional, such as Figures 1 to 3 As shown, when the second gate 230 is electrically connected to a signal line, for example, when the second gate 230 is electrically connected to a scan signal line Scan, and the second gate 230 and the scan signal line Scan are integrally disposed on the same layer, the second gate 230 can be the portion of the scan signal line Scan that overlaps with the first semiconductor 220 along the thickness direction Z. For example, when the first channel region 221 extends along the first direction X and the scan signal line Scan extends along the second direction Y, the first channel region 221 is the portion of the first semiconductor 220 that overlaps with the scan signal line Scan along the thickness direction Z. The length of the first channel region 221 in the first direction X is determined by the linewidth of the scan signal line Scan, and the channel width of the first channel region 221 in the second direction Y is determined by the width of the first semiconductor 220 itself. Since the second gate 230 can be the portion of the scan signal line Scan that overlaps with the first semiconductor 220 along the thickness direction Z, the length of the second gate 230 in the second direction Y is determined by the channel width of the first channel region 221 in the second direction Y.

[0030] Optionally, the first channel region 221 is the region where the projection of the first semiconductor 220 on the substrate 100 and the projection of the second gate 230 on the substrate 100 overlap; that is, in the direction perpendicular to the plane of the substrate 100, the first channel region 221 is the region of the first semiconductor 220 that overlaps with the second gate 230. The second gate 230 can control the conduction and cutoff of the first channel region 221. When the first channel region 221 is in the conduction state, the first source region 222 and the first drain region 223 are mutually connected. When the first channel region 221 is in the cutoff state, the first source region 222 and the first drain region 223 are mutually insulated. The first source region 222 is electrically connected to the source of the switching transistor 200, and the first drain region 223 is electrically connected to the drain of the switching transistor 200.

[0031] In some other alternative embodiments, such as Figure 1 , Figure 4 and Figure 5 As shown, the second gate 230 and the scan signal line Scan are located in different conductive layers. The second gate 230 and the scan signal line Scan are connected by a via. The second gate 230 is a separately configured conductive block. The length of the second gate 230 in the second direction Y is greater than the length of the first channel region 221 in the second direction Y. The length of the second gate 230 in the first direction X determines the length of the first channel region 221 in the first direction X.

[0032] The dimensions of the first gate 210 and the second gate 230 can be the same. Or, as... Figure 4As shown, in some alternative embodiments, the length of the first gate 210 in the first direction X is less than the length of the first channel region 221 in the first direction X.

[0033] In these optional embodiments, the length of the first gate 210 in the first direction X is less than the length of the first channel region 221 in the first direction X. This means that there are areas in the first channel region 221 not covered by the first gate 210, reducing the control capability of the first gate 210 over the first channel region 221. A larger voltage needs to be applied to the first gate 210 to transition the first channel region 221 from the off state to the on state. This makes the threshold voltage Vth of the switching transistor 200 more positive, reducing the off-state leakage current of the switching transistor 200 and increasing the on-state current, resulting in faster charging speeds and better circuit compensation.

[0034] In related technologies, when the first semiconductor 220 and the driving semiconductor 320 are arranged on the same layer, the switching transistor 200 requires a larger on-state current. Therefore, the switching transistor 200 needs two gate structures, a first gate 210 and a second gate 230. Related technologies achieve a positive threshold voltage Vth bias for the switching transistor 200 by increasing the spacing between the first gate 210 and the first semiconductor 220. However, the driving transistor 300 requires better compensation and lower grayscale performance, necessitating a smaller spacing between the shielding portion 310 and the driving semiconductor 320.

[0035] To increase the spacing between the first gate 210 and the first semiconductor 220, the first gate 210 is typically positioned between the first sub-electrode 410 and the substrate 100 in related technologies. Conversely, to reduce the spacing between the shield 310 and the driving semiconductor 320, the shield 310 is typically positioned between the first sub-electrode 410 and the driving semiconductor 320, for example, by placing the shield 310 and the second sub-electrode 420 on the same layer. Therefore, at least one conductive layer for mounting the first gate 210 and one insulating layer need to be added between the first sub-electrode 410 and the substrate 100, and this conductive layer also needs to be patterned. At least two conductive layers are provided between the shield 310 and the substrate 100, one for mounting the first gate 210 and the other for mounting the first sub-electrode 410. This not only increases the thickness of the display panel but also makes the fabrication of the display panel more complex.

[0036] In the display panel provided in this embodiment, the first semiconductor 220 and the driving semiconductor 320 are firstly disposed on the same layer, and the shielding portion 310 and the second sub-electrode 420 are also disposed on the same layer. The shielding portion 310 is a conductive layer adjacent to the driving semiconductor 320. The small distance between the shielding portion 310 and the driving semiconductor 320 enables better compensation and lower grayscale effect. Then, the first gate 210 and the first sub-electrode 410 or the second sub-electrode 420 are disposed on the same layer, eliminating the need to add a conductive layer between the first sub-electrode 410 and the substrate 100 to accommodate the first gate 210, thus simplifying the film structure and fabrication process of the display panel. However, the distance between the first gate 210 and the first channel region 221 will decrease. In this embodiment, by reducing the length of the second gate 230 in the first direction X, the overlap area of ​​the first channel region 221 and the first gate 210 along the thickness direction Z is reduced, thereby weakening the control of the first gate 210 on the first channel region 221. This makes the threshold voltage Vth of the switching transistor 200 more positive, ensuring the device performance of the switching transistor 200. Therefore, this embodiment not only simplifies the film structure and fabrication process of the display panel but also ensures the device performance of the switching transistor 200.

[0037] Optionally, the second gate 230 is electrically connected to the scan signal line Scan, rather than being directly electrically connected to the first gate 210. For example, the second gate 230 is part of the scan signal line Scan, allowing the scan control signal to quickly control the conduction and cutoff of the first channel region 221 through the second gate 230. Alternatively, the scan signal line Scan is located on the side of the second gate 230 facing away from the substrate 100, and the scan signal line Scan and the second gate 230 are connected by a via.

[0038] Optional, such as Figure 6 As shown, the length of the first gate 210 in the second direction Y is less than the length of the first channel region 221 in the second direction Y. The second direction Y intersects the first direction X, and the second direction Y and the first direction X are parallel to the plane containing the substrate 100. Optionally, the first direction X, the second direction Y, and the thickness direction Z are all perpendicular to each other.

[0039] In these optional embodiments, the length of the first gate 210 in the second direction Y is less than the length of the first channel region 221 in the second direction Y. Therefore, the first gate 210 may also result in areas on the first channel region 221 not covered by the first gate 210. This reduces the control capability of the first gate 210 over the first channel region 221, requiring a larger voltage to be applied to the first gate 210 to transition the first channel region 221 from the off state to the on state. This makes the threshold voltage Vth of the switching transistor 200 more positive, reducing the off-state leakage current of the switching transistor 200 and increasing the on-state current, thus achieving faster charging speeds and better circuit compensation.

[0040] Optional, such as Figure 7 As shown, the length of the first gate 210 in the first direction X and the length of the first gate 210 in the second direction Y are both smaller than the first channel region 221, so as to further reduce the overlap area of ​​the first gate 210 and the first channel region 221 along the thickness direction Z, reduce the control force of the first gate 210 on the first channel region 221, and make the threshold voltage Vth of the switching transistor 200 more positive, thereby achieving faster charging speed and better circuit compensation effect.

[0041] In some alternative embodiments, such as Figure 4 As shown, the length of the second gate 230 in the second direction Y is greater than or equal to the length of the first channel region 221 in the second direction Y. The second gate 230 is part of the scan signal line Scan, and the lengths of the second gate 230 and the first channel region 221 in the second direction Y can be the same. For example, the second gate 230 is the portion of the scan signal line Scan that overlaps with the first semiconductor 220 along the thickness direction Z. Alternatively, the length of the second gate 230 in the second direction Y can be larger. For example, if the scan signal line Scan extends along the second direction Y, the length of the second gate 230 in the second direction Y can be appropriately increased.

[0042] In some alternative embodiments, such as Figure 4 and Figure 7 As shown, the length of the first gate 210 in the first direction X is less than the length of the second gate 230 in the first direction X.

[0043] Referring to the above, the first channel region 221 is the portion of the first semiconductor 220 that overlaps with the second gate 230 along the thickness direction Z. The length of the first channel region 221 in the first direction X is determined by the length of the second gate 230 in the second direction Y. When the length of the first gate 210 in the first direction X is less than the length of the second gate 230 in the first direction X, making the length of the first gate 210 in the first direction X less than the length of the first channel region 221 in the first direction X, the overlap area between the first gate 210 and the first channel region 221 can be reduced, thus reducing the control exerted by the first gate 210 on the first channel region 221, and making the threshold voltage Vth of the switching transistor 200 more positive.

[0044] Optionally, the second sub-electrode 420 and the shielding portion 310 are disposed in the same layer, that is, the second sub-electrode 420 and the shielding portion 310 are located in the same conductive layer. For example, both the second sub-electrode 420 and the shielding portion 310 are located in the second conductive layer M2. In the first sub-electrode 410 and the second sub-electrode 420, the second sub-electrode 420 is farther away from the substrate 100 relative to the first sub-electrode 410, and the distance between the second sub-electrode 420 and the driving semiconductor 320 in the thickness direction Z is small. The co-layering of the second sub-electrode 420 and the shielding portion 310 results in a smaller distance between the shielding portion 310 and the driving semiconductor 320, which can achieve better compensation effect and larger subthreshold swing.

[0045] In one of the optional implementations, such as Figure 2 and Figure 5 As shown, the driving semiconductor 320 includes a driving channel region 321 and a driving source region 322 and a driving drain region 323 located on both sides of the driving channel region 321 in the first direction X. The driving channel region 321 is the region where the driving semiconductor 320 and the driving gate 330 overlap in a direction perpendicular to the plane of the substrate 100. The length of the driving channel region 321 in the first direction X is less than the length of the shielding portion 310 in the first direction X.

[0046] The electrical connection between the shield 310 and the driving semiconductor 320 is equivalent to applying a bias at the same potential as the source on the side of the driving channel away from the driving gate 330. This allows the shield 310 to provide a fixed back-gate bias. This bias causes the back side of the driving channel to be in an accumulation or depletion state, thereby shifting the threshold voltage in the forward direction and increasing the subthreshold swing. In addition, the shield 310 and the driving source region 322 are at the same potential, that is, the shield 310 and the source of the driving transistor 300 are at the same potential. Combined with the small distance between the shield 310 and the driving channel region 321, this can effectively change the band bending on the back side of the driving channel region 321, while making the current change in the subthreshold region smoother (i.e., increasing the subthreshold swing), meeting the requirement of precise current control of the driving transistor 300 at low gray levels.

[0047] In these alternative embodiments, the shielding portion 310 has a longer length in the first direction X and a larger distribution area. On the one hand, this allows the shielding portion 310 to better block light from the non-display side from entering the driving channel region 321. On the other hand, the larger shielding portion 310 can better cover the entire driving channel region 321 and even extend to the edges of the driving source region 322 and the driving drain region 323, allowing the back gate bias to be evenly distributed throughout the driving channel region 321, improving the uneven threshold voltage or subthreshold swing caused by local potential differences. Furthermore, the larger shielding portion 310 can better shield the electric field lines from the driving drain region 323, reducing the drain-induced barrier reduction phenomenon, keeping the threshold voltage stable under short-channel conditions, and improving the saturation characteristics of the device.

[0048] Optionally, the length of the drive channel region 321 in the second direction Y is less than the length of the shielding portion 310 in the second direction Y, so as to further increase the distribution area of ​​the shielding portion 310.

[0049] like Figure 2 and Figure 5 As shown, the first gate 210 and the second sub-electrode 420 are disposed in the same layer; for example, the first gate 210, the second sub-electrode 420, and the shielding portion 310 are all located in the second conductive layer M2. Alternatively, as... Figure 8 As shown, the first gate 210 and the first sub-electrode 410 are arranged in the same layer.

[0050] In some alternative embodiments, referring to the above, the pixel circuit 500 includes not only the switching transistor 200, the driving transistor 300, and the first capacitor 400 described above, but may also include other transistors or capacitors. For example, such as Figures 1 to 8 As shown, the pixel circuit 500 also includes a light-emitting control transistor and a data-writing transistor 530. The light-emitting control transistor is connected between the power signal line and the driving transistor 300, or the light-emitting control transistor is connected to the output terminal of the driving transistor 300. The data-writing transistor 530 is connected between the data signal line Data and the first capacitor 400. The switching transistor 200 includes at least one of the light-emitting control transistor and the data-writing transistor 530.

[0051] Optionally, the output terminal of the driving transistor 300 is one of its source and drain terminals that is not connected to the driving power signal line Vdd. For example, the source of the driving transistor 300 is connected to the driving power signal line Vdd, and the drain of the driving transistor 300 is the output terminal; or the drain of the driving transistor 300 is connected to the driving power signal line Vdd, and the source of the driving transistor 300 is the output terminal. Optionally, the output terminal of the driving transistor 300 is connected to the shielding portion 310 and the second sub-plate 420.

[0052] Optional, such as Figure 2 and Figure 3 As shown, one of the source and drain of the data writing transistor 530 is connected to the data signal line Data, and the other is connected to the first sub-plate 410. For example, as Figure 3 As shown, in the equivalent circuit diagram of pixel circuit 500, pixel circuit 500 includes a first node N1. Data writing transistor 530, first sub-electrode plate 410 and driving gate 330 of driving transistor 300 are all connected to the first node N1, that is, data writing transistor 530, first sub-electrode plate 410 and driving gate 330 of driving transistor 300 are electrically connected to each other.

[0053] In these alternative embodiments, at least one of the light-emitting control transistor and the data writing transistor 530 is a switching transistor 200, that is, at least one of the light-emitting control transistor and the data writing transistor 530 is a dual-gate structure, and one of the gates and one of the plates of the first capacitor 400 are on the same layer, which can simplify the manufacturing process of the display panel.

[0054] Optionally, the number of light-emitting control transistors can be one or two. For example, there are two light-emitting control transistors, namely a first light-emitting control transistor 510 and a second light-emitting control transistor 520. The first light-emitting control transistor 510 is connected between the driving power signal line Vdd and the driving transistor 300. One end of the second light-emitting control transistor 520 is connected to the driving transistor 300, and the other end is used to connect to the pixel electrode of the sub-pixel 120. Optionally, the equivalent circuit diagram of the pixel circuit 500 includes a second node N2, and the output terminals of the second light-emitting control transistor 520, the second sub-electrode plate 420, the shielding part 310, and the driving transistor 300 are all connected to the second node N2.

[0055] In some alternative embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 500 further includes a first reset transistor 540, a second capacitor 560, and a second reset transistor 550. The first reset transistor 540 is connected to the driving gate 330 of the driving transistor 300; the second capacitor 560 is electrically connected to the driving transistor 300 and the first capacitor 400; the second reset transistor 550 is connected to the second capacitor 560; wherein, the second capacitor 560 includes a third sub-plate 561 and a fourth sub-plate 562, the fourth sub-plate 562 is located on the side of the third sub-plate 561 away from the substrate 100, and the third sub-plate 561 and the fourth sub-plate 562 at least partially overlap along a direction perpendicular to the plane of the substrate 100; one of the third sub-plate 561 and the fourth sub-plate 562 is electrically connected to the first sub-plate 410, and the other of the third sub-plate 561 and the fourth sub-plate 562 is electrically connected to the second reset transistor 550, and the switching transistor 200 includes at least one of the first reset transistor 540 and the second reset transistor 550.

[0056] Optionally, when the pixel circuit 500 includes the first node N1 described above, the first reset transistor 540 can be connected to the first node N1 and connected to the driving gate 330 through the first node. Optionally, when the pixel circuit 500 includes the second node N2 described above, the third sub-plate 561 is connected to the second node N2, and the fourth plate is connected to the second reset transistor 550.

[0057] In these alternative embodiments, the first reset transistor 540 can reset the first node N1 and the driving gate 330, the second reset transistor 550 can reset the second node N2 and the output of the driving transistor 300, and the second capacitor 560 is an auxiliary storage capacitor. The first reset transistor 540, the second reset transistor 550 and the second capacitor 560 can improve the performance of the pixel circuit 500. At least one of the first reset transistor 540 and the second reset transistor 550 is the aforementioned switching transistor 200. That is, one of the gates of at least one of the first reset transistor 540 and the second reset transistor 550 is on the same layer as one of the plates of the first capacitor 400. For example, the gate of at least one of the first reset transistor 540 and the second reset transistor 550 and one of the plates of the first capacitor 400 are reused. A portion of the conductive area on the conductive layer can serve as the gate of at least one of the first reset transistor 540 and the second reset transistor 550, or as one of the plates of the first capacitor 400. This simplifies the manufacturing process and wiring structure of the display panel, improves the manufacturing efficiency of the display panel, and reduces the distribution area of ​​the pixel circuit 500, so as to increase the aperture ratio of the sub-pixel 120.

[0058] Optionally, the driving gate 330 and the second gate 230 are disposed on the same layer, and one of the third sub-electrode plate 561 and the fourth sub-electrode plate 562 is disposed on the same layer as the driving gate 330, so as to further simplify the film layer structure of the display panel. For example, the third sub-electrode plate 561 is on the same layer as the driving gate 330 and the second gate 230, and the third sub-electrode plate 561 is electrically connected to the shielding portion 310.

[0059] Optionally, the switching transistor 200 further includes a first source 240 and a first drain 250, with the first source 240 electrically connected to the first source region 222 and the first drain 250 electrically connected to the first drain region 223. One of the third sub-plate 561 and the fourth sub-plate 562 is disposed on the same layer as the driving gate 330, and the other of the third sub-plate 561 and the fourth sub-plate 562 is disposed on the same layer as the first source 240 and the first drain 250, to further simplify the film layer structure of the display panel. Alternatively, the other of the third sub-plate 561 and the fourth sub-plate 562 may be located between the film layer containing the first source 240 and the film layer containing the second gate 230, to reduce the distance between the third sub-plate 561 and the fourth sub-plate 562 and increase the capacitance of the second capacitor 560.

[0060] Optionally, the multiple conductive layers of the display panel include a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 stacked in a direction away from the substrate 100. Optionally, the material of each conductive layer may include at least one of molybdenum and titanium. For example, the material of the first conductive layer M1 may include molybdenum, the material of the second conductive layer M2 may include titanium, the material of the third conductive layer M3 may include molybdenum and / or titanium, the material of the fourth conductive layer M4 may include molybdenum, and the material of the fifth conductive layer M5 may include a metallic material, such as titanium and / or molybdenum. Optionally, an active layer is located between the second conductive layer M2 and the third conductive layer M3. Optionally, a first insulating layer 610 is provided between the first conductive layer M1 and the second conductive layer M2, and the material of the first insulating layer 610 may include silicon oxide. A second insulating layer 620 is provided between the second conductive layer M2 and the active layer, and the material of the second insulating layer 620 may include at least one of silicon oxide and silicon nitride. For example, the material of the second insulating layer 620 may include a stacked silicon oxide layer and a silicon nitride layer. A third insulating layer 630 is provided between the active layer and the third conductive layer M3, and the material of the third insulating layer 630 may include silicon oxide. A fourth insulating layer 640 is provided between the third conductive layer M3 and the fourth conductive layer M4, and the material of the fourth insulating layer 640 may include silicon nitride. A fifth insulating layer 650 is provided between the fourth conductive layer M4 and the fifth conductive layer M5, and the material of the fifth insulating layer 650 may include at least one of silicon oxide and silicon nitride, for example, the material of the fifth insulating layer 650 may include a stacked silicon oxide layer and a silicon nitride layer.

[0061] Optionally, the second gate 230, the driving gate 330, and the third sub-electrode 561 are located in the third conductive layer M3. Optionally, the fourth sub-electrode 562 is located in the fourth conductive layer M4.

[0062] Optionally, the driving transistor 300 includes a driving source 340 and a driving drain 350, the driving source 340 being electrically connected to the driving source region 322, and the driving drain 350 being electrically connected to the driving drain region 323. The driving source 340 and the driving drain 350 are located in the fifth conductive layer M5. Optionally, the first source 240 and the first drain 250 are located in the fifth conductive layer M5.

[0063] In some alternative embodiments, such as Figure 2 , Figure 5 and Figure 8 As shown, one or two insulating layers are disposed between the first gate 210 and the first semiconductor 220. For example, as Figure 8 As shown, when the first gate 210 is located in the first conductive layer M1, there are two insulating layers between the first gate 210 and the first semiconductor 220. Figure 2 and Figure 5As shown, when the first gate 210 is located in the second conductive layer M2, there is an insulating layer between the first gate 210 and the first semiconductor 220.

[0064] In some optional embodiments, the distance between the first gate 210 and the first semiconductor 220 is 50nm to 200nm. For example, when the first gate 210 is located in the second conductive layer M2, and there is an insulating layer, namely the second insulating layer 620, between the first gate 210 and the first semiconductor 220, and the thickness of the second insulating layer 620 is 50nm to 200nm, the distance between the first gate 210 and the first semiconductor 220 is 50nm to 200nm.

[0065] Alternatively, in some other optional embodiments, the distance between the first gate 210 and the first semiconductor 220 is 100nm to 350nm. For example, when the first gate 210 is located in the first conductive layer M1, and there is a first insulating layer 610 and a second insulating layer 620 between the first gate 210 and the first semiconductor 220, the thickness of the first insulating layer 610 is 50nm to 150nm, and the thickness of the second insulating layer 620 is 50nm to 200nm, then the distance between the first gate 210 and the first semiconductor 220 is 100nm to 350nm.

[0066] In related technologies, in order to ensure a sufficiently large distance between the first gate 210 and the first semiconductor 220, the first gate 210 is often located between the first conductive layer M1 and the substrate 100. The first gate 210, the first sub-electrode 410, and the second sub-electrode 420 are located in three different conductive layers, and there are at least three insulating layers between the first gate 210 and the first semiconductor 220. This not only increases the thickness of the display panel, but also adds two masking processes because an additional conductive layer is needed to set the first gate 210, which increases the process complexity of the display panel and seriously reduces the manufacturing efficiency of the display panel.

[0067] In this embodiment, by placing the first gate 210 on the first conductive layer M1 or the second conductive layer M2, the fabrication of at least two film layers can be simplified, effectively simplifying the display panel fabrication process. Furthermore, to address the issue of the first gate 210 being too close to the first semiconductor 220, the length of the first gate 210 in the first direction X and / or the second direction Y is made shorter than the length of the first channel region 221 in the first direction X and / or the second direction Y. This weakens the control exerted by the first gate 210 on the first channel region 221, requiring a larger voltage to be applied to the first gate 210 to transition the first channel region 221 from the off state to the on state. This makes the threshold voltage Vth of the switching transistor 200 more positive, reducing the off-state leakage current of the switching transistor 200, increasing the on-state current of the switching transistor 200, achieving faster charging speed and better circuit compensation.

[0068] In some alternative embodiments, such as Figure 2 , Figure 5 and Figure 8 As shown, the display panel also includes a buffer layer 110, which is disposed on one side of the substrate 100. The switching transistor 200, the driving transistor 300, and the first capacitor 400 are all disposed on the side of the buffer layer 110 facing away from the substrate 100. An insulating layer is disposed between the first gate 210 and the buffer layer 110, or the first gate 210 and the buffer layer 110 are in contact; or the distance between the first gate 210 and the buffer layer 110 is 50nm to 150nm. For example, as... Figure 8 As shown, when the first gate 210 is located on the first conductive layer M1, the first conductive layer M1 is directly disposed on the buffer layer 110, and the first gate 210 and the buffer layer 110 can be in direct contact. Alternatively, as... Figure 2 and Figure 5 As shown, when the first gate 210 is located in the second conductive layer M2, there is a first insulating layer 610 between the first gate 210 and the buffer layer 110. The thickness of the first insulating layer 610 is 50nm~150nm, so the distance between the first gate 210 and the buffer layer 110 is 50nm~150nm.

[0069] In some alternative embodiments, such as Figure 4 , Figure 6 and Figure 7 As shown, the display panel also includes a first connecting portion 710, a second connecting portion 720, and a third connecting portion 730; the first connecting portion 710 is on the same layer as the first gate 210 and electrically connected, the second connecting portion 720 is on the same layer as the second gate 230 and electrically connected; the first connecting portion 710 and the second connecting portion 720 are electrically connected through the third connecting portion 730.

[0070] In these alternative embodiments, the second gate 230 and the first gate 210 are electrically connected to each other via a first connection portion 710, a second connection portion 720 and a third connection portion 730.

[0071] Optionally, the third connection portion 730 is disposed in the same layer as the first source electrode 240 and the first drain electrode 250, for example, the third connection portion 730 is located in the fifth conductive layer M5. In these optional embodiments, disposing the third connection portion 730 in the same layer as the first source electrode 240 and the first drain electrode 250 allows the insulating layer to be perforated before fabricating the fifth conductive layer M5, enabling the via-connected devices to be interconnected through the connection portion within the fifth conductive layer M5, thereby simplifying the fabrication process of the display panel.

[0072] Optionally, as described above, when the driving semiconductor 320 and the shielding portion 310 are electrically connected to each other through conductive portions, such as... Figure 2 , Figure 5 and Figure 8 As shown, the display panel also includes a first conductive portion 130, which is disposed on the same layer as the third connecting portion 730. One end of the first conductive portion 130 is connected to the driving semiconductor 320 via a via, and the other end of the first conductive portion 130 is connected to the shielding portion 310 via a via, so that the driving semiconductor 320 and the shielding portion 310 can be electrically connected to each other through the first conductive portion 130. In addition, since the first conductive portion 130 and the third connecting portion 730 are on the same layer, the connecting vias for connecting the third connecting portion 730 and the first connecting portion 710, the third connecting portion 730 and the second connecting portion 720, the first conductive portion 130 and the driving semiconductor 320, and the first conductive portion 130 and the shielding portion 310 can be prepared in the same process step, which can further simplify the manufacturing process of the display panel.

[0073] Optionally, the first connecting portion 710 is located on one side of the first gate 210 in the second direction Y, and the length of the first connecting portion 710 in the first direction X is less than the length of the first gate 210 in the first direction X. The location of the first connecting portion 710 on one side of the first gate 210 in the second direction Y, rather than the first direction X, avoids increasing the size of the first gate 210 in the first direction X. It also allows the connection via between the first connecting portion 710 and the third connecting portion 730 to be spaced apart from the first channel region 221 along the second direction Y, improving the problem of positional interference. Furthermore, the shorter length of the first connecting portion 710 in the first direction X compared to the first gate 210 in the first direction X also avoids increasing the actual size of the first gate 210 in the second direction Y, ensuring that the actual size of the first gate 210 is sufficiently small and that the control exerted by the first gate 210 on the first channel region 221 is sufficiently small.

[0074] Optionally, the first capacitor 400 and / or the second capacitor 560 are located between the switching transistor 200 and the driving transistor 300.

[0075] The beneficial effects of the embodiments of this application will be illustrated below with reference to a set of comparative examples, including Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4. The display panels provided in Embodiments 1 to 4 all include a substrate 100 and a switching transistor 200 disposed on the substrate 100. The switching transistor 200 includes a first gate 210, a first semiconductor 220, a second gate 230, a first source 240, and a first drain 250 stacked in a direction away from the substrate 100. An insulating layer is disposed between the first gate 210 and the first semiconductor 220, an insulating layer is disposed between the first semiconductor 220 and the second gate 230, and an insulating layer is disposed between the first semiconductor 220 and the first source 240 and the first drain 250. The first semiconductor 220 includes a first channel region 221 and a first source 240 and a first drain 250 located on both sides of the first channel region 221 in a first direction X. In each embodiment, the threshold voltage Vth, the length of the first channel region 221 in the first direction X is L, and the distance between the first channel region 221 and the first gate 210 in the thickness direction Z is h. L and / or h are different between any two embodiments in Embodiments 1 to 4.

[0076] Simulations of Examples 1 to 4 yielded the following results: Figures 9 to 12 The graph shown shows that, Figure 9 This is a graph of Example 1. Figure 10 This is a graph of Example 2. Figure 11 This is a graph of Example 3. Figure 12 These are graphs from Example 4. In each graph, the horizontal axis represents the voltage applied to the second gate 230, in volts (V), and the vertical axis represents the drain current, in amperes (A). Figures 9 to 12 Merging Figure 13 , Figure 13 The graphs include those from Examples 1 to 4. Combined with... Figures 1 to 13 Based on the results and the correspondence between L and h in each embodiment, the following table is obtained: A comparison of Embodiments 1 and 2 shows that when the length L of the first channel region 221 in the first direction X remains constant, increasing the distance h between the first channel region 221 and the first gate 210 in the thickness direction Z increases the threshold voltage Vth, making the threshold voltage Vth more positive. A comparison of Embodiments 1 and 4, and Embodiments 2 and 3 shows that when the distance h between the first channel region 221 and the first gate 210 remains constant, decreasing the length L of the first channel region 221 in the first direction X effectively increases the threshold voltage Vth. In this embodiment, when the first gate 210 is located in the first conductive layer M1 or the second conductive layer M2, and the first gate 210 is on the same layer as the first sub-electrode 410 or the second sub-electrode 420, and the distance between the first gate 210 and the first semiconductor 220 is relatively close, the threshold voltage Vth of the switching transistor 200 can be kept within a preset range by changing the size of the first gate 210.

[0077] like Figure 14 As shown, an embodiment of the second aspect of the present invention also provides a display device 1, including the display panel 10 of any of the embodiments of the first aspect described above. Since the display device 1 provided by the embodiment of the second aspect of the present invention includes the display panel 10 of any of the embodiments of the first aspect described above, the display device 1 provided by the embodiment of the second aspect of the present invention has the beneficial effects of the display panel 10 of any of the embodiments of the first aspect described above, which will not be repeated here.

[0078] The display device 1 in this embodiment of the invention includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0079] like Figure 15 As shown, an embodiment of the third aspect of this application also provides a method for manufacturing a display panel. The display panel can be any of the display panels provided in the above embodiments. Please refer to the accompanying documentation. Figures 1 to 15 The methods for manufacturing display panels include: Step S01: A first conductive layer M1, a first insulating layer 610, and a second conductive layer M2 are sequentially prepared on one side of the substrate 100. The first conductive layer M1 includes a first sub-electrode 410, and the second conductive layer M2 includes a second sub-electrode 420 and a shielding portion 310. The first conductive layer M1 or the second conductive layer M2 includes the first gate 210 described above.

[0080] Optionally, when the display panel includes a buffer layer 110, a buffer layer 110 located between the first conductive layer M1 and the substrate 100 is also formed in step S01.

[0081] Optionally, the first gate 210 is located in the first conductive layer M1. For example... Figure 16 As shown, step S01 includes: Step S011: As Figure 17 As shown, a first conductive material layer is disposed on one side of the substrate 100, and the first conductive material layer is patterned to form a first conductive layer M1 including a first gate 210 and a first sub-electrode 410. Step S012: Prepare a first insulating layer 610 on the side of the first conductive layer M1 that is away from the substrate 100.

[0082] Step S013: As Figure 18 As shown, a second conductive material layer is provided on the side of the first insulating layer 610 away from the substrate 100, and the second conductive material layer is patterned to form a second conductive layer M2 including a second sub-electrode 420 and a shielding portion 310.

[0083] In some alternative embodiments, the first gate 210 is located in the second conductive layer M2, such as... Figure 19 As shown, step S01 includes: Step S011': As Figure 20 As shown, a first conductive material layer is disposed on one side of the substrate 100, and the first conductive material layer is patterned to form a first conductive layer M1 including a first sub-electrode 410.

[0084] Step S012': Prepare a first insulating layer 610 on the side of the first conductive layer M1 that is away from the substrate 100.

[0085] Step S013': As Figure 21 As shown, a second conductive material layer is disposed on the side of the first insulating layer 610 away from the substrate 100, and the second conductive material layer is patterned to form a second conductive layer M2 including a first gate 210, a second sub-electrode 420, and a shielding portion 310.

[0086] by Figure 2 and Figure 21 Taking the film layer structure of the display panel shown as an example, optionally, after step S01, the following method is also included: Step S02: Prepare a second insulating layer 620 on the side of the second conductive layer M2 that is away from the substrate 100.

[0087] Step S03: As Figure 22 As shown, a metal oxide material layer is disposed on the side of the second insulating layer 620 away from the second conductive layer M2, and the metal oxide material layer is patterned to form an active layer, which includes a first semiconductor 220 and a driving semiconductor 320.

[0088] Optionally, when the pixel circuit 500 of the display panel includes other transistors, such as light-emitting control transistors, first reset transistors 540 and second reset transistors 550, the active layer in step S03 may also include semiconductors of other transistors.

[0089] Step S04: Prepare a third insulating layer 630 on the side of the active layer away from the substrate 100.

[0090] Step S05: As Figure 23 As shown, a third conductive material layer is disposed on the side of the third insulating layer 630 away from the substrate 100, and the third conductive material layer is patterned to form a third conductive layer M3. The third conductive layer M3 includes a second gate 230, a third sub-electrode 561 and a driving gate 330.

[0091] Optionally, in step S05, as follows Figure 24 As shown, the first semiconductor 220 and the driving semiconductor 320 can be ion implanted using the second gate 230 and the driving gate 330 as masks, so that the first semiconductor 220 includes a first channel region 221, a first source region 222 and a first drain region 223, and the driving semiconductor 320 includes a driving channel region 321, a driving source region 322 and a driving drain region 323. Figure 24 The arrows in the middle indicate the direction of ion implantation.

[0092] Optionally, when the pixel circuit 500 of the display panel includes other transistors, the third conductive layer M3 in step S05 may also include the gates of other transistors. Optionally, when the display panel includes a scan signal line Scan, and a portion of the scan signal line Scan serves as the first gate 210, the third conductive layer M3 in step S05 may also include the scan signal line Scan. When the display panel includes a light emission control signal line, and a portion of the light emission control signal line serves as the gate of the light emission control transistor, the third conductive layer M3 may also include the light emission control signal line.

[0093] Step S06: Prepare a fourth insulating layer 640 on the side of the third conductive layer M3 that is away from the substrate 100.

[0094] Step S07: As Figure 25 As shown, a fourth conductive material layer is disposed on the side of the fourth insulating layer 640 away from the substrate 100, and the fourth conductive material layer is patterned to form a fourth sub-electrode 562.

[0095] Step S08: Prepare a fifth insulating layer 650 on the side of the fourth conductive layer M4 that is away from the substrate 100.

[0096] Step S09: As Figure 2As shown, a fifth conductive material layer is disposed on the side of the fifth insulating layer 650 away from the substrate 100, and the fifth conductive material layer is patterned to form a fifth conductive layer M5. The fifth conductive layer M5 includes a first source 240, a first drain 250, a driving source 340, and a driving drain 350.

[0097] Optionally, when the pixel circuit 500 of the display panel includes other transistors, the third conductive layer M3 in step S09 also includes the source and drain of other transistors.

[0098] Optionally, when the display panel includes the third connecting portion 730 and the first conductive portion 130 as described above, the first connecting portion 710 can be prepared in step S01, the second connecting portion 720 can be prepared in step S05, and the third connecting portion 730 and the first conductive portion 130 can be prepared in step S09.

[0099] Optional, such as Figure 26 As shown, before step S09, at least one of the first insulating layer 610, the second insulating layer 620, the third insulating layer 630, the fourth insulating layer 640, and the fifth insulating layer 650 can be made into a via to form a connection via, such that the first source 240 and the first source region 222 are connected by a via, the first drain 250 and the first drain region 223 are connected by a via, the third connection portion 730 and the first connection portion 710 are connected by a via, the third connection portion 730 and the second connection portion 720 are connected by a via, the driving source 340 and the driving source region 322 are connected by a via, the driving drain 350 and the driving drain region 323 are connected by a via, the first conductive portion 130 and the driving semiconductor 320 are connected by a via, and the first conductive portion 130 and the shielding portion 310 are connected by a via.

[0100] In the display panel manufacturing method provided in this application embodiment, the first gate 210 is located in the first conductive layer M1, so that the first gate 210 and the first sub-electrode 410 can be formed in the same step S011, or the first gate 210 is located in the second conductive layer M2, so that the first gate 210, the second sub-electrode 420 and the shielding part 310 can be formed in the same step S013', which can effectively simplify the manufacturing process of the display panel.

[0101] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; A switching transistor is disposed on the substrate. The switching transistor includes a first gate, a first semiconductor, and a second gate. The first semiconductor is located on the side of the first gate facing away from the substrate, and the second gate is located on the side of the first semiconductor facing away from the substrate. A driving transistor is disposed on the substrate. The driving transistor includes a shielding portion, a driving semiconductor, and a driving gate. The driving semiconductor is located on the side of the shielding portion away from the substrate and is electrically connected to the shielding portion. The driving gate is located on the side of the driving semiconductor away from the substrate. A first capacitor is disposed on the substrate. The first capacitor includes a first sub-plate and a second sub-plate. The second sub-plate is located on the side of the first sub-plate away from the substrate and is perpendicular to the plane of the substrate. The first sub-plate and the second sub-plate at least partially overlap. The first sub-plate is electrically connected to the driving gate, and the second sub-plate is electrically connected to the shielding portion. In this configuration, one of the first sub-electrode plate and the second sub-electrode plate is disposed in the same layer as the first gate.

2. The display panel according to claim 1, characterized in that, Both the driving semiconductor and the first semiconductor comprise metal oxides and are disposed in the same layer.

3. The display panel according to claim 1, characterized in that, The first semiconductor includes a first channel region and a first source region and a first drain region located on both sides of the first channel region in a first direction. The first channel region is the region where the first semiconductor and the second gate overlap in a direction perpendicular to the plane of the substrate. Wherein, the length of the first gate in the first direction is less than the length of the first channel region in the first direction; And / or, the length of the first gate in the second direction is less than the length of the first channel region in the second direction, the second direction intersects the first direction, and the second direction and the first direction are parallel to the plane of the substrate.

4. The display panel according to claim 3, characterized in that, The length of the second gate in the second direction is greater than or equal to the length of the first channel region in the second direction.

5. The display panel according to claim 1, characterized in that, The first semiconductor includes a first channel region and a first source region and a first drain region located on both sides of the first channel region in a first direction. The first channel region is the region where the first semiconductor and the second gate overlap in a direction perpendicular to the plane of the substrate. Wherein, the length of the first gate in the first direction is less than the length of the second gate in the first direction.

6. The display panel according to claim 1, characterized in that, The shielding part and the second sub-electrode plate are arranged in the same layer.

7. The display panel according to claim 1, characterized in that, The driving semiconductor includes a driving channel region and driving source regions and driving drain regions located on both sides of the driving channel region in a first direction. The driving channel region is the area where the driving semiconductor and the driving gate overlap in a direction perpendicular to the plane of the substrate. Wherein, the length of the drive channel region in the first direction is less than the length of the shielding portion in the first direction.

8. The display panel according to claim 1, characterized in that, Also includes: A pixel circuit, the pixel circuit including the driving transistor, the switching transistor and the first capacitor; The pixel circuit also includes: A light-emitting control transistor is connected between the power signal line and the driving transistor, or connected to the output terminal of the driving transistor; A data writing transistor is connected between the data signal line and the first capacitor; The switching transistor includes at least one of the light-emitting control transistor and the data writing transistor.

9. The display panel according to claim 8, characterized in that, Also includes: The first reset transistor is connected to the drive gate of the drive transistor; The second capacitor is electrically connected to the driving transistor and the first capacitor; The second reset transistor is connected to the second capacitor; The second capacitor includes a third sub-plate and a fourth sub-plate. The fourth sub-plate is located on the side of the third sub-plate away from the substrate, and the third and fourth sub-plates at least partially overlap in a direction perpendicular to the plane of the substrate. One of the third and fourth sub-plates is electrically connected to the first sub-plate, and the other of the third and fourth sub-plates is electrically connected to the second reset transistor. The switching transistor includes at least one of the first reset transistor and the second reset transistor.

10. The display panel according to claim 1, characterized in that, One or two insulating layers are disposed between the first gate and the first semiconductor.

11. The display panel according to claim 1, characterized in that, The distance between the first gate and the first semiconductor is 50nm~200nm; Alternatively, the distance between the first gate and the first semiconductor is 100nm~350nm.

12. The display panel according to claim 1, characterized in that, Also includes: A buffer layer is disposed on one side of the substrate, and the switching transistor, the driving transistor, and the first capacitor are all disposed on the side of the buffer layer opposite to the substrate. An insulating layer is disposed between the first gate and the buffer layer, or the first gate and the buffer layer are in contact; or the distance between the first gate and the buffer layer is 50nm~150nm.

13. The display panel according to claim 1, characterized in that, Also includes: The second capacitor includes a third sub-plate and a fourth sub-plate, wherein the fourth sub-plate is located on the side of the third sub-plate away from the substrate, and the third sub-plate and the fourth sub-plate at least partially overlap in a direction perpendicular to the plane of the substrate. One of the third sub-electrode plate and the fourth sub-electrode plate is disposed in the same layer as the second gate.

14. The display panel according to claim 13, characterized in that, The third sub-electrode and the second gate are disposed on the same layer.

15. The display panel according to claim 14, characterized in that, The switching transistor further includes a first source and a first drain, both of which are connected to the first semiconductor via. The film layer containing the fourth sub-electrode is located between the film layers containing the first source and the first drain and the film layer containing the second gate.

16. The display panel according to claim 1, characterized in that, The first semiconductor includes a first channel region and a first source region and a first drain region located on both sides of the first channel region in a first direction. The first channel region is the region where the first semiconductor and the second gate overlap in a direction perpendicular to the plane of the substrate. The display panel further includes a first connecting portion, a second connecting portion, and a third connecting portion; the first connecting portion is on the same layer as the first gate and electrically connected, the second connecting portion is on the same layer as the second gate and electrically connected; the first connecting portion and the second connecting portion are electrically connected through the third connecting portion.

17. The display panel according to claim 16, characterized in that, The switching transistor further includes a first source and a first drain disposed on the same layer. The first source and the first source region are electrically connected through a via, and the first drain and the first drain region are electrically connected through a via. The third connection portion is disposed on the same layer as the first source.

18. The display panel according to claim 16, characterized in that, The first connection portion is located on one side of the first gate in the second direction, and the length of the first connection portion in the first direction is less than the length of the first gate in the first direction.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1-18.

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