Display panel and display device

Abstract

A display panel includes gate driving units respectively located at different curved sections, and at least part of signal lines are connected with the gate driving units of the different curved sections. The signal lines include a first signal segment and at least two second signal segments, the first signal segment is arranged at a stress concentration section, and the second signal segments are respectively arranged at two curved sections adjacent to the stress concentration section. The stress concentration section removes the gate driving units and only retains the signal lines, so that peeling of the gate driving units caused by stress increase can be avoided, normal display effect of the display panel is ensured, and the risk of failure of the display panel is reduced or eliminated. The application further provides a display device including the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Narrow bezels and even bezel-less designs have become an important development trend for high-end display products. Quad-curved display panels, due to their ability to visually further reduce bezel width, are gradually becoming the mainstream high-end product form.

[0003] Existing quad-curved display panels typically bend all four edges of the panel simultaneously. Stress concentration is prone to occur at the junction of two adjacent curved edges, which leads to a high risk of failure for the display panel.

[0004] It should be noted that the information in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the problem that stress concentration leads to a high risk of failure in the display panel, and to provide a display panel and a display device.

[0006] According to one aspect of the present invention, a display panel is provided, the display panel having a display area and a frame area located around the display area, characterized in that the frame area has a plurality of curved surfaces, stress concentration portions are formed between adjacent curved surfaces, and the display panel includes a plurality of gate driving units and a plurality of signal lines, wherein the plurality of gate driving units are respectively disposed on different curved surfaces. At least a portion of the signal lines are connected to gate drive units on different curved surfaces. The signal lines include a first signal segment and at least two second signal segments. The first signal segment is located at the stress concentration part, and the second signal segments are respectively located on two curved surfaces adjacent to the stress concentration part. The two ends of the first signal segment are respectively connected to the two second signal segments.

[0007] In one embodiment of the present invention, the display panel includes: Substrate; At least one gate layer is disposed on one side of the substrate; At least one source / drain conductive layer is disposed on the side of the gate layer away from the substrate. The first signal segment is disposed in one of the gate layer or the source / drain conductive layer. The first signal segment includes at least two sub-signal segments. The at least two sub-signal segments are disposed in at least two of the at least one gate layer and at least one source / drain conductive layer. One of the sub-signal segments is directly connected to the first signal segment, and the two ends of the remaining sub-signal segments are connected to each other through the first via.

[0008] In one embodiment of the present invention, the signal lines include a first signal line, a second signal line, and a third signal line. The second signal line is disposed on the side of the first signal line away from the display area, and the third signal line is disposed on the side of the second signal line away from the display area. The display panel also includes a first adapter cable and a second adapter cable. The first adapter cable and the second adapter cable are respectively connected to the gate driving units of two adjacent curved surfaces. The first adapter cable is disposed between the first signal line and the second signal line, and the second adapter cable is disposed between the second signal line and the third signal line. The distance between the first signal line and the first adapter cable is less than the distance between the first signal line and the second signal line, and the distance between the third signal line and the second adapter cable is less than the distance between the second signal line and the third signal line.

[0009] In one embodiment of the present invention, among a plurality of first signal segments, the orthographic projections of each sub-signal segment of the same first signal segment on the substrate overlap with each other.

[0010] In one embodiment of the present invention, the sub-signal segment includes a first sub-signal segment, a second sub-signal segment, and a third sub-signal segment. The first signal segment of the first signal line includes at least two first sub-signal segments, and the orthographic projections of the at least two first sub-signal segments on the substrate overlap each other. The first signal segment of the second signal line includes at least two second sub-signal segments, and the orthographic projections of the at least two second sub-signal segments on the substrate overlap each other. The first signal segment of the third signal line includes at least two third sub-signal segments, and the orthographic projections of the at least two third sub-signal segments on the substrate overlap each other.

[0011] In one embodiment of the present invention, among at least a portion of the plurality of first signal segments, at least two sub-signal segments of the same first signal segment do not overlap in their orthogonal projections onto the substrate.

[0012] In one embodiment of the present invention, at least two third sub-signal segments include three third sub-signal segments, one third sub-signal segment is connected to two second signal segments at both ends, one third sub-signal segment is located on the side of the second signal segment closer to the display area, and the other third sub-signal segment is located on the side of the second signal segment farther from the display area.

[0013] In one embodiment of the present invention, both the first adapter line and the second adapter line include at least two sub-adapter segments. The at least two sub-adapter segments of the first adapter line and the second adapter line are respectively disposed in at least two of at least one gate layer and at least one source / drain conductive layer. The orthographic projections of the at least two sub-adapter segments of the first adapter line and the second adapter line on the substrate do not overlap with each other.

[0014] In one embodiment of the present invention, the sub-signal segment includes at least two sub-signal segments, which are respectively disposed in different layers of at least one gate layer and at least one source / drain conductive layer. The sub-signal segment includes a straight segment, the two ends of which are respectively connected to one end of a bent segment, and the other end of the bent segment is connected to a second signal segment. The orthographic projections of the straight segments of different sub-signal segments on the substrate overlap each other, and the orthographic projections of the bent segments of different sub-signal segments on the substrate do not overlap at least partially.

[0015] In one embodiment of the present invention, at least one gate layer includes a first gate layer and a second gate layer, and at least one source / drain conductive layer includes a first source / drain conductive layer and a second source / drain conductive layer. The first gate layer, the second gate layer, the first source / drain conductive layer, and the second source / drain conductive layer are sequentially disposed along a direction away from the substrate. The display panel further includes a gate insulating layer, a first planarization layer, and a second planarization layer. The gate insulating layer is disposed between the gate layer and the first source / drain conductive layer, the first planarization layer is disposed between the first source / drain conductive layer and the second source / drain conductive layer, and the second planarization layer is disposed on the side of the second source / drain conductive layer away from the first source / drain conductive layer.

[0016] In one embodiment of the present invention, at least one of the gate insulating layer, the first planarization layer and the second planarization layer in the stress concentration area includes a plurality of stress buffer sections spaced apart.

[0017] In one embodiment of the present invention, there are multiple stress buffer portions in a first direction. The greater the distance between the stress concentration portion and two adjacent curved surfaces, the smaller the width of the stress buffer portion. The first direction is the extension direction of the signal line.

[0018] In one embodiment of the present invention, the width of the first signal segment is greater than the width of the second signal segment, or the first signal segment is configured as a curved structure.

[0019] The display panel of the present invention includes gate driving units located on different curved surfaces, and at least a portion of signal lines are connected to the gate driving units on the different curved surfaces. Each signal line includes a first signal segment and at least two second signal segments. The first signal segment is located at a stress concentration area, and the second signal segments are respectively located on two curved surfaces adjacent to the stress concentration area. The stress concentration area removes the gate driving units, retaining only the signal lines. This avoids stress increase causing peeling of the gate driving units, ensuring the normal display effect of the display panel and reducing or eliminating the risk of display panel failure.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This is a partial planar schematic diagram of the display panel involved in the related technology.

[0023] Figure 2 This is a partial planar schematic diagram of the first type of display panel according to an embodiment of the present invention.

[0024] Figure 3 for Figure 2 A magnified view of part A in the middle.

[0025] Figure 4 This is a cross-sectional schematic diagram of a first type of display panel according to an embodiment of the present invention.

[0026] Figure 5 This is another cross-sectional schematic diagram of the first type of display panel involved in the embodiments of the present invention.

[0027] Figure 6 This is a partial planar schematic diagram of the second type of display panel according to an embodiment of the present invention.

[0028] Figure 7 for Figure 6 A magnified view of part B in the middle.

[0029] Figure 8 This is a cross-sectional schematic diagram of a second type of display panel according to an embodiment of the present invention.

[0030] Figure 9 This is another cross-sectional schematic diagram of the second type of display panel involved in the embodiments of the present invention.

[0031] Figure 10 This is a partial planar schematic diagram of the third type of display panel according to an embodiment of the present invention.

[0032] Figure 11 for Figure 10 A magnified view of part C in the middle.

[0033] Figure 12 This is a cross-sectional schematic diagram of the third type of display panel according to an embodiment of the present invention.

[0034] Figure 13 This is a partial planar schematic diagram of the fourth type of display panel according to an embodiment of the present invention.

[0035] In the diagram: 1-Gate driver unit, 2-Signal line, 21-First signal line, 211-Timing control signal line, 212-First clock signal line, 213-Second clock signal line, 22-Second signal line, 23-Third signal line, 24-Fourth signal line, 201-First signal segment, 2011-Sub-signal segment, 2012-First sub-signal segment, 2013-Second sub-signal segment, 2014-Third sub-signal segment, 2015-Sub-signal segment, 2016-Straight segment, 2017-Bend segment, 202-Second signal segment, 3-Adapter line, 31-First Adapter line, 32-second adapter line, 301-sub-adapter segment, 4-substrate, 5-gate layer, 51-first gate layer, 52-second gate layer, 6-source-drain conductive layer, 61-first source-drain conductive layer, 62-second source-drain conductive layer, 63-third source-drain conductive layer, 7-gate insulating layer, 71-first gate insulating layer, 72-second gate insulating layer, 81-first planarization layer, 82-second planarization layer, 83-third planarization layer, 10-stress buffer section, 100-display area, 200-border area, 2001-curved surface area, 2002-stress concentration section. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted. Furthermore, the drawings are merely illustrative of the invention and are not necessarily drawn to scale.

[0037] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0038] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0039] With the continuous development of display technology, consumers have increasingly higher requirements for the appearance of terminal devices. Narrow bezels or even bezel-less designs have become an important development trend for high-end display devices. Among them, four-side curved display panels are gradually becoming the mainstream form of high-end display devices because they can visually further reduce the bezel width while providing users with a more rounded and smooth grip.

[0040] like Figure 1 As shown, in the quadrangular geometry, a stress concentration area 2002 is formed at the junction (i.e., the R-angle region) between two adjacent curved surfaces 2001. The stress value of the stress concentration area 2002 is significantly higher than that of the planar surface and the curved surface 2001, and the stress state is complex, typically subjected to a combination of tensile stress, compressive stress, and shear stress. With the continuous improvement of end-product reliability standards, the failure risk caused by the above-mentioned stress concentration problem has increased dramatically, mainly in the following aspects: Under the complex stress conditions of the stress concentration zone 2002, the inorganic film layer is highly susceptible to microcracks. Once the inorganic layer cracks, its function of blocking water and oxygen will fail, allowing external moisture to penetrate the light-emitting device along the cracks, ultimately leading to defects such as growing dark spots (GDS) or dark spots in the display area 100. Over time, these defects will gradually expand, eventually causing partial or complete failure of the display panel.

[0041] The signal line 2 located in the stress concentration part 2002 is prone to breakage or open circuit at the stress concentration point, which will lead to obstruction of electrical signal transmission, causing abnormal charging of sub-pixels, resulting in defects such as screen display disorder and abnormal display.

[0042] Under continuous stress, the organic planarization layer is prone to interface peeling at the stress concentration point 2002. This peeling phenomenon will spread from the outside to the inside as the reliability test time goes on. If it affects the gate drive unit 1 (GOA unit) or the transceiver (Via) of the pixel electrode, it will cause serious horizontal white bars, bright lines or large areas of black screen problems.

[0043] In summary, the reliability of the stress concentration area 2002 in existing quad-curved display panels still needs improvement when facing long-term reliability testing. How to maintain the quad-curved appearance while ensuring the normal display effect of the display panel, reducing or eliminating the risk of display panel failure, and thus meeting the reliability requirements for the next 40 days or even longer, is the technical problem that this invention urgently needs to solve.

[0044] Based on this, embodiments of the present invention provide a display panel. For example... Figures 2 to 13 As shown, the display panel has a display area 100 and a frame area 200 located around the display area 100. The frame area 200 has multiple curved surfaces 2001, and stress concentration portions 2002 are formed between two adjacent curved surfaces 2001. The display panel includes multiple gate driving units 1 and multiple signal lines 2. The multiple gate driving units 1 are respectively disposed on different curved surfaces 2001. At least some of the signal lines 2 are connected to the gate driving units 1 of different curved surfaces 2001. The signal lines 2 include a first signal segment 201 and at least two second signal segments 202. The first signal segment 201 is disposed on the stress concentration portion 2002. The second signal segments 202 are respectively disposed on two curved surfaces 2001 adjacent to the stress concentration portion 2002. The two ends of the first signal segment 201 are respectively connected to the two second signal segments 202.

[0045] Gate driving units 1 are located on different curved surfaces 2001. At least some signal lines 2 are connected to the gate driving units 1 on the different curved surfaces 2001 to ensure normal transmission of gate signals. The signal lines 2 include a first signal segment 201 and at least two second signal segments 202. The first signal segment 201 is located in the stress concentration section 2002, and the second signal segments 202 are respectively located on two curved surfaces 2001 adjacent to the stress concentration section 2002. The stress concentration section 2002 removes the gate driving units 1, retaining only the signal lines 2. This avoids stress increase causing the gate driving units 1 to peel off. Within a specified time, the voltage of the gate signal lines 2 can be charged to a set high level, ensuring the normal display effect of the display panel and reducing or eliminating the risk of display panel failure.

[0046] The display panel involved in the embodiments of the present invention will be described in detail below with reference to specific examples.

[0047] like Figure 2 and Figure 3As shown, the display panel has a display area 100 and a bezel area 200 located around the display area 100. The bezel area 200 has multiple curved surfaces 2001, and stress concentration portions 2002 are formed between adjacent curved surfaces 2001. The bezel area 200 is provided with multiple signal lines 2 and multiple gate driving units 1. The multiple signal lines 2 include a first signal line 21, a second signal line 22, a third signal line 23, and a fourth signal line 24. The first signal line 21 is located close to the display area 100, the second signal line 22 is located on the side of the first signal line 21 away from the display area 100, the third signal line 23 is located on the side of the second signal line 22 away from the display area 100, and the fourth signal line 24 is located on the side of the third signal line 23 away from the display area 100.

[0048] The first signal line 21 includes a timing control signal line 211, a first clock signal line 212, a second clock signal line 213, and an initial signal line. The timing control signal line 211 loads a frame start signal, triggering the gate driving unit 1 to output the first line scan signal. The first clock signal line 212 and the second clock signal line 213 load a pair of complementary differential clock signals, controlling the scan signal output by the gate driving unit 1 to shift down line by line. The initial signal line loads an initialization signal, which is a precharge voltage used to initialize the sub-pixels. The second signal line 22 loads a first switch control signal, which is high, controlling the transistors in the display area 100 to turn on, allowing data signals to be written to the sub-pixels. The third signal line 23 loads a second switch control signal, which is low, controlling the transistors in the display area 100 to turn off. The fourth signal line 24 provides a common signal for the entire gate driving circuit.

[0049] The timing control signal line 211 loads the frame start signal, triggering the gate drive unit 1 to output the first row scan signal. The first clock signal line 212 and the second clock signal line 213 load a pair of complementary differential clock signals, controlling the scan signal output by the gate drive unit 1 to shift down row by row, controlling the gate drive line of a certain row to output the first switch control signal, turning on the transistor connected to the gate drive line of that row. The third signal line 23 loads the second switch control signal, controlling the transistors connected to the gate drive lines of the remaining rows to turn off. The transistors are pre-charged by the initialization signal and then written with the data signal.

[0050] like Figure 4As shown, the display panel includes a substrate 4, at least one gate layer 5, and at least one source / drain conductive layer 6. The at least one gate layer 5 is disposed on one side of the substrate 4, and the at least one source / drain conductive layer 6 is disposed on the side of the gate layer 5 away from the substrate 4. The display panel includes a gate layer 5 and a source / drain conductive layer 6, with a gate insulating layer 7 between the gate layer 5 and the source / drain conductive layer 6. Specifically, the display panel includes a first gate layer 51 and a first source / drain conductive layer 61. The first source / drain conductive layer 61 is disposed on the side of the first gate layer 51 away from the substrate 4, and a first gate insulating layer 71 is disposed between the first source / drain conductive layer 61 and the first gate layer 51.

[0051] like Figure 5 As shown, the gate layer 5 may further include a second gate layer 52, and at least one source / drain conductive layer 6 may further include a second source / drain conductive layer 62. The second gate layer 52 is disposed on the side of the first gate insulating layer 71 away from the substrate 4. A second gate insulating layer 72 is disposed between the second gate layer 52 and the first source / drain conductive layer 61, and the second source / drain conductive layer 62 is disposed on the side of the first source / drain conductive layer 61 away from the substrate 4. Figure 5 As shown, the display panel may also have a first planarization layer 81 and a second planarization layer 82. The gate insulating layer 7 is disposed between the gate layer 5 and the first source / drain conductive layer 61. The first planarization layer 81 is disposed between the first source / drain conductive layer 61 and the second source / drain conductive layer 62. The second planarization layer 82 is disposed on the side of the second source / drain conductive layer 62 away from the first source / drain conductive layer 61.

[0052] The signal line 2 includes a first signal segment 201 and at least two second signal segments 202. The first signal segment 201 is located at the stress concentration part 2002, and the second signal segments 202 are respectively located at two curved surfaces 2001 adjacent to the stress concentration part 2002. The two ends of the first signal segment 201 are respectively connected to the two second signal segments 202.

[0053] The first signal segment 201 is disposed on one of the gate layer 5 or the source / drain conductive layer 6. The second signal segment 202 includes at least two sub-signal segments 2011, which are disposed on at least two of the gate layer 5 or the source / drain conductive layer 6. One sub-signal segment 2011 is directly connected to the first signal segment 201, and the two ends of the remaining sub-signal segments 2011 are interconnected through a first via. The first signal segment 201 includes at least two sub-signal segments 2011. If a sub-signal segment 2011 is disconnected due to stress concentration, the first signal segment 201 of one of the two adjacent curved surfaces 2001 can continue to conduct to the first signal segment 201 of the other curved surface 2001 through the sub-signal segments 2011 of other layers, thus avoiding interference with signal transmission.

[0054] In a plurality of first signal segments 201, the orthographic projections of each sub-signal segment 2011 of the same first signal segment 201 on the substrate 4 overlap with each other. Sub-signal segments 2011 include first sub-signal segments 2012, second sub-signal segments 2013 and third sub-signal segments 2014. The second signal segment 202 of the first signal line 21 includes at least two first sub-signal segments 2012, and the orthographic projections of the at least two first sub-signal segments 2012 on the substrate 4 overlap with each other. The second signal segment 202 of the second signal line 22 includes at least two second sub-signal segments 2013, and the orthographic projections of the at least two second sub-signal segments 2013 on the substrate 4 overlap with each other. The second signal segment 202 of the third signal line 23 includes at least two third sub-signal segments 2014, and the orthographic projections of the at least two third sub-signal segments 2014 on the substrate 4 overlap with each other.

[0055] Because the stress concentration area 2002 only contains signal line 2 and lacks other complex structures such as gate driving unit 1, its flatness is significantly improved compared to the curved area 2001 and display area 100. The area of ​​the stress concentration area 2002, excluding signal line 2, mainly consists of gate insulating layer 7, first planarization layer 81, and second planarization layer 82. All three layers act as planarization films, resulting in good flatness and minimal stress diffusion in the stress concentration area 2002. The stress concentration area 2002 has a first dimension in the first direction, ranging from 500-800 μm, which can be determined based on the simulated maximum stress range. The stress concentration area 2002 also has a second dimension in the second direction, which is greater than or equal to the dimension of gate driving unit 1 in the second direction, ranging from 200-500 μm. Both optical microscopy (OM) imaging and focused ion beam (FIB) detection methods can detect the differences between the stress concentration area 2002 and other areas.

[0056] In at least a portion of the first signal segment 201, the orthographic projections of at least two sub-signal segments 2011 of the same first signal segment 201 onto the substrate 4 do not overlap. For example... Figures 6 to 9As shown, at least two third sub-signal segments 2014 include three third sub-signal segments 2014. One third sub-signal segment 2014 has its two ends connected to two second signal segments 202 respectively. One third sub-signal segment 2014 is located on the side of the second signal segment 202 closer to the display area 100, and the other third sub-signal segment 2014 is located on the side of the second signal segment 202 away from the display area 100. Since there are gaps between the different third sub-signal segments 2014 in the second direction, to connect the third sub-signal segments 2014 of different layers to the second signal segments 202 of the third signal line 23, one third sub-signal segment 2014 needs to be connected through a first via, and the other two third sub-signal segments 2014 need to be folded back towards the second signal segment 202, and these two third sub-signal segments 2014 need to be connected to the aforementioned third sub-signal segment 2014 through a second via.

[0057] The first adapter line 31 and the second adapter line 32 each include at least two sub-adapter segments 301. The at least two sub-adapter segments 301 of the first adapter line 31 and the second adapter line 32 are respectively disposed in at least two of the at least one gate layer 5 and at least one source-drain conductive layer 6. The orthographic projections of the at least two sub-adapter segments 301 of the first adapter line 31 and the second adapter line 32 on the substrate 4 do not overlap with each other. The two ends of the at least two sub-adapter segments 301 are respectively connected to the gate driving unit 1 on two adjacent curved surfaces 2001.

[0058] like Figures 10 to 12 As shown, in the gate layer 5 and the source / drain conductive layer 6, the sub-signal segment 2011 includes at least two sub-signal segments 2015. The at least two sub-signal segments 2015 are respectively disposed in different layers of at least one gate layer 5 and at least one source / drain conductive layer 6. The sub-signal segment 2015 includes a straight segment 2016. The two ends of the straight segment 2016 are respectively connected to one end of the bent segment 2017. The other end of the bent segment 2017 is connected to the second signal segment 202. The orthographic projections of the straight segments 2016 of different sub-signal segments 2015 on the substrate 4 overlap with each other. The orthographic projections of the bent segments 2017 of different sub-signal segments 2015 on the substrate 4 do not overlap at least partially. This can reduce the stress on the sub-signal segment 2011 in the stress concentration part 2002, ensure the reliability of the sub-signal segment 2011, and prevent the first signal segment 201 from breaking at the stress concentration part 2002.

[0059] like Figure 12As shown, multiple bends 2017 of the same sub-signal segment 2011 are respectively disposed on the first gate layer 51, the second gate layer 52, the first source / drain conductive layer 61 and the second source / drain conductive layer 62. At least one source / drain conductive layer 6 may include a third source / drain conductive layer 63. The third source / drain conductive layer 63 is disposed on the side of the second planarization layer 82 away from the substrate 4. The multiple bends 2017 of the same sub-signal segment 2011 may also be provided with a third source / drain conductive layer 63. The side of the third source / drain conductive layer 63 away from the substrate is provided with a third planarization layer 83.

[0060] In the stress concentration section 2002, to prevent breakage of the signal line 2 and the adapter line 3, the width of the first signal segment 201 is greater than the width of the second signal segment 202, or the first signal segment 201 can be configured as a curved structure. Similarly, the width of the first adapter segment can be greater than the width of the second adapter segment, or the first adapter segment can be configured as a curved structure. Even under greater stress, the wider first signal segment 201 and the first adapter segment are less prone to breakage, while the curved first signal segment 201 and the first adapter segment can be straightened, thus buffering stress through deformation.

[0061] like Figure 13 As shown, in the stress concentration section 2002, at least one of the gate insulating layer 7, the first planarization layer 81 and the second planarization layer 82 includes a plurality of stress buffer sections 10 spaced apart. The plurality of stress buffer sections 10 are subjected to less stress than the gate insulating layer 7, the first planarization layer 81 and the second planarization layer 82 which are provided on the entire surface.

[0062] The first planarization layer 81 can be configured to include multiple stress buffer sections 10. In the first direction, the greater the distance between the stress concentration section 2002 and the two adjacent curved sections 2001, the greater the stress on the stress concentration section 2002. The stress is greatest at the middle position furthest from the two curved sections 2001. Therefore, the smallest stress buffer block is used. In the first direction, along the direction close to the curved section 2001, the width of the multiple stress buffer sections 10 gradually increases.

[0063] Multiple stress buffer portions 10 are symmetrically arranged about the centerline of the stress concentration portion 2002 in the second direction. The greater the distance from the centerline in the first direction, the larger the area of ​​the orthogonal projection of the stress buffer portion 10 on the substrate 4. The stress buffer portion 10 is smallest in the region where the stress is greatest, and its area gradually decreases along the direction of stress reduction, thus better dispersing the stress. The first direction is the extension direction of the signal line 2, and the second direction is perpendicular to the first direction. The first direction is the x-direction in the figure, and the second direction is the y-direction in the figure.

[0064] like Figure 13As shown, the orthographic projection of the stress buffer portion 10 onto the substrate 4 is rectangular. The rectangular stress buffer portion 10 is simpler to manufacture and has lower cost. In other embodiments, the orthographic projection of the stress buffer portion 10 onto the substrate 4 can also be a polygonal, S-shaped, or arc-shaped shape, which, compared to the rectangular stress buffer portion 10, can better cope with complex stress conditions.

[0065] It should be noted that the above embodiments are interconnected and can be combined to form other solutions. The solutions of the present invention are not limited to those described in the above embodiments. Those skilled in the art will readily conceive of other embodiments of the invention upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A display panel having a display area and a border area surrounding the display area, characterized in that, The border area has multiple curved surfaces, with stress concentration areas formed between adjacent curved surfaces. The display panel includes: Multiple gate driving units, each of which is disposed on a different curved surface; Multiple signal lines, at least some of which are connected to gate driving units on different curved surfaces, each signal line including a first signal segment and at least two second signal segments. The first signal segment is located at the stress concentration portion, and the second signal segments are respectively located on two curved surfaces adjacent to the stress concentration portion. The two ends of the first signal segment are respectively connected to the two second signal segments.

2. The display panel according to claim 1, characterized in that, The display panel includes: Substrate; At least one gate layer is disposed on one side of the substrate; At least one source / drain conductive layer is disposed on the side of the gate layer away from the substrate. The first signal segment is disposed on one of the gate layer or the source / drain conductive layer. The first signal segment includes at least two sub-signal segments. The at least two sub-signal segments are disposed on at least two of the gate layer and the source / drain conductive layer. One of the sub-signal segments is directly connected to the first signal segment, and the two ends of the remaining sub-signal segments are connected to each other through a first via.

3. The display panel according to claim 2, characterized in that, The signal lines include a first signal line, a second signal line, and a third signal line. The second signal line is located on the side of the first signal line away from the display area, and the third signal line is located on the side of the second signal line away from the display area. The display panel also includes a first adapter cable and a second adapter cable. The first adapter cable and the second adapter cable are respectively connected to the gate driving units of two adjacent curved surfaces. The first adapter cable is located between the first signal line and the second signal line, and the second adapter cable is located between the second signal line and the third signal line. The distance between the first signal line and the first adapter cable is less than the distance between the first signal line and the second signal line, and the distance between the third signal line and the second adapter cable is less than the distance between the second signal line and the third signal line.

4. The display panel according to claim 3, characterized in that, In a plurality of first signal segments, the orthographic projections of each sub-signal segment of the same first signal segment onto the substrate overlap each other.

5. The display panel according to claim 4, characterized in that, The sub-signal segment includes a first sub-signal segment, a second sub-signal segment, and a third sub-signal segment. The first signal segment of the first signal line includes at least two first sub-signal segments, and the orthographic projections of the at least two first sub-signal segments on the substrate overlap each other. The first signal segment of the second signal line includes at least two second sub-signal segments, and the orthographic projections of the at least two second sub-signal segments on the substrate overlap each other. The first signal segment of the third signal line includes at least two third sub-signal segments, and the orthographic projections of the at least two third sub-signal segments on the substrate overlap each other.

6. The display panel according to claim 3, characterized in that, In at least a portion of the plurality of first signal segments, the orthographic projections of at least two sub-signal segments of the same first signal segment onto the substrate do not overlap.

7. The display panel according to claim 6, characterized in that, At least two third sub-signal segments include three third sub-signal segments, one third sub-signal segment having its two ends connected to two second signal segments respectively, one third sub-signal segment located on the side of the second signal segment closer to the display area, and the other third sub-signal segment located on the side of the second signal segment away from the display area.

8. The display panel according to claim 6, characterized in that, Both the first adapter line and the second adapter line include at least two sub-adapter segments. The at least two sub-adapter segments of the first adapter line and the second adapter line are respectively disposed in at least two of the at least one gate layer and at least one source / drain conductive layer. The orthographic projections of the at least two sub-adapter segments of the first adapter line and the second adapter line on the substrate do not overlap with each other.

9. The display panel according to claim 2, characterized in that, The sub-signal segment includes at least two sub-signal segments, which are respectively disposed in different layers of at least one gate layer and at least one source / drain conductive layer. Each sub-signal segment includes a straight segment, with both ends of the straight segment connected to one end of a bent segment. The other end of the bent segment is connected to the second signal segment. The orthographic projections of the straight segments of different sub-signal segments on the substrate overlap each other, and the orthographic projections of the bent segments of different sub-signal segments on the substrate do not overlap at least partially.

10. The display panel according to claim 1, characterized in that, The display panel includes at least one gate layer comprising a first gate layer and a second gate layer, and at least one source / drain conductive layer comprising a first source / drain conductive layer and a second source / drain conductive layer. The first gate layer, the second gate layer, the first source / drain conductive layer, and the second source / drain conductive layer are sequentially disposed along a direction away from the substrate. The display panel further includes a gate insulating layer, a first planarization layer, and a second planarization layer. The gate insulating layer is disposed between the gate layer and the first source / drain conductive layer. The first planarization layer is disposed between the first source / drain conductive layer and the second source / drain conductive layer. The second planarization layer is disposed on the side of the second source / drain conductive layer away from the first source / drain conductive layer.

11. The display panel according to claim 10, characterized in that, In the stress concentration area, at least one of the gate insulating layer, the first planarization layer, and the second planarization layer includes a plurality of stress buffer sections spaced apart.

12. The display panel according to claim 11, characterized in that, In a first direction, there are multiple stress buffer portions. The greater the distance between the stress concentration portion and two adjacent curved surfaces, the smaller the width of the stress buffer portion. The first direction is the extension direction of the signal line.

13. The display panel according to claim 1, characterized in that, The width of the first signal segment is greater than the width of the second signal segment, or the first signal segment is set as a curved structure.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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