A semiconductor power module drain pin and pin short circuit test method and system

Abstract

The application relates to the technical field of semiconductor power module testing, and discloses a semiconductor power module pin leakage and pin short circuit testing method and system. The model, product identification code and pin electrical layout data of a module to be tested are acquired; a matching resistance of a clamp is measured to confirm that the clamp is in place and identify the model of the clamp, and the consistency of the clamp, the module and a testing program is checked; the pins are divided into independent pins, a same-electrode multi-pin group and a different-electrode pin pair which should be kept electrically isolated; the effectiveness of the independent pins and candidate reference pins is detected by using a switch probe, and the reference pins confirmed to be effective are used to conduct full-coverage conduction detection on the remaining pins in the same group; the resistance of the different-electrode pin pair is measured to distinguish direct short circuit, abnormal insulation and normal insulation state; abnormal items are retested, and test data is stored in association. The application can improve the coverage, reliability and traceability of pin leakage and abnormal connection detection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power module production and testing technology, specifically to a method and system for testing leaked pins and short circuits in semiconductor power modules. Background Technology

[0002] Semiconductor power modules typically have multiple pins on a direct copper-clad ceramic (DBC), active metal brazing (AMB), or other insulating substrates for leading out gate, emitter, temperature sensing, and other control signals. During pin assembly and soldering, errors in material loading, positioning, soldering, and operation can lead to issues such as missing pins, insufficient pin height, poor contact, solder bridging between different electrode pins, metal foreign object connections, or insulation abnormalities. Especially when multiple pins are connected in parallel on the same electrode, the missing pin can still maintain electrical connection through other pins, making it difficult to detect through overall module electrical performance testing.

[0003] Currently, production mainly employs manual visual inspection or automated optical inspection. Manual inspection is affected by personnel experience, visual fatigue, lighting, and observation angle, resulting in low inspection efficiency and consistency. It can typically only identify visible pin omissions or obvious bridging. While automated optical inspection can improve automation, it has higher equipment and maintenance costs and is easily affected by obstructions, reflections, and changes in image templates. It is also difficult to directly identify hidden short circuits, high-resistance short circuits, and degraded insulation performance located at the pin roots or between conductive areas of the substrate.

[0004] Existing technologies also disclose solutions for detecting missing pins in power modules using probe fixtures. These solutions form a detection loop using probes corresponding to the power module pins and determine whether a pin is missing based on whether the loop is conductive. However, when multiple pins of the same electrode are connected in parallel, even if one pin is missing, the detection loop may still be maintained by the other pins. Therefore, it is difficult to achieve one-by-one, full-coverage detection of each pin within the same electrode group, and it is also difficult to distinguish between missing reference pins, missing ordinary pins, and abnormal probe contact.

[0005] In the field of integrated circuit testing, there are also open / short circuit testing techniques for pin-to-pin, pin-to-all pins, or all pins to a single pin, as well as techniques that use dual-contact or Kelvin probes to improve resistance measurement accuracy or confirm contact status. However, the aforementioned techniques are generally used to determine the electrical status of the pins of packaged devices, and do not form a linkage mechanism for power modules with multiple parallel pins on the same electrode to first confirm the existence of candidate reference pins, and then use the confirmed valid reference pin to perform full-coverage testing on the remaining pins in the group. When a reference pin is missing, existing reference-based testing may also incorrectly interpret the simultaneous failure of multiple test paths as the absence of multiple non-reference pins.

[0006] Furthermore, different power module models have different pin counts, electrode groups, probe arrangements, and test procedures. Simply identifying the fixture model cannot guarantee that the fixture is properly clamped in place, or that the fixture model, the module under test (DUT) model, and the current test procedure are compatible. Incorrect fixtures, incorrect procedures, or incomplete clamping can all lead to misjudgments or missed detections. Existing single continuity thresholds are also insufficient to distinguish between direct metal short circuits, high-resistance short circuits, and insulation degradation. Moreover, some systems only output pass or fail results, lacking the original measurement values ​​for each test channel and traceability information corresponding to the product identification code.

[0007] Therefore, a test method and system are needed that can establish the expected conduction relationship within the group and the expected isolation relationship between different electrodes based on the electrical layout of the power module pins, first verify the validity of the candidate reference pins, then perform full coverage testing of the multi-pin group with the same electrode, and complete the consistency verification of fixture placement, fixture identity, module model and test program before formal testing, so as to simultaneously detect missing pins, direct short circuits between different electrode pins and insulation abnormalities. Summary of the Invention

[0008] The purpose of this invention is to provide a method and system for testing leaked pins and short circuits in semiconductor power modules, in order to solve the problems that it is difficult to detect hidden electrical abnormalities by manual or optical inspection, that ordinary conductive fixtures cannot cover multiple pins of the same electrode for individual testing, and that incorrect fixtures, incorrect programs, or improper fixture positioning may cause misjudgments.

[0009] To achieve the above objectives, this invention provides a testing method executed by a test fixture, a multi-channel resistance tester, a channel switching module, a control computer, a product identification acquisition device, a test status indication device, and a data storage module. The method includes the following steps: S1. Obtain Product Information: Read the module model, product identification code, and version information of the semiconductor power module under test, and retrieve the pin electrical layout data, test channel mapping table, and test threshold configuration corresponding to the module model; the product identification code can be obtained through QR code, barcode, RFID, or manual input.

[0010] S2. Fixture positioning and identification: The test fixture is brought to the preset clamping position so that the fixture positioning contact is closed; during the identification phase, the isolating switch is closed so that the matching resistor identification branch forms a measurement circuit. The matching resistor is measured by a multi-channel resistance tester, and the test fixture model is identified based on whether the measured resistance value falls into the preset identification window.

[0011] S3. Consistency Interlock: The identified test fixture model is checked for consistency with the model of the module under test, the test program number, and the test program version. If any of the correspondences are inconsistent, the control computer will prevent the start of the formal pin test and output a fixture error, program error, or module model error message.

[0012] S4. Establish test relationships: Based on the pin electrical layout data, divide the pins into independent pins, multi-pin groups with the same electrode, and pairs of opposite electrode pins that should be electrically isolated, and establish the conduction test relationship within the group, the expected isolation test relationship between opposite electrodes, and the mapping relationship between the test channel and each probe.

[0013] S5. Independent Pin Missing Detection: Select the switch probe corresponding to the independent pin and measure the resistance Rfs between the force end and sense end of the switch probe; when Rfs meets the pin existence determination condition, the pin is determined to exist; when Rfs does not meet the determination condition, proceed to contact abnormality investigation or pin missing retest.

[0014] S6. Detection of multiple pin groups with the same electrode: First, confirm the physical existence of the candidate reference pin; when the candidate reference pin is valid, measure the continuity between it and each non-reference pin in the same group based on the pin; when the candidate reference pin is invalid, perform a self-test on the backup reference pin, and continue the detection within the group after the backup reference pin is valid; a ring, tree or star topology with redundant edges can also be used to determine the abnormal pin based on the combination of failed paths and the results of node validity detection.

[0015] S7. Detection of abnormal connection between opposite electrodes: After completing the fixture identification, disconnect the isolating switch to allow the matching resistor identification branch to exit the measurement circuit; select the corresponding pin pair according to the expected isolation relationship of the opposite electrodes, measure the resistance between the pin pairs, and classify the results into direct short circuit, insulation abnormality and normal insulation according to the direct short circuit threshold R2 and the insulation abnormality upper limit R3.

[0016] S8. Abnormal Retesting and Classification: When any test item is initially determined to be abnormal, repeated measurements are performed according to a preset number of times N. Based on the consistency, dispersion, fixture status, standard sample status, and measurement status of other modules under test in the same channel, the abnormality is classified as product abnormality, contact abnormality, or fixture, probe, and test equipment abnormality.

[0017] S9. Result Output and Traceability: Outputs the specific abnormal pin or pin pair, the abnormality category and the final judgment result, and stores the module model, product identification code, fixture number, test program number and version, test channel, original measurement value, threshold, initial test and retest results and test time in association.

[0018] The present invention also provides a testing system for performing the above-described method. The testing system includes a test fixture, a multi-channel resistance tester, a channel switching module, a control computer, a product identification acquisition device, a data storage module, and a test status indication device.

[0019] The test fixture is used to position and clamp the power module under test (DUT) and ensure that each probe makes corresponding contact with the module pins. The test fixture includes a base, a module positioning seat mounted on the base, a replaceable probe plate, a clamping mechanism, a guiding mechanism, a switch probe assembly, a standard probe assembly, connection terminals, a matching resistor identification branch, and a disconnect switch. The module positioning seat surrounds the probe plate and has positioning surfaces, slots, or posts that mate with the shape of the DUT, ensuring that each pin of the DUT is aligned with its corresponding probe when it is supported and positioned.

[0020] The switch probe assembly corresponds to the independent pin or candidate reference pin that requires physical presence confirmation, and includes the probe body, force terminal, sense terminal, and switch contact controlled by the pin push-in action; the ordinary probe assembly corresponds to other pin positions respectively. For opposite electrode pin pairs, dedicated paired probes are not used; instead, the channel switching module selects two probes at corresponding pin positions to form a measurement channel.

[0021] The matching resistor identification branch is set on the test fixture. When the fixture is not in position, the fixture position contact is open, and the matching resistor cannot be measured. After the fixture is in position, the fixture position contact is closed, and the isolating switch is closed during the identification stage, so that the matching resistor is connected to the measurement channel. After the identification is completed, the control computer controls the isolating switch to open, so that the matching resistor identification branch is isolated from the formal pin test channel, so as to avoid the matching resistor affecting the independent pin conduction judgment or the high resistance measurement of different electrodes.

[0022] For independent pins, when the pin is not present at the test location, the pin height is insufficient, or the clamp has not reached the preset position, the force and sense terminals of the switch probe remain disconnected. When the clamp is in position and the pin reaches the preset push-in stroke, the pin drives the switch contacts to close, forming a conductive loop between the force and sense terminals. The control computer determines the presence of the pin based on the measured resistance between the two terminals.

[0023] In one embodiment, the first conduction threshold R1 is set to 100Ω. When Rfs ≤ 100Ω, it is determined that the corresponding pin exists and the probe contact meets the detection conditions; when Rfs > 100Ω or is in an over-range open circuit state, it is initially determined that the pin is missing, the pin height is insufficient, or the probe contact is abnormal. R1 can also be selected in the range of 10Ω to 100Ω according to the distribution of probe contact resistance, wire resistance, and channel switch conduction resistance.

[0024] To avoid misjudging a misplaced fixture as a missing pin, the system first performs a matching resistor placement detection before performing pin detection. To avoid directly judging occasional poor contact as product defects, the system can maintain the clamped state and repeat sampling when an anomaly occurs for the first time, or loosen the fixture, reposition the module, and clamp it again before measuring.

[0025] When a single electrode has multiple pins, simply measuring the overall conductivity of the electrode cannot guarantee that every pin is installed. This invention divides multiple pins belonging to the same electrode into multi-pin groups, ensuring that each pin within a group participates in at least one test path that verifies its physical presence.

[0026] In the reference-based detection implementation, a candidate reference pin is selected from a group of multiple pins with the same electrode, and its physical existence is first confirmed using the force and sense terminals of its corresponding switch probe. When the candidate reference pin is valid, the resistance between the candidate reference pin and each non-reference pin in the group is measured sequentially; for a group containing m pins, all non-reference pins can be covered using m-1 continuity test paths within the group.

[0027] When a candidate reference pin fails the self-test, the system does not directly interpret the failure of all tests within the group as multiple non-reference pins being missing. Instead, it marks the candidate reference pin as abnormal and verifies the validity of the backup reference pin. If the backup reference pin is valid, it continues to test other pins using the backup reference pin. When multiple candidate reference pins are invalid, the system outputs multiple pin abnormalities, fixture misalignment, or group contact abnormalities based on the results of the fixture positioning channel and other electrode groups.

[0028] As an alternative to or supplement to benchmark testing, ring topology, tree topology, or star topology with at least one redundant edge can be used. In ring topology, the absence of a single pin usually causes the two adjacent test paths to fail simultaneously; tree topology is used to identify anomalous branches, and redundant star topology uses additional test edges to identify benchmark failures. For tree topology, the specific missing pin should be determined by combining node self-test results or additional redundant paths.

[0029] The control computer saves the candidate reference order, test topology, and failure mode mapping table for each multi-pin group with the same electrode, and determines the abnormal pin or abnormal branch based on the measured failure channel combination. The test relationship can be pre-configured in the test program or generated according to the number of pins, electrode attributes, and spatial location.

[0030] The control computer determines the expected isolation relationship between dissimilar electrodes based on the electrical layout data of the module under test. The pin pair under test can include all different electrode combinations, or preferentially include different electrode pin pairs located in the same soldering area, spatially adjacent, with pad spacing less than a preset distance, or with solder bridging paths.

[0031] In a non-limiting embodiment, the direct short-circuit threshold R2 is set to 1kΩ, and the upper limit for insulation abnormality R3 is set to 10MΩ. When R≤1kΩ, it is determined to be a direct short circuit or low-resistance bridging; when 1kΩ<R≤10MΩ, it is determined to be a high-resistance short circuit or insulation abnormality; and when R>10MΩ, it is determined to be normal insulation. R2 and R3 can also be adjusted according to the module structure, test voltage, environmental conditions, and the resistance distribution of normal and defective samples.

[0032] For modules whose internal circuitry creates natural resistance, semiconductor junctions, or other electrical connections between certain opposite electrode pins, instead of using a uniform threshold, independent expected resistance windows, test polarities, test ranges, and anomaly categories are set for different pin pairs based on the module's circuit structure, measurement polarity, test voltage, and normal sample reference values.

[0033] To reduce the impact of humidity, contamination, and measurement time on high-resistance measurements, after selecting the opposite electrode pin pair, wait for a preset stabilization time before performing one or more samplings, and use the average value, median value, or consistent value for judgment. The test voltage and test time should be lower than the allowable conditions of the internal components of the module to avoid damage to the module under test.

[0034] The matching resistor identification branch is formed by connecting the clamp positioning contact, the disconnecting switch, and the matching resistor in series. When the clamp is not in position, the clamp positioning contact is open; when the clamp is in position and the identification stage begins, both the clamp positioning contact and the disconnecting switch are closed, and the multi-channel resistance tester measures the matching resistor; after identification is completed, the disconnecting switch is opened, and the matching resistor is removed from the formal test circuit.

[0035] Different fixture models have non-overlapping matching resistor identification windows. For example, fixtures JG-01, JG-02, and JG-03 can be set with matching resistors of 1.0kΩ, 2.2kΩ, and 4.7kΩ respectively, using identification windows that are ±5% of the nominal value. The control computer saves a binding table of "Identification Window - Fixture Model - Adaptor Module Model - Test Program Number and Version"; if the measured resistance value falls outside all windows, or if the three are mismatched, the formal test is prohibited from starting.

[0036] The isolating switch can be implemented using a relay, analog switch, or multiplexer. During the identification phase, the channel switching module selects the matching resistor identification branch; after identification is completed, the control computer first disconnects the isolating switch and then selects the formal pin test channel, thereby avoiding the matching resistor and pin test circuit being connected in parallel during switching.

[0037] Through the above interlocking process, it can be confirmed that the fixture is in place, the fixture is correct, the module model is correct, and the test program is compatible before the formal test, thereby reducing misjudgments, missed inspections, and false passes caused by incorrect fixtures, incorrect programs, or fixtures not being tightened.

[0038] To monitor the accuracy of the testing system, a standard normal sample and at least one defective sample from the following categories are configured: standard missing sample, standard short-circuit sample, and standard insulation abnormal sample. The standard normal sample has complete pins and no abnormal connections between opposite electrodes; the standard missing sample is missing a pin at a preset pin position; the standard short-circuit sample forms a defined low-resistance connection between preset opposite electrode pin pairs; and the standard insulation abnormal sample forms a defined high-resistance connection between preset pin pairs.

[0039] The control computer executes standard sample tests when the equipment is powered on, shifts change, fixtures are changed, programs are switched, a preset number of tests is reached, or the operator actively triggers the test. Testing of the module under test is only permitted if the measured results of the standard normal sample and at least one defective sample are consistent with the expected results; otherwise, the equipment is locked, and a prompt is given to check the probes, fixture wiring, channel switching module, and resistance tester.

[0040] The control computer can also record the long-term measurement trends of each channel of the standard sample. When the resistance of a certain channel does not exceed the qualified threshold but continues to approach the control limit or drifts significantly, it will provide an early warning of probe wear, contamination, or increased circuit contact resistance.

[0041] When a certain test item is initially determined to be abnormal, the control computer performs a retest according to a preset number N. In one embodiment, N is 3, and the original value of each measurement is saved. The retest can be performed by repeatedly selecting channels and sampling while the fixture is kept clamped, or it can include measurements after reclamping.

[0042] If multiple measurements in the same channel remain consistently within the abnormal range, and the standard sample and other modules under test are normal in that channel, the product is deemed abnormal. If the measured value fluctuates between the normal and abnormal ranges, it is deemed a contact abnormality and the device is re-clamped. If a preset number of consecutive modules under test or standard samples all show abnormalities in the same channel, the fixture, probe, or testing equipment is deemed abnormal and the equipment is locked.

[0043] The final retest rule can adopt a continuous consistency rule, a majority voting rule, or a dispersion rule. In one embodiment, a product is deemed abnormal when all three measurements fall within the same abnormal range; a contact abnormality is determined when the difference between any two measurements exceeds a preset fluctuation threshold. To avoid defective products being mistakenly released due to a single instance of normal contact, the rule of "passing any retest constitutes acceptance" is not adopted.

[0044] The control computer associates and saves the test data with the product identification code. The saved content includes module model, BOM information, production batch, product identification code, fixture model and number, fixture identification resistance value, test program number and version, channel number, tested pin or pin pair, electrode group, expected state, measured value, judgment threshold, initial test result, number of retests, value of each retest, anomaly category, final result, and test time.

[0045] When quality problems occur, the fixtures, programs, and original measurement values ​​of each channel used during testing can be queried according to the product identification code; statistics can also be performed according to the same fixture, the same channel, or the same batch to identify trends of probe wear, fixture offset, and abnormal processes.

[0046] By adopting the above technical solution, the present invention has the following beneficial effects: 1. The test procedure can simultaneously detect missing independent pins, missing multiple pins on the same electrode, direct short circuits between different electrodes, and insulation abnormalities. 2. By first confirming the validity of the candidate reference pin, and then performing full coverage testing within the same electrode group, the risk of misjudgment of the entire group due to the missing reference pin itself is reduced. 3. By using a backup reference or redundant topology, each pin in a multi-pin group with the same electrode has a verifiable test path, and abnormal pins or abnormal branches can be located based on the combination of failed channels and the results of node self-test. 4. By establishing the intra-group conduction relationship and the expected isolation relationship of opposite electrodes based on the electrical layout, the test object corresponds to the module electrode attributes and spatial bridging risk; 5. By setting direct short-circuit thresholds and insulation fault limits, different levels of abnormal connections can be classified, instead of just outputting general continuity results; 6. The matching resistor, fixture positioning contact and disconnect switch are used to achieve consistency interlocking of fixture positioning, fixture identity, module model and test program, and to prevent the matching resistor from affecting the formal test; 7. Improve the ability to distinguish between product abnormalities, contact abnormalities, and test equipment abnormalities by monitoring standard samples, retesting abnormalities, and classifying abnormality sources; 8. By using replaceable probe boards or complete test fixtures and corresponding test programs, different models of power modules can be adapted to reduce the cost of switching models; 9. By saving the original measurement values, test conditions, and retest records and associating them with the product identification code, quality traceability and equipment status analysis can be achieved. Attached Figure Description

[0047] Figure 1 This is a block diagram of the overall structure of the test system of the present invention.

[0048] Figure 2 This is a schematic diagram of the test fixture structure of the present invention.

[0049] Figure 3 This is a schematic diagram of the switch probe and independent pin detection status of the present invention.

[0050] Figure 4 This is a circuit diagram for the fixture matching resistor identification and isolation of the present invention.

[0051] Figure 5 This is a schematic diagram of the pin electrode grouping and testing relationship of the present invention.

[0052] Figure 6 This is a schematic diagram of the reference full-coverage detection of the same electrode multi-pin group according to the present invention.

[0053] Figure 7 This is a schematic diagram of the redundant detection topology of the same electrode multi-pin group of the present invention.

[0054] Figure 8 This is a schematic diagram of the graded detection of short circuits and insulation abnormalities of the opposite electrode pins in this invention.

[0055] Figure 9 This is a flowchart illustrating the consistency interlocking process of the fixture, module, and test program of this invention.

[0056] Figure 10 This is a flowchart of the overall testing method of the present invention.

[0057] Figure 11 This is a flowchart of the abnormal retesting and abnormal source classification process of the present invention.

[0058] Figure 12 This is a flowchart of the standard sample monitoring and equipment locking process of this invention.

[0059] Figure 13 This is a traceability diagram of the test data for this invention.

[0060] Reference numerals: Test system 10; Test fixture 20; Base 21; Module positioning seat 22; Probe plate 23; Clamping mechanism 24; Guide mechanism 25; Connection terminal 26; Matching resistor identification branch 28; Disconnecting switch 29; Switch probe assembly 30; Force terminal 31; Sense terminal 32; Probe body 33; Fixture positioning contact 34; Ordinary probe assembly 40; Multi-channel resistance tester 50; Channel switching module 51; Control computer 60; Data storage module 65; Display module 66; Product identification acquisition device 70; Test status indicator device 80; Power under test module 100; Pin 101. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0063] In this invention, "connection" can be a direct electrical connection or an indirect electrical connection formed through a channel switching module, relay, analog switch, connector, or wire; "conduction" and "open circuit" should be understood in conjunction with a preset resistance threshold, and are not limited to ideal zero resistance and infinite resistance. The "pin" used in the accompanying drawings has the same meaning as "pin" as referred to herein.

[0064] Example 1: Overall Structure of the Test System like Figure 1 As shown, the testing system 10 includes a test fixture 20, a multi-channel resistance tester 50, a channel switching module 51, a control computer 60, a data storage module 65, a product identification acquisition device 70, and a test status indicator device 80. The display module 66 is the software display interface in the control computer 60, used to display channel measurement values, abnormal pins, and retest results; the test status indicator device 80 is an external audio-visual indicator device at the workstation, used to display the status of preparation, testing, pass, fail, fixture error, and equipment malfunction.

[0065] like Figure 2 As shown, the test fixture 20 includes a base 21, a module positioning seat 22, a probe plate 23, a clamping mechanism 24, a guiding mechanism 25, a connection terminal 26, a matching resistor identification branch 28, a switch probe assembly 30, and a general probe assembly 40. The module positioning seat 22 surrounds the probe plate 23 and supports and restricts the power module 100 under test through positioning grooves or positioning posts, so that the pins 101 are aligned with the corresponding probes; the clamping mechanism 24 clamps the module downward along the direction defined by the guiding mechanism 25.

[0066] The switch probe assembly 30 corresponds to the position of an independent pin or candidate reference pin, while the general probe assembly 40 corresponds to the position of other pins. Each probe is connected to the channel switching module 51 via the connection terminal 26. The channel switching module 51 selects two probes or selects the force terminal 31 and sense terminal 32 of the switch probe to form a corresponding measurement channel.

[0067] Example 2: Fixture Identification and Testing Interlock like Figure 4 and Figure 9As shown, the matching resistor identification branch 28 is formed by connecting the clamp positioning contact 34, the disconnecting switch 29, and the matching resistor Rm in series. When the clamping mechanism 24 has not reached the preset position, the clamp positioning contact 34 is open; after reaching the preset position, the clamp positioning contact 34 is closed. During the clamp identification stage, the control computer 60 controls the disconnecting switch 29 to close, the channel switching module 51 selects the matching resistor identification branch 28, and the multi-channel resistance tester 50 measures the matching resistor Rm.

[0068] The control computer 60 compares the measured identification resistance value Rid with the pre-stored identification window. Taking fixtures JG-01, JG-02, and JG-03 as examples, their matching resistors can be 1.0kΩ, 2.2kΩ, and 4.7kΩ, respectively, and the identification window is ±5% of the corresponding nominal value. The control computer 60 identifies the fixture model according to the window where Rid is located, and matches the fixture model with the module model, test program number, and version read by the product identification acquisition device 70; if the matching fails, the test is locked and an alarm is triggered.

[0069] After identification is completed, the control computer 60 first controls the isolating switch 29 to disconnect the matching resistor identification branch 28, and then switches the channel switching module 51 to the formal pin test state. Therefore, the matching resistor Rm does not participate in the subsequent independent pin continuity test and the high resistance test of the opposite electrode.

[0070] Example 3: Test Relationship Configuration and Overall Process Based on Electrical Layout like Figure 5 As shown, the control computer 60 calls the electrical layout data or test configuration file corresponding to the module model. The test configuration file includes pin number, electrode, probe corresponding channel, same electrode group number, candidate reference order, pin pairs that should be connected within the group, expected isolation pin pairs for different electrodes, test range, and judgment threshold. Taking the pin set P={P1, P2, ..., Pn} as an example, it is divided into independent pin sets S and multiple pin groups G1~Gq of the same electrode according to the electrode attributes, and the expected isolation relationship for different electrodes F is established.

[0071] like Figure 10 As shown, the test method sequentially performs the following steps: product information acquisition, matching resistance measurement, consistency verification of fixtures, modules and test programs, test relationship generation, independent pin detection, multi-pin group detection of the same electrode, short circuit and insulation abnormality detection of different electrodes, abnormal retest classification and test data storage.

[0072] Example 4: Detection of Missing Independent Pins like Figure 3As shown, the switch probe assembly 30 includes a probe body 33, a force terminal 31, a sense terminal 32, and a clamp positioning contact 34. After the clamp interlock passes, the multi-channel resistance tester 50 measures the resistance Rfs between the force terminal 31 and the sense terminal 32. When pin 101 is missing or has not reached the trigger stroke, the contact is open, and Rfs is greater than R1 or is an open circuit; when pin 101 is present and the trigger stroke is reached, the contact is closed, and Rfs is not greater than R1.

[0073] In this embodiment, R1 is 100Ω, and the median value of Rfs is collected three times consecutively. If all three measurements are greater than R1, it is initially determined that the corresponding pin is missing; if the three measurements fluctuate on both sides of R1, it is determined that the contact is unstable and the pin is re-clamped.

[0074] Example 5: Multi-pin group detection and reference switching with the same electrode like Figure 6 As shown, taking the multi-pin group G1={P2, P3, P4} with the same electrode as an example, P2 is the first candidate reference pin, and P3 is the backup reference pin. First, confirm the existence of P2 by checking the force and sense terminals of the corresponding switch probe. When P2 is valid, measure P2-P3 and P2-P4 respectively; if P2-P3 is not conducting but P2-P4 is conducting, the P3 fault is initially located; if P2-P3 is conducting but P2-P4 is not conducting, the P4 fault is initially located.

[0075] When P2 fails the self-test, the system marks P2 as abnormal and performs a force / sense self-test on P3; when P3 is valid, P3-P4 is measured using P3 as a backup baseline. This process avoids the misinterpretation that the simultaneous failure of P2-P3 and P2-P4 due to the absence of P2 is a simultaneous absence of P3 and P4.

[0076] like Figure 7 As shown, multi-pin groups with the same electrode can also adopt ring, tree, or redundant star topologies. The ring topology locates the abnormal pin based on the intersection of two adjacent failure paths; the tree topology determines the abnormal branch based on the failure path and combines it with node self-test to determine the specific pin; the redundant star topology identifies the failure of the reference pin by adding test edges.

[0077] Example 6: Graded Detection of Abnormal Connections Between Different Electrodes like Figure 8 As shown, after completing the pin missing detection, the control computer 60 selects the corresponding pin pair according to the expected isolation relationship of the opposite electrodes. Using R2 as the direct short-circuit threshold and R3 as the upper limit of insulation abnormality: when R≤R2, the output is "direct short circuit"; when R2<R≤R3, the output is "insulation abnormality"; and when R>R3, the output is "normal insulation". In one embodiment, R2 is 1kΩ and R3 is 10MΩ.

[0078] For pin pairs with internal semiconductor junctions or normal finite resistance values, the test configuration file stores their test polarity, test range, and expected resistance window, respectively. After channel selection, a preset settling time is waited before multiple samplings are performed to reduce the impact of humidity, contamination, and switching transients on high-resistance measurements.

[0079] Example 7: Anomaly Retesting and Anomaly Source Classification like Figure 11 As shown, if the initial test of a certain channel fails, three repeated measurements are performed. If the measured value fluctuates between the normal range and the abnormal range, it is determined to be a contact abnormality, and the device is re-clamped and returned for retesting. If the measured value is stable in the abnormal range after multiple measurements, further checks are made to whether the standard sample and other modules under test are normal in the same channel.

[0080] When the standard sample and other modules under test are normal in the same channel, it is determined that the current module has missing pins, short circuits, or insulation abnormalities. When the standard sample or a preset number of consecutive modules under test all show abnormalities in the same channel, it is determined that the fixture, probe, or test equipment is abnormal, the equipment is locked, and a check is prompted.

[0081] Example 8: Standard Sample Monitoring like Figure 12 As shown, when the equipment is started, shifts are changed, fixtures are changed, programs are switched, or the preset number of tests is reached, standard normal samples and at least one standard defective sample are tested sequentially. The standard defective sample can be a standard missing sample, a standard short-circuit sample, or a standard insulation abnormality sample.

[0082] The module under test is allowed to be tested only if all measured results are consistent with the expected results; if a standard normal sample is judged to be unqualified, or if a standard defective sample is not identified in the designated channel, the control computer 60 outputs a verification failure, prompts to check the probe, fixture, channel switching module 51 and multi-channel resistance tester 50, and locks the equipment.

[0083] Example 9: Test Data Traceability and Alternative Implementation Methods like Figure 13 As shown, the data storage module 65 establishes a test record for each product identification code, and saves the product and fixture information, program and test configuration, original measurement values ​​of each channel, retest values, anomaly categories and final judgments in association; the display module 66 is used to query and display test records according to the product identification code.

[0084] The fixture identification element can also be a capacitor, an coded switch or a memory chip, but the interlocking relationship between fixture identification, fixture positioning confirmation and test procedure consistency should be maintained; the channel switching module 51 can be composed of a relay matrix, an analog switch matrix or a multiplexer; abnormal connection of opposite electrodes can also be determined by applying a test voltage and measuring leakage current, insulation resistance or equivalent conductance.

[0085] This invention is applicable to semiconductor power module production lines that use DBC, AMB or other substrates and have multiple lead-out pins. It can detect missing pins, direct short circuits between different electrodes and insulation abnormalities after pin soldering or module assembly. By changing the test fixture or probe board and calling the corresponding test program, it can be adapted to different module models.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Equivalent substitutions or conventional modifications made by those skilled in the art without departing from the technical concept of the present invention should all be included within the scope of protection of the present invention.

Claims

1. A method for testing leaking pins and short circuits in semiconductor power modules, characterized in that, include: S1. Obtain the module model, product identification code, and pin electrical layout data of the semiconductor power module under test; S2. Make the test fixture reach the preset clamping position so that the fixture positioning contact closes and the matching resistor identification branch forms a measurement circuit; measure the resistance value of the matching resistor identification branch, and determine whether the test fixture is in place and the test fixture model is determined based on whether the measured resistance value falls into the preset identification window. S3. Verify the consistency between the test fixture model and the module model, as well as the number and version of the test program to be called. If the verification is inconsistent, prohibit the start of formal testing. S4. Based on the pin electrical layout data, divide the pins into independent pins, multi-pin groups with the same electrode, and opposite electrode pin pairs that should be electrically isolated, and establish a mapping relationship between the test channel and each pin or pin pair. S5. For the independent pin, measure the resistance or conduction state between the force terminal and the sense terminal of the switch probe corresponding to the independent pin to determine whether the independent pin exists. S6. For the multi-pin group with the same electrode, first confirm the validity of the candidate reference pin by using the force and sense terminals of the corresponding switch probes of the candidate reference pin; when the candidate reference pin is valid, make the candidate reference pin form an intra-group continuity test path with each non-reference pin in the same group; when the candidate reference pin is invalid, confirm the validity of the backup reference pin, and when the backup reference pin is valid, perform an intra-group continuity test with it to determine the abnormal pin based on the failed combination of the test path; S7. After completing the test fixture identification, disconnect the matching resistor identification branch, select the pin test channel, measure the resistance between the opposite electrode pin pairs, and determine the measurement result as a direct short circuit, insulation abnormality or normal insulation state according to the preset threshold. S8. When any test item is initially determined to be abnormal, perform N repeated measurements. Based on the stability of the multiple measurements and the measurement status of the standard sample and other modules under test in the same channel, classify the abnormality into product abnormality, contact abnormality, or test equipment abnormality, and associate and store the fixture identification information, test channel, original measurement value, abnormality category, and final result with the product identification code.

2. The method according to claim 1, characterized in that, Different models of test fixtures are equipped with non-overlapping matching resistor identification windows; during the identification phase, the fixture positioning contact and the isolating switch are both in the closed state to measure the matching resistance. After the identification is completed, the isolating switch is disconnected to electrically isolate the matching resistor identification branch from the formal pin test channel.

3. The method according to claim 1, characterized in that, The switch probe includes a probe body, a force terminal, a sense terminal, and a switch contact controlled by the pin push-in action; when the resistance Rfs between the force terminal and the sense terminal is not greater than the first conduction threshold R1, it is determined that the corresponding pin exists; when Rfs is greater than R1 or is in an open circuit state, it enters the pin missing or contact abnormality retest.

4. The method according to claim 1, characterized in that, For a multi-pin group with m pins on the same electrode, a valid reference pin is used to form m-1 in-group continuity test paths with m-1 non-reference pins, so that each non-reference pin has a dedicated test path to verify its existence.

5. The method according to claim 1, characterized in that, The multi-pin group with the same electrode also adopts a ring topology, tree topology, or star topology with redundant edges. Abnormal pins or abnormal branches are determined based on the failed combinations of test paths, and the location of missing pins is determined in combination with the node validity detection results.

6. The method according to claim 1, characterized in that, The different electrode pin pairs are determined based on the electrode properties and spatial adjacency of the pins, and include at least different electrode pin pairs located in the same soldering area, with a pad spacing less than a preset distance, or with a solder bridging path.

7. The method according to claim 1, characterized in that, Set a direct short circuit threshold R2 and an insulation abnormality upper limit R3; when the measured resistance R≤R2, it is determined to be a direct short circuit; when R2<R≤R3, it is determined to be an insulation abnormality; when R>R3, it is determined to be normal insulation. For opposite electrode pin pairs that have normal finite resistance due to internal semiconductor junctions or internal circuits of the module, set the desired resistance window, test polarity, test range, and stabilization waiting time corresponding to the pin pair.

8. The method according to claim 1, characterized in that, When the equipment is powered on, shifts are changed, fixtures are changed, test programs are switched, or the preset number of tests is reached, at least one defective sample among the standard normal sample, standard missing sample, standard short-circuit sample, and standard insulation abnormal sample shall be used for verification; when the actual test results are inconsistent with the expected results, the test module shall not be tested.

9. The method according to claim 1, characterized in that, The N repeated measurements include repeated sampling while keeping the fixture in a clamped state and / or repeated measurements after re-clamping; when multiple measurement values ​​are stable in the abnormal range, it is determined that the product is abnormal; when the measurement value fluctuates between the normal range and the abnormal range, it is determined that the contact is abnormal; when a preset number of consecutive test modules or standard samples all show abnormalities in the same channel, it is determined that the fixture, probe or test equipment is abnormal.

10. A test system for missing pins, short circuits, and insulation abnormalities in semiconductor power modules, characterized in that, The system includes a test fixture, a multi-channel resistance tester, a channel switching module, a control computer, a data storage module, and a product identification acquisition device. The test fixture includes a module positioning base, a probe board, a switch probe assembly, a general probe assembly, a matching resistor identification branch, and an isolating switch disposed in the matching resistor identification branch. The channel switching module is used to select the matching resistor identification branch, the force terminal and sense terminal of the switch probe assembly, and the measurement channel formed by any two ordinary probes or switch probes; the control computer is used to perform fixture positioning and identification, consistency verification of fixture model and module model and test program, validity detection of candidate reference pins, continuity test within the same electrode group, graded detection of different electrode pin pairs and abnormal retest classification, and controls the disconnecting switch to open after completing fixture identification; The data storage module establishes test records according to the product identification code. The test records include at least the module model, fixture number, fixture identification resistance value, test program number and version, test channel, tested pin or pin pair, original measurement value, retest value, anomaly category, final result and test time.

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