Methods of forming recessed terminals and electronic devices including recessed terminals

Abstract

Embodiments of the present disclosure relate to methods of forming recessed terminals and electronic devices including recessed terminals. An electronic device includes a body of semiconductor material, the semiconductor material including silicon, the body including a source region and a body region; a trench in the body, the trench having a sidewall along the source region and a bottom wall along the body region; a first silicide region in direct contact with the source region; and a second silicide region in direct contact with the body region. A first thickness of the first silicide region is different than a second thickness of the second silicide region.

Description

Technical Field

[0001] This disclosure relates to a method of forming electrical contacts for an electronic device, and to the electronic device itself. Background Technology

[0002] Insulated gate bipolar transistors (IGBTs) and other discrete power devices typically use trench-based designs to reduce the cell size in the device portion that houses the body and source regions.

[0003] Chemical vapor deposition (CVD) can be used to deposit metal barrier layers of equal thickness on the bottom surface and sidewalls of trenches. However, even when using CVD to form metal barrier layers, increasing the thickness of the metal barrier layer on the sidewalls leads to an increase in the thickness of the metal barrier layer on the bottom surface of the trench. Furthermore, CVD processes are typically not used for metal layer deposition in the fabrication of discrete devices, resulting in increased manufacturing costs.

[0004] For the reasons mentioned above, there is a need to provide an alternative for the fabrication of silicide regions that produces a lateral portion of the silicide region that is thicker than the bottom portion of the silicide region, while minimizing the mechanical stress between the semiconductor substrate and the metal barrier layer.

[0005] Generally, a manufacturing process is required that allows the fabrication of devices in which the lateral portions of the silicide region have a different thickness than the corresponding bottom portion of the silicide region (and can be adjusted according to the design). Summary of the Invention

[0006] According to this disclosure, a method for forming electrical contacts of an electronic device and an electronic device are provided.

[0007] A method of forming an electrical contact for an electronic device, the method comprising: forming a body comprising a semiconductor material comprising silicon, the body comprising: a first region having a first conductivity and a second region having a second conductivity opposite to the first conductivity and extending over the first region; forming a trench in the body that completely penetrates the second region and reaches the first region, the trench having sidewalls exposing the second region and a bottom wall exposing the first region; forming a first metal layer in direct contact with the second region on the sidewalls of the trench, the first metal layer including a first surface directly on the bottom wall; forming a gap in the first metal layer exposing a first portion of the bottom wall; forming a second metal layer in contact with the first region at the first portion of the bottom wall, the second metal layer having a first surface directly on the bottom wall of the trench, the first surface being coplanar with the first surface of the first metal layer; and forming a first silicide region at the interface between the second region and the first metal layer by one or more heat treatments, and forming a second silicide region at the interface between the first region and the second metal layer.

[0008] The first thickness of the first silicide region is different from the second thickness of the second silicide region. The first thickness of the first silicide region is greater than the second thickness of the second silicide region.

[0009] Forming the first silicide region includes performing a first heat treatment at a first temperature, and forming the second silicide region includes performing a second heat treatment at a second temperature lower than the first temperature. The first temperature is in the range of 600°C to 900°C, and the second temperature is in the range of 450°C to 800°C.

[0010] The first metal layer has a first thickness, and the second metal layer has a second thickness lower than the first thickness, and forming the first silicide region and the second silicide region includes performing contextual heat treatment.

[0011] The first metal layer is made of a first metal material, and the second metal layer is made of a second metal material, wherein in the solid semiconductor material, the first metal material and the second metal material have corresponding diffusion coefficients such that the diffusion coefficient of the first metal material is greater than the diffusion coefficient of the second metal material.

[0012] The first metal layer is made of a first metal material selected from the following: titanium (Ti), titanium silicide (TiSi), and titanium nitride (TiN), and the second metal layer is made of a second metal material selected from the following, having a thickness or composition different from the first metal material: Ti, TiSi, and TiN.

[0013] The method includes forming a buried region in a first region at the bottom wall of a trench, the buried region having a first conductivity and a doping concentration higher than that of the first region, wherein forming a second metal layer includes forming a second metal layer in contact with the first region through the buried region, and a second silicide region extending at least partially within the buried region.

[0014] The method also includes forming a dielectric layer on the second region, and forming a trench includes forming a trench that extends completely through the dielectric layer. Attached Figure Description

[0015] To better understand this disclosure, preferred embodiments thereof will now be described by way of non-limiting example only with reference to the accompanying drawings, in which: Figure 1 A portion of the IGBT device is shown in a side view; and Figures 2A to 2H A side view illustrates a portion of the manufacturing steps of an IGBT according to an embodiment of the present disclosure. Detailed Implementation

[0016] Figure 1An electronic device 1, particularly an IGBT, is partially shown, which is limited to a portion of the IGBT 1 including the gate terminals and the body and source region. Figure 1 The diagram is shown as a three-axis system with mutually orthogonal X, Y, and Z axes, and is a side sectional view of the IGBT1 in the XZ plane.

[0017] IGBT 1 includes a semiconductor substrate 2, which in turn includes a collector layer 5, a drift layer 7 extending on a first surface 5a of the collector layer 5, and a body region 4 extending on a surface 7a of the drift layer 7 opposite to the first surface 5a of the collector layer 5 along the Z-axis. A back metal contact 9 extends along the Z-axis on a second surface 5b opposite to the first surface 5a of the collector layer 5.

[0018] The semiconductor substrate 2 also includes a source region 6, which is included between recessed gate terminals 3 (i.e., gate terminals 3 are formed in trenches within the substrate 2). The gate terminals 3 include a gate dielectric layer 3a and a gate conductive layer 3b in a known manner. The source region 6 extends on the surface 4a of the body region 4.

[0019] The semiconductor substrate 2 is made of silicon, for example, and may include one or more epitaxial layers.

[0020] Body region 4 is made of P-type doped silicon with a first dopant concentration, which is included in a 1x10⁻¹⁰ kJ / m² configuration. 16 at / cm 3 With 1x10 18 at / cm 3 between.

[0021] Source region 6 is made of N-type doped silicon with a second dopant concentration, which is included in a 1x10⁻⁶ m² / 4²·cm ... 19 at / cm 3 With 1x10 20 at / cm 3 between.

[0022] For example, a dielectric layer 8 is deposited along the Z-axis on the face 6a of the source region 6 opposite to the face 4a of the bulk region 4 by chemical vapor deposition.

[0023] The dielectric layer 8 is made of doped or undoped silicon oxide (SiO2), aluminum oxide (Al2O3), or silicon nitride / silicon oxide stacks, and has a thickness of, for example, 1 µm along the Z-axis. The dielectric layer 8 has an upper surface 8a opposite the surface 6a of the source region 6 along the Z-axis.

[0024] Then, for example, by photolithography and etching techniques, a trench 10 is formed in the dielectric layer 8 at the upper surface 8a toward the semiconductor substrate 2. The trench 10 extends along the Z-axis, completely through the dielectric layer 8, completely through the source region 6, and extends within the depth of the body region 4, ending within the body region 4. The trench 10 has a depth of, for example, 0.3 µm along the Z-axis, and has an extension of, for example, 0.3 µm parallel to the XY plane at the upper surface 8a.

[0025] The trench 10 has sidewalls 11 and a bottom surface 10c. The sidewalls 11 include a first portion 10a and a second portion 10b. The first portion 10a extends toward the dielectric layer 8 and forms the interface between the trench 10 and the dielectric layer 8. The second portion 10b extends toward the source region 6 and forms the interface between the trench 10 and the source region 6. The bottom surface 10c extends toward the body region 4 and forms the interface between the trench and the body region 4.

[0026] After forming the trench 10, a body contact region 12 (buried within the body region 4) is formed by implanting ions into the body region 4 at the bottom surface 10c of the trench 10. The body contact region 12 extends a certain distance along the Z-axis from the bottom surface 10c of the trench 10 within the body region 4. The body contact region 12 is made of P-type doped silicon with a third doping concentration higher than the first doping concentration and is contained within a 1x10⁻¹⁰ kJ / g²·s⁻¹ ... 18 at / cm3 and 1x10 20 Between at / cm3.

[0027] Then, a metal barrier layer 14 is deposited in the trench 10 and on the upper surface 8a of the dielectric layer 8 by physical vapor deposition (PVD). The metal barrier layer 14 extends in physical continuity on the sidewalls 11 and bottom surface 10c of the trench 10.

[0028] The metal barrier layer 14 is a stack of different materials including a titanium (Ti) layer and a titanium nitride (TiN) layer, wherein the Ti layer is in direct physical contact with the dielectric layer 8 and the source region 6 at the sidewall 11, and in direct physical contact with the body region 4 at the bottom surface 10c of the trench 10.

[0029] In detail, the first portion 14a of the metal barrier layer 14 extends in physical contact with the body region 4 at the bottom surface 10c and has a corresponding thickness t1 along the Z-axis, which is between 5 nm and 100 nm. The second portion 14b of the metal barrier layer 14 extends in physical contact with the dielectric layer 8 and the source region 6 at the sidewall 11 and has a corresponding thickness t2 in a direction orthogonal to the sidewall 11, which is between 5 nm and 100 nm. Due to the inherent characteristics of the PVD process used to form the metal barrier layer 14, the thickness t2 is lower than the thickness t1.

[0030] After depositing the metal barrier layer 14, a silicide region 16 is formed at the interface between the metal barrier layer 4 and the semiconductor substrate 2, for example by performing a heat treatment at a temperature between 450°C and 900°C for 10 seconds and 300 seconds.

[0031] In detail, during the heat treatment, Ti ions diffuse from the metal barrier layer 14 into the source region 6 and the bulk region 4; simultaneously, Si ions diffuse in the opposite direction, particularly from the source region 6 into the metal barrier layer 14. Then, the Ti ions react with the Si ions in the source region 6 and the bulk region 4, respectively, to form the titanium silicide material of the silicide region 16.

[0032] The silicide region 16 includes a lateral portion 16a extending in the source region 6 at the second portion 10b of the sidewall 11 and a bottom portion 16b extending at the bottom surface 10c of the trench 10 in the body region 4 and in direct electrical contact with the body contact region 12.

[0033] Because the thickness t2 of the second portion 14b is less than the thickness t1 of the first portion 14a of the metal barrier layer 14, the number of titanium ions available for the Ti-Si interdiffusion process in the second portion 14a is less than the number of Ti ions available for the Ti-Si interdiffusion process in the first portion 14a. Therefore, the lateral portion 16a of the silicide region 16 is thinner than the bottom portion 16b of the silicide region 16.

[0034] Specifically, the lateral portion 16a has a corresponding thickness ts1 in a direction orthogonal to the sidewall 11, for example, between 10 nm and 200 nm; the bottom portion 16b has a thickness ts2 in a direction parallel to the Z-axis, for example, between 10 nm and 200 nm, wherein the thickness ts1 is less than the thickness ts2.

[0035] After the formation of the silicide region 16, a source metal contact 18 is formed in the trench 10 in a manner known per se, for example by a series of metal deposition and chemical mechanical polishing (CMP) steps. Specifically, the source metal contact 18 includes: a metal filler layer 20 made of tungsten (W) or copper (Cu) that extends in the trench 10 and completely fills the trench 10; and a metal contact layer 22 made of Al or Cu that extends at least partially over a metal barrier layer 14 above the upper surface 8a of the dielectric layer 8 and over the metal filler layer 20, and is in electrical contact with the metal filler layer 20.

[0036] During the operation of IGBT 1, current flows from source region 6 to source metal contact 18 through the lateral portion 16a of silicide region 16. Simultaneously, body contact region 12 is biased to the device's body voltage by source metal contact 18 through bottom portion 16b of silicide region 16.

[0037] While proper biasing of the bottom portion 16b is necessary for the body contact region 12, mechanical stress is introduced between the semiconductor substrate 2 and the metal barrier layer 14. This mechanical stress may cause cracks to form in the metal barrier layer 14, and this mechanical stress increases with the increase of the thickness ts2 of the bottom portion 16b.

[0038] To achieve a good ohmic contact between the source region 6 and the source metal contact 18, a thick lateral portion 16a of the silicide region 16 is required, particularly more than 5 nm thick. This can be achieved by increasing the thickness t2 of the second portion 14b of the metal barrier layer 14.

[0039] However, increasing the thickness t2 of the second part 14b will also increase the thickness t1 of the first part 14a.

[0040] Therefore, increasing the thickness ts1 of the lateral portion 16a leads to an increase in the thickness ts2 of the bottom portion 16b, which in turn results in higher mechanical stress between the semiconductor substrate 2 and the metal barrier layer 14.

[0041] Figures 2A to 2H The side view illustrates the manufacturing steps of an electronic device 100, particularly a portion of an IGBT, which are limited to those steps that contribute to understanding the features of this disclosure. Figures 2A to 2H The view is located in a three-axis coordinate system of mutually orthogonal axes X, Y, and Z on the XZ plane.

[0042] In the following description, reference will be made to IGBT devices without losing the generality of this disclosure, which can be applied to the manufacture of general electronic devices having one or more trench-based terminals.

[0043] refer to Figure 2A The IGBT 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may include one or more epitaxial layers.

[0044] Specifically, the semiconductor substrate 102 includes a collector layer 105, a drift layer 107 extending on a first surface 105a of the collector layer 105, and a body region 104 extending on a surface 107a of the drift layer 107, the surface 107a being opposite to the first surface 105a of the collector layer 105 along the Z-axis. A backside metal contact 109 extends on a second surface 105b of the collector layer 105, which is opposite to the first surface 105a along the Z-axis.

[0045] The semiconductor substrate 102 also includes a source region 106, which extends on a surface 104a of the body region 104 opposite to the surface 107a of the drift layer 107 along the Z-axis.

[0046] The semiconductor substrate 102 also includes first and second gate regions 103, which extend in corresponding trenches within the semiconductor substrate 102 and define a body region 104 and a source region 106. The first and second gate regions 103 have corresponding gate dielectric layers 103a and corresponding gate conductive layers 103b in a manner known per se. The portion of the IGBT 100 included between the first and second gate regions 103 is the emitter region of the IGBT 100.

[0047] The semiconductor substrate 102 is made of, for example, silicon or silicon carbide.

[0048] Body region 104 has a first conductivity, such as P-type, and the body region has a conductivity including 1x10 16 at / cm3 and 1x10 18 The first dopant concentration is between at / cm3.

[0049] Source region 106 has a second conductivity opposite to the first conductivity, for example, N-type, and the source region has a conductivity including 1x10 19 at / cm3 and 1x10 20 The second dopant concentration is between at / cm3.

[0050] The thickness of the source region 106 along the Z-axis is, for example, between 100 nm and 500 nm.

[0051] IGBT 100 also includes a dielectric layer 108 extending along the Z-axis on a surface 106a of the source region 106 opposite to the surface 104a of the body region 104.

[0052] The dielectric layer 108 is made of, for example, doped or undoped silicon oxide (SiO2), aluminum oxide (Al2O3), or silicon nitride / silicon oxide stacks, and the thickness of the dielectric layer along the Z-axis is, for example, between 0.5µm and 2µm, particularly equal to 1µm. The dielectric layer 108 has an upper surface 108a opposite to the surface 106a of the source region 106 along the Z-axis.

[0053] A trench 110 is formed in the dielectric layer 108 at the upper surface 108a, facing the semiconductor substrate 102. The trench 110 extends along the Z-axis with a major dimension, completely passing through the dielectric layer 108 and completely through the source region 106, reaching the body region 104. Figure 2A In the embodiment shown, the trench 110 extends in the body region 104 and terminates within the body region 104.

[0054] In another embodiment (not shown), the trench 110 reaches the body region 104, exposing a portion of the surface 104a of the body region 104 (i.e., without penetrating into the body region).

[0055] The groove 110 has dimensions along the Z-axis, for example, between 0.5µm and 3µm.

[0056] The trench 110 has sidewalls 111 and a bottom surface 110c. The sidewalls 111 extend with a major dimension transverse to the XY plane, thereby connecting the bottom surface 110c of the trench 110 to the upper surface 108a of the dielectric layer 108. The sidewalls 111 include a first lateral portion 110a and a second lateral portion 110b. At the first portion 110a, the surface of the dielectric layer 108 is exposed; at the second portion 110b, the surface of the source region 106 is exposed; and at the bottom surface 110c, the surface of the body region 104 is exposed.

[0057] The trench 110 is formed, for example, by photolithography and etching steps, such as by dry etching such as reactive ion etching (RIE) or deep reactive ion etching (DRIE), or alternatively, by wet etching.

[0058] refer to Figure 2B After forming the trench 110, a body contact region 112 may optionally be formed within the body region 104 (e.g., by ion implantation). In one embodiment, the body contact region 112 is a buried region that extends in the body region 104 corresponding to the bottom surface 110c of the trench 110, and is spaced along the Z-axis from the top surface 110c of the trench 110. In another embodiment (not shown), the body contact region 112 has a surface that is coplanar with or adjacent to the bottom surface 110c of the trench 110.

[0059] The body contact region 112 has a first conductivity, particularly P-type, and has a third dopant concentration that is higher than the first dopant concentration, and includes a concentration of 1x10⁻⁶. 18 at / cm3 and 1x10 20 Between at / cm3.

[0060] Then, when the body contact area 112 and the bottom surface 110c of the trench 110 are not coplanar, the bottom surface 110c of the trench 110 is etched to reach the body contact area 112. Thus, a new bottom surface 110c of the trench 110 is formed within the body contact area 112.

[0061] refer to Figure 2C A first metal layer 114 is deposited in the trench 110 and on the upper surface 108a of the dielectric layer 108 by physical vapor deposition. The first metal layer 114 extends on the sidewalls 111 and the bottom surface 110c of the trench 110 with physical and electrical continuity.

[0062] In one embodiment, the first metal layer 114 is made of titanium (Ti) or titanium nitride (TiN) or titanium silicon (TiSi) or includes Ti, TiN or TiSi.

[0063] In another embodiment, the first metal layer 114 is a stack of different metal material layers, including, for example, a Ti (or TiSi) layer and a TiN layer, wherein the Ti (or TiSi) layer is in direct physical contact with the dielectric layer 108 and the source region 106 at the sidewall 111, and in direct physical contact with the body region 104 at the bottom surface 110c of the trench 110.

[0064] In detail, a first portion 114a of the first metal layer 114 extends at the bottom surface 110c and has a corresponding thickness t1′ along the Z-axis, which is between 5 nm and 100 nm. A second portion 114b of the first metal layer 114 extends at the sidewall 111 and has a thickness t2′ orthogonal to the sidewall 111, which is less than the thickness t1′ and is between 5 nm and 100 nm. As a result of the manufacturing process, a third portion 114c of the first metal layer 114 extends on the upper surface 108a of the dielectric layer 108.

[0065] refer to Figure 2D Anisotropic etching is performed, which is configured to preferentially remove the portion of the first metal layer 114 parallel to the XY plane; therefore, the etching step preferentially removes the first portion 114a and the third portion 114c of the first metal layer 114, thereby exposing the surface portion 112a of the body contact area 112.

[0066] Anisotropic etching is performed, for example, by a RIE or DRIE. In another embodiment, anisotropic etching is performed via a high dose (e.g., a dose equal to 1 x 10⁻⁶). 15 The first portion 114a and the third portion 114c of the first metal layer 114 are damaged by ion implantation, and then a wet etching step is performed.

[0067] It should be noted that, Figure 2D After anisotropic dry etching, the second portion 114b of the first metal layer 114 remains on the sidewall 111 of the trench 110, particularly on the second portion 110b of the sidewall 111.

[0068] refer to Figure 2EThen, a first heat treatment is performed at a first temperature T1 (e.g., between 600°C and 900°C) for 60 seconds to form the lateral silicide region 116. Specifically, during the first heat treatment, Ti atoms diffuse from the second portion 114b of the first metal layer 114 into the source region 106 (and in some embodiments, into the body region 104), and vice versa, Si atoms diffuse from the source region 106 into the second portion 114b of the first metal layer 114. The Ti ions then react with the Si ions in the source region 106 (and in some embodiments, in the body region 104) to form a titanium silicide (TiSi / TiSi2) material perpendicular to the silicide region 116.

[0069] Therefore, the lateral silicide region 116 extends within the source region 106, particularly in physical and electrical contact with the source region 106. The lateral silicide region 116 has a thickness ts1′ between 5 nm and 200 nm in a direction orthogonal to the sidewall 111.

[0070] refer to Figure 2F Then, a second metal layer 118 is deposited in the trench 110 and on the upper surface 108a of the dielectric layer 108, for example by physical vapor deposition (PVD).

[0071] The second metal layer 118 extends in the trench 110 and has physical continuity on the second portion 114b of the first metal layer 114 and the surface 112a of the body contact area 112.

[0072] In detail, a portion 118a of the second metal layer 118 extends in direct physical contact with the surface 112a of the body contact area 112, and has a thickness t3 in a direction parallel to the Z-axis, which is between 5 nm and 100 nm, specifically equal to 20 nm.

[0073] In one embodiment, the second metal layer 118 is made of titanium (Ti), titanium nitride (TiN), or titanium silicon (TiSi), or comprises Ti, TiN, or TiSi.

[0074] In another embodiment, the second metal layer 118 is a stack of different material layers, including, for example, a Ti (or TiSi) layer and a TiN layer, wherein the Ti (or TiSi) layer is in direct physical contact with the surface 112a of the body contact region 112.

[0075] refer to Figure 2G A second heat treatment is performed at a second temperature T2 (e.g., between 450°C and 800°C) for 60 seconds to form the bottom silicide region 120.

[0076] The bottom silicide region 120 extends in the bulk contact region 112 at the surface 112a and has a thickness ts2′ along the Z-axis between 5 nm and 200 nm.

[0077] In one embodiment, the thickness ts1′ is different from the thickness ts2′.

[0078] In one embodiment, the thickness ts1′ is greater than the thickness ts2′, specifically, the thickness ts1′ is equal to 50 nm and the thickness ts2′ is equal to 10 nm.

[0079] In another embodiment, the thickness ts2′ is greater than the thickness ts1′, specifically, the thickness ts2′ is equal to 50 nm and the thickness ts1′ is equal to 10 nm.

[0080] In another embodiment, the thickness ts2′ is equal to the thickness ts1′.

[0081] During the second heat treatment, Ti atoms diffuse from the second portion 118a of the second metal layer 118 into the bulk contact region 112, and vice versa, Si atoms diffuse from the bulk contact region 112 into the second portion 118a of the second metal layer. The Ti ions then react with the Si ions in the bulk contact region 112 to form titanium silicide (TiSi / TiSi2) material in the bottom silicide region 120.

[0082] In one embodiment, the second temperature T2 is lower than the first temperature T1 so that the T2 process does not affect the layer formed during the T1 process. Therefore, by utilizing different temperatures to form the lateral silicide region 116 and the bottom silicide region 120, their respective thicknesses can be adjusted without imposing limitations on the thickness of the first metal layer 114 or the second metal layer 118.

[0083] refer to Figure 2H After forming the bottom silicide region 120, the source metal contact 122 is formed in the trench 110 in a manner known per se, for example by a series of metal deposition and chemical mechanical polishing (CMP) steps.

[0084] Specifically, the source metal contact 122 includes a metal filler layer 122a extending in the trench 110, and (optionally) a metal contact layer 122b extending at least partially over a second metal layer 118 above the upper surface 108a of the dielectric layer 108, and electrically contacting the metal filler layer 122a on the metal filler layer 122b.

[0085] The metal filler 122a is made of, for example, tungsten (W) or copper (Cu).

[0086] The metal contact layer 122b is made of, for example, Al or Cu.

[0087] The advantages of this disclosure are clearly evident from the above.

[0088] Specifically, by forming the lateral silicide region 116 and the bottom silicide region 120 through ion diffusion from the first metal layer 114 in the first heat treatment and through ion diffusion from the second metal layer 118 in the second heat treatment, respectively, a thicker lateral silicide region 116 compared to the bottom silicide region 120 can be obtained. Therefore, decoupling the formation of the vertical silicide region 116 from the formation of the bottom silicide region 120 allows for an increase in the thickness ts1′ of the vertical silicide region 116 without increasing the mechanical stress introduced by the bottom silicide region 120 in the semiconductor substrate 102. In other words, the thickness and phase of the vertical silicide region 116 can be adjusted relative to the thickness and phase of the bottom silicide region 120, respectively.

[0089] Finally, it is obvious that modifications and changes can be made to the content described and shown herein without departing from the scope of this disclosure.

[0090] In particular, even though IGBTs have been referenced in the above description, this disclosure can also be applied to other types of electronic devices, such as high-voltage discrete devices, low-voltage discrete devices, or BCD devices.

[0091] Furthermore, in some embodiments, the first heat treatment can be avoided, and the respective thicknesses and phases of the lateral silicide region 116 and the bottom silicide region 120 can be adjusted by: depositing a first metal layer 114 that is thicker than the second metal layer 118; or by depositing a second metal layer 118 made of a different material than the first metal layer 114; and performing a single heat treatment after the deposition of the second metal layer 118.

[0092] A method for forming an electrical contact of an electronic device is summarized as comprising the following steps: providing a solid (102; 104, 106) comprising a semiconductor material including silicon, the solid comprising a first region (104) having a first conductivity (P), a second region (106) having a second conductivity (N) opposite to the first conductivity (P) and extending over the first region (104); forming a trench (110) in the solid (102; 104, 106) that completely penetrates the second region (106) and reaches the first region (104), the trench having sidewalls (111; 110b) exposing the second region (106) and a bottom wall exposing the first region (104). (110c); A first metal layer (114) is formed on the sidewalls (111; 110b) of the trench (110), which is in direct contact with the second region (106), and the first metal layer (114) is absent at at least a portion of the bottom wall (110c); A second metal layer (118) in contact with the first region (104) is formed at said portion of the bottom wall (110c); A first silicide region (116) is formed at the interface between the second region (106) and the first metal layer (114) by one or more heat treatments, and a second silicide region (120) is formed at the interface between the first region (104) and the second metal layer (118).

[0093] The first thickness (ts1′) of the first silicide region (116) is different from the second thickness (ts2′) of the second silicide region.

[0094] The first thickness (ts1′) of the first silicide region (116) is greater than the second thickness (ts2′) of the second silicide region (120).

[0095] Forming the first silicide region (116) includes performing a first heat treatment at a first temperature (T1); and forming the second silicide region (120) includes performing a first heat treatment at a second temperature (T2) below the first temperature.

[0096] The first temperature is in the range of 600°C to 900°C, and the second temperature is in the range of 450°C to 800°C.

[0097] The first metal layer (114) has a first thickness (t2′), and the second metal layer (118) has a second thickness (t3) that is less than the first thickness (t2′); and forming the first silicide region (116) and the second silicide region (120) includes performing a thermal process.

[0098] The first metal layer (114) is made of a first metal material, and the second metal layer (118) is made of a second metal material, wherein in the semiconductor material of the solid (102), the first metal material and the second metal material have corresponding diffusion coefficients such that the diffusion coefficient of the first metal material is greater than the diffusion coefficient of the second metal.

[0099] The first metal layer (114) is made of a first metal material selected from the following: Ti or TiSi and TiN; and the second metal layer (118) is made of a second metal material selected from the following, having a thickness or composition different from the first metal material: Ti, TiSi and TiN.

[0100] The step of forming the first metal layer (114) includes: depositing the first metal layer (114) on the sidewalls and bottomwalls of the trench; and selectively removing the first metal layer (114) from said portion of the bottomwall.

[0101] The method further includes the step of forming a buried region (112) in a first region (104) at the bottom wall (110c) of the trench (110), the buried region having a first conductivity (P) and a doping concentration higher than that of the first region (104), wherein the step of forming a second metal layer (118) includes forming a second metal layer (118) in contact with the first region (104) through the buried region (112), and a second silicide region (120) extends at least partially within the buried region (112).

[0102] The method also includes the step of forming a dielectric layer (108) on the second region (106), and the step of forming a trench (110) includes the step of forming a trench (110) that completely penetrates the dielectric layer (108).

[0103] An electronic device (100) is generally defined as comprising: a semiconductor material entity (102; 104, 106) comprising silicon, the entity comprising a first region (104) having a first conductivity (P) and a second region (106) having a second conductivity (N) opposite to the first conductivity (P) and extending over the first region (104); a trench (110) in the entity (102; 104, 106) extending completely through the second region (106) and reaching the first region (104), the trench having sidewalls (110) along the second region (106). 11; 110b) and the bottom wall (110c) along the first region (104); a first silicide region (116) extending between the second region (106) and the sidewall (111; 110b) and in direct contact with the second region (106); and a second silicide region (120) extending between the first region (104) and the bottom wall (110c) and in direct contact with the first region (104), wherein the first thickness (ts1′) of the first silicide region (116) is different from the second thickness (ts2′) of the second silicide region.

[0104] The first thickness (ts1′) of the first silicide region (116) is greater than the second thickness (ts2′) of the second silicide region (120).

[0105] The electronic device (100) further includes: a first metal layer (114) on the sidewalls (111; 110b) of the trench (110); and a second metal layer (118) on the bottom wall (110c) of the trench (110), wherein a first silicide region (116) is between and in direct contact with the second region (106) and the first metal layer (114), and wherein a second silicide region (120) is between and in direct contact with the first region (104) and the second metal layer (118).

[0106] The first metal layer (114) is made of a first metal material, and the second metal layer (118) is made of a second metal material, wherein in the semiconductor material of the solid (102), the first metal material and the second metal material have corresponding diffusion coefficients such that the diffusion coefficient of the first metal material is greater than the diffusion coefficient of the second metal.

[0107] The first metal layer (114) is made of a first metal material of Ti or TiSi and TiN; and the second metal layer (118) is made of a second metal material of Ti, TiSi and TiN, which has a thickness or composition different from that of the first metal material.

[0108] The electronic device also includes a buried region (112) in a first region (104) at the bottom wall (110c) of the trench (110), the buried region having a first conductivity (P) and a doping concentration higher than that of the first region (104), wherein a second silicide region (120) extends at least partially within the buried region (112). The electronic device (100) is an IGBT and also includes a dielectric layer (108) on a second region (106), wherein: the first region (104) is the body region of the electronic device (100); the second region (106) is the source region of the electronic device (100); the trench (110) extends completely through the dielectric layer (108); and a third metal layer (122a) extends within the trench on the second metal layer (118) to form the emitter terminal of the electronic device.

[0109] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0110] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for forming an electrical contact of an electronic device includes: An entity comprising a semiconductor material including silicon is formed, the entity comprising a first region having a first conductivity and a second region having a second conductivity opposite to the first conductivity and extending over the first region; A trench is formed in the entity, the trench completely passing through the second region and reaching the first region, the trench having sidewalls exposing the second region and bottomwalls exposing the first region; A first metal layer is formed on the sidewall of the trench that is in direct contact with the second region, the first metal layer including a first surface directly on the bottom wall; A gap is formed in the first metal layer to expose a first portion of the bottom wall; A second metal layer is formed at the first portion of the bottom wall in contact with the first area. The second metal layer has a first surface directly on the bottom wall of the trench, and the first surface of the second metal layer is coplanar with the first surface of the first metal layer. as well as Through one or more heat treatments, a first silicide region is formed at the interface between the second region and the first metal layer, and a second silicide region is formed at the interface between the first region and the second metal layer.

2. The method according to claim 1, wherein the first thickness of the first silicide region is different from the second thickness of the second silicide region.

3. The method according to claim 2, wherein the first thickness of the first silicide region is greater than the second thickness of the second silicide region.

4. The method of claim 1, wherein forming the first silicide region comprises performing a first heat treatment at a first temperature, and forming the second silicide region comprises performing a second heat treatment at a second temperature below the first temperature.

5. The method of claim 4, wherein the first temperature is in the range of 600°C to 900°C, and the second temperature is in the range of 450°C to 800°C.

6. The method according to claim 1, wherein: The first metal layer has a first thickness, and the second metal layer has a second thickness lower than the first thickness; and Forming the first silicide region and the second silicide region includes performing an ambient heat treatment.

7. The method of claim 1, wherein the first metal layer is made of a first metal material and the second metal layer is made of a second metal material, wherein in the semiconductor material of the entity, the first metal material and the second metal material have corresponding diffusion coefficients such that the diffusion coefficient of the first metal material is greater than the diffusion coefficient of the second metal material.

8. The method of claim 1, wherein the first metal layer is made of a first metal material selected from the group consisting of titanium (Ti), titanium silicide (TiSi), and titanium nitride (TiN), and the second metal layer is made of a second metal material selected from the group consisting of Ti, TiSi, and TiN, having a thickness or composition different from that of the first metal material.

9. The method of claim 1, further comprising forming a buried region in the first region at the bottom wall of the trench, the buried region having the first conductivity and a doping concentration higher than that of the first region. The formation of the second metal layer includes forming a second metal layer that contacts the first region through the buried region, and The second silicide region extends at least partially within the buried area.

10. The method of claim 1, further comprising forming a dielectric layer on the second region, wherein forming the trench comprises forming the trench completely through the dielectric layer.

11. An electronic device, comprising: An entity comprising a semiconductor material including silicon, the entity comprising a first region having a first conductivity and a second region having a second conductivity opposite to the first conductivity and extending over the first region; A trench, in the entity, extends completely through the second region and to the first region in a first direction, the trench having a sidewall along the second region and a bottom wall along the first region; The burial area is located in the first area and is aligned with the bottom wall along the first direction; A first metal layer is located in the trench; A second metal layer is formed in the trench, wherein both the first metal layer and the second metal layer are in contact with the burial area; A first silicide region extends between the second region and the sidewall, and is in direct contact with the second region; and A second silicide region extends between the first region and the bottom wall, and is in direct contact with the first region. The first thickness of the first silicide region is different from the second thickness of the second silicide region.

12. The electronic device of claim 11, wherein the first thickness of the first silicide region is greater than the second thickness of the second silicide region.

13. The electronic device according to claim 11, wherein... The first metal layer is applied to the sidewalls and bottom wall of the trench, with gaps in the first metal layer exposing a portion of the bottom wall of the trench; and The second metal layer is located in the gap, directly on the bottom wall of the trench. The first silicide region is located between the second region and the first metal layer and is in direct contact with both the second region and the first metal layer, and the second silicide region is located between the first region and the second metal layer and is in direct contact with both the first region and the second metal layer.

14. The electronic device of claim 13, wherein the first metal layer is made of a first metal material and the second metal layer is made of a second metal material, wherein in the semiconductor material of the entity, the first metal material and the second metal material have corresponding diffusion coefficients such that the diffusion coefficient of the first metal material is greater than the diffusion coefficient of the second metal material.

15. The electronic device of claim 13, wherein the first metal layer is made of a first metal material selected from the group consisting of titanium (Ti), titanium silicide (TiSi), and titanium nitride (TiN); and the second metal layer is made of a second metal material selected from the group consisting of Ti, TiSi, and TiN, having a thickness or composition different from that of the first metal material.

16. The electronic device of claim 11, wherein the buried region has the first conductivity and a doping concentration higher than that of the first region, and the second silicide region extends at least partially within the buried region.

17. The electronic device of claim 11, wherein the electronic device is an insulated gate bipolar transistor (IGBT), and the electronic device further comprises a dielectric layer on the second region, wherein: The first region is the body region of the electronic device; The second region is the source region of the electronic device; The trench extends completely through the dielectric layer; and A third metal layer extends within the trench on the second metal layer, thereby forming the emitter terminal of the electronic device.

18. A device comprising: Substrate; The first region is located on the substrate; The second zone is located above the first zone; A trench extending completely through the first region and the second region along a first direction, the trench including multiple sidewalls and end surfaces; The burial area is aligned with the end surface along the first direction; A first silicide region extends between the second region and the sidewall, and is in direct contact with the second region; and A second silicide region extends between the first region and the bottom wall and is in direct contact with the first region, the second silicide region being located within the burial area.

19. The device of claim 18, wherein the trench extends into the substrate along the first direction.

20. The device of claim 18, further comprising: A first metal layer, on the plurality of sidewalls, having a first surface on a first portion of the end surface; and A second metal layer is formed on the first metal layer, wherein the second metal has a first surface on a second portion of the end surface, and the first surface of the first metal layer is coplanar with the first surface of the second metal.

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