A barrier layer for a metal interconnect structure, an interconnect structure and a method of forming the same

Abstract

The application provides a metal interconnection structure barrier layer, an interconnection structure and a forming method of the interconnection structure, and the forming method of the barrier layer comprises the following steps: providing a substrate, the substrate being provided with an interlayer material layer and a trench structure; sequentially depositing a tantalum nitride layer and a tantalum layer on the surface of the substrate to form the barrier layer, the barrier layer being provided with a suspended structure at the opening of the trench structure; introducing a first process gas to perform a weakening treatment on the barrier layer under a low radio frequency bias power, the first process gas comprising a halogen gas; and introducing a second process gas to perform a directional etching treatment on the barrier layer under a high radio frequency bias power to remove the suspended structure, the second process gas comprising argon and hydrogen. In the scheme, the crystal characteristics of the barrier layer in different regions are different, the selective reaction of the suspended structure is realized by the halogen gas, and the directional ion bombardment and H reduction are combined, so that the selective removal of the suspended structure is finally realized, and the barrier layer structure is ensured to be complete, thereby providing a more perfect growth foundation for a subsequent copper filling process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a metal interconnect structure barrier layer, an interconnect structure, and a method for forming the same. Background Technology

[0002] As integrated circuit technology nodes evolve towards 7 nm and below, the trench gap size of metal interconnect structures (copper interconnect structures) is decreasing dramatically, while the aspect ratio is continuously increasing. The formation process of copper interconnect structures typically includes the following steps: forming a trench structure in the interlayer material layers (usually including an etch barrier layer and an interlayer dielectric layer); then forming a barrier layer Ta / TaN within the trench using a PVD process; and finally, filling and planarizing with copper metal. However, with the increase in trench aspect ratio, during the barrier layer formation process, due to the poor step coverage of the PVD process, overhang structures are easily formed at the opening edge of the trench. This causes the subsequent copper filling process to close at the opening first, resulting in voids in the copper interconnect.

[0003] Referring to US patent application US20020058409A1, a similar problem is mentioned, proposing to remove the protruding material at the opening by sputter etching after depositing a PVD film (which may be a pad / barrier layer and / or a seed layer), and then fill the trench / via / contact hole. However, this process mostly uses pure physical bombardment, which makes it difficult to effectively remove the suspended structure at the opening without damaging the integrity of the barrier layer at the bottom of the trench.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] The purpose of this invention is to provide a metal interconnect structure barrier layer, an interconnect structure, and a method for forming the same, so as to remove the suspended structure at the opening of the barrier layer without damaging the rest of the barrier layer, thereby providing a more perfect growth basis for subsequent copper filling processes.

[0006] To address the aforementioned problems, firstly, a method for forming a metal interconnect structure barrier layer is provided, comprising the following steps: S1. A substrate is provided, wherein an interlayer material layer and a trench structure located in the interlayer material layer are formed on the substrate; S2. A tantalum nitride layer and a tantalum layer are sequentially deposited on the surface of the substrate to form a barrier layer, wherein the barrier layer has a suspension structure at the opening of the trench structure; S3. Introduce a first process gas and perform plasma weakening treatment on the barrier layer under low radio frequency bias power to weaken the suspension structure. The first process gas includes halogen gas. S4. Introduce a second process gas and perform directional etching on the barrier layer under high radio frequency bias power to remove the suspension structure. The second process gas includes argon and hydrogen.

[0007] In this scheme, the crystal characteristics of the barrier layer in different regions are utilized to achieve selective reaction of the suspended structure through halogen gas, thereby further weakening its structure. Combined with directional ion bombardment and H reduction, the selective removal of the suspended structure is finally achieved while ensuring the integrity of the barrier layer structure, providing a more perfect growth basis for the subsequent copper filling process.

[0008] Following step S4, the process further includes: introducing pure hydrogen gas to perform plasma reduction treatment on the barrier layer to remove residual halogen gas atoms on the surface of the barrier layer. This further removes residual halogen atoms from the surface, improves the wettability during copper seed layer deposition, and prevents the re-formation of copper suspensions.

[0009] The halogen gas is any one or a combination of Cl2 and BCl3. Cl2 is preferred for better selectivity.

[0010] The first process gas also includes an inert gas as a carrier gas.

[0011] The low RF bias power is less than 100 W; the high RF bias power is greater than 200 W.

[0012] The tantalum nitride layer and the tantalum layer are formed by physical vapor deposition.

[0013] The interlayer material layer includes an etch stop layer and an interlayer dielectric layer stacked sequentially.

[0014] Secondly, this application also provides a metal interconnect structure barrier layer, obtained according to the method for forming a metal interconnect structure barrier layer according to any one of the first aspects.

[0015] Thirdly, this application also provides a method for forming a metal interconnect structure, comprising the following steps: According to any one of the first aspects, a method for forming a metal interconnect structure barrier layer is used to form the barrier layer on the substrate; A copper seed layer is formed on the surface of the substrate; Fill with copper metal; Perform surface planarization treatment.

[0016] In this scheme, selective removal of the suspension structure can effectively improve the deposition and metal filling effect of the copper seed layer.

[0017] Fourthly, this application also provides a metal interconnect structure, obtained according to the method for forming a metal interconnect structure described in the third aspect.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include the following: This solution utilizes the differences in the crystal characteristics of the barrier layer in different regions to achieve selective reaction of the suspended structure through halogen gas, so as to further weaken its structure. Combined with directional ion bombardment and H reduction, the suspended structure can be selectively removed without damaging the rest of the barrier layer, providing a more perfect growth basis for the subsequent copper filling process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the formation process of the metal interconnect structure barrier layer provided by the present invention.

[0021] Figure 2 This is a schematic diagram of the plasma weakening treatment of the barrier layer provided by the present invention.

[0022] Figure 3 This is a schematic diagram of the directional etching process of the barrier layer provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the metal interconnect structure provided by the present invention. Detailed Implementation

[0024] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0025] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0027] Example 1 like Figure 1 The diagram shown is a flowchart illustrating the formation process of the metal interconnect structure barrier layer provided in an embodiment of the present invention. Figure 2 and Figure 3 Two of the main processing steps are shown. (Refer to the reference.) Figures 1 to 3 As shown, this embodiment provides a method for forming a metal interconnect structure barrier layer and the metal interconnect structure barrier layer. The method includes the following steps: Step 1: Provide a substrate; It is understood that the solution in this application is a further optimization and improvement based on existing metal interconnect structures and metal interconnect processes. In the prior art, after the device layer is fabricated on the wafer, a metal interconnect structure needs to be fabricated on top of the device layer as a signal transmission channel between devices (e.g., transistors). This involves first fabricating tungsten contacts (CTs) and tungsten plugs in the device layer, then fabricating the first layer of metal interconnect structure on top of the device layer, followed by the subsequent fabrication of the remaining metal interconnect structures. This multi-layered metal interconnect structure provides a physical guarantee for signal transmission between devices. The fabrication of the metal interconnect structure typically involves etching interconnect trenches and vias in the interlayer dielectric (IMD or ILD) and depositing metal to form metal interconnects.

[0028] Specifically, refer to Figure 2 First, a substrate 1 is provided, on which a device layer (not shown in the figure) or a metal interconnect structure (not shown in the figure) has been formed. On the substrate 1, an interlayer material layer is formed, which is the basis for fabricating the metal interconnect structure of the current layer. It typically includes an etch stop layer 2 and an interlayer dielectric layer 3 in sequence. Of course, in order to realize the pattern definition and trench etching in the interlayer material layer, a buffer layer 4 and a hard mask layer 5 are usually also provided.

[0029] It is understandable that the structure and materials of the interlayer materials can be based on existing processes. For example, the etching barrier layer 2 is generally made of nitrogen-doped silicon carbide, the interlayer dielectric layer 3 is mostly made of low-k or ultra-low-k dielectric layers, the buffer layer 4 can be made of silicon oxynitride, and the hard mask layer 5 is generally made of titanium nitride.

[0030] Continue to refer to Figure 2 As shown, a trench structure 7 is formed in the interlayer material layer. It can be understood that this trench structure 7 is subsequently used to fill copper metal to form interconnects. Of course, to achieve the connection of metal interconnect structures between adjacent layers, vias (not shown in the figure) are usually also formed; this is prior art and will not be elaborated upon here.

[0031] Step 2: Form a barrier layer; It is understandable that in existing processes, a barrier layer 6 is typically formed before filling the trench structure 7 with copper metal material. This layer serves to prevent copper from diffusing into the medium and also acts as an adhesion layer between the copper and the medium. In existing mature processes, the barrier layer 6 has a double-layer structure, with an outer tantalum nitride layer and an inner tantalum layer.

[0032] In this embodiment, a tantalum nitride layer and a tantalum layer are sequentially deposited on substrate 1 using a PVD process to obtain a barrier layer 6. As described in the background art, the existing barrier layer 6 is formed by PVD deposition. However, there is an inherent deposition angle effect during PVD deposition, which causes the growth rate at the opening of the trench structure 7 (in this application, the opening refers to the open area at the top of the trench structure 7) to be faster than at the bottom. As the technology node shrinks and the aspect ratio of the trench structure 7 increases, this effect becomes more significant, making it easier to form an inwardly protruding suspension structure 60 at the edge of the opening, such as... Figure 2 As shown in the image.

[0033] Step 3: Chemically weaken the suspension structure 60 of the barrier layer 6; refer to Figure 1 After the barrier layer 6 is formed, in order to avoid the adverse effects of the suspended structure 60 on the subsequent copper filling process, it is necessary to remove it using a suitable process. In the prior art, ion bombardment (such as argon ions) is generally used to remove the suspended structure 60, but this is prone to incomplete removal or damage to the barrier layer 6.

[0034] To avoid the shortcomings of existing solutions, the applicant discovered through research that during the PVD deposition process of the tantalum layer, although the growth rate at the opening of the trench structure 7 is faster due to the deposition angle effect, resulting in the formation of the suspended structure 60, the grains of the suspended structure 60 at the opening are usually arranged in a columnar pattern, leading to high grain boundary density and significant tensile stress in this region. In contrast, the thin film grains at the bottom / sidewalls of the trench structure 7 are more dense, with a significantly lower grain boundary density. Based on this difference, this application proposes to introduce halogen gas and utilize its selective reaction characteristics at grain boundaries to first weaken the suspended structure 60, and then etch it away. It should be understood that because the suspended structure 60 at the opening has a high grain boundary density and disordered atomic arrangement, it has higher surface energy and chemical activity. Halogen free radicals will preferentially adsorb and react at the grain boundaries, thereby generating volatile metal halides (such as TaCl5). The purpose of this step is not to completely remove the film, but to weaken the structural integrity of part of the suspended structure 60 through chemical reaction and increase its porosity; while the dense area at the bottom has few grain boundaries and low reactivity, only an extremely thin passivation layer is formed on the surface, and the main body is not damaged.

[0035] Specifically, a first process gas is introduced to perform plasma weakening treatment on the barrier layer 6 under low radio frequency bias power to weaken the suspension structure 60. The first process gas includes halogen gas and an inert gas as a carrier gas.

[0036] In this embodiment, the halogen gas used is Cl2. In other embodiments, it can be any one or a combination of Cl2 and BCl3. Cl2 is preferred due to its suitable electronegativity, which allows for a suitable reaction rate and excellent selectivity. In this embodiment, the carrier gas used is Ar. In other embodiments, it can be any one or a combination of Ar or He.

[0037] In this embodiment, the low RF bias power is less than 100 W. The low RF bias power is chosen because the plasma weakening process here mainly utilizes the chemical reaction between free radicals and tantalum. Therefore, a lower RF bias power is more conducive to ionizing and generating a large number of halogen free radicals to promote and suspend the chemical reaction of structure 60, making its structure looser. Simultaneously, it can reduce the ion bombardment effect, further avoiding adverse damage to the remaining parts.

[0038] In this embodiment, the processing time for this step is not strictly limited, and the completion point of the process can be determined in real time by the built-in sensor in the cavity. It is understood that the intensity of the Cl characteristic spectral line in the in-situ optical emission spectroscopy (OES) signal is 837.6 nm. A feasible example is: in this step, as the processing proceeds, the metal halide formation rate decreases. When the detected spectral line intensity decays to 10%~20% of the initial intensity and tends to stabilize, it indicates that the grain boundary reaction in the chemical weakening is saturated, and this step can be terminated.

[0039] Step 4: Etch the suspension structure 60 of the barrier layer 6; As described above, after plasma weakening treatment, the porosity and structure of the suspension structure 60 are loose, while the remaining areas of the barrier layer 6 are basically unaffected. Therefore, selective removal of the suspension structure 60 is achieved through etching. Specifically, a second process gas is introduced, and the barrier layer 6 is directionally etched under high RF bias power to remove the suspension structure 60. The second process gas includes argon and hydrogen.

[0040] In this step, Ar / H2 is used as the process gas, and a high RF bias power (>200W) is applied for directional etching perpendicular to the substrate surface. On one hand, the geometric shielding effect allows high-energy Ar ions to preferentially bombard the chemically weakened porous structure at the opening, removing it via physical sputtering. Simultaneously, the additional H2 plasma reduces the metal halides generated in the previous step back to metal and volatilizes to remove halogen components, preventing residue. Compared to existing simple ion bombardment processes, this etching process combines physical sputtering and chemical removal, achieving efficient removal of the suspended structure 60 while minimizing the impact on other areas. The structure after removal of the suspended structure 60 is shown in the reference image. Figure 3 As shown.

[0041] In this embodiment, the volumetric flow rate ratio of Ar / H2 can be controlled within the range of 2:1 to 4:1, preferably 3:1.

[0042] In this embodiment, the processing time for this step is not strictly limited, and the completion point of the process can be determined in real time by the built-in sensor in the cavity. It can be understood that in this step, H2 will be reduced to HCl. Therefore, a feasible example is: in this step, the HCl mass spectrum peak (m / z=36) in the RGA residual gas analysis signal is used for judgment. When the mass spectrum peak signal drops to the baseline noise level, it indicates that the halogen has been completely removed.

[0043] Step 5: Perform surface restoration treatment on barrier layer 6.

[0044] After the above steps, the removal of the suspended structure 60 and the reduction of halogen atoms can be achieved. Of course, to further ensure the removal of residual halogen atoms, pure hydrogen gas can be introduced to perform plasma reduction treatment on the barrier layer 6 to completely remove residual halogen gas atoms from the barrier layer surface. In this embodiment, the introduction of pure H2 for gentle plasma treatment of the surface can remove trace amounts of residual halogen atoms, repair surface damage caused by bombardment, activate the barrier layer surface, and ensure good nucleation and adhesion of the subsequent copper seed layer. Thus, after the cleaning process, a clean and dense surface is provided to improve the wettability of the copper seed, promote the layer-by-layer growth of the subsequent copper seed layer during deposition, and prevent the copper from forming a suspended structure again.

[0045] It is understandable that this step is a preferred procedure. If the previous steps are thorough and there are few residues, this step can be skipped.

[0046] As shown above, this ultimately forms barrier layer 6, which can be referenced. Figure 3 As shown.

[0047] In this embodiment, a metal interconnect structure barrier layer is also provided, which can be obtained according to the method for forming a metal interconnect structure barrier layer described in this embodiment.

[0048] Example 2 In this embodiment, a method for forming a metal interconnect structure and a metal interconnect structure are also provided. This method is based on a method for forming a barrier layer in a metal interconnect structure as described in Embodiment 1. The method for forming a metal interconnect structure includes the following steps: Step 1: Provide a substrate; Refer to Example 1.

[0049] Step 2: Form a barrier layer; Refer to Example 1.

[0050] Step 3: Chemically weaken the suspension structure 60 of the barrier layer 6; Refer to Example 1.

[0051] Step 4: Etch the suspension structure 60 of the barrier layer 6; Refer to Example 1.

[0052] Step 5: Perform surface restoration treatment on barrier layer 6.

[0053] Refer to Example 1.

[0054] Step 6: Deposit a copper seed layer; Understandably, copper filling processes typically employ electrochemical copper plating. Before electroplating, a continuous, uniform, and extremely thin copper film needs to be formed to provide conductive "seeds" for subsequent electroplating, guiding the copper to grow from the bottom up. Currently, the mainstream process for copper seed layers is physical vapor deposition (PVD), which is an existing technology and will not be elaborated upon here.

[0055] Step 7: Fill with copper metal; Electrochemical copper plating is used to fill the trench structure 7 and through holes, which is an existing technology and will not be described in detail here. The structure after filling can be seen from [reference needed]. Figure 4 As shown.

[0056] Step 8: Perform surface planarization treatment; This is generally done using CMP (Chemical Motion Process) to remove excess material layers and form a flat, globally consistent base plane (not shown in the figure) on the surface of substrate 1, providing a foundation for subsequent photolithography and etching. This is an existing technology and will not be elaborated on here.

[0057] In this embodiment, a metal interconnect structure is also provided, which can be obtained according to the metal interconnect structure forming method described in this embodiment.

[0058] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0059] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for forming a barrier layer in a metal interconnect structure, characterized in that, Includes the following steps: S1. A substrate is provided, wherein an interlayer material layer and a trench structure located in the interlayer material layer are formed on the substrate; S2. A tantalum nitride layer and a tantalum layer are sequentially deposited on the surface of the substrate to form a barrier layer, wherein the barrier layer has a suspension structure at the opening of the trench structure; S3. Introduce a first process gas and perform plasma weakening treatment on the barrier layer under low radio frequency bias power to weaken the suspension structure. The first process gas includes halogen gas. S4. Introduce a second process gas and perform directional etching on the barrier layer under high radio frequency bias power to remove the suspension structure. The second process gas includes argon and hydrogen.

2. The method for forming a barrier layer of a metal interconnect structure according to claim 1, characterized in that, After step S4, the following is also included: Pure hydrogen gas is introduced to perform plasma reduction treatment on the barrier layer to remove residual halogen gas atoms on the surface of the barrier layer.

3. The method for forming a barrier layer of a metal interconnect structure according to claim 1, characterized in that, The halogen gas is any one or a combination of Cl2 and BCl3.

4. The method for forming a barrier layer of a metal interconnect structure according to claim 3, characterized in that, The first process gas also includes an inert gas as a carrier gas.

5. The method for forming a barrier layer of a metal interconnect structure according to claim 1, characterized in that, The low RF bias power is less than 100 W; the high RF bias power is greater than 200 W.

6. The method for forming a barrier layer of a metal interconnect structure according to claim 1, characterized in that, The tantalum nitride layer and the tantalum layer are formed by physical vapor deposition.

7. The method for forming a barrier layer of a metal interconnect structure according to claim 1, characterized in that, The interlayer material layer includes an etch stop layer and an interlayer dielectric layer stacked sequentially.

8. A barrier layer for a metal interconnect structure, characterized in that, The method for forming a metal interconnect structure barrier layer according to any one of claims 1 to 7 is obtained.

9. A method for forming a metal interconnect structure, characterized in that, Includes the following steps: A method for forming a metal interconnect structure barrier layer according to any one of claims 1 to 7, wherein the barrier layer is formed on the substrate; A copper seed layer is formed on the surface of the substrate; Fill with copper metal; Perform surface planarization treatment.

10. A metal interconnect structure, characterized in that, The method for forming a metal interconnect structure according to claim 9 is obtained.

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