Semiconductor device structure and method of fabricating the same

Abstract

The application provides a semiconductor device structure and a preparation method thereof. A local composite conductive layer is arranged between a first gold layer and a second gold layer in a through hole region, so that a support layer is located inside a back hole metal and forms support for the back hole region. In a packaging welding process, the risk of back hole collapse caused by mutual fusion of welding material and metal layer can be reduced. At the same time, the direct connection between the gold layers in the outer region of the through hole is maintained, which is beneficial to maintaining the conductivity, weldability and packaging reliability of the back metal, thereby improving the electrical connection reliability, packaging yield and long-term use stability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] As semiconductor devices evolve towards higher frequencies, higher power, and higher integration, an increasing number of devices employ through-hole structures that extend the metal layer from the front side of the device to the back side. This reduces interconnect path impedance and improves the device's grounding, heat dissipation, and package interconnect performance. For example, in high electron mobility transistor (HEMT) devices, particularly silicon carbide (SiC)-based gallium nitride (GaN) HEMT devices, the source metal layer is typically extended to the back side of the device via a through-hole structure. A backhole metal layer is formed within the backhole and on the back side of the substrate to achieve electrical connection between the source metal layer and the back-side package structure.

[0003] In subsequent packaging processes, the back side of the device needs to be connected to the packaging substrate, copper plate, or other support structures via solder. When the packaging soldering material and the back hole metal layer contain the same or easily interfacial metal components, the solder is prone to interfacial fusion with the back hole metal layer during the melting process. Because metals such as gold (Au) have good ductility but relatively insufficient structural support, the back hole metal layer located in the back hole area is prone to deformation under the action of solder melting, thermal stress, and packaging pressure. In severe cases, this can lead to back hole collapse, thereby affecting the reliability of the electrical connection between the metal layer to be led out and the back side of the device, and reducing the packaging yield and long-term reliability of the semiconductor device. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device structure and its fabrication method, which solves the problem that the back hole metal layer is prone to interfusion with the packaging welding material during the packaging welding process, resulting in back hole collapse, which in turn affects the electrical connection reliability and packaging yield of the semiconductor device.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device structure, the method comprising:

[0006] An intermediate structure is provided, the intermediate structure including a substrate having opposing first and second sides, a metal layer to be led out located on the first side of the substrate, and a via penetrating the substrate and exposing the metal layer to be led out;

[0007] A first composite conductive layer is formed, which covers the surface of the second side of the substrate, the side of the via, and the metal layer to be led out exposed by the via. The first composite conductive layer includes an adhesion layer and a first seed layer stacked sequentially.

[0008] A first gold layer is formed on the surface of the first seed layer away from the adhesion layer;

[0009] A second composite conductive layer is formed, which covers the first gold layer located within the through hole and extends a predetermined distance from the edge of the through hole opening to the outside of the through hole; wherein, the second composite conductive layer includes a support layer and a second seed layer stacked sequentially;

[0010] A second gold layer is formed on the surface of the second seed layer away from the support layer and on the surface of the first gold layer not covered by the second composite conductive layer.

[0011] Optionally, the thickness of the second gold layer is greater than or equal to the thickness of the first gold layer.

[0012] Optionally, the material of the adhesion layer includes one or more combinations of Ti, Ni, W, TiW, and NiW, the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW, the first seed layer is an Au layer, and the second seed layer is an Au layer.

[0013] Optionally, the first composite conductive layer is formed by sputtering deposition, the second composite conductive layer is formed by sputtering deposition, the first gold layer is formed by electroplating, and the second gold layer is formed by electroplating.

[0014] Optionally, after forming the second gold layer, the method further includes:

[0015] A patterned photoresist layer is formed on the side of the second gold layer away from the substrate;

[0016] Using the patterned photoresist layer as a mask, the second gold layer and the first gold layer in the dicing area are etched away.

[0017] Remove the patterned photoresist layer and etch away the first composite conductive layer in the dicing area.

[0018] Optionally, before forming the first composite conductive layer, the first side of the substrate is bonded to the sapphire carrier using bonding wax; after forming the second gold layer, the substrate and the sapphire carrier are debonded.

[0019] The present invention also provides a semiconductor device structure, the semiconductor device structure comprising:

[0020] A substrate having a first side and a second side opposite to each other;

[0021] The metal layer to be brought out is located on the first side of the substrate;

[0022] A via, penetrating the substrate and exposing the metal layer to be brought out;

[0023] A first composite conductive layer covers the surface of the second side of the substrate, the side of the via, and the metal layer to be led out exposed by the via. The first composite conductive layer includes an adhesion layer and a first seed layer stacked sequentially.

[0024] The first gold layer is located on the surface of the first seed layer away from the adhesion layer;

[0025] A second composite conductive layer covers the first gold layer located within the through hole and extends a predetermined distance from the edge of the through hole opening to the outside of the through hole; wherein, the second composite conductive layer includes a support layer and a second seed layer stacked sequentially.

[0026] The second gold layer is located on the surface of the second seed layer away from the support layer and on the surface of the first gold layer that is not covered by the second composite conductive layer.

[0027] Optionally, the preset distance is 0.5μm to 2.5μm.

[0028] Optionally, the thickness of the second gold layer is greater than or equal to the thickness of the first gold layer.

[0029] Optionally, the material of the adhesion layer includes one or more combinations of Ti, Ni, W, TiW, and NiW; the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW.

[0030] Optionally, the adhesion layer is a TiW layer, the first seed layer is an Au layer, the thickness of the adhesion layer is 60nm~100nm, and the thickness of the first seed layer is 200nm~500nm; the support layer is a TiW layer, the second seed layer is an Au layer, the thickness of the support layer is 200nm~300nm, and the thickness of the second seed layer is 100nm~200nm.

[0031] Optionally, the substrate is a SiC substrate, and the intermediate structure further includes an epitaxial layer formed between the SiC substrate and the metal layer to be led out, wherein the metal layer to be led out is a source metal layer.

[0032] As described above, the semiconductor device structure and its fabrication method of the present invention have the following beneficial effects: By sequentially distributing a first composite conductive layer, a first gold layer, a second composite conductive layer, and a second gold layer within a via that penetrates the substrate and exposes the metal layer to be led out, and on the second side of the substrate, and by making the second composite conductive layer cover the first gold layer located within the via and extending a predetermined distance from the edge of the via opening to the outside of the via, a support layer in the second composite conductive layer is sandwiched between the first gold layer and the second gold layer and is mainly distributed in the corresponding region of the via. This allows for the formation of a continuous and reliable conductive lead-out path between the metal layer to be led out and the second side of the substrate. Simultaneously, the support layer enhances the mechanical support strength and thermal deformation resistance of the metal stack in the via region, solving the problems encountered in the packaging and soldering process of existing semiconductor devices. This addresses the issue of via collapse caused by the fusion of the encapsulation soldering material with the metal layer inside the via, softening of the gold layer due to heat, or deformation under encapsulation pressure. Furthermore, because the second composite conductive layer only covers the first gold layer inside the via and extends a predetermined distance outwards, the surface of the first gold layer not covered by the second composite conductive layer can still directly contact the second gold layer. This ensures good metal continuity, conductivity, and encapsulation soldering fusion in the outer region of the via, preventing the support layer from being distributed over a large area and affecting the reliable connection between the back metal layer and the encapsulation soldering material. Ultimately, this achieves a balance between the via's anti-collapse capability, the reliability of the back lead-out of the metal layer to be led out, the conductivity of the back metal, and the reliability of the encapsulation connection, thereby improving the packaging yield and long-term reliability of semiconductor devices. Attached Figure Description

[0033] Figure 1 The diagram shows a flow chart of the method for fabricating the semiconductor device structure of the present invention.

[0034] Figure 2 The diagram shows a cross-sectional view of the intermediate structure bonded to the sapphire carrier according to the present invention.

[0035] Figure 3 The diagram shown is a cross-sectional view of the structure after the formation of the first composite conductive layer according to the present invention.

[0036] Figure 4 The diagram shows a cross-sectional structure after the formation of the first gold layer according to the present invention.

[0037] Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the second composite conductive layer in this invention.

[0038] Figure 6 The diagram shows a cross-sectional structure after the formation of the second gold layer according to the present invention.

[0039] Figure 7 The diagram shown is a cross-sectional view of the patterned photoresist layer formed according to the present invention.

[0040] Figure 8 The diagram shows a cross-sectional structure of the dicing area after etching the second and first gold layers.

[0041] Figure 9 The diagram shows a cross-sectional structure after the photoresist layer has been removed and the first composite conductive layer has been etched according to the present invention.

[0042] Figure 10 The diagram shown is a schematic cross-sectional view of the semiconductor device after debonding according to the present invention.

[0043] Component labeling explanation: 1 Intermediate structure, 10 Substrate, 11 Epitaxial layer, 12 Metal layer to be led out, 13 Through hole, 14 Sapphire carrier, 15 Bonding wax, 2 First composite conductive layer, 3 First gold layer, 4 Second composite conductive layer, 5 Second gold layer, 6 Patterned photoresist layer. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] This embodiment provides a method for fabricating a semiconductor device structure, such as... Figure 1 As shown, the preparation method includes:

[0047] S1, providing an intermediate structure, the intermediate structure including a substrate having opposing first and second sides, a metal layer to be led out located on the first side of the substrate, and a via penetrating the substrate and exposing the metal layer to be led out;

[0048] S2, forming a first composite conductive layer, the first composite conductive layer covering the surface of the second side of the substrate, the side of the via and the metal layer to be led out exposed by the via, the first composite conductive layer including an adhesion layer and a first seed layer stacked in sequence;

[0049] S3, a first gold layer is formed on the surface of the first seed layer away from the adhesion layer;

[0050] S4, forming a second composite conductive layer, the second composite conductive layer covering the first gold layer located in the through hole, and extending a predetermined distance from the edge of the through hole opening to the outside of the through hole; wherein, the second composite conductive layer includes a support layer and a second seed layer stacked sequentially;

[0051] S5, a second gold layer is formed on the surface of the second seed layer away from the support layer and on the surface of the first gold layer not covered by the second composite conductive layer.

[0052] The semiconductor device structure fabrication method of this embodiment involves sequentially forming a first composite conductive layer, a first gold layer, a second composite conductive layer, and a second gold layer in a via that penetrates the substrate and exposes the metal layer to be led out. The second composite conductive layer covers the first gold layer located within the via and extends a predetermined distance from the edge of the via opening outwards. A support layer in the second composite conductive layer is sandwiched between the first and second gold layers and is mainly distributed in the corresponding region of the via. This ensures that the metal layer to be led out is reliably led to the second side of the substrate via the via, while also forming a supporting layer in the via region. The metal sandwich structure solves the problem in existing technologies where the packaging soldering material easily fuses with the metal layer inside the via during the melting process, leading to via collapse due to the high ductility of the gold layer and insufficient structural support. At the same time, the second gold layer is formed on the surface of the first gold layer that is not covered by the second composite conductive layer, so that the outer area of ​​the via can still maintain good metal continuity, conductivity, and packaging soldering interfacilitation. Thus, while suppressing via collapse, it also takes into account the back conductivity of the semiconductor device, the reliability of the package connection, and the process compatibility, thereby improving the packaging yield and long-term reliability of the semiconductor device.

[0053] The semiconductor device structure and its fabrication method of this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that in this embodiment, the first side can be the side used to form the front metal layer of the device, and the second side can be understood as the side opposite to the first side used to form the back metal layer. The above-mentioned directional terms are only for the convenience of describing the relative positional relationships between the structures in conjunction with the accompanying drawings, and are not intended to limit the absolute spatial orientation of the semiconductor device structure during actual fabrication, packaging, or use.

[0054] like Figure 2 As shown, step S1 is performed first to provide an intermediate structure 1, which includes a substrate 10 having a first side and a second side, a metal layer 12 to be led out located on the first side of the substrate 10, and a via 13 that penetrates the substrate 10 and exposes the metal layer 12 to be led out.

[0055] Specifically, the substrate 10 can be a substrate used to support the semiconductor epitaxial structure and the front-side device structure. As an example, the substrate 10 is a silicon carbide (SiC) substrate, and the intermediate structure 1 further includes an epitaxial layer 11 formed between the SiC substrate and the lead-out metal layer 12, where the lead-out metal layer 12 is a source metal layer. Thus, the semiconductor device structure can be applied to high electron mobility transistor (HEMT) devices, especially SiC-based GaN RF HEMT devices. In such devices, the source terminal typically needs to be led out to the back of the device through a back via structure penetrating the substrate 10 to reduce ground inductance, improve RF characteristics, and facilitate subsequent connection to a packaging substrate, heat sink, or metal carrier plate.

[0056] Specifically, the metal layer 12 to be led out is formed on the side of the epitaxial layer 11 away from the substrate 10. The epitaxial layer 11 may include a gallium nitride (GaN) channel layer, a barrier layer, a buffer layer or other group III nitride semiconductor layers. In this embodiment, the epitaxial layer 11 is used to refer only to the functional semiconductor layer located between the substrate 10 and the metal layer 12 to be led out, and the specific number of layers and material combination of the epitaxial layer 11 are not limited.

[0057] As an example, the via 13 can be formed using a dry etching process. For instance, plasma etching, deep reactive ion etching (DRIE), or other etching processes suitable for SiC materials can be used to etch the via 13 from the second side of the substrate 10. The cross-sectional shape of the via 13 can be a trapezoidal shape (wider at the top and narrower at the bottom), a nearly vertical columnar shape, a cone shape, or other shapes that expose the metal layer 12 to be brought out. The sides of the via 13 can be inclined surfaces, and the bottom of the via 13 exposes the metal layer 12 to be brought out, thereby providing a basis for the subsequent formation of a metallization structure within the via 13.

[0058] As an example, before forming the first composite conductive layer 2, the first side of the substrate 10 is bonded to the sapphire carrier 14 using bonding wax 15; after the subsequent formation of the second gold layer 5, the substrate 10 and the sapphire carrier 14 are debonded. Specifically, the first side of the substrate 10 is temporarily fixed to the sapphire carrier 14, and the bonding wax 15 is located between the sapphire carrier 14 and the intermediate structure 1 to provide mechanical support for the intermediate structure 1 and protect the metal layer 12 to be led out and the epitaxial layer 11. Since the substrate 10 may have a small thickness or large stress during back-side etching and back-side metallization, the sapphire carrier 14 can reduce the risk of wafer warpage, breakage, and damage to front-side devices.

[0059] It should be noted that the sapphire carrier 14 is mainly used as a temporary carrier and does not necessarily constitute a necessary component of the final product. In other embodiments, the sapphire carrier 14 can also be replaced by a glass carrier, silicon carrier, quartz carrier, ceramic carrier, or other temporary carriers with sufficient rigidity, temperature resistance, and process compatibility; the bonding wax 15 can also be replaced by temporary bonding adhesive, heat-release adhesive, UV-release adhesive, or other debonding materials. After completing the second gold layer 5 and necessary subsequent processes, the bonding wax 15 can be removed by heating, solvent immersion, UV irradiation, mechanical peeling, or a combination thereof, thereby separating the intermediate structure 1 from the sapphire carrier 14.

[0060] like Figure 3 As shown, step S2 is then performed to form a first composite conductive layer 2. The first composite conductive layer 2 covers the surface of the second side of the substrate 10, the side of the via 13, and the metal layer 12 exposed by the via 13. The first composite conductive layer 2 includes an adhesion layer and a first seed layer stacked sequentially.

[0061] Specifically, the adhesion layer in the first composite conductive layer 2 is used to improve the bonding force between the subsequent metal layer and the substrate 10, the side of the via 13 and the metal layer 12 to be led out; the first seed layer is used to provide a conductive seed layer for the subsequent formation of the first gold layer 3, so that the electroplated metal can grow continuously along the first seed layer.

[0062] As an example, the first composite conductive layer 2 can be formed using a sputtering deposition process. Specifically, the first composite conductive layer 2 can be formed using a sputtering deposition process in physical vapor deposition (PVD), whereby the adhesion layer and the first seed layer are sequentially deposited on the surface of the second side of the substrate 10, the side surface of the via 13, and the exposed metal layer 12 at the bottom of the via 13. Forming the first composite conductive layer 2 using a sputtering deposition process helps improve the coverage continuity of the first composite conductive layer 2 on the inner wall and bottom of the via 13.

[0063] As an example, the material of the adhesion layer includes one or more combinations of titanium (Ti), nickel (Ni), tungsten (W), titanium-tungsten alloy (TiW), and nickel-tungsten alloy (NiW), and the first seed layer is a gold (Au) layer. Further, the adhesion layer can be a TiW layer, which has good adhesion, barrier properties, and heat resistance, thus improving the bonding reliability between the first composite conductive layer 2 and the underlying structure; the Au layer can serve as a seed layer for subsequent electroplating to form the first gold layer 3.

[0064] As a preferred example, the adhesion layer is a TiW layer, the first seed layer is an Au layer, the thickness of the adhesion layer is 60nm~100nm, and the thickness of the first seed layer is 200nm~500nm. When the thickness of the adhesion layer is set to 60nm~100nm, it provides good adhesion and barrier properties without significantly increasing the stress on the first composite conductive layer 2. When the thickness of the first seed layer is set to 200nm~500nm, it ensures good continuity and conductivity of the first seed layer to meet the requirements of uniformity in subsequent electroplating.

[0065] like Figure 4 As shown, step S3 is then performed to form a first gold layer 3 on the surface of the first seed layer away from the adhesion layer.

[0066] Specifically, the first gold layer 3 can be formed on the surface of the first seed layer in the first composite conductive layer 2 by an electroplating process. Since the first seed layer covers the surface of the second side of the substrate 10, the side of the via 13, and the exposed metal layer 12 at the bottom of the via 13, the first gold layer 3 can also correspondingly cover the surface of the second side of the substrate 10, the side of the via 13, and the bottom region of the via 13. The first gold layer 3 can increase the conductive metal thickness inside the via 13 and on the second side of the substrate 10, reduce the conductive path resistance, and provide a continuous metal bearing surface for the subsequent formation of the second composite conductive layer 4.

[0067] like Figure 5 As shown, step S4 is then performed to form a second composite conductive layer 4. The second composite conductive layer 4 covers the first gold layer 3 located in the through hole 13 and extends a predetermined distance from the edge of the opening of the through hole 13 to the outside of the through hole 13. The second composite conductive layer 4 includes a support layer and a second seed layer stacked in sequence.

[0068] Specifically, the second composite conductive layer 4 covers the first gold layer 3 located within the through-hole 13, such that the support layer in the second composite conductive layer 4 is sandwiched between the first gold layer 3 and the subsequently formed second gold layer 5. Gold has good ductility and solderability. When the subsequent encapsulation soldering material melts and fuses with the gold, the area located in the through-hole 13 is easily deformed by the combined effects of thermal stress, encapsulation pressure, and material fusion. By inserting the support layer between the first gold layer 3 and the second gold layer 5, the mechanical support capacity of the metallized structure in the through-hole 13 area can be improved, thereby reducing the risk of the through-hole 13 collapsing.

[0069] As an example, the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW. Further, the support layer can be a TiW layer, and the second seed layer can be an Au layer. The thickness of the support layer can be 200nm~300nm, and the thickness of the second seed layer can be 100nm~200nm. Compared to a simple Au layer, the TiW layer has higher structural rigidity and thermal stability, and can form a support framework in the metallized structure of the through-hole 13. The second seed layer is located on the side of the support layer away from the first gold layer 3, used to improve the electroplating continuity and interface adhesion during the subsequent electroplating of the second gold layer 5. Thus, the second composite conductive layer 4 can balance the support function with electroplating process compatibility.

[0070] As a preferred example, the preset distance is 0.5μm to 2.5μm. That is, the second composite conductive layer 4 not only covers the internal region of the through-hole 13, but also extends 0.5μm to 2.5μm from the edge of the through-hole 13 outwards. By extending the second composite conductive layer 4 a certain distance outwards from the through-hole 13, the metal support capacity at the opening of the through-hole 13 can be enhanced, reducing the risk of cracking, collapse, or metal retraction at the opening edge due to stress concentration during the encapsulation and welding process. If the preset distance is too small, the support effect of the second composite conductive layer 4 on the edge of the through-hole 13 opening will be limited; if the preset distance is too large, the second composite conductive layer 4 will cover too much of the outer region of the through-hole 13, potentially affecting the direct contact and encapsulation welding fusion between the first gold layer 3 and the second gold layer 5 in the outer region of the through-hole 13. Therefore, setting the preset distance to 0.5μm to 2.5μm achieves a better balance between support effect and conductivity and welding performance.

[0071] As an example, the second composite conductive layer 4 can be formed using a sputtering deposition process. Specifically, the second composite conductive layer 4 can first be formed on the surface of the first gold layer 3 by full-area sputtering, and then patterned by photolithography and etching processes to remove the portion of the second composite conductive layer 4 that does not need to be retained outside the via 13, retaining only the portion of the first gold layer 3 covering the via 13 and extending outward from the edge of the via 13 opening by the predetermined distance. Thus, the second composite conductive layer 4 can form a local support structure in the region of the via 13, while in the region away from the via 13, the surface of the first gold layer 3 can still be directly used for the subsequent formation of the second gold layer 5.

[0072] like Figure 6 As shown, step S5 is then performed, in which a second gold layer 5 is formed on the surface of the second seed layer away from the support layer and on the surface of the first gold layer 3 not covered by the second composite conductive layer 4.

[0073] Specifically, the second gold layer 5 can be formed by an electroplating process. Since the second composite conductive layer 4 includes the second seed layer, and the first gold layer 3, which is not covered by the second composite conductive layer 4, can also serve as a seed layer, the second gold layer 5 can be formed simultaneously on the surface of the second seed layer away from the support layer and on the surface of the first gold layer 3, which is not covered by the second composite conductive layer 4. Thus, the second gold layer 5 covers the second composite conductive layer 4 in the via 13 region and is directly connected to the first gold layer 3 in the region outside the via 13, so that the final back metal layer has both good overall conductive continuity and a local support and reinforcement structure in the via 13 region.

[0074] As an example, the thickness of the formed second gold layer 5 is greater than or equal to the thickness of the first gold layer 3, so that the second gold layer 5 forms a back-side solder metal layer of sufficient thickness to meet the requirements of subsequent encapsulation soldering, current transmission, and heat conduction. Preferably, the thickness of the formed second gold layer 5 is greater than or equal to four times the thickness of the first gold layer 3. Further, the thickness of the second gold layer 5 can be about 4 μm, and the thickness of the first gold layer 3 can be about 1 μm, not limited to this embodiment. Since the second composite conductive layer 4 is located between the first gold layer 3 and the second gold layer 5 and is mainly distributed in the region of the via 13, the thicker second gold layer 5 can cover and encapsulate the second composite conductive layer 4, so that the final back-side metal surface still mainly appears as an Au metal surface, which is beneficial for forming a reliable connection with the encapsulation soldering material.

[0075] In subsequent encapsulation processes, the encapsulation soldering material can be a solder or sintered material disposed between the second gold layer 5 and the encapsulation substrate, copper plate, heat sink, or other support structure. The encapsulation soldering material may include gold-tin solder, tin-based solder, silver sintered material, gold-based soldering material, or other materials capable of forming a bond with the back metal layer. When the encapsulation soldering material melts or softens during reflow, sintering, or hot pressing, it may fuse or diffuse with Au in the second gold layer 5. Because the via 13 region is provided with the support layer in the second composite conductive layer 4, the support layer provides support between the first gold layer 3 and the second gold layer 5, thereby resisting metal body sagging caused by material fusion, thermal stress, and encapsulation pressure.

[0076] Furthermore, as an example, after the formation of the second gold layer 5 is completed, the second gold layer 5, the first gold layer 3, and the first composite conductive layer 2 can form a continuous back metal layer on the second side of the substrate 10. To avoid metal connectivity between adjacent chips in the scribe line region, or to meet subsequent wafer dicing and packaging separation requirements, the metal layer in the scribe line region can be patterned and removed. For example... Figures 7 to 9 As shown, after forming the second gold layer 5, the process further includes:

[0077] like Figure 7 As shown, a patterned photoresist layer 6 is formed on the side of the second gold layer 5 away from the substrate 10. The patterned photoresist layer 6 covers the area where the back metal needs to be retained and exposes the dicing area where the metal needs to be removed.

[0078] like Figure 8 As shown, using the patterned photoresist layer 6 as a mask, the second gold layer 5 and the first gold layer 3 in the dicing region are etched away. As an example, a wet etching solution suitable for Au or other metal etching processes can be used for removal. By first removing the thicker Au metal layer in the dicing region, metal residue, burrs, or bridging that could affect the chip edge reliability during subsequent dicing processes can be avoided.

[0079] like Figure 9 As shown, the patterned photoresist layer 6 is removed, and the first composite conductive layer 2 in the scribe line region is etched away. Since the first composite conductive layer 2 includes the adhesion layer and the first seed layer (the first seed layer may include Au, and the adhesion layer may include TiW or other metal materials), after removing the second gold layer 5 and the first gold layer 3, the remaining first composite conductive layer 2 in the scribe line region can be further removed using a corresponding etchant or etching process to ensure that the metal layer in the scribe line region is sufficiently broken. This improves the stability of subsequent dicing processes and reduces the risk of short circuits between adjacent devices.

[0080] like Figure 10 As shown, after forming the second gold layer 5 and completing the necessary back-side metal patterning, the substrate 10 and the sapphire carrier 14 are debonded to remove the sapphire carrier 14 and the bonding wax 15. After debonding, the first side of the semiconductor device structure can be exposed, and the metal layer 12 to be led out is electrically connected to the back side of the device through the first composite conductive layer 2, the first gold layer 3, the second composite conductive layer 4, and the second gold layer 5 within the via 13. Subsequent conventional processes such as cleaning, annealing, dicing, die bonding, soldering, sintering, or encapsulation can be performed as needed.

[0081] This embodiment also provides a semiconductor device structure, such as Figure 10 As shown, the semiconductor device structure includes:

[0082] Substrate 10 has a first side and a second side opposite to each other;

[0083] The metal layer 12 to be brought out is located on the first side of the substrate 10;

[0084] Through-hole 13 penetrates the substrate 10 and exposes the metal layer 12 to be brought out;

[0085] The first composite conductive layer 2 covers the surface of the second side of the substrate 10, the side of the via 13, and the metal layer 12 exposed by the via 13. The first composite conductive layer 2 includes an adhesion layer and a first seed layer stacked sequentially.

[0086] The first gold layer 3 is located on the surface of the first seed layer away from the adhesion layer;

[0087] The second composite conductive layer 4 covers the first gold layer 3 located within the through hole 13 and extends a predetermined distance from the edge of the opening of the through hole 13 to the outside of the through hole 13; wherein, the second composite conductive layer 4 includes a support layer and a second seed layer stacked sequentially.

[0088] The second gold layer 5 is located on the surface of the second seed layer away from the support layer and on the surface of the first gold layer 3 that is not covered by the second composite conductive layer 4.

[0089] Specifically, the semiconductor device structure can be fabricated using the aforementioned semiconductor device structure fabrication method, but is not limited to this; other suitable fabrication methods are also possible. In this embodiment, the semiconductor device structure, by providing a first composite conductive layer and a first gold layer covering the metal layer to be led out within a via of the substrate, and by providing a second composite conductive layer extending a predetermined distance from the edge of the via opening to the outside of the via on the first gold layer located within the via, and by providing a second gold layer on the second composite conductive layer and the first gold layer not covered by the second composite conductive layer, allows the support layer in the second composite conductive layer to be located between the first and second gold layers, providing enhanced support for the metal structure in the via region. This improves the deformation resistance of the metal structure within the via during the packaging and soldering process, solving the problem of deformation in existing semiconductor devices. In conductor device structures, the back hole metal layer is prone to deformation or even collapse under the action of solder melting, thermal stress, and packaging pressure. Furthermore, the second composite conductive layer only covers the first gold layer inside the through hole and extends a predetermined distance outward from the through hole, so that the area outside the through hole not covered by the second composite conductive layer is still directly connected by the first gold layer and the second gold layer. This ensures good conductive contact and packaging connection performance between the back metal layer on the second side of the substrate and the packaging soldering material, achieving the beneficial effects of balancing the structural support of the through hole area, reliable lead-out of the metal layer to be led out, conductivity continuity of the back metal, and packaging soldering reliability.

[0090] As a preferred example, the preset distance is 0.5μm to 2.5μm. With this size setting, the second composite conductive layer 4 can cover the stress-prone area at the opening of the through hole 13, enhancing the anti-collapse ability at the edge of the through hole 13; at the same time, the second composite conductive layer 4 will not extend excessively into the back metal area far away from the through hole 13, thereby helping to ensure that the first gold layer 3 and the second gold layer 5 are directly connected over a large area.

[0091] As an example, the thickness of the second gold layer 5 is greater than or equal to the thickness of the first gold layer 3. Preferably, the thickness of the second gold layer 5 is greater than or equal to four times the thickness of the first gold layer 3, so that the second gold layer 5 can serve as the main back-side soldering metal layer and provide sufficient metal thickness for subsequent encapsulation soldering. The first gold layer 3 serves as a conductive transition layer located below the second composite conductive layer 4, forming a reliable bottom conductive base together with the first composite conductive layer 2. The second gold layer 5 and the first gold layer 3, in conjunction with the second composite conductive layer 4, enable the via 13 region to have both low-resistance conductivity and strong structural support.

[0092] As an example, the material of the adhesion layer includes one or more combinations of Ti, Ni, W, TiW, and NiW; the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW. All of the above materials can be used as metallic or alloy materials with good adhesion, heat resistance, or mechanical strength. Specifically, when TiW is used as the adhesion layer, it can enhance the bonding force between the first composite conductive layer 2 and the substrate 10, the sidewalls of the via 13, and the metal layer 12 to be led out; when TiW is used as the support layer, it can provide mechanical support for the Au metal layer within the via 13 and, to a certain extent, prevent excessive interfading between the packaging soldering material and the underlying Au metal layer.

[0093] As a preferred example, the adhesion layer is a TiW layer, the first seed layer is an Au layer, the thickness of the adhesion layer is 60nm~100nm, and the thickness of the first seed layer is 200nm~500nm; the support layer is a TiW layer, the second seed layer is an Au layer, the thickness of the support layer is 200nm~300nm, and the thickness of the second seed layer is 100nm~200nm. In this structure, the first composite conductive layer 2 can correspond to a TiW / Au stack, and the second composite conductive layer 4 can also correspond to a TiW / Au stack. The TiW layer in the first composite conductive layer 2 is mainly used for adhesion, and the Au layer in the first composite conductive layer 2 is mainly used for electroplating the first gold layer 3; the TiW layer in the second composite conductive layer 4 is mainly used for supporting the metal in the via 13 region, and the Au layer in the second composite conductive layer 4 is mainly used for electroplating the second gold layer 5.

[0094] It should be noted that the support layer in the second composite conductive layer 4 and the adhesion layer in the first composite conductive layer 2 can be made of the same material or different materials. Both can include TiW, but they differ in structural location and main function. The adhesion layer in the first composite conductive layer 2 is located between the substrate 10, the side of the via 13, and the metal layer to be led out 12 and the first seed layer, and is mainly used to improve adhesion and provide a base for electroplating; the support layer in the second composite conductive layer 4 is located between the first gold layer 3 and the second gold layer 5, and is mainly retained in the via 13 region, and is mainly used to support the Au metal body in the via 13 to prevent collapse during subsequent encapsulation soldering.

[0095] As an example, the substrate 10 is a SiC substrate, and the intermediate structure 1 further includes an epitaxial layer 11 formed between the SiC substrate and the metal layer 12 to be led out, wherein the metal layer 12 to be led out is a source metal layer. Specifically, the semiconductor device structure can be a SiC-based GaN RF device, and the source metal layer is electrically connected to the second gold layer 5 on the back side of the device through the via 13, thereby forming a low-impedance source ground path. Since the via 13 region is provided with the second composite conductive layer 4, the semiconductor device structure can better maintain the stability of the back hole metal morphology during subsequent surface mounting, sintering, or soldering packaging processes, reducing poor contact, open circuits, local stress concentration, or reliability degradation caused by back hole collapse.

[0096] Furthermore, in subsequent encapsulation, the encapsulation solder material contacts and forms a connection with the second gold layer 5. Because the second gold layer 5 has a relatively large thickness, it can provide sufficient solder metal and a low-impedance electrical connection. Since the second composite conductive layer 4 is located between the first gold layer 3 and the second gold layer 5 within the through-hole 13, it can maintain the support strength of the through-hole 13 region when the second gold layer 5 and the encapsulation solder material undergo partial fusion, reducing the possibility of the Au metal in the through-hole 13 collapsing downwards due to softening or flow.

[0097] In this embodiment, the via 13 can be a back via, and the first composite conductive layer 2, the first gold layer 3, the second composite conductive layer 4, and the second gold layer 5 can together constitute the back via metal layer. The back via metal layer not only enables the electrical connection between the metal layer 12 to be led out and the back of the device, but also undertakes certain functions of heat conduction and encapsulation connection. By placing the second composite conductive layer 4 in the region of the via 13, the reliability of the back via structure can be improved without significantly sacrificing the solderability of the back metal, making it suitable for high-frequency, high-power semiconductor devices or those with high grounding reliability requirements.

[0098] It should also be noted that both the first composite conductive layer 2 and the second composite conductive layer 4 in this embodiment may include a two-layer structure. However, it is not excluded that a transition layer, barrier layer, protective layer, or other functional layer may be further provided between the adhesion layer and the first seed layer, between the support layer and the second seed layer, or above or below them. As long as the second composite conductive layer 4 includes the support layer for supporting the metallization structure of the via 13 region and is located between the first gold layer 3 and the second gold layer 5, the technical effect of improving the collapse resistance of the via 13 can be achieved.

[0099] In summary, the semiconductor device structure and fabrication method of the present invention, by sequentially distributing a first composite conductive layer, a first gold layer, a second composite conductive layer, and a second gold layer within a via that penetrates the substrate and exposes the metal layer to be led out, and on the second side of the substrate, and by having the second composite conductive layer cover the first gold layer located within the via and extending a predetermined distance from the edge of the via opening outwards, and by having a support layer in the second composite conductive layer sandwiched between the first and second gold layers and mainly distributed in the corresponding region of the via, a continuous and reliable conductive lead-out path can be formed between the metal layer to be led out and the second side of the substrate. Simultaneously, the support layer enhances the mechanical support strength and thermal deformation resistance of the metal stack in the via region, solving the problem of packaging and soldering issues in existing semiconductor devices. This invention addresses the problem of via collapse caused by material fusion with the metal layer inside the via, softening of the gold layer due to heat, or deformation under packaging pressure. Furthermore, because the second composite conductive layer only covers the first gold layer inside the via and extends a predetermined distance outward, the surface of the first gold layer not covered by the second composite conductive layer can still directly contact the second gold layer. This ensures good metal continuity, conductivity, and interfacial bonding between the via and the packaging solder, preventing the support layer from being widely distributed and affecting the reliable connection between the back metal layer and the packaging solder material. Ultimately, it achieves a balance between the via's anti-collapse capability, the reliability of the back lead-out of the metal layer, the conductivity of the back metal, and the reliability of the packaging connection, thereby improving the packaging yield and long-term reliability of semiconductor devices. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device structure, characterized in that, The preparation method includes: An intermediate structure is provided, the intermediate structure including a substrate having opposing first and second sides, a metal layer to be led out located on the first side of the substrate, and a via penetrating the substrate and exposing the metal layer to be led out; A first composite conductive layer is formed, which covers the surface of the second side of the substrate, the side of the via, and the metal layer to be led out exposed by the via. The first composite conductive layer includes an adhesion layer and a first seed layer stacked sequentially. A first gold layer is formed on the surface of the first seed layer away from the adhesion layer; A second composite conductive layer is formed, which covers the first gold layer located within the through hole and extends a predetermined distance from the edge of the through hole opening to the outside of the through hole; wherein, the second composite conductive layer includes a support layer and a second seed layer stacked sequentially; A second gold layer is formed on the surface of the second seed layer away from the support layer and on the surface of the first gold layer not covered by the second composite conductive layer.

2. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: The thickness of the second gold layer is greater than or equal to the thickness of the first gold layer.

3. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: The material of the adhesion layer includes one or more combinations of Ti, Ni, W, TiW, and NiW, the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW, the first seed layer is an Au layer, and the second seed layer is an Au layer.

4. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: The first composite conductive layer is formed by sputtering deposition, the second composite conductive layer is formed by sputtering deposition, the first gold layer is formed by electroplating, and the second gold layer is formed by electroplating.

5. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, After the second gold layer is formed, the process also includes: A patterned photoresist layer is formed on the side of the second gold layer away from the substrate; Using the patterned photoresist layer as a mask, the second gold layer and the first gold layer in the dicing area are etched away. Remove the patterned photoresist layer and etch away the first composite conductive layer in the dicing area.

6. The method for fabricating a semiconductor device structure according to claim 1, characterized in that: Before forming the first composite conductive layer, the first side of the substrate is bonded to the sapphire carrier using bonding wax; after forming the second gold layer, the substrate and the sapphire carrier are debonded.

7. A semiconductor device structure, characterized in that, The semiconductor device structure includes: A substrate having a first side and a second side opposite to each other; The metal layer to be brought out is located on the first side of the substrate; A via, penetrating the substrate and exposing the metal layer to be brought out; A first composite conductive layer covers the surface of the second side of the substrate, the side of the via, and the metal layer to be led out exposed by the via. The first composite conductive layer includes an adhesion layer and a first seed layer stacked sequentially. The first gold layer is located on the surface of the first seed layer away from the adhesion layer; A second composite conductive layer covers the first gold layer located within the through hole and extends a predetermined distance from the edge of the through hole opening to the outside of the through hole; wherein, the second composite conductive layer includes a support layer and a second seed layer stacked sequentially. The second gold layer is located on the surface of the second seed layer away from the support layer and on the surface of the first gold layer that is not covered by the second composite conductive layer.

8. The semiconductor device structure according to claim 7, characterized in that: The preset distance is 0.5μm~2.5μm.

9. The semiconductor device structure according to claim 7, characterized in that: The thickness of the second gold layer is greater than or equal to the thickness of the first gold layer.

10. The semiconductor device structure according to claim 7, characterized in that: The material of the adhesion layer includes one or more combinations of Ti, Ni, W, TiW, and NiW; the material of the support layer includes one or more combinations of Ti, Ni, W, TiW, and NiW.

11. The semiconductor device structure according to claim 7, characterized in that: The adhesion layer is a TiW layer, the first seed layer is an Au layer, the thickness of the adhesion layer is 60nm~100nm, and the thickness of the first seed layer is 200nm~500nm; the support layer is a TiW layer, the second seed layer is an Au layer, the thickness of the support layer is 200nm~300nm, and the thickness of the second seed layer is 100nm~200nm.

12. The semiconductor device structure according to claim 7, characterized in that: The substrate is a SiC substrate, and the intermediate structure further includes an epitaxial layer formed between the SiC substrate and the metal layer to be led out, wherein the metal layer to be led out is a source metal layer.

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