A via patterning method and system for semiconductor processes

Abstract

The application provides a connection hole patterning method of a semiconductor process, a semiconductor structure formed by using the connection hole patterning method, and a patterning system. The connection hole patterning method is used for forming a semiconductor structure containing multiple connection holes, and the multiple connection holes include at least one group of connection holes, and each group of connection holes includes two connection holes with a center distance less than or equal to a first preset distance. The connection hole patterning method and system of the semiconductor process provided by the application are obviously superior to the guided self-assembly lithography technology and the multiple patterning technology in the prior art in the case that the center distance of two holes is far away from the intrinsic period of block copolymer, and the self-top-down guided self-assembly lithography technology is used to improve the problem that the yield of the formed product is low due to the instability of photoresist caused by heat in the self-bottom-up guided self-assembly lithography technology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and system for patterning interconnect holes in semiconductor processes. Background Technology

[0002] With the development of integrated circuit technology, people's demands for integrated circuits in terms of computing power, processing speed, and data transmission efficiency are increasing. Therefore, it is necessary to manufacture chips with higher integration levels to meet the demand for more efficient information processing. Chip integration level refers to the number of electronic components that can be integrated per unit area of ​​the chip. Higher integration level means the chip can accommodate more functional units, thus achieving more efficient information processing. To improve chip integration level, stacking technology is often used to integrate different functional units vertically into a single unit, forming a multi-layer structure. This increases the number of electronic components integrated per unit area. Multiple interconnecting holes are often used between different layers to achieve electrical connections. Existing technologies often employ Directed Self-Assembly (DSA) lithography or multi-patterning lithography to fabricate these interconnecting holes.

[0003] Guided self-assembly lithography is an advanced lithography technique based on the self-assembly principle of block copolymers. It uses a specific guiding mechanism to transfer nanoscale self-assembled patterns onto a substrate, thereby achieving ultra-high resolution pattern fabrication. Existing guided self-assembly techniques employ a bottom-up approach to fabricate the target pattern. The main steps include: first, fabricating a guide template on a wafer using traditional lithography techniques; then, coating the guide template with block copolymer material and performing self-assembly under appropriate conditions; during self-assembly, the block copolymer molecules spontaneously form an ordered structure based on their chemical properties, thus replicating a pattern finer than the guide template; finally, through etching and other process steps, transferring the self-assembled pattern of the block copolymer into the target material layer on the wafer to form the final target pattern. Existing guided self-assembly (DSA) lithography techniques often employ elliptical or racetrack-shaped guide templates when fabricating target patterns containing multiple interconnecting holes. These guide templates are only suitable for creating patterns between two interconnecting holes with a hole spacing close to the intrinsic period of the block copolymer material. When fabricating patterns between two interconnecting holes with a hole spacing significantly different from the intrinsic period of the block copolymer material, the resulting pattern deviates considerably from the target pattern. Furthermore, the spacing between multiple guide templates is also limited by the lithography size. Based on current lithography sizes, the minimum spacing between two guide templates can be around 80 nm. Therefore, when the spacing between two interconnecting holes exceeds the distance supported by an elliptical or racetrack-shaped guide template but is less than the minimum spacing between guide templates, existing DSA techniques cannot be used.

[0004] The core of multi-patterning technology is to break down the fabrication of multiple closely spaced interconnects, which are difficult to produce in a single photolithography process, into multiple etching steps. Each step uses a single photolithography process to create multiple interconnects that are farther apart. Through multiple etching processes, the desired pattern is finally formed. However, multi-patterning technology has certain limitations in fabricating multiple interconnect patterns. This technology requires splitting the process into multiple photomasks and exposing them sequentially, resulting in complex steps. Furthermore, it must account for errors such as overlay accuracy, which can lead to significant deviations in the feature size and spacing of the fabricated interconnects, affecting product yield.

[0005] To address the aforementioned problems, the present invention provides a method and system for patterning interconnect holes in semiconductor processes. Summary of the Invention

[0006] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0007] To overcome the above-mentioned defects, the present invention aims to provide a method and system for patterning interconnects in semiconductor processes, so as to make up for the shortcomings of existing guided self-assembly photolithography technology and multiple patterning technology in the fabrication of interconnects.

[0008] According to one aspect of the present invention, a method for patterning interconnects in a semiconductor process is provided for forming a semiconductor structure containing a plurality of interconnects, wherein the plurality of interconnects includes at least one group of interconnects, and each group of interconnects includes two interconnects with a centroid distance less than or equal to a first preset distance.

[0009] In one embodiment, the interconnect patterning method includes: sequentially forming a planarization layer, an anti-reflection layer, and a photoresist layer on a substrate; performing photolithography on the photoresist layer and generating a guide pattern corresponding to each group of interconnects, the guide pattern including two first patterns respectively centered on one of the group of interconnects and a connecting portion connecting the two first patterns, the diameter of the first pattern being greater than a first dimension and less than twice the first dimension, and the width of the connecting portion being less than the first dimension; etching the anti-reflection layer and the planarization layer using the guide pattern as a mask to form a guide template in the anti-reflection layer and the planarization layer; introducing a block copolymer into the guide template, the block copolymer undergoing phase separation within the guide template to form a first block distributed along the sidewall of the guide template and a second block surrounded by the first block; etching the block copolymer using a selective etching method to remove the second block; and etching the substrate using the remaining first block and the guide template as a mask to form a target pattern corresponding to the group of interconnects on the substrate.

[0010] Furthermore, etching the antireflective layer and planarization layer using the guide pattern as a mask includes: using the guide pattern as a mask to perform dry etching of the antireflective layer with fluorine-based gas to form a guide pattern on the antireflective layer; and using the guide pattern formed on the antireflective layer as a mask to etch the planarization layer with oxygen to form a guide template on the planarization layer.

[0011] In one embodiment, the thickness of the planarization layer is 100–200 nm.

[0012] Optionally, the thickness of the anti-reflective layer is less than 50 nm.

[0013] In one embodiment, the first preset distance is 85-95 nm.

[0014] Optionally, the first size is the intrinsic period of the block copolymer.

[0015] Furthermore, introducing block copolymers into the guide template includes: treating the guide template using a molecular brush grafting process; and coating the surface of the guide template with block copolymers and using a hot plate annealing process to cause the block copolymers to separate phases within the guide template, thereby forming a first block and a second block.

[0016] Furthermore, in the molecular brush grafting process, the molecular brush coating thickness is full coating, the hot plate annealing temperature is 200-300℃, the annealing time is less than 10 minutes, and the rinsing time is 30-60 seconds.

[0017] Optionally, the coating thickness of the block copolymer is 150–300 nm, the hot plate annealing temperature is 200–300 °C, and the annealing time is less than 10 min.

[0018] In one embodiment, the block copolymer is a polymer of styrene-b-methyl methacrylate, styrene-b-vinylpyridine, styrene-b-butadiene, styrene-b-isoprene, styrene-b-methyl methacrylate, styrene-b-alkenyl aromatic compounds, isoprene-b-ethylene oxide, butadiene-b-ethylene oxide, styrene-b-tert-butyl methacrylate, styrene-b-tetrahydrofuran, or styrene-b-methyl methacrylate, or a combination of polymers thereof.

[0019] In one embodiment, the block copolymer is a styrene-b-methyl methacrylate polymer, and in the step of selectively etching the guide template to remove the second block in the guide template, the etching selection ratio of the second block to the first block is greater than or equal to 2:1.

[0020] Furthermore, selectively etching the guide template to remove the second segment in the guide template includes:

[0021] The phase-separated methyl methacrylate polymer is completely etched away using dry etching, wherein the etching gas is one or any combination of O2, CO, and CO2.

[0022] Furthermore, the substrate includes a substrate and a hard mask on the substrate, the hard mask being a presentation layer of the target pattern, and the etching selection ratio of the hard mask and styrene is greater than or equal to 1.3:1.

[0023] In one embodiment, the hard mask is made of SiN, SiO2, or TiN material, and the thickness of the hard mask is less than 50 nm.

[0024] According to another aspect of the present invention, a semiconductor layout splitting method is provided, the semiconductor layout splitting method comprising: obtaining an original layout, the original layout having a plurality of interconnects, the plurality of interconnects including at least one set of paired interconnects, the paired interconnects including two interconnects with a design spacing less than or equal to a first preset distance; and splitting the original layout into a plurality of secondary layouts, wherein each set of paired interconnects is split into the same secondary layout.

[0025] According to another aspect of the present invention, a semiconductor structure is provided, including a substrate and a target pattern formed on the substrate, the target pattern being formed using the above-described interconnect patterning method.

[0026] According to another aspect of the present invention, a patterning system for semiconductor processes is provided, including a photolithography apparatus and an etching apparatus, wherein the photolithography apparatus and the etching apparatus cooperate to implement the above-described interconnect hole patterning method.

[0027] This invention provides a method and system for patterning interconnect holes in semiconductor processes. When the distance between the centroids of the two holes differs significantly from the intrinsic period of the block copolymer, the technical effect achieved is significantly better than the existing guided self-assembly lithography and multiple patterning techniques. Furthermore, by utilizing top-down guided self-assembly lithography, the problem of low product yield caused by the instability of photoresist when heated in bottom-up guided self-assembly lithography is improved. Attached Figure Description

[0028] The above-described features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of this disclosure in conjunction with the following accompanying drawings.

[0029] Figure 1 This is a schematic diagram of a semiconductor structure containing multiple connection holes in a specific embodiment provided according to one aspect of the present invention.

[0030] Figure 2 A schematic flowchart of a semiconductor process interconnect patterning method is shown in a specific embodiment.

[0031] Figure 3 A side cross-sectional schematic diagram of the initial semiconductor structure formed by the interconnect patterning method in a specific embodiment is shown.

[0032] Figure 4A A side cross-sectional view of a semiconductor structure containing a guide pattern formed in a specific embodiment is shown.

[0033] Figure 4B A top view of the semiconductor structure containing the guide pattern formed in this specific embodiment is shown.

[0034] Figure 4C A top view of a semiconductor structure containing a guide pattern is shown in another specific embodiment.

[0035] Figure 4D A top view of a semiconductor structure containing a guide pattern is shown in yet another specific embodiment.

[0036] Figure 5 A side cross-sectional view of a semiconductor structure including a guide template formed in a specific embodiment is shown.

[0037] Figure 6 A side cross-sectional view of a semiconductor structure formed after introducing a block copolymer into a guide template is shown in a specific embodiment.

[0038] Figure 7 A side cross-sectional schematic diagram of a semiconductor structure formed after selectively etching a portion of a block copolymer is shown in a specific embodiment.

[0039] Figure 8 A side cross-sectional schematic diagram of a semiconductor structure in which a target pattern is etched on a substrate is shown in a specific embodiment.

[0040] Figure 9 This is a simplified schematic diagram of a patterning system according to another aspect of the present invention.

[0041] For clarity, a brief explanation of the reference numerals in the accompanying drawings is provided below:

[0042] Connection holes 101-104;

[0043] 105-106 grouped connection holes;

[0044] 301 substrate;

[0045] 302 planarization layer;

[0046] 303 anti-reflective layer;

[0047] 304 photoresist layer;

[0048] 301a substrate;

[0049] 301b hard mask;

[0050] 41. Guiding graphics;

[0051] 411 First figure;

[0052] 412 Connecting part;

[0053] 51. Guide Template;

[0054] 60 block copolymer;

[0055] 61 First block;

[0056] 62 Second block;

[0057] 71 cylindrical slots;

[0058] 81 Target Pattern. Detailed Implementation

[0059] The following description is provided to enable those skilled in the art to implement and use the invention and adapt it to specific application contexts. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to a wide range of embodiments. Therefore, the invention is not limited to the embodiments given herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0060] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that practice of the invention is not necessarily limited to these specific details. In other words, well-known structures and devices are shown in block diagram form without being depicted in detail to avoid obscuring the invention.

[0061] Readers should note all documents and references submitted concurrently with this specification and open to public inspection, the contents of which are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes. Therefore, unless explicitly stated otherwise, each disclosed feature is merely one example of a set of equivalent or similar features.

[0062] Note that, where used, the markings left, right, front, back, top, bottom, front, back, clockwise, and counterclockwise are merely for convenience and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and / or orientation between different parts of an object. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0063] Note that, in practice, "further," "preferably," "even further," and "more preferably" are simply starting points for describing another embodiment based on the foregoing embodiments. The combination of the content following "further," "preferably," "even further," or "more preferably" with the foregoing embodiments constitutes the complete configuration of another embodiment. Any combination of several "further," "preferably," "even further," or "more preferably" settings following the same embodiment can form yet another embodiment.

[0064] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0065] According to one aspect of the present invention, a method for patterning interconnect holes in a semiconductor process is provided. The interconnect hole refers to a structure used in the integrated circuit manufacturing process to achieve electrical connections between different layers, such as contact holes or through-holes. This interconnect hole patterning method can be used to form semiconductor structures containing multiple interconnect holes, particularly semiconductor structures containing groups of interconnect holes.

[0066] A group of connecting holes refers to two connecting holes whose centroids are less than or equal to a first preset distance.

[0067] Figure 1A schematic diagram of a semiconductor structure containing multiple interconnect holes is shown in a specific embodiment. For example... Figure 1 As shown, the semiconductor structure includes multiple interconnects 101, 102, 103, and 104. Interconnects 101 and 102 form a group of interconnects 105. For Figure 1 For the circular connecting holes shown, the distance between the centroids refers to the distance between the centers of connecting holes 101 and 102. Those skilled in the art will understand that for connecting holes of other geometries, the centroid refers to the geometric center of each connecting hole.

[0068] The first preset distance refers to the minimum allowable spacing between two non-grouped interconnects due to the limitations of photolithography size in existing DSA technology. In some embodiments, the first preset distance can be set according to the minimum spacing between guide templates in existing DSA technology and the intrinsic period of the block copolymer used in this embodiment, for example, it can be 85-95 nm. It should be noted that the interconnect patterning method for semiconductor processes provided by the present invention is also applicable to the patterning of grouped interconnects with a centroid distance greater than the first preset distance. However, when the defined centroid distance is less than or equal to the first preset distance, the technical effect achieved is significantly better than that of the prior art.

[0069] Figure 2 A schematic flowchart of a semiconductor process interconnect patterning method is shown in a specific embodiment. Figures 3-8 It shows the use of Figure 2 This is a schematic diagram of a semiconductor structure formed by the interconnect patterning method shown. Wherein, Figure 3 A side cross-sectional schematic diagram of the initial semiconductor structure formed by the interconnect patterning method in a specific embodiment is shown. Figure 4A A side cross-sectional view of a semiconductor structure containing a guide pattern formed in a specific embodiment is shown. Figure 4B A top view of the semiconductor structure containing the guide pattern formed in this specific embodiment is shown. Figure 4C A top view of a semiconductor structure containing a guide pattern is shown in another specific embodiment. Figure 4D A top view of a semiconductor structure containing a guide pattern is shown in yet another specific embodiment. Figure 5 A side cross-sectional view of a semiconductor structure including a guide template formed in a specific embodiment is shown. Figure 6 A side cross-sectional view of a semiconductor structure formed after introducing a block copolymer into a guide template is shown in a specific embodiment. Figure 7 A side cross-sectional schematic diagram of a semiconductor structure formed after selectively etching a portion of a block copolymer is shown in a specific embodiment. Figure 8A side cross-sectional schematic diagram of a semiconductor structure in which a target pattern is etched on a substrate is shown in a specific embodiment.

[0070] Reference Figure 2 The method for patterning the connection hole may include the following steps S21 to S26.

[0071] Step S21 is: sequentially forming a planarization layer, an anti-reflection layer, and a photoresist layer on the substrate.

[0072] The substrate refers to the layer in which the target pattern is formed, corresponding to the connecting hole.

[0073] For example, in such Figure 3 In the illustrated embodiment, a planarization layer 302, an anti-reflection layer 303, and a photoresist layer 304 are formed on the substrate 301. Specifically, in this embodiment, the substrate 301 includes a substrate 301a and a hard mask 301b. Those skilled in the art will understand that in other embodiments, the substrate may also be a target patterning layer structure composed of other structures or materials.

[0074] A planarization layer is a layered structure formed to achieve planarization of the substrate surface. Those skilled in the art will understand that the planarization layer can be an existing or future planarization layer material such as spin-on carbon (SOC) or spin-on glass (SOG). Preferably, the thickness of the planarization layer is 100–200 nm to meet subsequent etching requirements.

[0075] The anti-reflective layer is a layered structure formed by anti-reflective materials that reduce surface light reflection. Those skilled in the art will understand that the anti-reflective layer can be an existing or future anti-reflective layer such as a silicon-containing anti-reflective layer, a fluorine-containing anti-reflective layer, or a nitride anti-reflective layer. Preferably, to achieve better photolithography results, the thickness of the anti-reflective layer 303 is less than 50 nm.

[0076] A photoresist layer is a layered structure composed of photoresist materials. Those skilled in the art will understand that the photoresist layer can be composed of existing or future photoresist materials such as i-line photoresist, krypton fluoride photoresist (KrF), argon fluoride (ArF) photoresist, argon fluoride immersion (ArFi) photoresist, and extreme ultraviolet (EUV) photoresist. Furthermore, the photoresist material can be either positive or negative; the specific type of photoresist can be selected by those skilled in the art.

[0077] For example, the planarization layer can be formed by processes such as chemical mechanical polishing, spin coating, or deposition. The anti-reflective layer can be formed by processes such as spin coating, specific coating, or deposition. The photoresist layer can be formed by processes such as spin coating, static coating, or dynamic spraying. This invention does not limit the specific formation methods of the planarization layer, anti-reflective layer, and photoresist layer.

[0078] Those skilled in the art will understand that step S21 is used to form an initial semiconductor structure, but in practical applications, the formation order and process of multiple structures in this step may be different depending on the application scenario, and may even cover other transitional structural layers.

[0079] Step S22 is: performing photolithography on the photoresist layer and generating guide patterns corresponding to each group of interconnect holes.

[0080] For example, such as Figure 4A and Figure 4B In the embodiment shown, after photolithography is performed on the photoresist layer 304, a guide pattern 41 is generated on the photoresist layer 304.

[0081] For example, in the photolithography step of the photoresist layer, the exposure light source varies depending on the type of photoresist selected. For instance, for photoresists such as ultraviolet (i-line) photoresist, krypton fluoride photoresist (KrF) photoresist, argon fluoride (ArF) photoresist, immersion argon fluoride (ArFi) photoresist, or extreme ultraviolet (EUV) photoresist, ultraviolet light, krypton fluoride (KrF) excimer laser, argon fluoride (ArF) excimer laser, and extreme ultraviolet light can be used as the exposure light source, respectively.

[0082] The guide graphic refers to the planar graphic corresponding to the photomask of the guide template.

[0083] For example, the generated guide pattern includes two first patterns, each with one of the grouped connecting holes as its centroid, and a connecting portion connecting the two first patterns.

[0084] In some embodiments, refer to Figure 4B The guide graphic 41 includes two circular first graphics 411 and a strip-shaped connecting portion 412 connecting the two first graphics 411.

[0085] In other embodiments, reference is made to Figure 4CThose skilled in the art will understand that the length of the connecting portion 412 can be greater than or equal to 0. That is, when the distance between the two connecting holes is relatively close, the length of the connecting portion 412 can be 0, in which case the two first patterns 411 partially overlap.

[0086] Furthermore, the diameter of the first shape is greater than the first dimension but less than twice the first dimension, and the width of the connecting part is less than the first dimension.

[0087] The first dimension refers to the intrinsic period of the block copolymer used. In principle, under certain temperature conditions, block copolymers undergo microscopic phase separation to form repeating periodic structures such as layered, columnar, or spherical structures. The characteristic length of the periodic structure is the intrinsic period of the block copolymer.

[0088] The diameter of the first pattern being greater than the first size but less than twice the first size means that the diameter of the first pattern can accommodate one and only one characteristic length of block copolymer. The width of the connecting portion refers to the dimension of the connecting portion perpendicular to the extension direction of the line connecting the centroids of the two first patterns it connects, such as... Figure 4B The dimension of the width 413 of the connecting part 412 shown.

[0089] It should be noted that the first size will vary depending on the type of block copolymer used. Those skilled in the art can select block copolymers with different intrinsic periods according to the actual design size of the connecting hole. Generally speaking, the size of the connecting hole formed by a certain block copolymer is about 1 / 3 of the intrinsic period of that block copolymer.

[0090] Step S23 is: using the guide pattern as a mask to etch the anti-reflection layer and the planarization layer to form a guide template on the anti-reflection layer and the planarization layer.

[0091] For example, with Figure 4A The guide pattern 41 in the image is used as a mask to etch the anti-reflection layer 302 and the planarization layer 303, which can form a pattern such as... Figure 5 The guide template 51 shown.

[0092] In some embodiments, the antireflection layer 302 and the planarization layer 303 may be etched using existing or future etching methods, such as dry etching methods like plasma etching, ion beam etching, or reactive ion etching.

[0093] In some embodiments, the antireflective layer 302 may be etched using one or more of fluorine-based gases, oxygen, argon, and helium as the etching gas. The planarization layer 303 may be etched using one or more of oxygen, carbon dioxide, nitrogen, and hydrogen as the etching gas.

[0094] In some specific embodiments, step S23 can be specified as: using the guide pattern as a mask, dry etching of the antireflective layer with fluorine-based gas to form the guide pattern on the antireflective layer; and using the guide pattern formed on the antireflective layer as a mask, etching of the planarization layer with oxygen to form the guide template on the planarization layer.

[0095] A guide template is a three-dimensional pattern etched into the planarization layer with the same shape as the guide pattern. The main function of the guide template is to guide the self-assembly of block copolymers to form a specific shape.

[0096] It should be noted that any connecting hole in any group of connecting holes can also form a new group of connecting holes with other connecting holes, so that multiple connecting holes can be drawn using a guide graphic. For example, in... Figure 4D In the illustrated embodiment, connecting holes 101 and 102 constitute a group of connecting holes 105. Simultaneously, connecting hole 102 and connecting hole 103 can also constitute another group of connecting holes 106. Those skilled in the art will understand that a guide pattern may contain one or more groups of connecting holes, and multiple groups of connecting holes may share common connecting holes.

[0097] Those skilled in the art will understand that step S23 is used to etch the guide pattern of the photoresist layer downward into the planarization layer to form a three-dimensional guide template. In practical applications, depending on the application scenario, those skilled in the art can choose existing or future etching techniques for etching.

[0098] Step S24 is: introducing a block copolymer into the guide template, wherein the block copolymer separates phases within the guide template to form a first block distributed along the sidewall of the guide template and a second block surrounded by the first block.

[0099] Block polymers are polymers composed of different chain segments linked by covalent bonds.

[0100] For example, the block copolymer can be a polymer of styrene-b-methyl methacrylate, styrene-b-vinylpyridine, styrene-b-butadiene, styrene-b-isoprene, styrene-b-methyl methacrylate, styrene-b-alkenyl aromatic compounds, isoprene-b-ethylene oxide, butadiene-b-ethylene oxide, styrene-b-tert-butyl methacrylate, styrene-b-tetrahydrofuran, or styrene-b-methyl methacrylate, or a combination of polymers thereof.

[0101] For example, the introduction of block copolymers into the guide template can be achieved through existing or future block copolymer immobilization processes such as physical adsorption, ion exchange, electrostatic self-assembly, chemical precipitation, or chemical grafting.

[0102] In some specific embodiments, the introduction of block copolymers into the guide template can be achieved through a molecular brush grafting process. The guide template is treated using a molecular brush grafting process, and then the surface of the molecular brush grafted guide template is coated with the block copolymer to bond and fix the treated guide template to the block copolymer.

[0103] For example, the phase separation of block copolymers within a guided template can be achieved by existing or future phase separation processes such as laser annealing, microwave annealing, solvent vapor annealing, or hot plate annealing.

[0104] In some specific embodiments, a hot plate annealing process is used to cause the block copolymer to separate phases within a guiding template to form a first block and a second block.

[0105] To achieve better phase separation, the preferred method in the molecular brush grafting process is to use a full-coat molecular brush, a hot plate annealing temperature of 200–300°C, an annealing time of less than 10 min, and a rinsing time of 30–60 s.

[0106] Optionally, the coating thickness of the block copolymer is 150–300 nm, the hot plate annealing temperature is 200–300 °C, and the annealing time is less than 10 min.

[0107] The first block refers to the block that is closer to the guiding template after phase separation, and the second block refers to the block copolymer that is farther away from the guiding template after phase separation. Preferably, in some embodiments, the first block can be a non-etchable material, and the second block can be an etchable material. For example, in an embodiment using a styrene-b-methyl methacrylate polymer as the block copolymer, the first block is styrene, and the second block is methyl methacrylate. It is understood that during the phase separation of etchable and non-etchable materials, a suitable introducing block copolymer material can be selected based on the characteristics of the etchable and non-etchable materials. For example, in an embodiment using a styrene-b-methyl methacrylate polymer as the block copolymer, a molecular brush material with styrene affinity can be used for introduction.

[0108] exist Figure 6 In the specific embodiment shown, in order to prepare the connecting hole pattern, the block copolymer 60 forms a central cylindrical structure and an outer hollow cylindrical structure surrounding the cylindrical portion within the guiding template. In this embodiment, the polymer in the outer hollow cylindrical structure is the first block 61, and the polymer in the central cylindrical structure surrounded by the first block 61 is the second block 62.

[0109] Step S25 involves etching the block copolymer using a selective etching method to remove the second block.

[0110] Selective etching refers to etching methods that selectively remove certain blocks from a block copolymer while retaining other blocks.

[0111] For example, the selective etching method for removing the second block can be implemented using existing or future selective etching methods such as chemical etching, plasma etching, or photochemical etching.

[0112] In some embodiments, such as those using styrene-b-methyl methacrylate polymer as the block polymer, plasma etching can be used, employing O2, CO, or one or any combination of CO2 as the etching gas, to dry-etch the styrene-b-methyl methacrylate polymer to remove the phase-separated methyl methacrylate. In these specific embodiments, the etching ratio of the second block to the first block is greater than or equal to 2:1.

[0113] For example, such as Figure 7 As shown, after selectively etching the second segment 62, a cylindrical slot 71 is formed on the guide template. The cylindrical slot 71 is formed by being surrounded by the first segment 61 and can be used as a mask for the connection hole structure in subsequent processes.

[0114] Step S26 is: using the remaining first segment and the guide template as a mask to etch the substrate to form a target pattern on the substrate corresponding to the group of connecting holes.

[0115] More specifically, in Figure 3 In the illustrated embodiment, substrate 301a can be an existing or future substrate material such as a silicon substrate, gallium arsenide substrate, gallium nitride substrate, or silicon carbide substrate. Hard mask 301b can be an existing or future hard mask material such as SiN, SiO2, or TiN. The thickness of the hard mask can be set as needed; preferably, to achieve good etching effect, the thickness of the hard mask is less than 50 nm.

[0116] In some embodiments, etching of the substrate can be achieved using existing or future etching methods such as chemical etching, plasma etching, or photochemical etching.

[0117] In some specific embodiments, such as Figure 8 As shown, the hard mask is the presentation layer of the target pattern. Step S26 can be further refined to: etching the hard mask 301b to form the target pattern 81 corresponding to the group of interconnecting holes on the hard mask 301b.

[0118] In one specific embodiment, SiN material is selected as the material of the hard mask, and styrene-b-methyl methacrylate polymer is selected as the block copolymer. Then, plasma etching can be used to etch the hard mask, and fluorine-based gas is used as the etching gas. During the etching process of the hard mask, the etching selectivity ratio of the hard mask to styrene is greater than or equal to 1.3:1.

[0119] According to another aspect of the present invention, a semiconductor layout splitting method is also included, the semiconductor layout splitting method comprising: obtaining an original layout, the original layout having a plurality of interconnects, the plurality of interconnects including at least one set of paired interconnects, the paired interconnects including two interconnects with a design spacing less than or equal to a first preset distance; and splitting the original layout into a plurality of secondary layouts, wherein each set of paired interconnects is split into the same secondary layout.

[0120] In its invention application CN117784516A, the inventors disclosed a layout splitting method for advanced process contact hole / through-hole fabrication. The disclosed layout splitting method includes the following steps:

[0121] (1) For the original layout, based on the hole multiplication capability of the physical extension method-guided self-assembly technology, each hole pattern is grouped, wherein hole patterns with a distance less than or equal to a predetermined value are paired and grouped.

[0122] (2) For each group after grouping in step (1), set the size and shape of the guide template for each group;

[0123] (3) Based on the grouping results in step (1) and the size and shape of the guide template for each group set in step (2), adjust the graphic size of the original layout to generate the guide template layout;

[0124] (4) According to the first layout splitting method, the guide template layout generated in step (3) is split to obtain multiple splitting layers. The first layout splitting method includes the following principle: the minimum spacing between the guide templates of each group after grouping in the same splitting layer is greater than or equal to the resolution of the lithography machine used to manufacture the guide template.

[0125] Obviously, the main difference between the layout splitting method provided by this invention and the published layout splitting method is that the secondary layout split by the layout splitting method provided by this invention may include two pairs of connecting holes with a design spacing less than or equal to a first preset distance. These pairs of connecting holes on the secondary layout can be formed using the connecting hole patterning method provided by this invention.

[0126] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments. According to another aspect of the invention, a semiconductor structure is also included, comprising a substrate and a target pattern formed on the substrate, the target pattern being formed using the steps of the interconnect patterning method mentioned in any of the foregoing embodiments.

[0127] According to another aspect of the invention, a patterning system for semiconductor processes is also included, such as... Figure 9 As shown, the patterning system includes a photolithography device 91 and an etching device 92, which work together to implement the connection hole patterning method mentioned in any of the above embodiments.

[0128] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. However, it should be understood that the scope of protection of this invention should be determined by the appended claims and should not be limited to the specific structures and components of the embodiments described above. Various changes and modifications can be made to the embodiments by those skilled in the art within the spirit and scope of this invention, and these changes and modifications also fall within the scope of protection of this invention.

Claims

1. A method for patterning interconnect holes in semiconductor processes, characterized in that, For forming a semiconductor structure containing multiple interconnect holes, the multiple interconnect holes include at least one group of interconnect holes, each group of interconnect holes including two interconnect holes with a centroid distance less than or equal to a first preset distance, the interconnect hole patterning method includes: A planarization layer, an anti-reflection layer, and a photoresist layer are sequentially formed on the substrate; The photoresist layer is photolithographically etched, and a guide pattern corresponding to each group of interconnecting holes is generated. The guide pattern includes two first patterns with one of the group of interconnecting holes as the centroid and a connecting portion connecting the two first patterns. The diameter of the first pattern is greater than a first size but less than twice the first size, and the width of the connecting portion is less than the first size. The anti-reflection layer and the planarization layer are etched using the guide pattern as a mask to form a guide template on the anti-reflection layer and the planarization layer; A block copolymer is introduced into the guide template, and the block copolymer is phase-separated within the guide template to form a first block distributed along the sidewall of the guide template and a second block surrounded by the first block; The block copolymer is etched using a selective etching method to remove the second block; and The substrate is etched using the remaining first segment and the guide template as a mask to form a target pattern on the substrate corresponding to the group of connecting holes.

2. The method for patterning connecting holes as described in claim 1, characterized in that, Etching the antireflection layer and the planarization layer using the guide pattern as a mask includes: Using the guide pattern as a mask, the anti-reflective layer is dry-etched with a fluorine-based gas to form the guide pattern on the anti-reflective layer; and Using the guide pattern formed by the anti-reflective layer as a mask, oxygen is used to etch the planarization layer to form the guide template on the planarization layer.

3. The method for patterning connecting holes as described in claim 1 or 2, characterized in that, The thickness of the planarization layer is 100–200 nm, and / or the thickness of the antireflection layer is less than 50 nm.

4. The method for patterning connecting holes as described in claim 1, characterized in that, The first preset distance is 85-95 nm, and / or the first size is the intrinsic period of the block copolymer.

5. The method for patterning connecting holes as described in claim 1, characterized in that, Introducing block copolymers within the guiding template includes: The guide template is treated using a molecular brush grafting process; and The block copolymer is coated on the surface of the guide template and then subjected to a hot plate annealing process to separate the block copolymer within the guide template to form the first block and the second block.

6. The method for patterning connecting holes as described in claim 5, characterized in that, In the molecular brush grafting process, the molecular brush coating thickness is full coating, the hot plate annealing temperature is 200–300°C, the annealing time is less than 10 min, and the rinsing time is 30–60 s; and / or The block copolymer has a coating thickness of 150–300 nm, a hot plate annealing temperature of 200–300 °C, and an annealing time of less than 10 min.

7. The method for patterning connecting holes as described in claim 1, characterized in that, The block copolymer is a polymer of styrene-b-methyl methacrylate, styrene-b-vinylpyridine, styrene-b-butadiene, styrene-b-isoprene, styrene-b-methyl methacrylate, styrene-b-alkenyl aromatic compounds, isoprene-b-ethylene oxide, butadiene-b-ethylene oxide, styrene-b-tert-butyl methacrylate, styrene-b-tetrahydrofuran, or styrene-b-methyl methacrylate, or a combination of polymers thereof.

8. The method for patterning connecting holes as described in claim 1, characterized in that, The block copolymer is a styrene-b-methyl methacrylate polymer. In the step of selectively etching the guide template to remove the second block in the guide template, the etching ratio of the second block to the first block is greater than or equal to 2:

1.

9. The method for patterning connecting holes as described in claim 8, characterized in that, Selectively etching the guide template to remove the second segment in the guide template includes: The phase-separated methyl methacrylate polymer is completely etched away using dry etching, wherein the etching gas is one or any combination of O2, CO, and CO2.

10. The method for patterning connecting holes as described in claim 8, characterized in that, The substrate includes a substrate and a hard mask on the substrate, the hard mask being a presentation layer of the target pattern, and the etching selection ratio of the hard mask and styrene being greater than or equal to 1.3:

1.

11. The method for patterning connecting holes as described in claim 10, characterized in that, The hard mask is made of SiN, SiO2, or TiN material, and the thickness of the hard mask is less than 50 nm.

12. A semiconductor layout splitting method, characterized in that, The semiconductor layout splitting method includes: Obtain the original layout, wherein the original layout is designed with multiple connection holes, the multiple connection holes including at least one pair of connection holes, the pair of connection holes including two connection holes with a design spacing less than or equal to a first preset distance; and The original layout is split into several secondary layouts, wherein each set of paired connecting holes is split into the same secondary layout.

13. A semiconductor structure comprising a substrate and a target pattern formed on the substrate, characterized in that, The target pattern is formed using the connection hole patterning method as described in any one of claims 1 to 11.

14. A patterning system for semiconductor processes, comprising photolithography equipment and etching equipment, characterized in that, The photolithography equipment and etching equipment work together to implement the connection hole patterning method as described in any one of claims 1 to 11.

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