A semiconductor structure and a method of fabricating the same
Patent Information
- Application Number
- CN202510354671.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2026-09-29
AI Technical Summary
然而这样的结构往往会造成器件的可靠性降低
[0047]本公开实施例中，使用包括第一电介质层和第二电介质层的介电层(第一电介质层位于基底上，第一电介质层的介电常数不大于2.2；第二电介质层位于第一电介质层上，第二电介质层的介电常数大于第一电介质层的介电常数，第二电介质层的杨氏模量大于第一电介质层的杨氏模量)包围导电层来制备半导体结构(例如包括后段互连结构的半导体结构)，利用介电层的两层电介质层的不同k值和模量的平衡，实现小的寄生电容和稳定的界面膜层质量，能在器件延时和可靠性之间获得平衡，即，既可降低器件延时，又能够改善半导体器件的可靠性。
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Figure CN122847166A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Currently, the interconnect structures formed on integrated circuit chips consist of at least approximately 2-6 conductive layers. In one structure, a low-dielectric-constant dielectric layer is used to surround the conductive layers to improve signal speed and reduce signal crosstalk between adjacent conductive layers. However, such a structure often leads to reduced device reliability. Summary of the Invention
[0003] According to a first aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising:
[0004] The dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the substrate and has a dielectric constant of not more than 2.2. The second dielectric layer is located on the first dielectric layer and has a dielectric constant greater than that of the first dielectric layer. The Young's modulus of the second dielectric layer is greater than that of the first dielectric layer. The first dielectric layer and the second dielectric layer are provided with groove structures, and the groove structures penetrate the first dielectric layer and the second dielectric layer.
[0005] A conductive layer fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
[0006] In some embodiments, the semiconductor structure further includes: a first barrier layer located on the second dielectric layer and the conductive layer, and covering at least a portion of the second dielectric layer and at least a portion of the conductive layer.
[0007] In some embodiments, the semiconductor structure includes a plurality of conductive interconnect units, each conductive interconnect unit including the dielectric layer, the conductive layer and the first barrier layer, wherein each conductive interconnect unit is stacked along the thickness direction of the substrate and is electrically connected to the other conductive interconnect units.
[0008] In some embodiments, the semiconductor structure further includes a second barrier layer located between the substrate and the first dielectric layer, wherein the groove structure extends through the second barrier layer.
[0009] In some embodiments, the dielectric constant of the first barrier layer is greater than the dielectric constant of the second dielectric layer; and / or
[0010] The dielectric constant of the second barrier layer is greater than that of the second dielectric layer.
[0011] In some embodiments, the dielectric constant of the dielectric layer is 2.2-2.4; and / or
[0012] The dielectric constant of the first dielectric layer is 1.8-2.2; and / or
[0013] The dielectric constant of the second dielectric layer is 2.6-3; and / or
[0014] The Young's modulus of the first dielectric layer is 6-8 GPa; and / or
[0015] The Young's modulus of the second dielectric layer is 10-12 GPa; and / or
[0016] The porosity of the first dielectric layer is 28%-32%; and / or
[0017] The porosity of the second dielectric layer is 0%; and / or
[0018] The thickness of the first dielectric layer is 240-320 nm; and / or
[0019] The thickness of the second dielectric layer is 30-60 nm.
[0020] In some embodiments, the material of the first dielectric layer includes silicon carbide; and / or
[0021] The material of the second dielectric layer includes silicon carbide; and / or
[0022] The material of the first barrier layer includes at least one of silicon carbonitride, silicon carbon oxide, silicon nitride, and aluminum oxide; and / or
[0023] The material of the second barrier layer includes at least one of silicon carbonitride, silicon carbon oxide, silicon nitride, and aluminum oxide.
[0024] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:
[0025] A dielectric layer is formed on a substrate, the dielectric layer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer being located on the substrate and having a dielectric constant not greater than 2.2; the second dielectric layer being located on the first dielectric layer and having a dielectric constant greater than that of the first dielectric layer, and having a Young's modulus greater than that of the first dielectric layer.
[0026] A groove structure is formed in the dielectric layer, and the groove structure penetrates the first dielectric layer and the second dielectric layer;
[0027] A conductive layer is formed, which fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
[0028] In some embodiments, the preparation method further includes: forming a first barrier layer on the second dielectric layer and the conductive layer, the first barrier layer covering at least a portion of the second dielectric layer and at least a portion of the conductive layer.
[0029] In some embodiments, the fabrication method further includes: forming a plurality of conductive interconnect units, each conductive interconnect unit including the dielectric layer, the conductive layer and the first barrier layer, wherein each conductive interconnect unit is stacked along the thickness direction of the substrate and is electrically connected to the other conductive interconnect units.
[0030] In some embodiments, the methods for forming the dielectric layer, forming the groove structure, and forming the conductive layer include:
[0031] The first dielectric layer is formed on the substrate;
[0032] An initial second dielectric layer is formed on the first dielectric layer, wherein the dielectric constant of the initial second dielectric layer is greater than that of the first dielectric layer, and the Young's modulus of the initial second dielectric layer is greater than that of the first dielectric layer;
[0033] An initial groove structure is formed in the first dielectric layer and the initial second dielectric layer, the initial groove structure penetrating the first dielectric layer and the initial second dielectric layer;
[0034] An initial conductive layer is formed, which fills the initial groove structure;
[0035] The initial conductive layer and the initial second dielectric layer with a portion of their thickness are removed, and the remaining initial conductive layer is used as the conductive layer, the remaining initial second dielectric layer is used as the second dielectric layer, and the remaining initial groove structure is used as the groove structure. The conductive layer fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
[0036] In some embodiments, the preparation method further includes:
[0037] Before forming the first dielectric layer on the substrate, a second barrier layer is formed on the substrate;
[0038] The initial groove structure is formed in the second barrier layer, the first dielectric layer and the initial second dielectric layer, and the initial groove structure penetrates the second barrier layer, the first dielectric layer and the initial second dielectric layer.
[0039] In some embodiments, the method of forming the first dielectric layer includes:
[0040] In the presence of the precursor material, pore-forming agent and oxygen-containing gas of the first dielectric layer, an initial first dielectric layer is formed under the first deposition conditions.
[0041] The pore-forming agent is removed by UV curing to form the first dielectric layer.
[0042] The first deposition conditions include: a flow rate of 1500-2000 mg / min for the precursor material of the first dielectric layer, a flow rate of 240-280 sccm for the pore-forming agent, a flow rate of 40-60 sccm for the oxygen-containing gas, and a radio frequency power of 500-600 W.
[0043] In some embodiments, the method of forming the initial second dielectric layer includes:
[0044] The initial second dielectric layer is formed under the second deposition conditions in the presence of the precursor material of the second dielectric layer and oxygen-containing gas.
[0045] The second deposition conditions include: a flow rate of 3000-3500 mg / min for the precursor material of the second dielectric layer, a flow rate of 100-120 sccm for the oxygen-containing gas, a power of 500-600 W for high-frequency radio frequency, and a power of 70-100 W for low-frequency radio frequency.
[0046] In some embodiments, the steps of forming the first dielectric layer and forming the initial second dielectric layer are performed on the same machine.
[0047] In this embodiment, a semiconductor structure (e.g., a semiconductor structure including a back-end interconnect structure) is fabricated by surrounding a conductive layer with a dielectric layer comprising a first dielectric layer and a second dielectric layer (the first dielectric layer is located on the substrate, and the dielectric constant of the first dielectric layer is not greater than 2.2; the second dielectric layer is located on the first dielectric layer, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the Young's modulus of the second dielectric layer is greater than the Young's modulus of the first dielectric layer). By utilizing the balance of the different k values and moduli of the two dielectric layers, small parasitic capacitance and stable interface film quality are achieved, which can achieve a balance between device delay and reliability, that is, it can both reduce device delay and improve the reliability of semiconductor devices. Attached Figure Description
[0048] Figure 1 This is a schematic cross-sectional view of a semiconductor structure shown in an exemplary embodiment of the present disclosure;
[0049] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure shown in another exemplary embodiment of the present disclosure;
[0050] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure shown in another exemplary embodiment of the present disclosure;
[0051] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure shown in another exemplary embodiment of the present disclosure;
[0052] Figure 5 This is a process flow diagram illustrating an exemplary embodiment of the present disclosure of a method for fabricating a semiconductor structure;
[0053] Figures 6A to 6H This is a schematic diagram of the steps of a method for fabricating a semiconductor structure according to an exemplary embodiment of this disclosure. Detailed Implementation
[0054] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0055] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0056] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0057] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0058] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0059] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0060] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.
[0061] like Figure 1 As shown, in the related semiconductor structure including the back-end interconnect structure, the second barrier layer 4' is located on the substrate 1', the dielectric layer 2' is located on the second barrier layer 4', and a groove structure 6' is provided in the dielectric layer 2' and the second barrier layer 4', with the groove structure penetrating through the dielectric layer 2' and the second barrier layer 4'. The conductive layer 7' fills the groove structure 6', and the first barrier layer 5' is located on the dielectric layer 2' and the conductive layer 7'. In this semiconductor structure, a low dielectric constant dielectric layer 2' (e.g., an ultra-low dielectric layer with a dielectric constant of 2.65) is typically used to surround the conductive layer 7' to improve signal speed and reduce signal crosstalk in adjacent conductive layers 7' (i.e., reduce device delay). The inventors of this disclosure discovered in their research that such a low dielectric constant dielectric layer 2' has pores 8' (porosity 20%). The presence of pores leads to a significant decrease in the film's breakdown resistance, which is one of the reasons for the significant decrease in the reliability of semiconductor devices (including DRAM, logic devices, etc.), namely, TDDB (time dependent dielectric breakdown) failure. Therefore, with technological advancements (such as the advancement of logic nodes), the critical dimension (CD value) between conductive layers is further reduced. This necessitates abandoning the use of dielectric layers with lower K values and instead using dielectric layers with higher dielectric constants to improve the reliability of semiconductor devices. However, this leads to a significant increase in semiconductor device latency. Therefore, developing a semiconductor structure that can both reduce device latency and improve semiconductor device reliability has become particularly important.
[0062] The inventors of this disclosure further discovered in their research that by using a dielectric layer that surrounds a conductive layer and includes a first dielectric layer with an ultra-low dielectric constant (i.e., an ultra-low k value) and a second dielectric layer with a low k value and a high Young's modulus to stabilize the quality, a semiconductor structure can be fabricated. By utilizing the balance of the different k values and moduli of the two dielectric layers, small parasitic capacitance and stable interface film quality can be achieved, thus achieving a balance between device delay and reliability. That is, it can both reduce device delay and improve the reliability of semiconductor devices.
[0063] Therefore, this disclosure provides a semiconductor structure and its fabrication method, which can reduce device delay and improve the reliability of semiconductor devices.
[0064] like Figures 2-4 As shown, a first aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:
[0065] Base 1;
[0066] The dielectric layer 10 includes a first dielectric layer 2 and a second dielectric layer 3. The first dielectric layer 2 is located on the substrate 1, and the dielectric constant of the first dielectric layer 2 is not greater than 2.2. The second dielectric layer 3 is located on the first dielectric layer 2, and the dielectric constant of the second dielectric layer 3 is greater than the dielectric constant of the first dielectric layer 2. The Young's modulus of the second dielectric layer 3 is greater than the Young's modulus of the first dielectric layer 2. The first dielectric layer 2 and the second dielectric layer 3 are provided with a groove structure 6, and the groove structure 6 penetrates the first dielectric layer 2 and the second dielectric layer 3.
[0067] The conductive layer 7 fills the groove structure 6, and the top surface of the conductive layer 7 is flush with the top surface of the second dielectric layer 3.
[0068] In embodiments of this disclosure, such as Figures 2-4 As shown, the semiconductor structure further includes a first barrier layer 5, located on the second dielectric layer 3 and the conductive layer 7, and covering at least a portion of the second dielectric layer 3 and at least a portion of the conductive layer 7. Those skilled in the art should understand that when the conductive layer 7 is the top conductive layer, the first barrier layer 5 can cover the entire second dielectric layer 3 and the entire conductive layer 7; when the conductive layer 7 is not the top conductive layer, the first barrier layer 5 can cover at least a portion of the second dielectric layer 3 and at least a portion of the conductive layer 7.
[0069] In embodiments of this disclosure, such as Figure 4As shown, the semiconductor structure includes a plurality of conductive interconnect units 11. Each conductive interconnect unit 11 includes the dielectric layer 10, the conductive layer 7 and the first barrier layer 5. Each conductive interconnect unit 11 is stacked along the thickness direction of the substrate 1 and is electrically connected to each other.
[0070] In embodiments of this disclosure, such as Figures 2-4 As shown, the semiconductor structure further includes a second barrier layer 4 located between the substrate 1 and the first dielectric layer 2, and the groove structure 6 also penetrates the second barrier layer 4.
[0071] Those skilled in the art will understand that the substrate of the semiconductor structure in the embodiments of this disclosure can be a substrate or semiconductor wafer at any stage of the fabrication process of forming semiconductor elements, such as integrated circuits or discrete devices, on a substrate. In one embodiment, the substrate comprises a dielectric layer with an extremely low dielectric constant and a conductive layer on the semiconductor substrate. The substrate can be a photomask, a semiconductor wafer, or other workpiece known to those skilled in the art of electronic component manufacturing. In at least some embodiments, the substrate comprises any materials and structures used to manufacture any integrated circuit, passive (e.g., capacitor, inductor), and active (e.g., transistor, photodetector, laser, diode) microelectronic components. The substrate may comprise an insulating material (e.g., a dielectric material) separating such active and passive microelectronic components from one or more conductive layers formed on top of them. In one embodiment, the substrate is a semiconductor substrate comprising one or more dielectric layers, such as silicon carbonitride, silicon oxycarbide, silicon nitride, aluminum oxide, silicon dioxide, sapphire, and other dielectric materials. In one embodiment, the substrate is a wafer stack comprising one or more layers, which may include a conductive layer, a semiconductor layer, an insulating layer, or any combination thereof. The semiconductor structure in the embodiments of this disclosure may, for example, be a semiconductor structure including a back-end interconnect structure, comprising a substrate and at least one layer of back-end processed conductive interconnect structure. In one embodiment, such as… Figure 2 and Figure 3 As shown, the substrate illustrated may include semiconductor device structures fabricated by front-end and mid-end processes. The conductive interconnect units (not shown) including dielectric layer 10, conductive layer 7, and first barrier layer 5 can be the top conductive interconnect units in the back-end process, the first conductive interconnect units in the back-end process, or any one or more layers from the first to the top conductive interconnect units in the back-end process (this is for illustrative purposes only; not all conductive interconnect units in the back-end process are shown). In another embodiment, as... Figure 2 and Figure 3As shown, the substrate illustrated may include semiconductor device structures fabricated by front-end and mid-end processes, as well as at least one layer of conductive interconnect units in the back-end process. The conductive interconnect unit shown, including dielectric layer 10, conductive layer 7, and first barrier layer 5 (not shown), can be the top conductive interconnect unit in the back-end process, or one of the conductive interconnect units in the back-end process other than the at least one conductive interconnect unit and the top conductive interconnect unit, or any one or more layers in the back-end process other than the at least one conductive interconnect unit (for illustration only; not all conductive interconnect units in the back-end process are shown). In another embodiment, as... Figure 4 As shown, the substrate illustrated may include semiconductor device structures fabricated by front-end and mid-end processes. The two conductive interconnect units 11 shown (including dielectric layer 10, conductive layer 7, and first barrier layer 5) can be two conductive interconnect units in the back-end process, or can be understood as multi-layer (e.g., 2-6 layers) conductive interconnect units in the back-end process (this is for illustration only; not all conductive interconnect units in the back-end process are shown). In another embodiment, as... Figure 4 As shown, the substrate can include semiconductor device structures prepared by front-end and mid-end processes, as well as at least one layer of conductive interconnect units in the back-end process. The conductive interconnect unit 11 shown (including dielectric layer 10, conductive layer 7 and first barrier layer 5) can be the top conductive interconnect unit and the second-to-top conductive interconnect unit in the back-end process, or it can be understood as any two or more layers (such as 2-6 layers) of conductive interconnect units in the back-end process other than the at least one conductive interconnect unit (for illustration only, not all conductive interconnect units in the back-end process are shown).
[0072] In embodiments of this disclosure, such as Figure 2 As shown, the conductive layer 7 includes a metal diffusion barrier layer 713 and a metal layer 714. The metal diffusion barrier layer 713 can be at least one of Ta, Ti, TaN, and TiN, and the metal layer 714 can be made of copper or cobalt.
[0073] The inventors of this disclosure discovered in their research that a smaller k-value in the dielectric layer is more beneficial for improving device delay, but also more prone to causing TDDB failure and resulting in reduced reliability. Conversely, increasing the k-value of the dielectric layer causes device delay. Taking a semiconductor structure from the aforementioned related technologies as an example, and using copper as the metal layer material, the mechanism of TDDB failure is analyzed, which includes copper diffusion and the breaking of chemical bonds in the dielectric layer.
[0074] Copper diffusion: Copper atoms diffuse most easily at the corners of the top surface, conducting along the interface between the first barrier layer and the dielectric layer, and then diffusing as copper ions from positive bias to negative bias. Voltage and temperature accelerate this diffusion process (copper atoms continue to diffuse downwards along the interior of the dielectric layer after reaching the interface between the first barrier layer and the dielectric layer). During the entire diffusion process, copper ions can gain electrons to become copper atoms, and then copper atoms lose electrons to become copper ions again, continuing to diffuse. Copper atoms at the interface move slowly and are caught up by copper ions. If the caught-up copper ions gain electrons to become copper atoms, they will combine with other copper atoms to form copper particles. These particles continue to grow, forming bridges, which can cause catastrophic failure. TDDB failure is more likely to occur at the upper interface between the first barrier layer and the dielectric layer. During the formation of the conductive layer, etching and chemical mechanical polishing of the dielectric layer are performed. Due to the etching characteristics, the copper-copper CD on the upper surface is smaller, resulting in a greater electric field strength at the same voltage, making it easier to break down and cause TDDB failure. After chemical mechanical polishing (CMP), the upper interface of the dielectric layer undergoes a cleaning step. CMP causes the chemical bonds in the dielectric layer to break, and the high porosity of the dielectric layer leads to water absorption during the cleaning process, resulting in a deterioration in the dielectric layer's quality. Furthermore, the copper oxide reduction step during the formation of the first barrier layer causes plasma damage, further deteriorating the dielectric layer's quality. These factors make the upper interface of the dielectric layer extremely unstable, and its deterioration becomes the primary cause of TDDB failure.
[0075] The breaking of chemical bonds in the dielectric layer occurs due to two main factors: thermo-chemical reactions under the influence of temperature and electric field, and damage caused by electron impacts on these bonds. Copper diffusion and the breaking of dielectric bonds are actually complementary processes. Copper atoms, being relatively large, compress and catalyze the breaking of dielectric bonds during diffusion. This breaking of bonds, in turn, reduces the dielectric layer's effectiveness as a barrier layer, further accelerating copper diffusion.
[0076] The inventors of this disclosure use a dielectric layer that surrounds a conductive layer, comprising a first dielectric layer with an ultra-low dielectric constant (i.e., an ultra-low k value) and a second dielectric layer with a low k value and a high Young's modulus, to fabricate a semiconductor structure. By balancing the different k values and moduli of the two dielectric layers, small parasitic capacitance and stable interface film quality are achieved, thus achieving a balance between device delay and reliability. In other words, device delay can be reduced while improving the reliability of semiconductor devices.
[0077] Specifically, the first dielectric layer has a lower k-value and higher porosity. In the embodiments of this disclosure, the dielectric constant of the first dielectric layer 2 can be 1.8-2.2 (significantly lower than the dielectric constant of dielectric layers in related technologies). In another embodiment of this disclosure, such as... Figure 2-4 As shown, the first dielectric layer 2 has pores 8, and the porosity of the first dielectric layer 2 can be 28%-32% (significantly higher than the porosity of dielectric layers in related technologies).
[0078] In embodiments of this disclosure, the Young's modulus of the first dielectric layer can be 6-8 GPa.
[0079] In embodiments of this disclosure, the thickness of the first dielectric layer can be 240-320 nm.
[0080] Specifically, the second dielectric layer has higher and more stable quality, and can resist plasma attacks from chemical mechanical polishing and copper oxide reduction treatment. Therefore, it has a low k value and a high Young's modulus and no porosity. The less porosity, the higher the degree of cross-linking, the greater the Young's modulus, the stronger the barrier ability, and the stronger its own breakdown resistance. Therefore, it is less likely to cause TDDB failure.
[0081] In embodiments of this disclosure, the dielectric constant of the second dielectric layer can be 2.6-3.
[0082] In embodiments of this disclosure, the Young's modulus of the second dielectric layer can be 10-12 GPa.
[0083] In embodiments of this disclosure, such as Figure 2-4 As shown, there are no pores in the second dielectric layer 3, that is, the porosity of the second dielectric layer 3 is 0%.
[0084] In embodiments of this disclosure, the thickness of the second dielectric layer can be 30-60 nm.
[0085] In embodiments of this disclosure, the material of the first dielectric layer may be any material capable of satisfying the aforementioned performance; for example, the material of the first dielectric layer may include silicon oxycarbonate.
[0086] In the embodiments of this disclosure, the material of the second dielectric layer can be any material capable of satisfying the aforementioned performance, for example, the material of the second dielectric layer may include silicon oxycarbon.
[0087] In the embodiments of this disclosure, the dielectric constant of the dielectric layer including the aforementioned first dielectric layer and second dielectric layer is 2.2-2.4 (significantly lower than the dielectric constant of dielectric layers in related technologies), which has significantly higher device delay capability, and the quality of its upper surface is significantly improved, thereby realizing a window at advanced nodes that both reduces the K value of the dielectric layer, reduces device delay, and improves reliability.
[0088] In embodiments of this disclosure, a first barrier layer is used to prevent metal diffusion of the conductive layer, and its dielectric constant is greater than that of the second dielectric layer.
[0089] In embodiments of this disclosure, a second barrier layer is used to prevent metal diffusion of the conductive layer, and its dielectric constant is greater than that of the second dielectric layer.
[0090] In embodiments of this disclosure, the material of the first barrier layer may include at least one of silicon carbonitride, silicon carbon oxycarbonate, silicon nitride, and aluminum oxide.
[0091] In embodiments of this disclosure, the material of the second barrier layer may include at least one of silicon carbonitride, silicon carbon oxycarbonate, silicon nitride, and aluminum oxide.
[0092] In embodiments of this disclosure, the thickness of the first barrier layer can be 40-50 nm.
[0093] In embodiments of this disclosure, the thickness of the second barrier layer can be 40-50 nm.
[0094] like Figure 5 As shown, a second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:
[0095] S1: A dielectric layer is formed on a substrate, the dielectric layer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer being located on the substrate, the dielectric constant of the first dielectric layer being no greater than 2.2; the second dielectric layer being located on the first dielectric layer, the dielectric constant of the second dielectric layer being greater than the dielectric constant of the first dielectric layer, and the Young's modulus of the second dielectric layer being greater than the Young's modulus of the first dielectric layer.
[0096] S2: A groove structure is formed in the dielectric layer, the groove structure penetrating the first dielectric layer and the second dielectric layer;
[0097] S3: Form a conductive layer that fills the groove structure and whose top surface is flush with the top surface of the second dielectric layer.
[0098] Figures 6A to 6H This is a schematic diagram of the steps of a method for fabricating a semiconductor structure according to an exemplary embodiment of this disclosure.
[0099] In this embodiment of the disclosure, the preparation method further includes: forming a first barrier layer on the second dielectric layer and the conductive layer, wherein the first barrier layer covers at least a portion of the second dielectric layer and at least a portion of the conductive layer.
[0100] In this embodiment of the disclosure, the fabrication method further includes: forming a plurality of conductive interconnect units, wherein each conductive interconnect unit includes the dielectric layer, the conductive layer and the first barrier layer, and each conductive interconnect unit is stacked along the thickness direction of the substrate and is electrically connected to the other conductive interconnect units.
[0101] In this embodiment of the disclosure, the method for forming the dielectric layer, the groove structure, and the conductive layer includes:
[0102] The first dielectric layer is formed on the substrate;
[0103] An initial second dielectric layer is formed on the first dielectric layer, wherein the dielectric constant of the initial second dielectric layer is greater than that of the first dielectric layer, and the Young's modulus of the initial second dielectric layer is greater than that of the first dielectric layer;
[0104] An initial groove structure is formed in the first dielectric layer and the initial second dielectric layer, the initial groove structure penetrating the first dielectric layer and the initial second dielectric layer;
[0105] An initial conductive layer is formed, which fills the initial groove structure;
[0106] The initial conductive layer and the initial second dielectric layer with a portion of their thickness are removed, and the remaining initial conductive layer is used as the conductive layer, the remaining initial second dielectric layer is used as the second dielectric layer, and the remaining initial groove structure is used as the groove structure. The conductive layer fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
[0107] In this embodiment of the disclosure, the preparation method further includes:
[0108] Before forming the first dielectric layer on the substrate, a second barrier layer is formed on the substrate;
[0109] The initial groove structure is formed in the second barrier layer, the first dielectric layer and the initial second dielectric layer, and the initial groove structure penetrates the second barrier layer, the first dielectric layer and the initial second dielectric layer.
[0110] Specifically, the preparation method of the embodiments of this disclosure includes:
[0111] like Figures 6A-6B As shown, a second barrier layer 4 is formed on the substrate 1, and a first dielectric layer 2 is formed on the second barrier layer 4;
[0112] like Figure 6CAs shown, an initial second dielectric layer 31 is formed on the first dielectric layer 2. The dielectric constant of the initial second dielectric layer 31 is greater than that of the first dielectric layer 2, and the Young's modulus of the initial second dielectric layer 31 is greater than that of the first dielectric layer 2.
[0113] like Figure 6D As shown, an initial groove structure 61 is formed in the second barrier layer 4, the first dielectric layer 2 and the initial second dielectric layer 31, and the initial groove structure 61 penetrates the second barrier layer 4, the first dielectric layer 2 and the initial second dielectric layer 31;
[0114] like Figure 6E As shown, an initial conductive layer 71 is formed, which fills the initial groove structure 61.
[0115] like Figure 6F As shown, the initial conductive layer 71 and the initial second dielectric layer 31 with a portion of their thickness are removed, the remaining initial conductive layer is used as the conductive layer 7, the remaining initial second dielectric layer is used as the second dielectric layer 3, and the remaining initial groove structure is used as the groove structure 6. The conductive layer 7 fills the groove structure 6, and the top surface of the conductive layer 7 is flush with the top surface of the second dielectric layer 3.
[0116] like Figure 6G As shown, a first barrier layer 5 is formed on the second dielectric layer 3 and the conductive layer 7, the first barrier layer 5 covering at least a portion of the second dielectric layer 3 and at least a portion of the conductive layer 7.
[0117] Specifically, the method for forming the first dielectric layer includes:
[0118] like Figure 6A As shown, in the presence of the precursor material of the first dielectric layer, the pore-forming agent 9 and the oxygen-containing gas, an initial first dielectric layer 21 is formed under the first deposition conditions;
[0119] like Figure 6B As shown, ultraviolet curing is performed to remove the pore-forming agent 9 and form the first dielectric layer 2;
[0120] The first deposition conditions include: a flow rate of 1500-2000 mg / min for the precursor material of the first dielectric layer, a flow rate of 240-280 sccm for the pore-forming agent, a flow rate of 40-60 sccm for the oxygen-containing gas, and a radio frequency power of 500-600 W.
[0121] The first deposition conditions may specifically include: introducing a precursor material, a pore-forming agent, and oxygen into the first dielectric layer; the flow rate of the precursor material is 1500-2000 mg / min; the flow rate of the pore-forming agent is 240-280 sccm; the flow rate of the oxygen is 40-60 sccm; the pressure is 7-9 Torr; after the chamber stabilizes, a 13.56 MHz radio frequency is turned on and the radio frequency power is controlled at 500-600 W; the deposition time is 45-50 s; and the initial thickness of the first dielectric layer is 300-400 nm.
[0122] The conditions for the ultraviolet curing treatment may specifically include: a time of 160-260s and a thickness of 240-320nm for the first dielectric layer.
[0123] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the dielectric constant of the first dielectric layer is not greater than 2.2, for example, it can be 1.8-2.2.
[0124] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the Young's modulus of the first dielectric layer is 6-8 GPa.
[0125] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the first dielectric layer 2 has pores 8, and the porosity of the first dielectric layer 2 is 28%-32%.
[0126] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the thickness of the first dielectric layer is 240-320 nm.
[0127] like Figure 6C As shown, specifically, the method for forming the initial second dielectric layer includes:
[0128] The initial second dielectric layer is formed under the second deposition conditions in the presence of the precursor material of the second dielectric layer and oxygen-containing gas.
[0129] The second deposition conditions include: a flow rate of 3000-3500 mg / min for the precursor material of the second dielectric layer, a flow rate of 100-120 sccm for the oxygen-containing gas, a power of 500-600 W for high-frequency radio frequency, and a power of 70-100 W for low-frequency radio frequency.
[0130] The second deposition conditions may specifically include: introducing precursor material and oxygen into the second dielectric layer, wherein the flow rate of the precursor material of the second dielectric layer is 3000-3500 mg / min, the flow rate of the oxygen-containing gas is 100-120 sccm, turning on 13.56 MHz radio frequency and controlling the radio frequency power to be 500-600 W, and simultaneously turning on 400 kHz radio frequency and controlling the radio frequency power to be 70-100 W (bombardment effect, which improves the film density), that is, controlling the power of high frequency radio frequency to be 500-600 W, the power of low frequency radio frequency to be 70-100 W, the deposition time to be 10-15 s, and the thickness of the initial second dielectric layer 31 to be 70-100 nm.
[0131] In the embodiments of this disclosure, the oxygen-containing gas may be oxygen.
[0132] In embodiments of this disclosure, the precursor material of the first dielectric layer may be at least one of dimethyldimethoxysilane (DMDMOS, CAS No.: 1112-39-6) and diethoxymethylsilane (DEMS, CAS No.: 2031-62-1).
[0133] In embodiments of this disclosure, the precursor material of the second dielectric layer may be at least one of dimethyldimethoxysilane (DMDMOS, CAS No.: 1112-39-6) and diethoxymethylsilane (DEMS, CAS No.: 2031-62-1).
[0134] In the embodiments of this disclosure, the pore-forming agent may be α-terpinene (ATRP, CAS No.: 99-86-5).
[0135] In embodiments of this disclosure, the steps of forming the first dielectric layer and forming the initial second dielectric layer are performed on the same machine. This reduces the number of steps and time spent moving between different machines, significantly reducing production costs and improving production efficiency.
[0136] like Figure 6E As shown, the initial conductive layer 71 may include an initial metal diffusion barrier layer 711 and an initial metal layer 712. The initial metal diffusion barrier layer 711 may be at least one of Ta, Ti, TaN, and TiN, and the initial metal layer 712 may be made of copper or cobalt. The processes for forming the initial metal diffusion barrier layer 711 and the initial metal layer 712 are conventional processes in the art and will not be described in detail here.
[0137] like Figure 6FAs shown, specifically, the step of removing a portion of the initial conductive layer 71 and the initial second dielectric layer 31 can be completed through chemical mechanical polishing and cleaning steps. The purpose of the chemical mechanical polishing step is to ensure that there is no short circuit between the metal layers. The thickness of the second dielectric layer obtained in this step is 30-60 nm.
[0138] Those skilled in the art should understand that, compared to the initial second dielectric layer, only the thickness of the second dielectric layer changes, while other properties such as dielectric constant, Young's modulus, and porosity remain unchanged.
[0139] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the dielectric constant of the second dielectric layer 3 is 2.6-3.
[0140] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the Young's modulus of the second dielectric layer 3 is 10-12 GPa.
[0141] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the porosity of the second dielectric layer 3 is 0%.
[0142] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the thickness of the second dielectric layer 3 is 30-60 nm.
[0143] like Figure 6F As shown, the conductive layer 7 may include a metal diffusion barrier layer 713 and a metal layer 714. The metal diffusion barrier layer 713 may be at least one of Ta, Ti, TaN, and TiN, and the metal layer 714 may be made of copper or cobalt.
[0144] like Figure 6H As shown, the fabrication method further includes: forming a plurality of conductive interconnect units 11, wherein each conductive interconnect unit 11 includes the dielectric layer 10, the conductive layer 7 and the first barrier layer 5, and each conductive interconnect unit 11 is stacked along the thickness direction of the substrate 1 and is electrically connected to each other.
[0145] The method for forming the conductive interconnect unit 11 can refer to the aforementioned method for forming the dielectric layer 10, the conductive layer 7 and the first barrier layer 5, and will not be repeated here.
[0146] The materials and other related descriptions of each film layer or structural layer prepared in the semiconductor structure preparation method disclosed herein can be referred to the materials and corresponding related descriptions of each film layer or structural layer of the semiconductor structure in the embodiments of this disclosure, and will not be repeated here.
[0147] In one embodiment of the semiconductor structure obtained by the semiconductor structure preparation method disclosed herein, the dielectric constant of the dielectric layer is 2.2-2.4.
[0148] In this embodiment, a semiconductor structure (e.g., a semiconductor structure including a back-end interconnect structure) is fabricated by surrounding a conductive layer with a dielectric layer comprising a first dielectric layer and a second dielectric layer (the first dielectric layer is located on the substrate, and the dielectric constant of the first dielectric layer is not greater than 2.2; the second dielectric layer is located on the first dielectric layer, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the Young's modulus of the second dielectric layer is greater than the Young's modulus of the first dielectric layer). By utilizing the balance of the different k values and moduli of the two dielectric layers, small parasitic capacitance and stable interface film quality are achieved, which can achieve a balance between device delay and reliability, that is, it can both reduce device delay and improve the reliability of semiconductor devices.
[0149] The semiconductor structure and fabrication method disclosed herein are applicable to all scenarios for balancing device delay and reliability, such as all semiconductor structures and fabrication methods including back-end interconnect structures, including but not limited to DRAM, logic devices, etc. Given that logic devices have more conductive layers in their back-end interconnect structures, it is particularly applicable to semiconductor structures and fabrication methods including back-end interconnect structures for logic devices in advanced nodes, such as semiconductor structures and fabrication methods including back-end interconnect structures with nodes of 7-10nm.
[0150] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0151] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0152] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0153] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: Base; The dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the substrate and has a dielectric constant of not more than 2.
2. The second dielectric layer is located on the first dielectric layer and has a dielectric constant greater than that of the first dielectric layer. The Young's modulus of the second dielectric layer is greater than that of the first dielectric layer. The first dielectric layer and the second dielectric layer are provided with groove structures, and the groove structures penetrate the first dielectric layer and the second dielectric layer. A conductive layer fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first barrier layer is located on the second dielectric layer and the conductive layer, and covers at least a portion of the second dielectric layer and at least a portion of the conductive layer.
3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure includes a plurality of conductive interconnect units, each of which includes the dielectric layer, the conductive layer and the first barrier layer. The conductive interconnect units are stacked along the thickness direction of the substrate and are electrically connected to each other.
4. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A second barrier layer is located between the substrate and the first dielectric layer, and the groove structure also extends through the second barrier layer.
5. The semiconductor structure according to claim 4, characterized in that, The dielectric constant of the first barrier layer is greater than the dielectric constant of the second dielectric layer; and / or The dielectric constant of the second barrier layer is greater than that of the second dielectric layer.
6. The semiconductor structure according to any one of claims 1-4, characterized in that, The dielectric constant of the dielectric layer is 2.2-2.4; and / or The dielectric constant of the first dielectric layer is 1.8-2.2; and / or The dielectric constant of the second dielectric layer is 2.6-3; and / or The Young's modulus of the first dielectric layer is 6-8 GPa; and / or The Young's modulus of the second dielectric layer is 10-12 GPa; and / or The porosity of the first dielectric layer is 28%-32%; and / or The porosity of the second dielectric layer is 0%; and / or The thickness of the first dielectric layer is 240-320 nm; and / or The thickness of the second dielectric layer is 30-60 nm.
7. The semiconductor structure according to any one of claims 1-4, characterized in that, The material of the first dielectric layer includes silicon carbide; and / or The material of the second dielectric layer includes silicon carbide; and / or The material of the first barrier layer includes at least one of silicon carbonitride, silicon carbon oxide, silicon nitride, and aluminum oxide; and / or The material of the second barrier layer includes at least one of silicon carbonitride, silicon carbon oxide, silicon nitride, and aluminum oxide.
8. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A dielectric layer is formed on a substrate, the dielectric layer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer being located on the substrate and having a dielectric constant not greater than 2.2; the second dielectric layer being located on the first dielectric layer and having a dielectric constant greater than that of the first dielectric layer, and having a Young's modulus greater than that of the first dielectric layer. A groove structure is formed in the dielectric layer, and the groove structure penetrates the first dielectric layer and the second dielectric layer; A conductive layer is formed, which fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
9. The preparation method according to claim 8, characterized in that, The preparation method further includes: A first barrier layer is formed on the second dielectric layer and the conductive layer, the first barrier layer covering at least a portion of the second dielectric layer and at least a portion of the conductive layer.
10. The preparation method according to claim 9, characterized in that, The preparation method further includes: Multiple conductive interconnect units are formed, each conductive interconnect unit including the dielectric layer, the conductive layer and the first barrier layer, and each conductive interconnect unit is stacked along the thickness direction of the substrate and electrically connected to each other.
11. The preparation method according to any one of claims 8-10, characterized in that, The methods for forming the dielectric layer, the groove structure, and the conductive layer include: The first dielectric layer is formed on the substrate; An initial second dielectric layer is formed on the first dielectric layer, wherein the dielectric constant of the initial second dielectric layer is greater than that of the first dielectric layer, and the Young's modulus of the initial second dielectric layer is greater than that of the first dielectric layer; An initial groove structure is formed in the first dielectric layer and the initial second dielectric layer, the initial groove structure penetrating the first dielectric layer and the initial second dielectric layer; An initial conductive layer is formed, which fills the initial groove structure; The initial conductive layer and the initial second dielectric layer with a portion of their thickness are removed, and the remaining initial conductive layer is used as the conductive layer, the remaining initial second dielectric layer is used as the second dielectric layer, and the remaining initial groove structure is used as the groove structure. The conductive layer fills the groove structure, and the top surface of the conductive layer is flush with the top surface of the second dielectric layer.
12. The preparation method according to claim 11, characterized in that, The preparation method further includes: Before forming the first dielectric layer on the substrate, a second barrier layer is formed on the substrate; The initial groove structure is formed in the second barrier layer, the first dielectric layer and the initial second dielectric layer, and the initial groove structure penetrates the second barrier layer, the first dielectric layer and the initial second dielectric layer.
13. The preparation method according to claim 11, characterized in that, The method for forming the first dielectric layer includes: In the presence of the precursor material, pore-forming agent and oxygen-containing gas of the first dielectric layer, an initial first dielectric layer is formed under the first deposition conditions. The pore-forming agent is removed by UV curing to form the first dielectric layer. The first deposition conditions include: a flow rate of 1500-2000 mg / min for the precursor material of the first dielectric layer, a flow rate of 240-280 sccm for the pore-forming agent, a flow rate of 40-60 sccm for the oxygen-containing gas, and a radio frequency power of 500-600 W.
14. The preparation method according to claim 11, characterized in that, The method for forming the initial second dielectric layer includes: The initial second dielectric layer is formed under the second deposition conditions in the presence of the precursor material of the second dielectric layer and oxygen-containing gas. The second deposition conditions include: a flow rate of 3000-3500 mg / min for the precursor material of the second dielectric layer, a flow rate of 100-120 sccm for the oxygen-containing gas, a power of 500-600 W for high-frequency radio frequency, and a power of 70-100 W for low-frequency radio frequency.
15. The preparation method according to claim 11, characterized in that, The steps of forming the first dielectric layer and forming the initial second dielectric layer are performed on the same machine.