Chip package structure and packaging method thereof, and electronic device

Abstract

The application provides a chip packaging structure and a packaging method thereof and an electronic device. The chip packaging structure comprises a substrate, a chip layer and a heat dissipation plate. The chip layer comprises a flat layer and a sub-chip. The flat layer is connected to at least the periphery of the sub-chip. The chip layer has a first surface and a second surface. The first surface and the second surface are opposite in the thickness direction of the chip layer. The first surface is connected to the substrate. The chip layer is provided with a connecting hole. The connecting hole is recessed from the second surface to the interior of the flat layer. The connecting hole is adjacent to the sub-chip. The heat dissipation plate comprises a body and a heat conductor. The heat conductor is fixedly connected to one side of the body. The heat conductor is connected to the hole wall of the connecting hole. The body is connected to the second surface of the chip layer. The thermal conductivity of the body is greater than or equal to 200 W / mK. The embodiments of the application can improve the heat dissipation performance of the chip packaging structure, thereby improving the performance and structural stability of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of electronic component packaging technology, specifically to a chip packaging structure and its packaging method, and electronic equipment. Background Technology

[0002] With the rapid development of network and intelligent technologies, the demand for ultra-high integration of chips is increasing, and chip packaging methods are also developing rapidly. Chip packaging structures can integrate multiple individual chips into a single chip package structure. These individual chips generate heat during operation, requiring timely heat dissipation to reduce junction temperature and improve chip performance. However, as integration levels increase, the heat dissipation performance of the chip packaging structure is becoming an increasingly important limiting factor for chip performance. Summary of the Invention

[0003] The embodiments of this application provide a chip packaging structure and packaging method thereof, as well as an electronic device, which can improve the heat dissipation performance of the chip packaging structure, thereby improving the performance and structural reliability of the chip packaging structure.

[0004] In a first aspect, this application provides a chip packaging structure, including a substrate, a chip layer, and a heat sink. The chip layer includes a planarization layer and a sub-chip. The planarization layer is at least connected to the periphery of the sub-chip. The chip layer has a first surface and a second surface, which are opposite to each other in the thickness direction of the chip layer. The first surface is connected to the substrate. The chip layer has a connection hole that is recessed from the second surface into the planarization layer and is adjacent to the sub-chip. The heat sink includes a body and a heat conductor. The heat conductor is fixedly connected to one side of the body and connected to the wall of the connection hole. The body is connected to the second surface of the chip layer, and the thermal conductivity of the body is greater than or equal to 200 W / mK.

[0005] In this embodiment, the chip packaging structure is equipped with a heat sink, and the thermal conductivity of the heat sink body is greater than or equal to 200 W / mK, exhibiting high thermal conductivity. The high thermal conductivity material can rapidly transfer heat from the chip packaging structure to the external environment, reducing heat accumulation near the chip layer.

[0006] Excessive operating temperature of the chip layer can affect the physical properties of the materials within it, thereby impacting its performance. Changes in the performance of internal circuit components can slow down their response to load variations and reduce their load adjustment capabilities. Overheating can also cause output voltage fluctuations or abnormal output current, further affecting the operational stability of the entire chip package structure. The chip package structure of this application can dissipate heat to the outside in a timely manner, reducing the operating temperature of the chip layer, extending its lifespan, and improving its operational stability.

[0007] Furthermore, because the chip layer and the heat sink are made of different materials, their coefficients of thermal expansion differ. During chip packaging operation, heat causes these differences in thermal expansion. This difference leads to interfacial stress between the heat sink and the chip layer. When this interfacial stress exceeds the adhesive force between the materials, delamination occurs.

[0008] In this embodiment, a heat conductor is provided on the body of the heat sink, which can be considered equivalent to a tenon structure on the body. The heat conductor can be embedded in the connection hole of the chip layer. The connection hole of the chip layer can be considered equivalent to a mortise structure of the chip layer. The heat sink and the chip layer are connected by a tenon and mortise joint through the heat conductor and the connection hole, thereby improving the bonding force between the heat sink and the chip layer and preventing the heat sink from delaminating relative to the chip layer due to heat generation during operation of the chip packaging structure.

[0009] Specifically, when the chip package structure heats up during operation, the heat conductor can press against the wall of the connecting hole. The heat conductor can undergo slight deformation under stress, thereby absorbing the stress between the heat sink and the chip layer, preventing excessive stress between them and thus avoiding delamination.

[0010] The main body is equipped with multiple heat conductors.

[0011] In this embodiment, the stress between the heat sink and the chip layer increases from the center to the edge. Therefore, the edge of the heat sink is more prone to detaching from the chip layer. Multiple heat conductors on the heat sink can be spaced apart. These multiple heat conductors divide the overall structure of the heat sink into multiple small stress regions. Each heat conductor can absorb the stress between the heat sink and the chip layer, thereby releasing the stress in its area and preventing stress from accumulating from the center to the edge. This improves the connection strength between the heat sink and the chip layer, preventing the edge of the heat sink from detaching from the chip layer.

[0012] The heatsink extends into the chip layer, with a large contact area between it and the chip layer. This large contact area means more pathways for heat transfer from the chip layer to the heatsink, allowing heat to be transferred more quickly. The heat is then transferred through the heatsink to the heat sink itself and finally dissipated into the external environment, completing the heat dissipation process.

[0013] In one possible implementation, the body material includes diamond.

[0014] In this embodiment, the thermal conductivity of diamond is approximately 2000 W / mK. Diamond's high thermal conductivity allows for more effective heat transfer from the chip package structure to the external environment, thus providing timely cooling. High temperature is one of the main causes of chip package structure failure. Prolonged operation in high-temperature environments can alter the material properties within the chip package structure, such as increased electromigration in the metal interconnect layers. This can lead to short circuits or open circuits within the chip package structure, reducing its lifespan. Therefore, improving the heat dissipation performance of the chip package structure helps lower the chip's operating temperature, reducing the risk of chip package structure failure due to high temperatures, and thus enhancing the reliability of the chip package structure.

[0015] Furthermore, diamond has high mechanical strength. Therefore, using diamond-based heat sinks can enhance the overall structural strength of the chip package, preventing breakage or damage caused by external stress, vibration, or impact. This high-strength chip package structure makes it more robust and reliable when integrated into electronic devices, helping to reduce the risk of damage during installation and improve production efficiency.

[0016] In one possible implementation, the chip package structure further includes a metal layer connected to the second surface and the wall of the connection hole, with a body connected to the side of the metal layer opposite to the second surface. A heat conductor is connected to the side of the metal layer opposite to the wall of the connection hole.

[0017] In this embodiment, the metal layer serves as a bonding layer, mitigating thermal stress arising from the mismatch in thermal expansion coefficients between the heat sink body and the planarization layer. The difference in thermal expansion coefficients between the body and the planarization layer can lead to stress concentration at the interface when the temperature changes, thus affecting the connection strength. The metal layer, acting as a bonding layer, absorbs and disperses these stresses, thereby protecting the connection between the body and the planarization layer from damage.

[0018] Furthermore, the metal layer covers the walls of the connection holes and connects to the heat conductor. When the heat conductor is a metallic material, the atoms within both the heat conductor and the metal layer form chemical bonds through covalent or metallic bonds. The bonding strength between the metal layer located within the connection holes and the heat conductor is significantly enhanced, thereby improving the connection strength between the heat sink and the chip layer.

[0019] In one possible implementation, the heat sink further includes a transition layer covering the surface of the body facing the heat conductor, the heat conductor being connected to the surface of the transition layer away from the body, and the transition layer being connected to a second surface.

[0020] The body itself is made of diamond. The heat conductor is made of metallic materials.

[0021] In this embodiment, diamond has a high interfacial energy with ordinary metals and poor wettability. In addition, diamond is prone to graphitization at high temperatures. These characteristics make direct bonding between diamond and metal difficult.

[0022] The transition layer may reduce the interfacial energy between the diamond material and the metal material, so that the metal material can more effectively wet the diamond surface, thereby improving the connection strength between the thermal conductor and the body of the metal material.

[0023] The transition layer consists of elements or compounds capable of forming chemical bonds with both diamond and metallic materials. These chemical bonds further enhance the connection between diamond and metallic materials, allowing the heat conductor to be firmly attached to the surface of the body, forming the tenon structure of the heat sink. This also ensures the stability of the connection between the body and the heat conductor at high temperatures.

[0024] In one possible implementation, the chip layer further includes a support layer and a wiring layer, with the wiring layer stacked on top of the support layer. The wiring layer faces the substrate, and the support layer faces the heat sink. A planarization layer covers the surface of the support layer facing away from the wiring layer, and this surface is a second surface. Connecting holes penetrate the planarization layer, and a portion of the support layer's surface facing away from the wiring layer is exposed relative to the connecting holes. The end face of the heat conductor facing away from the body contacts the support layer.

[0025] In this embodiment, the heat conductor can directly contact the support layer. Therefore, the heat generated by the signal transmission in the wiring layer can be directly transferred to the heat conductor through the support layer, without needing to pass through the planarization layer. This reduces the thermal resistance of the planarization layer during heat transfer, allowing heat to reach the heat sink more directly and quickly, and then be transferred to the external environment through the heat sink body, thereby improving the heat dissipation efficiency of the chip package structure. The chip package structure can dissipate internally generated heat more quickly, thus maintaining a lower operating temperature and slowing down the aging rate of the chip layers. This means that each part of the chip package structure can maintain its performance for a longer period, extending the lifespan of the chip package structure.

[0026] In one possible implementation, the chip layer includes a planarization layer and at least two sub-chips, the at least two sub-chips being disposed spaced apart on the substrate, and the planarization layer being located in the gap between the multiple sub-chips;

[0027] The connection hole is recessed from the surface of the planarization layer away from the substrate, and the connection hole is located between two adjacent sub-chips.

[0028] In this embodiment, the heat conductor can utilize the gaps between multiple sub-chips without occupying the thickness of the chip package structure, thus allowing for a thinner and lighter chip package structure. As sub-chips become increasingly complex and integrated, heat dissipation has become a key factor affecting the performance and lifespan of the chip package structure. A thinner overall package structure facilitates heat dissipation from the chip package structure, allowing it to be rapidly dissipated into the air via a heat sink, thereby ensuring the chip package structure operates at a suitable temperature and extending its lifespan.

[0029] As electronic devices become increasingly thinner and lighter, the reduction in the size of chip packaging structures makes it easier to integrate chips into various electronic devices, meeting the demands of modern electronic devices for miniaturization and lightweight design.

[0030] In one possible implementation, there are at least two chip layers, namely a first chip layer and a second chip layer, which are stacked together. The first chip layer is connected to the substrate, and the surface of the second chip layer facing away from the first chip layer is a second surface. A connection hole is recessed from the second surface of the second chip layer, penetrates the planarization layer of the second chip layer, and extends into the planarization layer of the first chip layer.

[0031] In this embodiment, the length of the heat conductor can exceed the thickness of one chip layer. This allows for a longer tenon structure in the mortise and tenon joint. When the heat conductor is embedded in the connection hole, the contact area between the heat conductor and the connection hole is larger, resulting in a tighter connection. This provides better mutual restraint between the heat sink and the chip layer, increasing the structural stability of the connection between the heat sink and the chip layer.

[0032] In addition, the larger contact area between the heat conductor and the chip layer increases the heat transfer efficiency between the chip layer and the heat conductor, allowing heat to be transferred more quickly from the chip layer to the heat conductor. The heat is then transferred through the heat conductor to the heat sink body and finally dissipated into the external environment, completing the heat dissipation process.

[0033] Secondly, this application provides an electronic device, including a circuit board and a chip package structure as described above, wherein the circuit board is connected to the chip package structure.

[0034] Thirdly, this application provides a packaging method for a chip packaging structure. This includes:

[0035] A chip layer is provided, the chip layer includes a first surface and a second surface, the first surface and the second surface are opposite to each other in the thickness direction of the chip layer, the chip layer includes a planarization layer and a sub-chip, the planarization layer is at least connected to the periphery of the sub-chip.

[0036] Connecting holes are formed in the planar layer of the chip layer. The connecting holes are recessed from the second surface and are adjacent to the sub-chip.

[0037] A heat sink is provided, which includes a body and a heat conductor. The heat conductor is fixedly connected to one side of the body, and the thermal conductivity of the body is greater than or equal to 200W / mK.

[0038] A heat sink is connected to the chip layer to form a chip package structure. A heat conductor is inserted into a connection hole and connected to the hole wall. The body is connected to the second surface of the chip layer.

[0039] In this embodiment, the heat sink and chip layer can be formed separately. Then, they are pressed together to form a chip package structure. Separate forming of the heat sink and chip layer makes the production process more flexible, allowing for optimization of the manufacturing processes and material selection for each according to actual needs. Furthermore, it avoids assembling defective heat sink products with the chip layer, or vice versa, preventing any impact on the yield of the chip package structure. This helps reduce overall manufacturing costs, improve production efficiency, and reduce material waste.

[0040] In one possible implementation, after attaching the heat sink to the chip layer, the packaging method further includes:

[0041] A substrate is formed on the chip layer away from the surface of the heat sink.

[0042] In one possible implementation, the step of providing the heat sink includes:

[0043] Provide the main body;

[0044] A transition layer is formed on the surface of the substrate;

[0045] A heat conductor is formed on the side of the transition layer away from the main body, so that the heat conductor, the transition layer and the main body form a heat dissipation plate.

[0046] In one possible implementation, after the interconnects are formed on the chip layer and before the heat sink is provided, the packaging method further includes:

[0047] A metal layer is formed on the second surface, covering the second surface and the wall of the connecting hole.

[0048] In one possible implementation, the step of connecting the heat sink to the chip layer includes:

[0049] The heat sink is bonded to the chip layer by hot pressing, and the metal layer covering the body is on the side away from the second surface. The heat conductor is bonded to the metal layer located in the connection hole by eutectic bonding.

[0050] In one possible implementation, the step of connecting the heat sink to the chip layer includes:

[0051] The heat sink is bonded to the surface of the metal layer away from the chip layer by welding, the body is fixedly connected to the surface of the metal layer away from the second surface by diffusion welding, and the heat conductor is fixedly connected to the metal layer located in the connection hole by diffusion welding.

[0052] In one possible implementation, the step of providing the chip layer includes:

[0053] Provide the first chip layer;

[0054] A wiring layer and a first pad layer are formed on the surface of the first chip layer, and the first pad layer is connected to the side of the wiring layer away from the first chip layer;

[0055] A second chip layer is formed on the surface of the first pad layer opposite to the wiring layer. The second chip layer includes a first surface and a second surface, which are opposite to each other in the thickness direction of the second chip layer. The chip layer includes a planarization layer and a sub-chip, and the planarization layer is at least connected to the periphery of the sub-chip.

[0056] Fourthly, this application also provides a packaging method for another chip packaging structure, including:

[0057] A heat sink is provided, which includes a body and a heat conductor. The heat conductor is fixedly connected to one side of the body, and the thermal conductivity of the body is greater than or equal to 200W / mK.

[0058] A sub-chip is formed on the surface of the heat sink where a heat conductor is provided, and the sub-chip is spaced apart from the heat conductor.

[0059] A planarization layer is formed on the surface of the heat sink where the heat conductor is located. The planarization layer covers the heat conductor and fills the gap between the sub-chip and the heat conductor.

[0060] In this embodiment, the planarization layer can be directly formed by covering the heat conductor. After covering the heat conductor, the planarization layer adapts to the shape of the heat conductor to form a porous structure. This avoids the situation where the porous structure of the planarization layer does not match the shape of the heat conductor, which could prevent the heat sink from connecting smoothly to the chip layer.

[0061] In one possible implementation, after a planarization layer is formed on the surface of the heat sink where the heat conductor is located, the encapsulation method further includes:

[0062] A substrate is formed on the surface of the sub-chip that is away from the heat sink.

[0063] In one possible implementation, forming a planar layer on the surface of the heat sink where a heat conductor is located includes:

[0064] A metal layer is formed on the surface of the heat sink where the heat conductor is located, and the metal layer covers the heat conductor.

[0065] A planarization layer is formed on the surface of the metal layer away from the heat conductor. The planarization layer covers the metal layer and fills the gap between the sub-chip and the heat conductor. Attached Figure Description

[0066] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0067] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0068] Figure 2 yes Figure 1 A cross-sectional schematic diagram of the first embodiment of the chip packaging structure shown;

[0069] Figure 3 This is a partial cross-sectional schematic diagram of the second embodiment of the chip packaging structure shown in Figure 1;

[0070] Figure 4 yes Figure 3 A partially exploded view of the chip packaging structure shown.

[0071] Figure 5 yes Figure 2 An exploded view of the third embodiment of the chip layer and heat sink shown;

[0072] Figure 6 yes Figure 2 A cross-sectional schematic diagram of the fourth embodiment of the chip layer shown;

[0073] Figure 7 yes Figure 2 A cross-sectional schematic diagram of the fifth embodiment of the chip layer shown;

[0074] Figure 8 This is a schematic flowchart of a chip packaging structure packaging method provided in an embodiment of this application;

[0075] Figure 9 yes Figure 8 A schematic cross-sectional view of the component formed after step one of S100 in the packaging method of the chip packaging structure shown.

[0076] Figure 10 yes Figure 8 A schematic cross-sectional view of the component formed after step two of S100 in the chip packaging structure shown in the packaging method.

[0077] Figure 11 yes Figure 8 A schematic cross-sectional view of the component formed after step three of S100 in the packaging method of the chip packaging structure shown.

[0078] Figure 12 yes Figure 8 A schematic cross-sectional view of the component formed after step four of S100 in the packaging method of the chip packaging structure shown.

[0079] Figure 13 yes Figure 8 A schematic cross-sectional view of the component formed after step five of S100 in the packaging method of the chip packaging structure shown.

[0080] Figure 14 yes Figure 8 A schematic cross-sectional view of the component formed after step six of S100 in the packaging method of the chip packaging structure shown.

[0081] Figure 15 yes Figure 8 A schematic cross-sectional view of the component formed after step seven of S100 in the packaging method of the chip packaging structure shown.

[0082] Figure 16 yes Figure 8 A schematic cross-sectional view of the component formed after step eight of S200 in the packaging method of the chip packaging structure shown.

[0083] Figure 17 yes Figure 8 A schematic cross-sectional view of the component formed after step ten of S400 in the chip packaging method shown in the diagram.

[0084] Figure 18 This is a schematic cross-sectional view of the component formed after step eleven of S500 in the chip packaging structure packaging method.

[0085] Figure 19 This is a schematic cross-sectional view of the component formed after step 12 of S500 in the chip packaging structure packaging method.

[0086] Figure 20 This is a schematic cross-sectional view of the component formed after S210 in the chip packaging structure packaging method.

[0087] Figure 21 This is another schematic flowchart of the packaging method for the chip packaging structure provided in the embodiments of this application;

[0088] Figure 22 yes Figure 21 A schematic cross-sectional view of the component formed after step one of S200 in the packaging method of the chip packaging structure shown.

[0089] Figure 23 yes Figure 21 A schematic cross-sectional view of the component formed after step two of S300 in the chip packaging structure shown in the packaging method.

[0090] Figure 24 yes Figure 21 A schematic cross-sectional view of the component formed after step three of S200 in the chip packaging structure shown in the packaging method.

[0091] Figure 25 yes Figure 21 A schematic cross-sectional view of the component formed after step four of S200 in the chip packaging method shown in the diagram.

[0092] Figure 26 yes Figure 21 A schematic cross-sectional view of the component formed after step five of S200 in the chip packaging structure shown in the packaging method.

[0093] Figure 27 This is a schematic cross-sectional view of the component formed after step six of S400 in the chip packaging structure packaging method. Detailed Implementation

[0094] The specific embodiments of this application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in other ways different from those described herein, and therefore, this application is not limited to these embodiments.

[0095] For ease of understanding, the terminology used in the embodiments of this application will be explained first.

[0096] Multiple: refers to two or more.

[0097] Connection: should be interpreted broadly. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through an intermediary.

[0098] The specific embodiments of this application will now be clearly described in conjunction with the accompanying drawings.

[0099] Electronic devices consist of a printed circuit board (PCB) and a chip package structure. The chip package structure is connected to the circuit board. The circuit board can supply current to the chip package structure, enabling the chip package structure to operate under the drive of the current.

[0100] Chip packaging structures can be applied to high-power chips and other devices that require high-performance computing, high bandwidth, etc., such as artificial intelligence chips, network chips, and memory chips.

[0101] For example, electronic devices can be mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, laptops, in-vehicle devices, wearable devices, augmented reality (AR) glasses, AR headsets, virtual reality (VR) glasses or VR headsets, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players or digital video recorders, etc.

[0102] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the electronic device 100 provided in this application embodiment. The electronic device 100 in this embodiment is described using a mobile phone as an example. However, it should be understood that this is not a limitation. The electronic device 100 includes a circuit board 10 and a chip package structure 20.

[0103] It should be noted that, Figure 1 The purpose of this illustration is merely to depict the connection relationship between the circuit board 10 and the chip package structure 20, and it is not intended to specifically limit the connection positions, specific structures, or quantities of each device. Furthermore, the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine certain components, or split certain components, or have different component arrangements.

[0104] The circuit board 10 can be a silicon printed circuit board, a laminated printed circuit board, a ceramic printed circuit board, an interposer, or any other suitable support structure.

[0105] In this embodiment, the circuit board 10 provides mounting locations for the chip package structure 20 and other electronic components (such as resistors, capacitors, transistors, etc.) of the electronic device 100. The circuit board 10 can be fixedly connected to the electronic components of the electronic device 100 by means of soldering, connector insertion, etc.

[0106] This application also provides various embodiments of different chip package structures 20 to illustrate the structure of different chip package structures 20.

[0107] In the first possible embodiment, please refer to Figure 2 , Figure 2 yes Figure 1The diagram shows a cross-sectional view of a first embodiment of the chip packaging structure 20. Embodiments of this application provide a chip packaging structure 20 that improves the heat dissipation performance of the chip packaging structure 20, thereby enhancing its operational stability.

[0108] The chip package structure 20 includes a heat sink 21, a chip layer 22, and a substrate 23. The heat sink 21, chip layer 22, and substrate 23 are stacked sequentially along the thickness direction of the chip package structure 20. The chip layer 22 includes a chip and is capable of operating under current to generate the required electrical signal. The chip layer 22 generates heat during operation. The heat sink 21 dissipates the heat from the chip layer 22 to the external environment. The substrate 23 is used for electrical connection between the chip package structure 20 and the circuit board 10.

[0109] The substrate 23 includes a conductive layer 231 and a conductive structure 232. The conductive structure 232 can be a structure such as solder balls for power connection. The conductive layer 231 includes a first surface 2311 and a second surface 2312. The first surface 2311 and the second surface 2312 are disposed opposite to each other. The first surface 2311 is electrically connected to the conductive structure 232. The second surface 2312 is used for electrical connection to the chip layer 22.

[0110] The heat sink 21 includes a body 211 and a heat conductor 212. The heat conductor 212 is connected to one side surface of the body 211. The body 211 is used to cover the chip layer 22. The heat conductor 212 is used to connect to the chip layer 22 to conduct heat out of the chip layer 22.

[0111] The body 211 includes a third surface 2111 and a fourth surface 2112. The third surface 2111 and the fourth surface 2112 are disposed opposite to each other along the thickness direction of the body 211. The thermal conductivity of the body 211 is greater than or equal to 200 W / mK. For example, the material of the body 211 can be a high thermal conductivity material, such as diamond. Diamond has a thermal conductivity of approximately 2000 W / mK.

[0112] In this embodiment, diamond has a high thermal conductivity, enabling it to more effectively transfer heat from the chip package structure 20 to the external environment, thereby cooling the chip package structure 20 in a timely manner. It is known that high temperature is one of the main causes of failure in the chip package structure 20. Prolonged operation in a high-temperature environment can alter the material properties inside the chip package structure 20, such as intensified electromigration in the metal interconnect layer, potentially leading to short circuits or open circuits within the chip package structure 20 and reducing its lifespan. Therefore, improving the heat dissipation performance of the chip package structure 20 helps reduce the chip's operating temperature, decreases the risk of failure due to high temperatures, and thus enhances the reliability of the chip package structure 20.

[0113] Furthermore, diamond has high mechanical strength. Therefore, using a heat sink 21 made of diamond can enhance the overall structural strength of the chip package structure 20, preventing breakage or damage caused by external stress, vibration, or impact. The high-strength chip package structure 20 makes it more robust and reliable when integrated into the electronic device 100, helping to reduce the risk of damage during installation and improve production efficiency.

[0114] A heat conductor 212 is connected to the third surface 2111 of the body 211. The heat conductor 212 protrudes from the third surface 2111 of the body 211. For example, there may be multiple heat conductors 212, which are spaced apart on the third surface 2111. The material of the heat conductor 212 may include a metallic material.

[0115] In one possible implementation, the heat sink 21 may further include a transition layer 213, which covers the third surface 2111 of the body 211, and the heat conductor 212 is disposed on the surface of the transition layer 213 away from the body 211.

[0116] In this embodiment, the diamond and the metal have a high interfacial energy and poor wettability. In addition, the diamond is prone to graphitization at high temperatures. These characteristics make direct bonding between the diamond and the metal difficult.

[0117] The heat sink 21 is provided with a transition layer 213, which can reduce the interfacial energy between the diamond material and the metal material, so that the metal material can more effectively wet the diamond surface, thereby improving the connection strength between the heat conductor 212 of the metal material and the body 211.

[0118] The transition layer 213 is composed of elements or compounds capable of forming chemical bonds with both diamond and metallic materials. These chemical bonds further enhance the connection between the diamond and the metallic materials, allowing the heat conductor 212 to be firmly attached to the surface of the body 211, forming the tenon structure of the heat sink 21. This also ensures that the connection between the body 211 and the heat conductor 212 remains stable at high temperatures.

[0119] In the second embodiment of this application, please refer to [reference needed]. Figure 3 and Figure 4 , Figure 3 This is a partial cross-sectional schematic diagram of the second embodiment of the chip packaging structure 20 shown in Figure 1. Figure 4 yes Figure 3The diagram shows a partially exploded view of the chip package structure 20. Unlike the first embodiment of the chip package structure 20, the chip layer 22 includes a plurality of sub-chips 221 and a planarization layer 222. The planarization layer 222 may be connected at least to the periphery of the sub-chips 221. The planarization layer 222 surrounds the periphery of each sub-chip 221 and fills the gaps between the plurality of sub-chips 221. The plurality of sub-chips 221 may have different functions, such as processing electrical signals. The planarization layer 222 integrates the plurality of sub-chips 221 and provides a flat surface for the chip layer 22.

[0120] Specifically, the heat sink 21 in this embodiment differs from the heat sink 21 in the first embodiment in that the number of heat conductors in the heat sink 21 in this embodiment can be at least three.

[0121] Chip layer 22 has a first surface 2201 and a second surface 2202, which are opposite to each other in the thickness direction of chip layer 22. The first surface 2201 is connected to the second surface 2312 of conductive layer 231 of substrate 23. The second surface 2202 is connected to the third surface 2111 of heat sink 21. A heat conductor 212 is inserted into the planarization layer between every two sub-chips 221.

[0122] Sub-chip 221 includes a wiring layer 2211, a device layer 2212, and a support layer 2213. Along the thickness direction of sub-chip 221, the wiring layer 2211, device layer 2212, and support layer 2213 are stacked sequentially. The wiring layer 2211 is used for communication with other sub-chips 221 or other circuits. The device layer 2212 is the structural layer that implements the main functions of the sub-chip 221. The support layer 2213 can be a carrier layer for the device layer 2212, supporting the wiring layer 2211 and the device layer 2212. In this embodiment, the support layer 2213 can be a silicon substrate.

[0123] In other possible implementations, the sub-chip 221 may also have a wiring layer 2211 and a support layer 2213, but without a device layer 2212. In this case, the sub-chip 221 can transmit electrical signals through the circuitry of the wiring layer 2211.

[0124] Please refer to the following: Figure 3 and Figure 4 A planarization layer 222 is connected to the second surface 2312 of the substrate 23. The planarization layer 222 covers the surface of the substrate 23 not covered by the sub-chip 221. A connection hole 2220 is recessed on the surface of the planarization layer 222 facing away from the substrate 23. The connection hole 2220 may be adjacent to the sub-chip 221. It should be explained that "adjacent to the sub-chip 221" means that the wall of the connection hole 2220 is in contact with the surface of the sub-chip 221. Alternatively, the wall of the connection hole 2220 may be spaced apart from the surface of the sub-chip 221.

[0125] For example, planarization layer 222 may be flush with the surface of support layer 2213 of sub-chip 221 facing away from wiring layer 2211. The surface of planarization layer 222 facing away from substrate 23 and the surface of sub-chip 221 facing away from wiring layer 2211 can form the second surface 2202 of chip layer 22. The surface of planarization layer 222 facing substrate 23 and the surface of wiring layer 2211 of sub-chip 221 facing away from support layer 2213 can form the first surface 2201 of chip layer 22. The second surface 2312 of substrate 23 is connected to the first surface 2201 of chip layer 22.

[0126] In this embodiment, the planarization layer 222 can effectively fill the gaps around the chip periphery, forming a relatively flat plane. The surface planarization of the chip layer 22 is crucial for subsequent process steps, ensuring the accuracy and reliability of subsequent processes such as photolithography and etching. A flat surface helps reduce process errors and improves the yield rate of the chip package structure 20.

[0127] The third surface 2111 of the body 211 of the heat sink 21 faces the second surface 2202 of the chip layer 22. The third surface 2111 of the body 211 is connected to the second surface 2202 of the chip layer 22. The heat conductor 212 of the heat sink 21 can be embedded in the connection hole 2220. The heat conductor 212 is connected to the hole wall of the connection hole 2220. It should be noted that the heat sink 21 is insulated from the chip layer 22.

[0128] In this embodiment, the thermal conductivity of the body 211 of the heat sink 21 of the chip package structure 20 is greater than or equal to 200 W / mK, which is a high thermal conductivity. The high thermal conductivity material can quickly transfer the heat of the chip package structure 20 to the external environment, reducing the accumulation of heat near the chip layer 22.

[0129] Currently, highly integrated chip packaging structures, especially 3D chip packaging structures, operate at excessively high temperatures, which can affect the physical properties of materials within the chip layer, thereby impacting its performance. Changes in the performance of circuit components within the chip layer can slow down its response to load changes and reduce its load adjustment capability. Overheating can also cause output voltage fluctuations or abnormal output currents, further affecting the operational stability of the entire chip packaging structure. The chip packaging structure of this application embodiment can dissipate heat to the outside in a timely manner, reducing the operating temperature of the chip layer, extending its lifespan, and improving its operational stability.

[0130] Furthermore, because the chip layer and the heat sink are made of different materials, their coefficients of thermal expansion differ. During chip packaging operation, heat causes these differences in thermal expansion. This difference leads to interfacial stress between the heat sink and the chip layer. When this interfacial stress exceeds the adhesive force between the materials, delamination occurs.

[0131] In this embodiment, a heat conductor 212 is provided on the body 211 of the heat sink 21. The heat conductor 212 can be equivalent to a tenon structure on the body 211. The heat conductor 212 can be embedded in the connection hole 2220 of the chip layer 22 and located between two sub-chips 221. The connection hole 2220 of the chip layer 22 can be equivalent to a mortise structure of the chip layer 22. The heat sink 21 and the chip layer 22 are connected by a tenon and mortise joint through the heat conductor 212 and the connection hole 2220, thereby improving the bonding force between the heat sink 21 and the chip layer 22 and preventing the phenomenon of delamination of the heat sink 21 relative to the chip layer 22 due to heat generation during the operation of the chip packaging structure 20.

[0132] Specifically, in the initial state of the chip package structure 20, the heat conductor 212 can directly or indirectly contact the wall of the connection hole 2220. There may be no contact force between the heat conductor 212 and the wall of the connection hole 2220, or only a small contact force. When the chip package structure 20 heats up during operation, the chip layer 22 and the heat sink 21 will expand due to heat. The deformation of the heat sink 21 may differ from the deformation of the chip layer 22. The heat conductor 212 can abut against the wall of the connection hole 2220. During the stress process, the heat conductor 212 can undergo slight deformation to absorb the stress between the heat sink 21 and the chip layer 22, reducing the difference in deformation between the body 211 of the heat sink 21 and the chip layer 22, thus preventing excessive stress between the heat sink 21 and the chip layer 22, which could lead to delamination between the body 211 of the heat sink 21 and the chip layer 22.

[0133] The stress between the heat sink 21 and the chip layer 22 increases from the center to the edge. Therefore, the edge of the heat sink 21 is more prone to detaching from the chip layer 22. Multiple heat conductors 212 of the heat sink 21 can be spaced apart. These multiple heat conductors 212 can divide the overall structure of the heat sink 21 into multiple small stress regions. Each heat conductor 212 can absorb the stress between the heat sink 21 and the chip layer 22, thereby releasing the stress in the area where the heat conductor 212 is located, preventing stress from accumulating from the center to the edge, thus improving the connection strength between the heat sink 21 and the chip layer 22, and preventing the edge of the heat sink 21 from detaching from the chip layer 22.

[0134] The heat conductor 212 extends into the interior of the chip layer 22, and the contact area between the heat conductor 212 and the chip layer 22 is relatively large. A large contact area means that there are more heat transfer paths from the chip layer 22 to the heat conductor 212, allowing heat to be transferred more quickly from the chip layer 22 to the heat conductor 212. The heat is then transferred through the heat conductor 212 to the body 211 of the heat sink 21, and then dissipated into the external environment, completing the heat dissipation process and improving heat dissipation efficiency. Multiple heat conductors 212 can transfer heat simultaneously, thereby evenly distributing heat across the entire body of the heat sink and improving the heat dissipation performance of the chip package structure 20. A chip package structure 20 with good heat dissipation performance can ensure that heat is quickly and evenly transferred from the chip layer to the heat sink, thereby improving overall heat dissipation efficiency.

[0135] For one possible implementation, please refer to [link / reference]. Figure 3 The chip package structure 20 also includes a metal layer 240. The metal layer 240 is connected to and covers the surface of the chip layer 22 facing away from the substrate 23 and the walls of the connection holes 2220. The body 211 and the heat conductor 212 are connected to the side of the metal layer 240 facing away from the chip layer 22.

[0136] In this embodiment, the metal layer 240 serves as a bonding layer, mitigating thermal stress caused by the mismatch in thermal expansion coefficients between the body 211 and the planarization layer 222 of the heat sink 21. The difference in thermal expansion coefficients between the body 211 and the planarization layer 222 can lead to stress concentration at the interface when the temperature changes, thus affecting the connection strength. The metal layer 240, as a bonding layer, absorbs and disperses these stresses, thereby protecting the connection between the body 211 and the planarization layer 222 from damage.

[0137] Furthermore, the metal layer 240 covers the wall of the connection hole 2220 and is connected to the heat conductor 212. When the heat conductor 212 is a metallic material, the atoms inside the heat conductor 212 and the metal layer 240 form chemical bonds through covalent bonds or metallic bonds. The bonding ability between the metal layer 240 and the heat conductor 212 located in the connection hole 2220 is significantly enhanced, thereby improving the connection strength between the heat sink 21 and the chip layer 22.

[0138] In the third possible embodiment, please refer to Figure 5 , Figure 5 yes Figure 2 The diagram shows an exploded view of the third embodiment of the chip layer 22 and heat sink 21. Unlike the first embodiment of the chip layer 22, the chip package structure 20 in this embodiment may include multiple chip layers 22, wiring layers 25, and a first pad layer 26.

[0139] The number of chip layers 22 can be two or more. For ease of definition, the two chip layers 22 are designated as first chip layer 22a and second chip layer 22b. First chip layer 22a and second chip layer 22b are stacked. Wiring layer 25 and first pad layer 26 are disposed between first chip layer 22a and second chip layer 22b.

[0140] The first chip layer 22a includes a plurality of sub-chips 221. For ease of description, the sub-chips 221 of the first chip layer 22a are defined as first sub-chips 221a. The plurality of first sub-chips 221a are spaced apart on the second surface 2312 of the conductive structure of the substrate 23. The wiring layer 2211 of each first sub-chip 221a is connected to the substrate 23. The support layer 2213 of the first sub-chip 221a is located on the side of the wiring layer 2211 facing away from the substrate 23. For example, the first chip layer 22a may include two first sub-chips 221a. For example, the support layer 2213 of the first chip layer 22a is provided with a plurality of vias 2214. The vias 2214 penetrate the support layer 2213 along its thickness direction. A metal material is deposited within the vias 2214, and the metal material is electrically connected to the device layer 2212.

[0141] The first chip layer 22a is provided with a first planarization layer 2221. The first planarization layer 2221 is connected to the side of the substrate 23 facing the first sub-chip 221a. The first planarization layer 2221 covers the surface of the substrate 23 not covered by the first sub-chip 221a. For example, the first planarization layer 2221 may be flush with the surface of the support layer 2213 of the first sub-chip 221a away from the wiring layer 2211. The surface of the first planarization layer 2221 away from the substrate 23 and the surface of the first sub-chip 221a away from the wiring layer 2211 can form the second surface 2202 of the first chip layer 22a. The surface of the first planarization layer 2221 facing the substrate 23 and the surface of the wiring layer 2211 of the first sub-chip 221a away from the support layer 2213 can form the first surface 2201 of the first chip layer 22a.

[0142] The first planarization layer 2221 may also be provided with a plurality of conductive vias 2222, which can penetrate the first planarization layer 2221 along the thickness direction of the first planarization layer 2221. The conductive vias 2222 are used to electrically connect the conductive layer 231 of the substrate 23 to the wiring layer 25.

[0143] Wiring layer 25 covers the second surface 2202 of the first chip layer 22a. Wiring layer 25 is connected to the first sub-chip 221a of the first chip layer 22a through vias in the support layer 2213. Wiring layer 25 has traces and is used to connect the first chip layer 22a and the second chip layer 22b.

[0144] The first pad layer 26 is connected to the surface of the wiring layer 25 opposite to the first chip layer 22a. The first pad layer 26 is electrically connected to the wiring layer 25. The first pad layer 26 is used to connect the wiring layer 25 to the second chip layer 22b.

[0145] The second chip layer 22b includes a plurality of sub-chips 221. For ease of description, the sub-chips 221 of the second chip layer 22b are defined as second sub-chips 221b. The plurality of second sub-chips 221b are spaced apart on the first pad layer 26. The routing layer 2211 of each second sub-chip 221b is connected to the first pad layer 26. The support layer 2213 of the second sub-chip 221b is located on the side of the routing layer 2211 facing away from the first pad layer 26. For example, the second chip layer 22b may include two second sub-chips 221b. The second sub-chips 221b may also have a second pad layer 2215. The second pad layer 2215 is connected to the surface of the routing layer 2211 of the second sub-chip 221b facing away from the support layer 2213. The second pad layer 2215 is electrically connected to the first pad layer 26, so that the routing layer 2211 of the second sub-chip 221b can communicate with the wiring layer 25.

[0146] It should be noted that the specific structure of the second sub-chip 221b of the second chip layer 22b is different from that of the first sub-chip 221a. The support layer 2213 of the second sub-chip 221b of the second chip layer 22b may not have through holes.

[0147] The second chip layer 22b has a second planarization layer 2223. The second planarization layer 2223 is connected to the side of the first pad layer 26 facing the second sub-chip 221b. The second planarization layer 2223 covers the surface of the first pad layer 26 not covered by the second sub-chip 221b. For example, the second planarization layer 2223 may be flush with the surface of the support layer 2213 of the second sub-chip 221b away from the trace layer 2211. The surface of the second planarization layer 2223 away from the first pad layer 26 and the surface of the second sub-chip 221b away from the trace layer 2211 can form the second surface 2202 of the second chip layer 22b. The surface of the second planarization layer 2223 facing the first pad layer 26 and the surface of the second pad layer 2215 of the second sub-chip 221b away from the trace layer 2211 can form the first surface 2201 of the second chip layer 22b.

[0148] A connection hole 2220 is provided in the second planarization layer 2223. The connection hole 2220 is recessed from the surface of the second planarization layer 2223 away from the first pad layer 26 (second surface 2202). The connection hole 2220 may be located between two adjacent second sub-chips 221b. Alternatively, the connection hole 2220 may be located at the periphery of the second sub-chip 221b and spaced apart from the second sub-chip 221b.

[0149] The third surface 2111 of the body 211 of the heat sink 21 faces the second surface 2202 of the second chip layer 22b. The body 211 is connected to the second surface 2202 of the chip layer 22. The heat conductor 212 of the heat sink 21 can be embedded in the connection hole 2220. The heat conductor 212 is connected to the hole wall of the connection hole 2220. It should be noted that the heat sink 21 is insulated from the chip layer 22.

[0150] As sub-chips become increasingly complex and integrated, heat dissipation has become a key factor affecting the performance and lifespan of chip packaging structures. In this embodiment, the heat conductor 212 can utilize the gaps between multiple sub-chips 221 without occupying space in the thickness of the chip packaging structure 20, thus allowing the chip packaging structure 20 to be made thinner and lighter. A thinner overall packaging structure is more conducive to heat dissipation from the chip packaging structure 20, which is then quickly dissipated into the air through the heat sink 21, thereby ensuring that the chip packaging structure 20 operates at a suitable temperature and extending its service life.

[0151] As electronic devices 100 become increasingly thinner and lighter, the reduction in the size of the chip packaging structure 20 makes it easier to integrate the chip packaging structure 20 into various electronic devices 100, meeting the needs of modern electronic devices 100 for miniaturization and lightweighting.

[0152] In the fourth possible embodiment, please refer to Figure 6 , Figure 6 yes Figure 2 This is a cross-sectional schematic diagram of the fourth embodiment of chip layer 22. (The last sentence appears to be incomplete and possibly refers to a different embodiment of chip layer 22.) Figure 2 The difference from the first embodiment shown is that the connection hole 2220 is recessed by the second surface 2202 of the second chip layer 22b, and the connection hole 2220 penetrates the second planarization layer 2223, the wiring layer 25 and the first pad layer 26 of the second chip layer 22b and extends into the first planarization layer 2221 of the first chip layer 22a.

[0153] The heat conductor 212 of the heat sink 21 is embedded in the connection hole 2220, and the heat conductor 212 extends from the second planarization layer 2223 to the first planarization layer 2221.

[0154] In this embodiment, the length of the heat conductor 212 can exceed the thickness of one chip layer 22. This allows for a longer tenon structure in the mortise and tenon connection. When the heat conductor 212 is embedded in the connection hole 2220, the contact area between the heat conductor 212 and the connection hole 2220 is larger, resulting in a tighter connection. This provides better mutual restraint between the heat sink 21 and the chip layer 22, increasing the structural stability of the connection between the heat sink 21 and the chip layer 22.

[0155] In addition, the larger contact area between the heat conductor 212 and the chip layer 22 increases the heat transfer efficiency between the chip layer 22 and the heat conductor 212, allowing heat to be transferred more quickly from the chip layer 22 to the heat conductor 212. The heat is then transferred through the heat conductor 212 to the body 211 of the heat sink 21, and then dissipated into the external environment to complete the heat dissipation process.

[0156] In the fifth possible embodiment, please refer to Figure 7 , Figure 7 yes Figure 2 The diagram shows a cross-sectional view of the fifth embodiment of chip layer 22. Unlike the first embodiment of chip layer 22, in this embodiment, the planarization layer 222 of chip layer 22 covers the side of the support layer 2213 away from the wiring layer 2211, and the surface of the planarization layer 222 away from the wiring layer 2211 is the second surface 2202 of chip layer 22.

[0157] The connection hole 2220 penetrates the planarization layer 222, and part of the support layer 2213 is exposed relative to the connection hole 2220 on the surface away from the wiring layer 2211.

[0158] The third surface 2111 of the body 211 of the heat sink 21 faces the second surface 2202 of the chip layer 22. The body 211 is connected to the second surface 2202 of the chip layer 22. The heat conductor 212 of the heat sink 21 can be embedded in the connection hole 2220. The heat conductor 212 is connected to the hole wall of the connection hole 2220. The end face of the heat conductor 212 facing away from the body 211 contacts the support layer 2213.

[0159] In this embodiment, the heat conductor 212 can directly contact the support layer 2213. Therefore, the heat generated by the signal transmission of the wiring layer 2211 can be directly transferred to the heat conductor 212 through the support layer 2213, without needing to pass through the planarization layer 222. This reduces the thermal resistance of the planarization layer 222 during heat transfer, allowing heat to reach the heat sink more directly and quickly, and then be transferred to the external environment through the body 211 of the heat sink 21, thereby improving the heat dissipation efficiency of the chip package structure 20. The chip package structure 20 can dissipate the internally generated heat more quickly, thus maintaining a lower operating temperature and slowing down the aging rate of the chip layer 22. This means that each part of the chip package structure 20 can maintain its performance for a longer period, extending the lifespan of the chip package structure 20.

[0160] It should be noted that in the chip packaging structure 20 provided in this application embodiment, the chip layer 22 is not limited to two layers, and the sub-chips 221 of each chip layer 22 are not limited to two. Multiple chip layers 22 can also be stacked in a stepped distribution, and the specific structure of the chip layer 22 and the heat sink 21 can be set according to the actual scenario requirements.

[0161] The following description, in conjunction with the packaging method of the chip packaging structure 20, further illustrates the chip packaging structure 20 provided in the embodiments of this application.

[0162] This application provides a packaging method for a chip packaging structure 20. Please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic flowchart of a packaging method for a chip packaging structure 20 provided in an embodiment of this application. The packaging method includes, but is not limited to, steps S100, S200, S300, and S400. The detailed description of steps S100, S200, S300, and S400 is as follows: used to manufacture the chip packaging structure 20 of any of the above examples.

[0163] S100: A chip layer 22 is provided, the chip layer 22 includes a first surface 2201 and a second surface 2202, the first surface 2201 and the second surface 2202 are opposite to each other in the thickness direction of the chip layer 22, the chip layer includes a planarization layer and a sub-chip, the planarization layer is at least connected to the periphery of the sub-chip.

[0164] S200: A connection hole 2220 is formed in the planarization layer of chip layer 22. The connection hole 2220 is recessed from the second surface 2202. The connection hole is adjacent to the sub-chip.

[0165] S300: Provides a heat sink 21, which includes a body 211 and a heat conductor 212. The heat conductor 212 is fixedly connected to one side of the body 211. The thermal conductivity of the body 211 is greater than or equal to 200W / mK.

[0166] S400: The heat sink 21 is connected to the chip layer 22 to form a package structure. The heat conductor 212 is inserted into the connection hole 2220 and connected to the hole wall of the connection hole 2220. The body 211 is connected to the second surface 2202 of the chip layer 22.

[0167] In this embodiment, the heat sink 21 and the chip layer 22 can be formed separately, and then pressed together. Separate forming of the heat sink 21 and the chip layer 22 makes the production process more flexible, allowing for optimization of the manufacturing processes and material selection for each according to actual needs. Furthermore, it avoids assembling defective products of the heat sink 21 with the chip layer 22, or vice versa, preventing any impact on the yield of the chip packaging structure 20. This helps reduce overall manufacturing costs, improve production efficiency, and reduce material waste.

[0168] The heat conductor 212 can be equivalent to the tenon structure on the main body 211. The heat conductor 212 can be embedded in the connection hole 2220 of the chip layer 22 and located between the two sub-chips 221. The connection hole 2220 of the chip layer 22 can be equivalent to the mortise structure of the chip layer 22. The heat sink 21 and the chip layer 22 are connected by the heat conductor 212 and the connection hole 2220, thereby improving the bonding force between the heat sink 21 and the chip layer 22 and preventing the heat sink 21 from delaminating relative to the chip layer 22 due to heat generation during the operation of the chip package structure 20.

[0169] Combination Figure 8 The aforementioned manufacturing method, in order to Figure 5 The illustrated embodiment is used as an example to illustrate the following. Figures 9-15 The specific methods for formal description are detailed below.

[0170] Providing chip layer 22 includes the following steps:

[0171] Please see Figure 9 , Figure 9 yes Figure 8 This is a schematic cross-sectional view of the component formed after step S100 in the packaging method of the chip packaging structure 20 shown. In step S100, the number of chip layers 22 can be multiple. For example, in an embodiment where the number of chip layers 22 is two, step S100 may include:

[0172] Provide the first chip layer 22a.

[0173] A wiring layer 25 and a first pad layer 26 are formed on the surface of the first chip layer 22a. The first pad layer 26 is connected to the side of the wiring layer 25 away from the first chip layer 22a.

[0174] A second chip layer 22b is formed on the surface of the first pad layer 26 opposite to the wiring layer 25. The second chip layer 22b includes a first surface 2201 and a second surface 2202. The first surface 2201 and the second surface 2202 are opposite to each other in the thickness direction of the second chip layer 22b. The chip layer 22b includes a planarization layer 222 and a sub-chip 221. The planarization layer 222 is at least connected to the periphery of the sub-chip 221.

[0175] Specifically, it includes:

[0176] Step 1: Provide a temporary substrate 40, and form two first sub-chips 221a on the surface of the temporary substrate 40. Multiple first sub-chips 221a are spaced apart. The multiple first sub-chips 221a are soldered onto the temporary substrate 40 using a flip-chip bonding method.

[0177] Please see Figure 10 , Figure 10 yes Figure 8A schematic cross-sectional view of the component formed after step two of S100 in the packaging method of the chip packaging structure 20 shown.

[0178] Step 2: Fill the gaps between the multiple first sub-chips 221a with a filler and cure to form a filler layer 50. The surface of the filler layer facing away from the temporary carrier 40 needs to be planarized by methods such as chemical mechanical polishing. The material of the filler layer 50 may include SiO2, organic resin, polyimide, etc.

[0179] Please see Figure 11 , Figure 11 yes Figure 8 A schematic cross-sectional view of the component formed after step three of S100 in the packaging method of the chip packaging structure 20 shown.

[0180] Step 3: Thin the fill layer 50 to form a planarization layer 222, exposing the metal conductors within the vias of the support layer 2213 of the first sub-chip 221a to the surface of the planarization layer 222. The thinning of the fill layer 50 can be performed using processes such as grinding and etching.

[0181] Please see Figure 12 , Figure 12 yes Figure 8 A schematic cross-sectional view of the component formed after step four of S100 in the packaging method of the chip packaging structure 20 shown.

[0182] Step 4: Conductive vias 2222 are fabricated on the planarization layer 222, and a metal layer is formed on the wall of the conductive vias 2222. The conductive vias 2222 are fabricated on the planarization layer 222 through processes such as exposure, development, and etching, and the metal layer of the conductive vias 2222 is formed through processes such as sputtering and electroplating of metal materials to form the first chip layer 22a.

[0183] Please see Figure 13 , Figure 13 yes Figure 8 A schematic cross-sectional view of the component formed after step five of S100 in the packaging method of the chip packaging structure 20 shown.

[0184] Step 5: Form a wiring layer 25 and a first pad layer 26 on the surface of the first chip layer 22a that is away from the temporary carrier 40.

[0185] Please see Figure 14 , Figure 14 yes Figure 8 A schematic cross-sectional view of the component formed after step six of S100 in the packaging method of the chip packaging structure 20 shown.

[0186] Step Six: Provide two second sub-chips 221b and attach them to the first pad layer 26 using flip-chip bonding. The bonding method can be hybrid bonding, micro-bump bonding, etc. The bonding interface material is not limited.

[0187] Please see Figure 15 , Figure 15 yes Figure 8 A schematic cross-sectional view of the component formed after step seven of S100 in the packaging method of the chip packaging structure 20 shown.

[0188] Step 7: Fill the gaps between the multiple second sub-chips 221b with a filler and cure to form a filler layer. The surface of the filler layer facing away from the temporary carrier 40 needs to be planarized by chemical mechanical polishing or other methods to form a second planarization layer 2223. The material of the filler layer may include SiO2, organic resin, polyimide, etc.

[0189] The following will be through Figure 16 Step S200 will be described in detail below.

[0190] Forming a connection hole 2220 in chip layer 22 includes the following steps:

[0191] Please see Figure 16 , Figure 16 yes Figure 8 A schematic cross-sectional view of the component formed after step eight of S200 in the packaging method of the chip packaging structure 20 shown.

[0192] Step 8: A connection hole 2220 recessed towards the first sub-chip 221a is formed on the surface of the second planarization layer 2223 of the second sub-chip 221b. Specifically, the pattern is defined by exposure and development, and photoresist, metal, inorganic thin film, etc. are used as masks. The second planarization layer 2223 is etched by plasma, ion beam, etc. to form the connection hole 2220.

[0193] The following will be through Figure 17 Step S300 will be described in detail below.

[0194] Providing heat sink 21 includes the following steps:

[0195] Please refer to the following: Figure 5 .

[0196] Step 9: Provide a body 211, form a transition layer 213 on the surface of the body 211, and form a heat conductor 212 on the side of the transition layer 213 away from the body 211, so that the heat conductor 212, the transition layer 213 and the body 211 form a heat dissipation plate 21.

[0197] Specifically, the pattern of the heat conductor 212 of the heat sink 21 is defined by exposure and development, and the heat conductor 212 is fabricated by sputtering, electroplating or other methods using photoresist as a mask.

[0198] The following will be through Figure 17 Step S400 will be described in detail below.

[0199] Providing heat sink 21 includes the following steps:

[0200] Please see Figure 17 , Figure 17 yes Figure 8 A schematic cross-sectional view of the component formed after step ten of S400 in the packaging method of the chip packaging structure 20 shown.

[0201] Step 10: Mount the heat sink 21 onto the surface of the second chip layer 22b, insert the heat conductor 212 into the connection hole 2220, and press the heat sink 21 and the chip layer 22 together. Specifically, the heat sink 21 and the chip layer 22 are bonded together by means of hot pressing or similar methods. The heat conductor 212 is inserted into the connection hole 2220 and bonded via eutectic bonding.

[0202] In one possible implementation, after the heat sink 21 is connected to the chip layer 22, the packaging method further includes S500.

[0203] S500: A substrate 23 is formed on the surface of the chip layer 22 away from the heat sink 21.

[0204] The following will be through Figures 18-19 Step S500 will be described in detail below.

[0205] Forming a substrate 23 on the surface of the chip layer 22 away from the heat sink 21 includes the following steps:

[0206] Please see Figure 18 , Figure 18 This is a schematic cross-sectional view of the component formed after step eleven of S500 in the packaging method of chip packaging structure 20.

[0207] Step 11: Remove temporary substrate 40.

[0208] Please see Figure 19 , Figure 19 This is a schematic cross-sectional view of the component formed after step twelve of S500 in the packaging method of chip packaging structure 20.

[0209] Step 12: A conductive layer 231 and a conductive structure 232 are formed on the surface of the first chip layer 22a opposite to the wiring layer 25. The conductors of the wiring layer 25 are made of metal, such as copper or aluminum.

[0210] Please see Figure 20 , Figure 20 This is a schematic cross-sectional view of the component formed after S210 in the packaging method of the chip package structure 20. In one possible implementation, after the connection hole 2220 is formed on the chip layer 22 and before the heat sink 21 is provided, the packaging method further includes:

[0211] S210: A metal layer 240 is formed on the second surface 2202, covering the second surface 2202 and the wall of the connecting hole 2220. The heat sink 21 is attached to the metal layer 240, and the heat conductor 212 is connected to the metal layer 240.

[0212] This application provides another packaging method for chip packaging structure 20. Please refer to [link to relevant documentation]. Figure 21 , Figure 21 This is another schematic flowchart of the packaging method for the chip packaging structure 20 provided in this application embodiment. Unlike the previous packaging method for the chip packaging structure 20, in this packaging method, the sub-chip 221 is directly formed on the heat sink 21. The packaging method includes, but is not limited to, steps S100, S200, and S300. A detailed description of steps S100, S200, and S300 is as follows:

[0213] S100: Provides a heat sink 21, which includes a body 211 and a heat conductor 212. The heat conductor 212 is fixedly connected to one side of the body 211. The thermal conductivity of the body 211 is greater than or equal to 200W / mK.

[0214] S200: A sub-chip 221 is formed on the surface of the heat sink 21 where a heat conductor 212 is provided, and the sub-chip 221 and the heat conductor 212 are spaced apart.

[0215] S300: A planarization layer 222 is formed on the surface of the heat sink 21 where the heat conductor 212 is provided. The planarization layer 222 covers the heat conductor 212 and fills the gap between the sub-chip 221 and the heat conductor 212.

[0216] In this embodiment, the planarization layer 222 can be directly formed by covering the heat conductor 212. After covering the heat conductor 212, the planarization layer 222 adapts to the shape of the heat conductor 212 to form a hole structure. This avoids the mismatch between the hole structure of the planarization layer 222 and the shape of the heat conductor 212, which would prevent the heat sink 21 from being properly connected to the chip layer 22.

[0217] In one possible implementation, after a planarization layer 222 is formed on the surface of the heat sink 21 where the heat conductor 212 is provided, the encapsulation method further includes S400.

[0218] S400: A substrate 23 is formed on the surface of the sub-chip 221 away from the heat sink 21.

[0219] Combination Figure 21 The aforementioned manufacturing method, in order to Figure 5 The illustrated embodiment is used as an example to illustrate the following. Figures 22-27 The specific methods for formal description are detailed below.

[0220] Forming a sub-chip 221 on the surface of the heat sink 21 where a heat conductor 212 is provided includes the following steps:

[0221] Please see Figure 22 , Figure 22 yes Figure 21 This is a schematic cross-sectional view of the component formed after step S200 in the packaging method of the chip packaging structure 20 shown. Step S200 specifically includes:

[0222] Step 1: A metal layer 240 is formed on the surface of the heat sink 21 where the heat conductor 212 is located, and the metal layer 240 covers the heat conductor 212. The body 211 of the heat sink 21 is then bonded to the surface of the support layer 2213 of the second sub-chip 221b. The metal layer 240 can be formed by sputtering, electroplating, or other methods. The body 211 of the heat sink 21 can be bonded to the support layer 2213 of the second sub-chip 221b by hot pressing or other methods.

[0223] Specifically, the following will be through Figure 23 Step S300 will be described in detail below.

[0224] Forming a planarization layer 222 on the surface of the heat sink 21 where the heat conductor 212 is provided includes the following steps:

[0225] Please see Figure 23 , Figure 23 yes Figure 21 A schematic cross-sectional view of the component formed after step two of S300 in the packaging method of the chip packaging structure 20 shown.

[0226] Step 2: A second planarization layer 2223 is formed on the surface of the metal layer 240 away from the heat conductor 212. The second planarization layer 2223 covers the metal layer 240 and fills the gap between the second sub-chip 221b and the heat conductor 212.

[0227] Specifically, a filler is used to fill the gaps between multiple second sub-chips 221b, and then cured to form a filler layer 50. The surface of the filler layer 50 facing away from the temporary carrier 40 needs to be planarized by means of chemical mechanical polishing or the like to form a second planarization layer 2223. The material of the filler layer 50 may include SiO2, organic resin, polyimide, etc.

[0228] A wiring layer 25 and a first pad layer 26 are sequentially formed on the surface of the second planarization layer 2223.

[0229] In some possible embodiments, S200 further includes steps three through five.

[0230] Please see Figure 24 , Figure 24 yes Figure 21 A schematic cross-sectional view of the component formed after step three of S200 in the packaging method of the chip packaging structure 20 shown.

[0231] Step 3: The first sub-chip 221a is soldered onto the surface of the first pad layer 26 using flip-chip bonding, which can be either hybrid bonding or micro-bump bonding.

[0232] Please see Figure 25 , Figure 25 yes Figure 21 A schematic cross-sectional view of the component formed after step four of S200 in the packaging method of the chip packaging structure 20 shown.

[0233] Step 4: Fill the gaps between the multiple first sub-chips 221a with a filler and cure to form a filler layer. The surface of the filler layer facing away from the temporary substrate 40 needs to be planarized by chemical mechanical polishing or other methods to form a first planarization layer 2221.

[0234] Please see Figure 26 , Figure 26 yes Figure 21 A schematic cross-sectional view of the component formed after step five of S200 in the packaging method of the chip packaging structure 20 shown.

[0235] Step 5: Conductive vias 2222 are fabricated in the first planarization layer 2221 and a metal material is formed. Specifically, conductive vias 2222 are fabricated in the planarization layer 222 through processes such as exposure, development, and etching, and a metal material is formed through processes such as sputtering and electroplating to form the first chip layer 22a.

[0236] Specifically, the following will be through Figure 27 Step S400 will be described in detail below.

[0237] Forming a substrate 23 on the surface of the sub-chip 221 away from the heat sink 21 includes the following steps:

[0238] Please see Figure 27 , Figure 27 This is a schematic cross-sectional view of the component formed after step six of S400 in the packaging method of chip packaging structure 20.

[0239] Step 6: A conductive layer 231 and a conductive structure 232 are formed on the surface of the first chip layer 22a opposite to the wiring layer 25. The wires of the wiring layer 25 are made of metal, such as copper or aluminum.

[0240] The above are exemplary embodiments of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A chip packaging structure, characterized in that, include: substrate; A chip layer, comprising a planarization layer and a sub-chip, wherein the planarization layer is at least connected to the periphery of the sub-chip, the chip layer has a first surface and a second surface, the first surface and the second surface being opposite to each other in the thickness direction of the chip layer, the first surface being connected to the substrate, and the chip layer having a connection hole, the connection hole being recessed from the second surface into the interior of the planarization layer, the connection hole being adjacent to the sub-chip; A heat sink, comprising a body and a heat conductor, wherein the heat conductor is fixedly connected to one side of the body and connected to the wall of the connecting hole, the body is connected to the second surface of the chip layer, and the thermal conductivity of the body is greater than or equal to 200W / mK.

2. The chip packaging structure according to claim 1, characterized in that, The material of the body includes diamond.

3. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a metal layer connected to the second surface and the wall of the connection hole, the body connected to the side of the metal layer away from the second surface, and the heat conductor connected to the side of the metal layer away from the wall of the connection hole.

4. The chip packaging structure according to claim 1, characterized in that, The heat sink further includes a transition layer that covers the surface of the body facing the heat conductor, the heat conductor being connected to the side of the transition layer away from the body, and the transition layer being connected to the second surface.

5. The chip packaging structure according to any one of claims 1-4, characterized in that, The chip layer further includes a support layer and a wiring layer, the wiring layer being stacked on top of the support layer. The wiring layer faces the substrate, and the support layer faces the heat sink. The planarization layer covers the surface of the support layer that faces away from the wiring layer, and the surface of the planarization layer that faces away from the wiring layer is the second surface. The connection hole penetrates the planarization layer, and a portion of the support layer's surface facing away from the wiring layer is exposed relative to the connection hole. The end face of the heat conductor facing away from the body contacts the support layer.

6. The chip packaging structure according to any one of claims 1-4, characterized in that, The chip layer includes a planarization layer and at least two sub-chips, the at least two sub-chips being disposed at intervals on the substrate, and the planarization layer being located in the gaps between the sub-chips; The connection hole is recessed on the surface of the planarization layer away from the substrate, and the connection hole is located between two adjacent sub-chips.

7. The chip packaging structure according to claim 6, characterized in that, The number of chip layers is at least two, and the at least two chip layers are a first chip layer and a second chip layer. The first chip layer and the second chip layer are stacked together. The first chip layer is connected to the substrate. The surface of the second chip layer that is away from the first chip layer is the second surface. The connection hole is recessed in the second surface of the second chip layer, and the connection hole penetrates the planarization layer of the second chip layer and extends into the planarization layer of the first chip layer.

8. An electronic device, characterized in that, It includes a circuit board and a chip package structure as described in any one of claims 1-7, wherein the circuit board is connected to the chip package structure.

9. A packaging method for a chip packaging structure, characterized in that, include: A chip layer is provided, the chip layer including a first surface and a second surface, the first surface and the second surface being opposite to each other in the thickness direction of the chip layer, the chip layer including a planarization layer and a sub-chip, the planarization layer being at least connected to the periphery of the sub-chip; A connection hole is formed in the planarization layer of the chip layer, the connection hole is recessed by the second surface, and the connection hole is adjacent to the sub-chip; A heat sink is provided, the heat sink comprising a body and a heat conductor, the heat conductor being fixedly connected to one side of the body, the thermal conductivity of the body being greater than or equal to 200W / mK; The heat sink is connected to the chip layer to form the chip package structure. The heat conductor is inserted into the connection hole and connected to the hole wall. The body is connected to the second surface of the chip layer.

10. The packaging method according to claim 9, characterized in that, After connecting the heat sink to the chip layer, the packaging method further includes: A substrate is formed on the chip layer away from the surface of the heat sink.

11. The packaging method according to claim 9 or 10, characterized in that, The steps for providing a heat sink include: Provide the main body; A transition layer is formed on the surface of the body; A heat conductor is formed on the side of the transition layer opposite to the body, so that the heat conductor, the transition layer and the body form a heat dissipation plate.

12. The packaging method according to claim 9 or 10, characterized in that, After the interconnect holes are formed on the chip layer and before the heat sink is provided, the packaging method further includes: A metal layer is formed on the second surface, the metal layer covering the second surface and the wall of the connecting hole.

13. The packaging method according to claim 12, characterized in that, The step of connecting the heat sink to the chip layer includes: The heat sink is bonded to the chip layer by hot pressing, the body covers the side of the metal layer away from the second surface, and the heat conductor is bonded to the metal layer located in the connection hole by eutectic bonding.

14. The packaging method according to claim 12, characterized in that, The step of connecting the heat sink to the chip layer includes: The heat sink is bonded to the surface of the metal layer away from the chip layer by welding. The body is fixedly connected to the surface of the metal layer away from the second surface by diffusion welding. The heat conductor is fixedly connected to the metal layer located in the connection hole by diffusion welding.

15. The packaging method according to claim 9 or 10, characterized in that, The steps for providing the chip layer include: Provide the first chip layer; A wiring layer and a first pad layer are formed on the surface of the first chip layer, and the first pad layer is connected to the side of the wiring layer opposite to the first chip layer. A second chip layer is formed on the surface of the first pad layer opposite to the wiring layer. The second chip layer includes a first surface and a second surface, which are opposite to each other in the thickness direction of the second chip layer. The chip layer includes a planarization layer and a sub-chip, and the planarization layer is at least connected to the periphery of the sub-chip.

16. A packaging method for a chip packaging structure, characterized in that, include: A heat sink is provided, the heat sink comprising a body and a heat conductor, the heat conductor being fixedly connected to one side of the body, the thermal conductivity of the body being greater than or equal to 200W / mK; A sub-chip is formed on the surface of the heat sink where the heat conductor is located, and the sub-chip is spaced apart from the heat conductor. A flat layer is formed on the surface of the heat sink where the heat conductor is located. The flat layer covers the heat conductor and fills the gap between the sub-chip and the heat conductor.

17. The packaging method according to claim 16, characterized in that, After the heat sink has a flattened layer formed on the surface of the heat conductor, the encapsulation method further includes: A substrate is formed on the surface of the sub-chip that is away from the heat sink.

18. The packaging method according to claim 16 or 17, characterized in that, The step of forming a planarization layer on the surface of the heat sink where the heat conductor is located includes: A metal layer is formed on the surface of the heat sink where the heat conductor is located, and the metal layer covers the heat conductor. A planarization layer is formed on the surface of the metal layer opposite to the heat conductor, the planarization layer covering the metal layer and filling the gap between the sub-chip and the heat conductor.

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