A trench stress buffer type multilayer high thermal conductivity composite substrate and a preparation method thereof

Abstract

The application provides a trench stress buffer type multilayer high-thermal-conductivity composite substrate and a preparation method thereof. The composite substrate comprises a plurality of functional layers and a plurality of heat dissipation layers which are alternately stacked from top to bottom, and an intermediate layer is arranged between two adjacent layers. The heat dissipation layer is provided with a plurality of trenches, and the trenches are filled with a medium material to form a distributed stress regulation unit for dividing a stress transmission path, relieving interface thermal stress concentration and inhibiting crack propagation. The application constructs a multidimensional heat conduction channel by alternately stacking the functional layer and the heat dissipation layer to efficiently dredge the internal heat. The distributed stress regulation structure is arranged in the heat dissipation layer to disperse the concentrated thermal stress of the heterogeneous interface, inhibit wafer warping, interface cracking and debonding defects. The application takes into account the heat dissipation performance and structural mechanical stability, the overall material selection is flexible, is suitable for various semiconductor preparation processes, and has strong expansion of the laminated structure and can be suitable for various three-dimensional heterogeneous integrated devices, and has outstanding industrial application value.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor heterogeneous integration, three-dimensional integration, chip heat dissipation and composite substrate technology, and in particular to a trench stress buffer type multilayer high thermal conductivity composite substrate and its preparation method. Background Technology

[0002] As artificial intelligence chips, high-performance computing chips, and three-dimensional heterogeneous integrated chips rapidly iterate towards higher integration, miniaturization, and higher frequency, chip power density is increasing exponentially. In addition, the three-dimensional heterogeneous integration process uses a vertical stacking method to integrate multiple functional thin films and device structures, resulting in a high concentration of heat sources inside the chip. The multi-layer barrier structure formed by stacking significantly extends the heat conduction path. Relying solely on the traditional unidirectional heat dissipation path of the bottom substrate can no longer meet the heat dissipation requirements of high heat flux density chips.

[0003] To address the bottleneck of chip heat dissipation, the current mainstream solution in the industry is to fabricate a heat dissipation substrate by placing a single layer of high thermal conductivity material on the bottom side of the chip's functional layer. Commonly used high thermal conductivity materials include silicon carbide, aluminum nitride, and diamond. Relying on the intrinsic high thermal conductivity of the material, the heat dissipation efficiency at the bottom of the device is improved. This type of single-layer heat dissipation substrate is suitable for conventional single-layer planar chip heat dissipation scenarios. However, in the case of multi-layer stacked three-dimensional heterogeneous integrated chips, due to the limitations of the stacking structure and the mismatch of heterogeneous material properties, traditional single-sided single-layer heat dissipation substrates expose many structural defects, making it difficult to achieve both efficient heat dissipation and structural mechanical stability.

[0004] Specifically, existing technologies have four major technical drawbacks: First, the heat dissipation path is singular and internal heat accumulation is severe. Traditional heat dissipation structures only place a high thermal conductivity heat dissipation layer at the bottom of all functional layers. The core heat-generating areas such as the active layer and interconnect dielectric layer of the chip are located on the upper layer of the stacked structure. The internal heat must penetrate vertically through multiple layers of dielectric and metal interconnect structure to be conducted to the bottom heat dissipation layer. The heat conduction path is long and the heat loss is large. During operation, heat is easily generated inside the chip, causing the operating temperature rise to exceed the standard and the device performance to degrade.

[0005] Secondly, the mismatch of physical properties at the heterogeneous interface induces asymmetric thermal stress. The high thermal conductivity heat dissipation material and the semiconductor functional layer material have significant differences in physical properties such as thermal expansion coefficient, elastic modulus, and crystal structure. When heterogeneous bonding is achieved by relying on a single bottom interface, the thermal deformation and mechanical deformation of the materials cannot be coupled, which easily leads to the formation of an asymmetric thermal stress field at the bonding interface. Long-term operation can easily cause interface stress distortion.

[0006] Third, structural constraints are unbalanced, making the substrate prone to failure and delamination. The bottom high thermal conductivity heat dissipation layer is only bonded to the semiconductor functional layer on its upper surface, and there is no matching constraint structure on the lower surface. Under the conditions of device annealing and cooling, wafer packaging, and long-term high and low temperature thermal cycling, the deformation stress caused by alternating hot and cold temperatures cannot be released, which in turn induces reliability failure problems such as overall substrate warping, heterogeneous interface cracking, and wafer bond delamination, significantly reducing the yield and service life of 3D stacked chips.

[0007] Fourth, stress buffering and thermal conductivity are mutually constrained. Existing improvement solutions mostly optimize the interface mechanical properties by thickening the continuous transition intermediate layer to alleviate thermal stress deformation; however, the transition medium generally has low thermal conductivity, and thickening the intermediate layer will directly increase the overall thermal resistance of the multi-layer stack interface, block the longitudinal heat conduction channel, and sacrifice the chip's heat dissipation capacity, resulting in a technical contradiction where stress buffering, structural stability, and high thermal conductivity cannot be achieved in a coordinated manner.

[0008] In summary, current heat dissipation substrates for three-dimensional heterogeneous integrated power chips generally suffer from technical challenges such as single heat dissipation path, concentrated interfacial thermal stress, high risk of wafer warping and cracking, and contradiction between heat dissipation performance and mechanical stability. There is an urgent need to develop a composite substrate structure that takes into account efficient heat conduction through multiple paths, multi-layer interfacial stress regulation, and packaging thermal cycling stability.

[0009] In view of this, the present invention is proposed. Summary of the Invention

[0010] The purpose of this invention is to provide a trench stress-buffered multilayer high thermal conductivity composite substrate and its preparation method, which overcomes the shortcomings of existing three-dimensional heterogeneous integrated chip heat dissipation substrates, such as single heat dissipation path, large heat accumulation inside the stack, thermal stress imbalance at the heterogeneous interface, high risk of wafer warping and cracking, and mutual restriction between stress buffer structure and high thermal conductivity.

[0011] In a first aspect, the present invention provides a trench stress-buffered multilayer high thermal conductivity composite substrate, comprising a plurality of functional layers and a plurality of heat dissipation layers alternately stacked from top to bottom, with an intermediate layer disposed between adjacent layers; the heat dissipation layers are provided with a plurality of trenches, the trenches being filled with a dielectric material to form distributed stress regulation units, used to divide stress transmission paths, alleviate interface thermal stress concentration and suppress crack propagation.

[0012] Preferably, the heat dissipation layer has two, three, or more layers.

[0013] Preferably, when the heat dissipation layer consists of two layers, from top to bottom, they are a first functional layer, a first intermediate layer, a first heat dissipation layer, a second intermediate layer, a second functional layer, a third intermediate layer, and a second heat dissipation layer; both the first heat dissipation layer and the second heat dissipation layer are provided with a plurality of through grooves.

[0014] Preferably, the trench width is 1nm to 1000nm, the trench depth is 10nm to 10μm, and the spacing between adjacent trenches is 0.1μm to 100μm.

[0015] Preferably, the dielectric material filling the trench is a single-layer material or a multi-layer composite material, selected from at least one or more combinations of silicon dioxide, alumina, silicon nitride, silicon nitride, aluminum nitride, boron nitride, hafnium dioxide, zirconium dioxide, silicon oxynitride, polyimide, benzocyclobutene, and other low dielectric constant dielectric materials; it can also be a metallic material, serving as a through-hole or auxiliary functional layer for heat dissipation, while also enabling power supply interconnection.

[0016] Preferably, the shape of the groove can be a regular shape such as a rectangle or a circle, or it can be an irregular shape.

[0017] Preferably, the functional layer is selected from at least one or more combinations of AI chip functional layer, logic circuit layer, storage circuit layer, power supply circuit layer, radio frequency device layer, sensor layer, power device layer, and optoelectronic device layer, and is compatible with diverse chip functions such as logic, storage, radio frequency, optoelectronic, sensing, and power supply.

[0018] Preferably, the material of the functional layer is selected from at least one or more combinations of silicon, germanium, silicon-germanium, carbon nanotubes, graphene, indium phosphide, gallium arsenide, gallium oxide, gallium nitride, aluminum gallium nitride, indium gallium nitride, silicon carbide, diamond, and other two-dimensional semiconductor materials and organic semiconductor materials.

[0019] Preferably, the material of the heat dissipation layer is selected from at least one or more combinations of silicon carbide, aluminum nitride, diamond, diamond-like carbon, boron nitride, alumina, high thermal conductivity ceramics, high thermal conductivity carbon-based composite materials, and high thermal conductivity metal-based composite materials.

[0020] Preferably, the intermediate layer material is a single-layer material or a multi-layer composite material, selected from at least one or more combinations of silicon dioxide, alumina, silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, hafnium oxide, zirconium oxide, polyimide, benzocyclobutene, and other low dielectric constant media.

[0021] In a second aspect, the present invention provides a three-dimensional heterogeneous integrated semiconductor device, which uses the trench stress-buffered multilayer high thermal conductivity composite substrate as a heat dissipation substrate.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects: (1) The present invention adopts an alternating stacked structure of functional layers and heat dissipation layers, which can flexibly arrange two, three or more heat dissipation layers, breaking through the traditional single bottom heat dissipation limitation; relying on high thermal conductivity materials such as silicon carbide, diamond, and aluminum nitride to build longitudinal and transverse composite heat conduction channels, heat can be quickly discharged through multiple dimensions between layers and at the bottom, which greatly shortens the heat conduction link of high heat flux density functional layers. At the same time, the intermediate layer adopts low dielectric and low thermal resistance dielectric material, which takes into account the interlayer insulation capability and avoids additional heat transfer loss, effectively solving the problem of device performance degradation caused by excessive temperature rise and heat accumulation under the stacking conditions of AI chips and power chips.

[0023] (2) In this invention, several trenches are etched through the heat dissipation layer and filled with a variety of dielectric materials to form distributed stress control units. Compared with a continuous stress buffer layer, the discrete trench structure can actively divide the longitudinal stress transmission path, disperse the concentrated thermal stress at the interface, and eliminate the asymmetric stress field caused by multi-layer heterogeneous stacking. Combined with COMSOL stress simulation verification, the average thermal stress of the bonding intermediate layer is significantly reduced after adding the trench structure, which can prevent cracks from extending laterally along the interface, avoid wafer warping, interlayer cracking, and debonding failures during annealing, packaging, and thermal cycling, and improve the packaging yield of three-dimensional stacked chips.

[0024] (3) Existing technologies rely on thickening a continuous intermediate layer to relieve stress, which inevitably leads to a surge in interfacial thermal resistance. This invention relies on embedded grooves in the heat dissipation layer to achieve stress regulation, without the need to thicken a low thermal conductivity transition medium. The stress buffer structure is integrated inside the high thermal conductivity heat dissipation layer, without adding extra interlayer thermal resistance. At the same time, the grooves can be matched with single-layer or multi-layer composite filling media. Insulating media can be used to optimize the interfacial bonding strength, or composite metal materials can be used to lay thermally conductive through holes, simultaneously strengthening the lateral heat dissipation capacity, and completely solving the industry technical pain point of mutual constraint between stress buffering and efficient heat dissipation.

[0025] (4) The composite substrate of the present invention can be flexibly expanded, and the basic structure of the double heat dissipation layer can be stacked into a multi-layer stacked structure as needed, with strong structural scalability; the overall architecture of the substrate is standardized and easy to integrate, and can be directly used as a general heat dissipation substrate to prepare three-dimensional heterogeneous integrated semiconductor devices, which are suitable for high-performance computing chips, automotive power electronics, radio frequency microwave devices, optoelectronic integrated chips and other fields, taking into account the preparation cost, device reliability and industrialization. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the trench stress buffer type multilayer high thermal conductivity composite substrate structure provided by the present invention.

[0028] Figure 2 The images show a comparison of the buffering effect of the substrates in Embodiment 2 and Comparative Example 2 of the present invention on interfacial stress; the left image is Comparative Example 2, and the right image is Embodiment 2.

[0029] Explanation of reference numerals in the attached drawings: 1. First functional layer; 2. First intermediate layer; 3. First heat dissipation layer; 4. Second intermediate layer; 5. Second functional layer; 6. Third intermediate layer; 7. Second heat dissipation layer; 8. Trench. Detailed Implementation

[0030] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1 This embodiment provides a trench stress buffer type multilayer high thermal conductivity composite substrate, including a number of functional layers and a number of heat dissipation layers stacked alternately from top to bottom, with an intermediate layer between adjacent layers; the heat dissipation layer is provided with a number of trenches, and the inside of the trenches is filled with a dielectric material to form distributed stress regulation units, which are used to divide the stress transmission path, alleviate the concentration of thermal stress at the interface and inhibit crack propagation.

[0034] like Figure 1 As shown, in this embodiment, the heat dissipation layer consists of two layers, which are arranged from top to bottom as a first functional layer 1, a first intermediate layer 2, a first heat dissipation layer 3, a second intermediate layer 4, a second functional layer 5, a third intermediate layer 6, and a second heat dissipation layer 7; both the first heat dissipation layer 3 and the second heat dissipation layer 7 are provided with a plurality of grooves 8.

[0035] In this embodiment, the width of the trench 8 is 200nm, the depth of the trench 8 is 2μm, and the spacing between adjacent trenches 8 is 3.5μm.

[0036] In this embodiment, the thickness of the first functional layer 1 and the second functional layer 5 is 500nm; the thickness of the first intermediate layer 2, the second intermediate layer 4, and the third intermediate layer 6 is 15nm; and the thickness of the first heat dissipation layer 3 and the second heat dissipation layer 7 is 350μm.

[0037] In this embodiment, the medium material filled in the trench is silicon dioxide.

[0038] In this embodiment, the materials of the first intermediate layer 2, the second intermediate layer 4, and the third intermediate layer 6 are silicon dioxide.

[0039] In this embodiment, the materials of the first heat dissipation layer 3 and the second heat dissipation layer 7 are silicon carbide.

[0040] In this embodiment, the first functional layer 1 and the second functional layer 5 are simulated heat generation for the AI ​​chip functional layers.

[0041] In this embodiment, the materials of the first functional layer 1 and the second functional layer 5 are silicon.

[0042] Example 2 This embodiment provides a trench stress-buffered multilayer high thermal conductivity composite substrate, which differs from the embodiment in that the intermediate layer material and the dielectric material filled in the trench are both alumina, while the rest is consistent with embodiment 1.

[0043] Comparative Example 1 This comparative example provides a composite substrate, which consists of a first functional layer 1, a first intermediate layer 2, and a first heat dissipation layer 3 from top to bottom. The heat dissipation layer does not have trenches, and the material, thickness, and other parameters of each layer are consistent with those of Example 1.

[0044] Comparative Example 2 This comparative example provides a composite substrate, which differs from Comparative Example 1 in that the intermediate layer material is aluminum oxide, while the other parameters remain the same as those of Comparative Example 1.

[0045] Test case The interface stress was verified using COMSOL multiphysics simulation software. Composite substrate models corresponding to the examples and comparative examples were built, and the material properties were uniformly calibrated to extract the average stress data of the bonding intermediate layer.

[0046] like Figure 2As shown, when alumina is used as the bonding intermediate layer, the difference in interface stress is compared between the trench structure of the multilayer high thermal conductivity composite substrate (Example 2) and the ordinary trenchless structure (Comparative Example 2). It was observed that at the same scale, the maximum and minimum values ​​of the stress in the functional layer structure between the two high thermal conductivity layers are better than the stress in the functional layer in the ordinary structure. The results show that the trench structure can alleviate the concentrated stress at the interface, reduce the overall average stress of the intermediate layer, and achieve mechanical protection of the functional layer.

[0047] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A trench stress-buffered multilayer high thermal conductivity composite substrate, characterized in that, It includes several functional layers and several heat dissipation layers stacked alternately from top to bottom, with an intermediate layer between adjacent layers; the heat dissipation layer has several through grooves, and the inside of the grooves is filled with a medium material to form distributed stress regulation units, which are used to divide the stress transmission path, alleviate the concentration of thermal stress at the interface and inhibit crack propagation.

2. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The heat dissipation layer may have two, three, or more layers.

3. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, When the heat dissipation layer consists of two layers, from top to bottom, they are a first functional layer, a first intermediate layer, a first heat dissipation layer, a second intermediate layer, a second functional layer, a third intermediate layer, and a second heat dissipation layer; both the first heat dissipation layer and the second heat dissipation layer are provided with a number of through grooves.

4. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The trench width is 1nm to 1000nm, the trench depth is 10nm to 10μm, and the spacing between adjacent trenches is 0.1μm to 100μm.

5. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The dielectric material filling the trench is a single-layer material or a multi-layer composite material, selected from at least one or more combinations of silicon dioxide, alumina, silicon nitride, silicon nitride, aluminum nitride, boron nitride, hafnium dioxide, zirconium dioxide, silicon oxynitride, polyimide, benzocyclobutene, metallic materials, and other low dielectric constant dielectric materials.

6. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The functional layer is selected from at least one or more combinations of AI chip functional layer, logic circuit layer, storage circuit layer, power supply circuit layer, radio frequency device layer, sensor layer, power device layer, and optoelectronic device layer.

7. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The material of the functional layer is selected from at least one or more combinations of silicon, germanium, silicon-germanium, carbon nanotubes, graphene, indium phosphide, gallium arsenide, gallium oxide, gallium nitride, aluminum gallium nitride, indium gallium nitride, silicon carbide, diamond, and other two-dimensional semiconductor materials and organic semiconductor materials.

8. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The material of the heat dissipation layer is selected from at least one or more combinations of silicon carbide, aluminum nitride, diamond, diamond-like carbon, boron nitride, aluminum oxide, high thermal conductivity ceramics, high thermal conductivity carbon-based composite materials, and high thermal conductivity metal-based composite materials.

9. The trench stress-buffered multilayer high thermal conductivity composite substrate according to claim 1, characterized in that, The intermediate layer material is a single-layer material or a multi-layer composite material, selected from at least one or more combinations of silicon dioxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, hafnium oxide, zirconium oxide, polyimide, benzocyclobutene, and other low dielectric constant media.

10. A three-dimensional heterogeneous integrated semiconductor device, characterized in that, The trench stress buffer type multilayer high thermal conductivity composite substrate described in any one of claims 1-9 is used as the heat dissipation substrate.

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