A method for preventing open circuit of ceramic substrate via holes

Abstract

The application provides a method for preventing open circuit of a ceramic substrate via, which comprises the following steps: 10, full-area scanning detection is performed on the ceramic substrate to establish a corresponding model of resistance abnormal fluctuation threshold-gas aggregation degree-via position, and the position, quantity, distribution rule and gas aggregation level of the via with gas aggregation phenomenon are obtained; 20, photoresist is applied to the ceramic substrate to form a photoresist layer on the surface of the ceramic substrate; and 30, according to the corresponding model established in step 10 and the size of the via, a special mask plate is designed to expose and develop the ceramic substrate. According to the detection result of the via with gas aggregation phenomenon on the ceramic substrate, the mask plate with the hollow area for forming the exhaust port at the via in the later stage is designed, a release path is provided for the gas expansion after the ceramic substrate is heated, the yield caused by the open circuit of the via is greatly reduced, and the product application demand is met to a greater extent.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for preventing open circuits in through-holes of ceramic substrates. Background Technology

[0002] In existing ceramic substrate manufacturing processes, the design and layout of vias and surface patterns focus solely on electrical conductivity and structural integrity, completely ignoring the fact that during the ceramic substrate heating process, the instantaneous pressure generated by the thermal expansion of residual gases inside the substrate and within the vias (including air adsorbed during manufacturing and trace amounts of gases released from the ceramic material itself) is the core cause of via open circuits. Figure 1 As shown, no corresponding gas release path or precise control process has been designed to address this cause.

[0003] In existing technologies, vias are generally designed with a fully enclosed or semi-enclosed layout. Conventional, crude adjustments such as increasing the via diameter, adjusting the adhesive thickness, and increasing the heating rate are used to attempt to alleviate the via-open phenomenon. However, these adjustments cannot fundamentally solve the problem of pressure accumulation caused by gas expansion. Increasing the via diameter leads to a decrease in the electrical performance of the substrate (such as signal interference and reduced insulation). Adjusting the adhesive thickness can easily result in uneven coating, which may block potential gas release channels. Ultimately, it is still impossible to prevent gas expansion from compressing the via walls and circuit connections, leading to via wall damage, circuit stripping, and the via-open phenomenon, causing the product's electrical performance to fail.

[0004] Statistics show that ceramic substrates manufactured using traditional processes experience a 5%-8% defect rate due to the Viaopen phenomenon after undergoing a bonding heating process at 300-400℃. In existing technologies, those skilled in the art generally fall into the mindset of "focusing solely on optimizing the V-via structure itself," failing to recognize the synergistic effect of "gas detection - venting structure - process control," and neglecting to fully consider the release path of gas expansion after heating the ceramic substrate (such as in the bonding process, where the heating temperature is typically between 300-400℃). When gas cannot be effectively released, it compresses the via walls and connecting lines, causing an open circuit between the via and the lines (i.e., the Viaopen phenomenon), ultimately leading to product electrical performance failure. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for preventing open vias in ceramic substrates. Based on the detection results of through holes with gas accumulation on the ceramic substrate, a mask plate with an exhaust port is designed to provide a release path for the gas expansion after the ceramic substrate is heated, which greatly reduces the defect rate caused by open vias and better meets the product application requirements.

[0006] To solve the above-mentioned technical problems, the technical solution adopted in the embodiments of the present invention is as follows: A method for preventing open vias in a ceramic substrate, the method comprising: Step 10: Perform full-area scanning detection on the ceramic substrate, establish a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and via location, and obtain the location, number, distribution pattern, and gas accumulation level of vias with gas accumulation phenomenon. Step 20: Apply photoresist to the ceramic substrate to form a photoresist layer on the surface of the ceramic substrate; Step 30: Based on the corresponding model and through-hole dimensions established in Step 10, design a special mask to expose and develop the ceramic substrate.

[0007] As a preferred example, step 10 specifically includes: Step 101: Perform full-area scanning detection on the ceramic substrate using a flying probe tester, and record the resistance value, open circuit location coordinates, and abnormal resistance fluctuation data at each via location. Step 102: Observe the microscopic condition of the inner wall of the through hole and the connection parts of the circuit; Step 103: Establish a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and orifice location to obtain the location, number, distribution pattern, and gas accumulation level of orifices exhibiting gas accumulation.

[0008] As a preferred example, step 20 specifically includes: Step 201: Pre-clean the ceramic substrate; Step 202: Based on the corresponding model established in step 10, set the corresponding photoresist spraying amount according to the gas accumulation level of the via, so that the photoresist layer thickness at the via position is different for different gas accumulation levels.

[0009] As a preferred example, step 30 specifically includes: Based on the corresponding model established in step 10, a special mask is designed; the hollow area of ​​the corresponding through hole on the special mask coincides with the through hole part, and the area of ​​the through hole edge covered by the special mask is the vent area. The vent area is part of the through hole and avoids the connection part with the surface line.

[0010] As a preferred example, the method further includes: Step 40: Verify the effectiveness of venting on the exposed and developed ceramic substrate.

[0011] As a preferred example, step 40 specifically includes: Step 401: Place the exposed and developed ceramic substrate into a simulated bonding heating environment for heating; Step 402: Cool the heated ceramic substrate and then perform a full-area scanning inspection. Step 403: If an open via is found, remove the photoresist layer and proceed to step 20 based on the test results.

[0012] As a preferred example, in step 30, the number of exhaust port areas is designed based on the gas accumulation level of the through hole obtained in step 10, and the number of exhaust port areas is 1-4.

[0013] As a preferred example, in step 202, the photoresist spraying amount is 3-5 μL / s. The photoresist spraying amount increases with the increase of the gas accumulation level, so that the thickness of the photoresist layer on the via increases with the increase of the gas accumulation level.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The technical solution of the present invention firstly establishes a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and via location to achieve precise positioning of gas accumulation area and quantitative classification of gas accumulation amount; then, based on the gas accumulation level, the photoresist spraying amount is designed so that the photoresist layer thickness on the via area with high gas accumulation level is thick. Because the metal layer on the via with high gas accumulation level is thick and heavy, it is not easy to be pushed open by gas expansion and thus open circuit; subsequently, based on the gas accumulation level, a special mask plate is designed for forming an exhaust port corresponding to the gas accumulation level at the via, achieving precise matching between the exhaust port and the gas accumulation amount, while ensuring that the exhaust port avoids the connection part between the via and the circuit, taking into account both exhaust function and electrical performance, greatly reducing the defect rate caused by via open circuit, and better meeting the product application requirements. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the phenomenon where gas causes open circuits in vias during the heating of a traditional ceramic substrate. Figure 2 This is a flowchart of a method for preventing open vias in ceramic substrates provided in an embodiment of the present invention; Figure 3 This is a perspective view of the ceramic substrate after the special mask plate is covered in step 30 of the method of this embodiment of the invention; The diagram shows: 1. Ceramic substrate; 2. Through hole; 3. Circuit; 5. Special mask plate; 51. Hollow area; 6. Vent area; 7. Metal layer. Detailed Implementation

[0016] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] like Figure 2 A method for preventing open vias in a ceramic substrate is shown, the method comprising: Step 10: Perform full-area scanning detection on ceramic substrate 1, establish a corresponding model of resistance abnormal fluctuation threshold - gas accumulation degree - via location, and obtain the location, number, distribution pattern and gas accumulation level of via 2 where gas accumulation occurs. Step 20: Photoresist is applied to the ceramic substrate 1 to form a photoresist layer on the surface of the ceramic substrate 1. Step 30: Based on the corresponding model established in step 10 and the size of the through hole 2, design a special mask plate 5 to expose and develop the ceramic substrate 1.

[0018] In the aforementioned method for preventing open vias in ceramic substrates, a fully integrated process of precise detection and positioning, customized coating, and targeted development and exposure is employed. The hollowed-out area 51 of a dedicated mask 5 is designed based on the degree of gas accumulation. Figure 3 As shown, the cutout area 51 of the special mask plate 5 overlaps with the through hole 2. The area of ​​the through hole 2 covered by the special mask plate 5 is the exhaust port area 6. After the metal layer is coated and the photoresist is cleaned, the exhaust port area 6 forms an exhaust port that matches the amount of gas accumulation, so as to realize the orderly and rapid release of gas and avoid the open circuit phenomenon of the through hole 2 from the root.

[0019] As a preferred example, step 10 specifically includes: Step 101: Perform full-area scanning detection on the ceramic substrate 1 using a flying probe testing device, and record the resistance value, open circuit location coordinates, and abnormal resistance fluctuation data at each via 2 location. Step 102: Observe the microscopic state of the inner wall of the through hole 2 and the connection part of the line 3; Step 103: Establish a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and through-hole location to obtain the location, number, distribution pattern, and gas accumulation level of through-hole 2 where gas accumulation occurs.

[0020] As a preferred example, step 20 specifically includes: Step 201: Pre-clean the ceramic substrate 1; Step 202: Based on the corresponding model established in step 10, set the corresponding photoresist spraying amount according to the gas accumulation level of via 2, so that the photoresist layer thickness at the via 2 position is different for different gas accumulation levels.

[0021] As a preferred example, step 30 specifically includes: Based on the corresponding model established in step 10, design a dedicated mask plate 5; such as Figure 3 As shown, the hollow area 51 on the special mask plate 5 corresponding to the through hole 2 partially overlaps with the through hole 2. The area covered by the special mask plate 5 at the edge of the through hole 2 is the exhaust port area 6. The exhaust port area 6 is part of the through hole 2 and avoids the connection part with the line 3.

[0022] As a preferred example, the method further includes: Step 40: Verify the effectiveness of venting on the exposed and developed ceramic substrate 1.

[0023] As a preferred example, step 40 specifically includes: Step 401: The exposed and developed ceramic substrate 1 is placed in a simulated bonding heating environment for heating; Step 402: Cool the heated ceramic substrate 1 and then perform a full-area scanning inspection; Step 403: If the via 2 is open, remove the photoresist layer and proceed to step 20 based on the test results.

[0024] As a preferred example, in step 30, the number of exhaust port regions 6 is designed based on the gas accumulation level of the through-hole 2 obtained in step 10, such as... Figure 3 As shown, the number of exhaust port areas 6 is 1-4.

[0025] Based on the gas accumulation level, a hollow area 51 is set to form an exhaust port area 6 with a corresponding width to the through hole 2, thus establishing a system that precisely matches the exhaust port with the gas accumulation. The higher the gas accumulation, the larger the exhaust port area 6 formed by the special mask plate 5 and the through hole 2, that is, the larger the exhaust port formed subsequently, thereby ensuring smoother gas discharge.

[0026] As a preferred example, in step 202, the photoresist spraying amount is 3-5 μL / s. The photoresist spraying amount increases with the increase of the gas accumulation level, so that the thickness of the photoresist layer on the via 2 increases with the increase of the gas accumulation level.

[0027] The thickness of the photoresist layer is set according to the gas accumulation level, which makes the thickness of the photoresist layer more compatible with the gas accumulation level. The higher the gas accumulation level, the thicker the photoresist layer in the corresponding area, and the thicker the metal layer formed later. It is less likely to be pushed up by the gas and cause the via 2 to be open.

[0028] The specific steps of the preferred embodiment method of the present invention are as follows: The first step is to perform detection and positioning analysis on the ceramic substrate 1.

[0029] First, a flying probe tester was used to perform a precise full-area scan of the ceramic substrate 1. The flying probe tester was a microcraft-E4 model, with a probe positioning error of ≤0.002mm in the X / Y directions and a resistance testing accuracy of ±0.01Ω. The flying probe tester completed the full-area test of the ceramic substrate 1 at a rate of 50 test points / second, simultaneously recording the resistance value, open circuit location coordinates, and abnormal resistance fluctuation data at each via 2.

[0030] Subsequently, combined with 50x optical microscopy, the microscopic state of the inner wall of the through hole 2 and the connection part of the line 3 was observed by scanning electron microscopy. The "through hole open circuit caused by gas expansion" and "the circuit break caused by other reasons such as hole wall damage, line 3 breakage, and impurity blockage" were accurately distinguished. A corresponding model of "resistance abnormal fluctuation threshold - gas accumulation degree - through hole location" was established to clarify the location, number, distribution pattern and gas accumulation level of the through hole 2.

[0031] The second step is to apply customized photoresist to the ceramic substrate 1.

[0032] First, before applying the coating, pre-clean the coating path with nitrogen 3-5 times, each cleaning time being 10-15 seconds, to remove residual impurities and moisture in the coating path and prevent impurities from clogging the vents reserved for later use.

[0033] Subsequently, a high-precision photoresist coater was used for photoresist application. During coating, the photoresist spray flow rate was precisely set according to the gas accumulation level determined in the first step. The photoresist spray flow rate was 3-5 μL / s, with a higher photoresist spray volume corresponding to the area containing via 2 where the gas accumulation was higher. During coating, the chuck rotation speed was 300-500 r / min, the coating time was 10-15 s, the radial movement accuracy of the chuck rotation was ≤0.003 mm, and the photoresist spraying system's dispensing error was ≤±1 μL, to avoid vent blockage or dimensional deviations due to uneven coating.

[0034] The photoresist coating thickness is 2-3μm, which not only ensures the stability of the photoresist coverage and its insulating properties, but also provides a precise thickness basis for reserving vents after subsequent development, achieving the linkage and adaptation of "coating parameters and gas accumulation".

[0035] High-temperature resistant photoresist is used, which can withstand bonding heating temperatures of 300-400℃ and has good insulation and corrosion resistance. This prevents the photoresist from softening and flowing during heating, thus avoiding clogging the exhaust port, and also ensures the electrical performance of the substrate.

[0036] The third step is to expose and develop the coated ceramic substrate 1.

[0037] Based on the corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and through-hole position obtained in the first step, and the size of through-hole 2, a dedicated mask plate 5 is designed. The size of through-hole 2 is designed and fabricated according to the dimensions of different products. The dedicated mask plate 5 has a hollow area 51 adapted to the gas accumulation level, so that the width of the exhaust port area 6 corresponding to the through-hole 2 is adapted to the gas accumulation level (for example, the width of the exhaust port area 6 formed in the area with high gas accumulation is 7-8μm; the width of the exhaust port area 6 formed in the area with medium gas accumulation is 5-6μm; and the width of the exhaust port area 6 formed in the area with low gas accumulation is 5μm). The exhaust port area 6 is set at the edge of the through-hole 2, with 1-4 in number, and avoids the connection between the through-hole 2 and the line 3, ensuring that the gas can be discharged in an orderly and rapid manner through the graded exhaust ports during heating, without affecting the electrical connection and structural stability between the through-hole 2 and the line 3.

[0038] The fourth step is to verify the effectiveness of venting on the exposed and developed ceramic substrate 1. The ceramic substrate 1 is placed in a simulated bonding heating environment (e.g., temperature 300-400℃, held for 30-60 minutes), and after cooling, it is again inspected using a flying probe tester and scanning electron microscope to verify the conductivity of the via 2 and the effectiveness of the venting port. If an open circuit is detected in the via 2 or a blockage is detected in the venting port, the coating parameters in the second step and the notch size and exposure parameters in the third step are adjusted according to the test results until there is no open circuit in the via 2, ensuring the stability and reliability of the process.

[0039] like Figure 1 As shown, in the prior art, the metal layer 7 completely covers the through hole 2, which prevents the through hole 2 from smoothly venting the gas. When the gas accumulation reaches a certain level, the gas will push the metal layer 7 open and release the internal gas. At this time, although the gas can be released smoothly, the metal layer 7 on the surface of the ceramic substrate 1 is disconnected from the line 3, which can easily cause a short circuit in the ceramic substrate 1, thereby reducing the electrical performance. In the prior art, it is impossible to simultaneously and efficiently balance the exhaust function and electrical performance.

[0040] The method of this invention first establishes a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and through-hole location to achieve precise positioning of gas accumulation area and quantitative classification of gas accumulation amount. Then, based on the level of gas accumulation amount, a special mask plate 5 is designed for forming an exhaust port at the through-hole corresponding to the gas accumulation level, so as to achieve precise matching between the exhaust port and the gas accumulation amount. At the same time, the exhaust port avoids the connection between through-hole 2 and line 3, taking into account both exhaust function and electrical performance, greatly reducing the failure rate caused by open circuit of through-hole 2, and better meeting the product application requirements.

[0041] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the specific embodiments described above. The specific embodiments and descriptions in the specification are merely for further illustrating the principles of the invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A method for preventing open circuits in through-holes of a ceramic substrate, characterized in that, The method includes: Step 10: Perform full-area scanning detection on the ceramic substrate, establish a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and via location, and obtain the location, number, distribution pattern, and gas accumulation level of vias with gas accumulation phenomenon. Step 20: Apply photoresist to the ceramic substrate to form a photoresist layer on the surface of the ceramic substrate; Step 30: Based on the corresponding model and through-hole dimensions established in Step 10, design a special mask to expose and develop the ceramic substrate.

2. The method according to claim 1, characterized in that, Step 10 specifically includes: Step 101: Perform full-area scanning detection on the ceramic substrate using a flying probe tester, and record the resistance value, open circuit location coordinates, and abnormal resistance fluctuation data at each via location. Step 102: Observe the microscopic condition of the inner wall of the through hole and the connection parts of the circuit; Step 103: Establish a corresponding model of resistance abnormal fluctuation threshold, gas accumulation degree, and orifice location to obtain the location, number, distribution pattern, and gas accumulation level of orifices exhibiting gas accumulation.

3. The method according to claim 1, characterized in that, Step 20 specifically includes: Step 201: Pre-clean the ceramic substrate; Step 202: Based on the corresponding model established in step 10, set the corresponding photoresist spraying amount according to the gas accumulation level of the via, so that the photoresist layer thickness at the via position is different for different gas accumulation levels.

4. The method according to claim 1, characterized in that, Step 30 specifically includes: Based on the corresponding model established in step 10, a special mask is designed; the hollow area of ​​the corresponding through hole on the special mask coincides with the through hole part, and the area of ​​the through hole edge covered by the special mask is the vent area. The vent area is part of the through hole and avoids the connection part with the surface line.

5. The method according to claim 1, characterized in that, The method further includes: Step 40: Verify the effectiveness of venting on the exposed and developed ceramic substrate.

6. The method according to claim 5, characterized in that, Step 40 specifically includes: Step 401: Place the exposed and developed ceramic substrate into a simulated bonding heating environment for heating; Step 402: Cool the heated ceramic substrate and then perform a full-area scanning inspection. Step 403: If an open via is found, remove the photoresist layer and proceed to step 20 based on the test results.

7. The method according to claim 4, characterized in that, In step 30, the number of exhaust port areas is designed based on the gas accumulation level of the through hole obtained in step 10, and the number of exhaust port areas is 1-4.

8. The method according to claim 3, characterized in that, In step 202, the photoresist spraying amount is 3-5 μL / s. The photoresist spraying amount increases with the increase of the gas accumulation level, so that the thickness of the photoresist layer on the via increases with the increase of the gas accumulation level.

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