Power element package

Abstract

The application discloses a power element package, which comprises a frame base island, a power element fixedly arranged on the frame base island, a mold plastic covering the frame base island and the power element, a drain electrode pin extending outward from one side of the frame base island and protruding from the mold plastic, a gate electrode pin located on one side of the drain electrode pin and extending and protruding from the mold plastic, a source electrode pin located on the other side of the drain electrode pin relative to the gate electrode pin and extending and protruding from the mold plastic, and a transfer element installed on the frame base island.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device packaging technology, and in particular to an improved GaN power device package. Background Technology

[0002] As is known to those skilled in the art, silicon MOS power devices are generally vertical devices, with their source and gate electrodes located on the front of the chip, and the drain electrode located on the back. In a TO 220 package, for example, the silicon MOS power device is fixed to a frame island connected to the drain pin with silver paste, and then the gate and source electrodes on the front of the chip are electrically connected to their respective gate and source pins using leads. Taking the TO 220 package as an example, the pin definitions from left to right represent the GDS configuration of the gate (G), drain (D), and source (S).

[0003] Gallium nitride (GaN) power devices are generally horizontal devices, meaning their drain, source, and gate are all located on the front side of the chip. If GaN power devices require encapsulated gate driver ICs, there is a problem with die-bonded ICs on the frame substrate islands, where high-voltage operation can damage the devices. Summary of the Invention

[0004] In view of this, the main objective of the present invention is to provide an improved GaN power device package that utilizes a modular packaging approach, enabling the GaN power device to be packaged together with a gate driver IC device or a low-voltage MOS (LV MOS) device, thereby effectively avoiding the problem of device damage caused by high-voltage operation.

[0005] The present invention provides a power device package comprising: a frame base island; a power device fixedly disposed on the frame base island; a molding compound covering the frame base island and the power device; a drain pin extending outward from one side of the frame base island and protruding from the molding compound; a gate pin located on one side of the drain pin and extending and protruding from the molding compound; a source pin located on the other side of the drain pin relative to the gate pin and extending and protruding from the molding compound; and a transfer element mounted on the frame base island, the transfer element being electrically connected to the power device, the frame base island, the gate pin, the source pin, or the drain pin via multiple leads.

[0006] According to an embodiment of the present invention, the transfer element comprises: a substrate; and an adhesive layer located between the substrate and the frame base island. According to an embodiment of the present invention, the substrate comprises a ceramic substrate, an aluminum substrate, or an FR5 fiberglass substrate. According to an embodiment of the present invention, the adhesive layer comprises silver paste.

[0007] According to an embodiment of the present invention, the transfer element includes: an insulating layer located on the substrate; a patterned copper circuit layer located on the insulating layer; and a protective layer covering the insulating layer and the patterned copper circuit layer.

[0008] According to an embodiment of the present invention, the thickness of the transfer element is between 0.1 mm and 1.0 mm.

[0009] According to an embodiment of the present invention, the power device is a GaN power device. According to an embodiment of the present invention, the GaN power device comprises a D-Mode GaN HEMT die.

[0010] According to an embodiment of the present invention, the power device package further includes: a low-voltage silicon-based MOS die disposed on the transfer element; and a resistor element disposed on the transfer element. According to an embodiment of the present invention, the resistor element is fixed to the transfer element using surface mount technology.

[0011] According to an embodiment of the present invention, the patterned copper circuit layer includes a separate first circuit and a second circuit, and the resistive element is connected across the first circuit and the second circuit. According to an embodiment of the present invention, the low-voltage silicon-based MOS die is die-bonded on the first circuit.

[0012] According to an embodiment of the present invention, the power element package further includes: a gate driving element disposed on the transfer element.

[0013] According to an embodiment of the present invention, the GaN power device comprises an E-Mode GaN HEMT die.

[0014] According to an embodiment of the present invention, the frame base island is connected to a heat sink.

[0015] According to an embodiment of the present invention, the frame base island, the heat sink, and the drain pin are integrally formed of copper metal. Attached Figure Description

[0016] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0017] Figure 1 This is a partial perspective view of a GaN power device package illustrated in an embodiment of the present invention;

[0018] Figure 2 For along Figure 1 A schematic cross-sectional view shown by tangent I-I' in the diagram;

[0019] Figure 3 for Figure 1 A cascaded circuit diagram of GaN power device packages in [the context of the image].

[0020] Figure 4 This is a partial perspective view of a GaN power device package illustrated in another embodiment of the present invention;

[0021] Figure 5 for Figure 4 Circuit diagram of GaN power device package;

[0022] Figure 6 This is a partial perspective view of a GaN power device package illustrated in yet another embodiment of the present invention;

[0023] Figure 7 for Figure 6 A schematic cross-sectional view shown by the tangent line II-II'.

[0024] Symbol explanation:

[0025] 1, 2, 3 GaN power device packages

[0026] 10 Frame Base Island

[0027] 11 Heat sink

[0028] 20 GaN power devices

[0029] 201 D-Mode GaN Transistor

[0030] 211 Source Pad

[0031] 212 Drain pad

[0032] 30 Transition Components

[0033] 310 base plate

[0034] 320 Adhesive Layer

[0035] 330 insulation layer

[0036] 340, 340a, 340b, 340c Patterned copper circuit layers

[0037] 340S First Line

[0038] 340D Second Line

[0039] 350 protective layer

[0040] 40 Low-voltage silicon-based MOS die

[0041] 401 Low-voltage nMOS transistor

[0042] 410 Drain pad

[0043] 420 gate pad

[0044] 50 Resistor Element

[0045] 60 Gate drive element

[0046] C capacitor

[0047] MC molding plastic

[0048] PD drain pin

[0049] PG gate pin

[0050] PS source pin

[0051] R resistor

[0052] t thickness

[0053] W1~W7 lead wires

[0054] ZD1 and ZD2 diodes Detailed Implementation

[0055] This invention provides several different embodiments for implementing various features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact," or it may mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and not to indicate any correlation between different embodiments and / or configurations.

[0056] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one element or feature and another element or feature in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor element during use and operation. As the orientation of the semiconductor element varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0057] Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply any prior ordinal number of the element, nor do they imply any order of arrangement or manufacturing process between elements. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to using the terminology of a second element, component, region, layer, or section.

[0058] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0059] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details are within the scope of knowledge of those skilled in the art.

[0060] III-V group (e.g., gallium nitride) high electron mobility transistors (HEMTs) can be divided into enhancement-mode (E-mode HEMTs) and depletion-mode (D-mode HEMTs). Common HEMT package types include transistor outline packages (TO), dual flat no-lead packages (DFN), and quad flat no-lead packages (QFN). The following examples use only the TO 220 package as an example; however, those skilled in the art will understand that the present invention can also be used for other types of package carrier structures, such as TO247, DFN8x8, DFN5x6, QFN8x8, and QFN5x6.

[0061] Please see Figures 1 to 3 ,in, Figure 1 This is a partial perspective view of a GaN power device package according to an embodiment of the present invention. Figure 2 For along Figure 1 A schematic cross-sectional view shown by the tangent I-I' in the diagram. Figure 3 Example Figure 1 The diagram shows a cascaded GaN power device package.

[0062] like Figures 1 to 3 As shown, the GaN power device package 1 includes a frame base island 10, a heat sink 11 connected to the frame base island 10, a drain pin PD extending outward from one side of the frame base island 10, a gate pin PG and a source pin PS located on both sides of the drain pin PD, and a GaN power device 20 mounted on the frame base island 10. According to an embodiment of the present invention, the pin configuration is defined from left to right as a GDS configuration of gate (G), drain (D), and source (S). According to an embodiment of the present invention, the frame base island 10, the heat sink 11, and the drain pin PD may be integrally formed of copper metal, but are not limited thereto. According to an embodiment of the present invention, the GaN power device 20 is, for example, a D-Mode GaN HEMT die.

[0063] According to embodiments of the present invention, such as Figure 1As shown in the enlarged view, the GaN power device package 1 further includes a transfer element 30, mounted on the frame base island 10 and located on one side of the GaN power device 20. According to an embodiment of the present invention, a low-voltage silicon-based MOS die 40 and a resistor element 50 are further disposed on the transfer element 30. According to an embodiment of the present invention, both the transfer element 30 and the resistor element 50 can be fixed to the transfer element 30 using surface mount technology. Figure 3 As shown, normally-off operation is achieved through a cascaded configuration consisting of a low-voltage nMOS transistor 401 in the low-voltage silicon-based MOS die 40, a D-Mode GaN transistor 201 in the GaN power device 20, and a resistor element 50. According to an embodiment of the present invention, the frame base island 10, the GaN power device 20, the transfer element 30, the resistor element 50, a portion of the drain pin PD, a portion of the gate pin PG, and a portion of the source pin PS are protected by a molding compound MC.

[0064] According to embodiments of the present invention, the transfer element 30 may be a substrate having patterned lines thereon, such as a high-temperature resistant substrate like a ceramic substrate, an aluminum substrate, or an FR5 fiberglass substrate, but is not limited thereto. According to embodiments of the present invention, for example, the ceramic substrate may contain alumina (Al2O3) or aluminum nitride (AlN), but is not limited thereto. For example, as... Figure 2 As shown, the thickness t of the transfer element 30 is approximately between 0.1 mm and 1.0 mm, and it may include a substrate 310, an adhesive layer 320 located between the substrate 310 and the frame base island 10, an insulating layer 330 located on the substrate 310, a patterned copper circuit layer 340 located on the insulating layer 330, and a protective layer 350 covering the insulating layer 330 and the patterned copper circuit layer 340. According to an embodiment of the present invention, the patterned copper circuit layer 340 may include, for example, separate first circuit 340S and second circuit 340D, and the resistive element 50 is connected across the first circuit 340S and the second circuit 340D using surface mount technology. According to an embodiment of the present invention, a low-voltage silicon-based MOS die 40 is die-bonded to the other end of the first circuit 340S using surface mount technology.

[0065] According to some embodiments of the present invention, if the substrate 310 is made of a non-conductive substrate material, such as ceramic or glass fiber, the insulating layer 330 may be omitted. According to embodiments of the present invention, the adhesive layer 320 adhesively fixes the substrate 310 to the frame base island 10. For example, the adhesive layer 320 may contain silver paste or other adhesive materials that can withstand temperatures up to at least 80-90°C.

[0066] According to an embodiment of the present invention, after the transfer element 30, on which a low-voltage silicon-based MOS die 40 and a resistor element 50 are fixed, and the GaN power element 20 are fixed on the frame base island 10, a wire bonding process is performed. The source pad 211 on the GaN power element 20 is electrically connected to the drain pad 410 on the low-voltage silicon-based MOS die 40 by a lead W1 (e.g., copper wire). The gate pad 420 on the low-voltage silicon-based MOS die 40 is electrically connected to the gate pin PG by a lead W2 (e.g., copper wire). The drain pad 212 on the GaN power element 20 is electrically connected to the frame base island 10 and the drain pin PD by a lead W3 (e.g., copper wire). The first line 340S of the transfer element 30 is electrically connected to the source pin PS by a lead W4 (e.g., copper wire), and the second line 340D of the transfer element 30 is electrically connected to another source pad 211 on the GaN power element 20 by a lead W5 (e.g., copper wire), thus forming the following configuration: Figure 3 The cascaded configuration is shown. Since the low-voltage silicon-based MOS die 40 is die-bonded on the transfer element 30, damage to the low-voltage element during operation can be avoided.

[0067] Please see Figure 4 and Figure 5 ,in, Figure 4 This is a partial perspective view of a GaN power device package according to another embodiment of the present invention. Figure 5 Example Figure 4 The circuit diagram of GaN power device packages in the image shows that the same areas, layers or components are still represented by the same symbols.

[0068] like Figure 4 and Figure 5 As shown, the GaN power device package 2 includes a frame base island 10, a heat sink 11 connected to the frame base island 10, a drain pin PD extending outward from one side of the frame base island 10, a gate pin PG and a source pin PS located on both sides of the drain pin PD, and a GaN power device 20 mounted on the frame base island 10. According to an embodiment of the present invention, the pin configuration is defined from left to right as a GDS configuration of gate (G), drain (D), and source (S). According to an embodiment of the present invention, the frame base island 10, the heat sink 11, and the drain pin PD may be integrally formed of copper metal, but are not limited thereto. According to an embodiment of the present invention, the GaN power device 20 is, for example, a D-Mode GaN HEMT die.

[0069] According to an embodiment of the present invention, the GaN power device package 2 also further includes a transfer element 30, mounted on the frame base island 10 and located on one side of the GaN power device 20. According to an embodiment of the present invention, a gate driver element 60 is mounted on the transfer element 30. According to an embodiment of the present invention, the gate driver element 60 can be fixed to the transfer element 30 using surface mount technology. Figure 5 As shown, normally-off operation is achieved through the cascaded configuration of the gate drive element 60 and the D-Mode GaN transistor 201 in the GaN power element 20. According to an embodiment of the present invention, the frame base island 10, GaN power element 20, transfer element 30, gate drive element 60, a portion of the drain pin PD, a portion of the gate pin PG, and a portion of the source pin PS are protected by a molding compound MC.

[0070] According to embodiments of the present invention, the transfer element 30 may be a substrate having patterned lines thereon, such as a ceramic substrate, an aluminum substrate, or an FR5 fiberglass substrate, but is not limited thereto. According to embodiments of the present invention, for example, the ceramic substrate may contain alumina (Al2O3) or aluminum nitride (AlN), but is not limited thereto. For example, the thickness of the transfer element 30 is approximately between 0.1 mm and 1.0 mm, and its structure is as follows: Figure 2 As shown, without further details. According to embodiments of the present invention, different potential contacts can be connected through the patterned copper circuit layer 340 and leads on the transfer element 30.

[0071] Please see Figure 6 and Figure 7 ,in, Figure 6 This is a partial perspective view of a GaN power device package according to yet another embodiment of the present invention. Figure 7 for Figure 6 The cross-sectional diagram shown by the tangent line II-II' shows that the same regions, layers or elements are still represented by the same symbols.

[0072] like Figure 6 and Figure 7As shown, the GaN power device package 3 also includes a frame base island 10, a heat sink 11 connected to the frame base island 10, a drain pin PD extending outward from one side of the frame base island 10, a gate pin PG and a source pin PS located on both sides of the drain pin PD, and a GaN power device 20 die-bonded on the transfer element 30. According to an embodiment of the present invention, the pin configuration from left to right is also a GDS configuration of gate (G), drain (D), and source (S). According to an embodiment of the present invention, the frame base island 10, the heat sink 11, and the drain pin PD can be integrally formed of copper metal, but are not limited thereto. According to an embodiment of the present invention, the GaN power device 20 is, for example, an E-Mode GaN HEMT die. According to an embodiment of the present invention, the drain pad and source pad of the GaN power device 20 can be electrically connected to the frame base island 10 and the source pin PS, respectively, via leads W5 and W6.

[0073] According to an embodiment of the present invention, the transfer element 30 may be a substrate having patterned circuitry thereon, such as a ceramic substrate, an aluminum substrate, or an FR5 fiberglass substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the ceramic substrate may contain alumina (Al2O3) or aluminum nitride (AlN), but is not limited thereto. The transfer element 30 may include patterned copper circuitry layers 340a, 340b, and 340c located on a substrate 310. The patterned copper circuitry layers 340a, 340b, and 340c are not connected to each other. On the transfer element 30, a resistor R and a capacitor C are connected across the patterned copper circuitry layers 340b and 340c using surface mount technology, forming a protection circuit with diodes ZD1 and ZD2, as shown in the figure. According to an embodiment of the present invention, the patterned copper circuitry layer 340c can be electrically connected to the gate pin PG via lead W7.

[0074] According to some embodiments of the present invention, if the substrate 310 is made of a non-conductive substrate material, such as ceramic or glass fiber, the insulating layer 330 may be omitted. According to embodiments of the present invention, the adhesive layer 320 adhesively fixes the substrate 310 to the frame base island 10. For example, the adhesive layer 320 may contain silver paste or other adhesive materials that can withstand temperatures up to at least 80-90°C.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A power device package comprising: Frame base island; The power components are fixedly mounted on the frame base island; The molding compound encapsulates the frame base island and the power component; The drain pin extends outward from one side of the frame base island and protrudes from the molding plastic; The gate pin is located on one side of the drain pin and extends and protrudes from the molding plastic; The source pin is located on the opposite side of the drain pin relative to the gate pin, and extends and protrudes from the molding compound; as well as The transfer element is mounted on the frame base island and is electrically connected to the power element, the frame base island, the gate pin, the source pin, or the drain pin via multiple leads.

2. The power device package as described in claim 1, wherein, This transition element includes: Substrate; and An adhesive layer is located between the substrate and the frame base island.

3. The power device package as described in claim 2, wherein, The substrate may be a ceramic substrate, an aluminum substrate, or an FR5 fiberglass substrate.

4. The power device package as described in claim 2, wherein, The adhesive layer contains silver paste.

5. The power device package as described in claim 2, wherein, This transition element includes: An insulating layer is located on the substrate; A patterned copper circuit layer is located on the insulating layer; and A protective layer covers the area around the insulating layer and the patterned copper circuit layer.

6. The power device package as described in claim 1, wherein, The thickness of the transfer element is between 0.1 mm and 1.0 mm.

7. The power device package as described in claim 1, wherein, This power device is a GaN power device.

8. The power device package as described in claim 7, wherein, This GaN power device contains a D-Mode GaN HEMT die.

9. The power device package as described in claim 7, wherein, Also includes: Low-voltage silicon-based MOS chips are disposed on this transfer element; and A resistive element is mounted on this transfer element.

10. The power device package as claimed in claim 9, wherein, The resistor element is fixed to the transfer element using surface mount technology.

11. The power device package as claimed in claim 9, wherein, The patterned copper circuit layer includes a separate first circuit and a second circuit, and the resistive element bridges the first circuit and the second circuit.

12. The power device package as claimed in claim 11, wherein, The low-voltage silicon-based MOS die is bonded to the first circuit.

13. The power device package as described in claim 7, wherein, Also includes: A gate driving element is disposed on the transfer element.

14. The power device package as claimed in claim 1, wherein, This GaN power device contains an E-Mode GaN HEMT die.

15. The power device package as claimed in claim 1, wherein, The frame base island is connected to the heat sink.

16. The power device package as described in claim 15, wherein, The frame island, the heat sink, and the drain pin are all made of a single piece of copper metal.

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