Electronic device, circuit board assembly, packaging structure and manufacturing method thereof

Abstract

Embodiments of the present application disclose an electronic device, a circuit board assembly, a packaging structure and a manufacturing method thereof, and relate to the technical field of chip stacking. The present application solves the problem of leakage near the sidewall of the junction between the existing substrate and the through silicon via in the dielectric layer and the silicon substrate. The packaging structure comprises a conductive hole, a first laminated structure and / or a second laminated structure. In the first laminated structure, the conductive hole is arranged through the second dielectric layer, the first dielectric layer, the substrate and part of the thickness of the adjacent next layer of the redistribution layer in the chip of the upper layer, and is electrically connected with the adjacent next layer of the redistribution layer. In the second laminated structure, the conductive hole is arranged through part of the thickness of the second dielectric layer, the first dielectric layer, the substrate and the interposer in the chip, and is electrically connected with the interposer. On the side away from the conductive hole, the included angle between the surface of the part of the first dielectric layer opposite to the hole wall of the conductive hole and the substrate is greater than the included angle between the surface of the part of the second dielectric layer opposite to the hole wall of the conductive hole and the substrate.

Description

Technical Field

[0001] This application relates to the field of chip stacking technology, and in particular to an electronic device, a circuit board assembly, a packaging structure, and a method for manufacturing the same. Background Technology

[0002] In 3D integrated circuit chip (IC) stacking processes, one of the core components is the through silicon via (TSV). TSVs are typically fabricated using dry etching processes. Current dry etching equipment primarily uses inductively coupled plasma (ICP) etching equipment.

[0003] When fabricating through-silicon vias (TSVs), a thick dielectric layer (such as silicon dioxide, SiO2) on top of the silicon substrate must first be etched. This dielectric layer can be considered as a mask layer for the silicon substrate etching (i.e., the hard mask for TSV etching). Therefore, the dielectric layer is etched first using photoresist as a mask. The TSV pattern on the photoresist is transferred to the dielectric layer. Then, the silicon substrate is etched using both the photoresist and the dielectric layer as mask layers to create the desired TSVs. Alternatively, the silicon substrate can be etched using the dielectric layer as a mask layer to create the desired TSVs.

[0004] Taking silicon dioxide (SiO2) as the dielectric layer as an example, due to the dry etching process using an ICP etching machine, the sidewalls of the SiO2 dielectric layer are relatively inclined (e.g., ≤87°). Therefore, in the subsequent process of fabricating through-silicon vias (TSVs), the etching depth of the insulating layer at the interface between the SiO2 dielectric layer and the silicon substrate within the blind via (which can be formed by filling with conductive material) is relatively large, leaving a very thin insulating layer at this location. Consequently, leakage current is prone to occur between the silicon substrate and the TSV at this location. Summary of the Invention

[0005] This application provides an electronic device, a circuit board assembly, a packaging structure, and a method for manufacturing the same, which solves the problem of leakage current occurring near the interface between the dielectric layer and the silicon substrate in existing silicon substrates and through-silicon vias.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, this application provides a packaging structure, including a stacked structure and conductive vias. The stacked structure can be a first stacked structure, a second stacked structure, or may include both. The first stacked structure includes at least two chips and at least one redistribution layer. The redistribution layer is stacked between two adjacent chips. The chip stack structure can have two or more chips. Correspondingly, the redistribution layer in the chip stack structure can be one, two, or more layers, with a redistribution layer between adjacent chip layers. The second stacked structure includes one or more chips and an interposer, with the one or more chips disposed on one side of the interposer. Furthermore, the multiple chips can be spaced apart. Each of the above chips includes a substrate, an insulating layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer and the second dielectric layer are sequentially stacked on one side of the substrate.

[0008] In the first stacked structure, the aforementioned conductive via extends through a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the adjacent next-layer redistribution layer in the upper-layer chip. Furthermore, the conductive via is electrically connected to the redistribution layer (internal conductive lines) it penetrates. An insulating layer within the chip through which the via extends can be wrapped around the sidewalls of the conductive via.

[0009] In the second stacked structure, the aforementioned conductive via is disposed through a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the interposer in the chip, and is electrically connected to the interposer (internal conductive lines). An insulating layer in the chip may be wrapped around the sidewalls of the conductive via.

[0010] The substrate can specifically be a silicon substrate. Correspondingly, the conductive via can be called a through-silicon via (TSV). Furthermore, on the side away from the conductive via, the angle between the portion of the surface of the first dielectric layer opposite to the wall of the conductive via and the substrate is a first angle. The angle between the portion of the surface of the second dielectric layer opposite to the wall of the conductive via and the substrate is a second angle. The first angle is greater than the second angle.

[0011] In other words, after dry etching using an inductively coupled plasma etching (ICP-C) machine, the sidewall tilt angle of the first dielectric layer within the conductive via is greater than that of the second dielectric layer within the conductive via. Here, the sidewall tilt angle refers to the tilt angle of the sidewall relative to the plane of the substrate. Therefore, if the second dielectric layer is silicon dioxide (SiO2), the sidewall tilt angle (i.e., the second included angle) of the second dielectric layer within the conductive via is less than or equal to 87°. Therefore, the sidewall tilt angle (i.e., the first included angle) of the first dielectric layer within the conductive via must be greater than 87°. Consequently, in the subsequent fabrication of through-silicon vias (TSVs), the etching amount of the insulating layer near the interface between the first dielectric layer and the substrate within the blind via (which can be formed by filling with conductive material) will be correspondingly smaller, leaving a thicker insulating layer at that location. This thicker insulating layer helps prevent leakage between the substrate and the conductive via at that location.

[0012] Furthermore, if the second dielectric layer is silicon dioxide (SiO2), its etching rate during dry etching is relatively slow, resulting in a smaller sidewall tilt angle within the conductive hole. Therefore, the first dielectric layer needs to be made of a material with a faster etching rate during dry etching to ensure a larger sidewall tilt angle within the conductive hole. In other words, during the dry etching process, the etching rate of the first dielectric layer is greater than that of the second dielectric layer.

[0013] Therefore, in some embodiments of this application, the first dielectric layer can specifically be silicon nitride (Si3N4) or a material with a dielectric constant less than 4. Materials with a dielectric constant less than 4 can be referred to as low-k materials. Specifically, the low-k material used in the first dielectric layer can be fluorosilicate glass (FSG), BD1 (black diamond 1), BD2 (black diamond 2), BD3 (black diamond 3), or Aurora, etc. Among these, BD1, BD2, BD3, and Aurora are all low-k materials based on carbon-doped silicon oxide deposited by chemical vapor deposition. These materials all exhibit relatively fast etching rates during dry etching.

[0014] Furthermore, to ensure that the thickness of the insulating layer left at the junction of the first dielectric layer outside the conductive hole and the substrate is sufficient to guarantee reliable insulation performance at that location, in the embodiments of this application, the first included angle is greater than or equal to 88°, and the second included angle is less than or equal to 87°.

[0015] Similarly, the first dielectric layer also needs to maintain a certain thickness. If the thickness of the first dielectric layer is too thin, the tilt angle of the portion of the surface opposite to the hole wall in the first dielectric layer will have little impact on subsequent processes. Therefore, in the embodiments of this application, the thickness of the first dielectric layer is greater than or equal to 1 / 5 of the total thickness of the first dielectric layer and the second dielectric layer.

[0016] Furthermore, considering that the material used in the first dielectric layer may have high stress or poor adhesion with the material of the substrate, in some embodiments of this application, the chip further includes an adhesive layer, which is stacked between the substrate and the first dielectric layer. The adhesive layer can improve the stress and adhesion between the first dielectric layer and the substrate.

[0017] Therefore, in some embodiments of this application, the substrate material is silicon. The adhesive layer material is silicon dioxide. Silicon dioxide has good adhesion to both silicon and silicon nitride (first dielectric layer), that is, the adhesive layer has good adhesion to both the substrate and the first dielectric layer.

[0018] Secondly, embodiments of this application also provide a method for manufacturing a packaging structure. This method includes the following steps:

[0019] Fabricate a first stacked structure and / or a first stacked structure. A redistribution layer and a second chip are sequentially and alternately stacked on a first chip to obtain a first stacked structure. A third chip is stacked on an interposer to obtain a second stacked structure. Each of the first, second, and third chips includes a substrate, an insulating layer, and a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate.

[0020] Fabrication of insulating layer and conductive vias: Through-holes with at least sidewalls covered by an insulating layer are formed within the second chip in the first stacked structure. Conductive vias are formed within the through-holes and at corresponding positions in the redistribution layer to obtain a package structure. The conductive vias penetrate a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the redistribution layer in the second chip and are electrically connected to the redistribution layer. Therefore, the insulating layer surrounds the sidewalls of the conductive vias.

[0021] In the third chip of the second stacked structure, a through-hole with at least its sidewalls covered by an insulating layer is formed. Conductive vias are formed within the through-hole and at corresponding positions in the interposer to obtain a package structure. The conductive vias penetrate a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the interposer in the third chip and are electrically connected to the interposer. Therefore, the insulating layer surrounds the sidewalls of the conductive vias.

[0022] Furthermore, for either the first or second stacked structure, on the side furthest from the conductive via, the angle between the portion of the first dielectric layer surface opposite the via wall and the substrate is a first angle. The angle between the portion of the second dielectric layer surface opposite the via wall and the substrate is a second angle. The first angle is greater than the second angle.

[0023] Therefore, the packaging structure described in the first aspect can be fabricated using the above-described manufacturing method.

[0024] Thirdly, this application also provides another method for manufacturing a packaging structure. This method includes the following steps:

[0025] Fabricate a first stacked structure layer and / or a first stacked structure layer. A redistribution structure and a second wafer are sequentially stacked on a first wafer to obtain the first stacked structure layer. A third wafer is stacked on an interposer to obtain the second stacked structure layer. Each of the first, second, and third wafers includes a substrate layer, a first dielectric structure, and a second dielectric structure. The first dielectric structure and the second dielectric structure are sequentially stacked on one side of the substrate layer.

[0026] An insulating structure and multiple conductive vias are fabricated. Multiple vias, at least on their sidewalls covered by an insulating layer, are formed within a second wafer in the first stacked structure layer. Multiple conductive vias are formed within these vias on the second wafer and at positions corresponding to the vias in the redistribution structure. The conductive vias penetrate a portion of the thickness of the second dielectric structure, the first dielectric structure, the substrate layer, and the redistribution structure in the first wafer, and are electrically connected to the redistribution structure. Therefore, the insulating layer surrounds the sidewalls of the corresponding conductive vias.

[0027] Multiple vias, at least those with sidewalls covered by an insulating layer, are formed within the third wafer in the second stacked structure layer. Multiple conductive vias are formed within the vias of the third wafer and at corresponding positions in the intermediate plate. These conductive vias penetrate a portion of the thickness of the second dielectric structure, the first dielectric structure, the substrate layer, and the intermediate plate in the third wafer, and are electrically connected to the intermediate plate. Therefore, the insulating layer surrounds the sidewalls of the corresponding conductive vias.

[0028] Multiple chip package structures are fabricated. The first stacked structure layer is diced to obtain multiple chip package structures, each including the first stacked structure and conductive vias. The first stacked structure includes an insulating layer, a first chip, a redistribution layer, and a second chip stacked sequentially.

[0029] And / or, the second stacked structure layer is cut to obtain multiple chip package structures including the second stacked structure and conductive holes. The second stacked structure includes an insulating layer, an interposer layer stacked sequentially, and a third chip.

[0030] Furthermore, in either the first or second stacked structure, the first chip, the second chip, and the third chip all include a substrate, an insulating layer, and a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate. On the side away from the conductive via, the angle between the portion of the surface of the first dielectric layer opposite to the wall of the conductive via and the substrate is a first angle, and the angle between the portion of the surface of the second dielectric layer opposite to the wall of the conductive via and the substrate is a second angle. The first angle is greater than the second angle.

[0031] Therefore, the packaging structure described in the first aspect can also be manufactured using the above manufacturing method.

[0032] Fourthly, embodiments of this application also provide a circuit board assembly. The circuit board assembly includes a circuit board and the packaging structure described in the first aspect, with the packaging structure disposed on the circuit board. Since the packaging structure in the circuit board assembly of this application is identical in structure to the packaging structure described in the first aspect, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here.

[0033] Fifthly, embodiments of this application also provide an electronic device. This electronic device includes a controller and the circuit board assembly described in the fourth aspect above, the circuit board assembly being electrically connected to the controller. Since the circuit board assembly in the electronic device of this application has the same structure as the circuit board assembly described in the fourth aspect above, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here. Attached Figure Description

[0034] To illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0035] Figure 1 This is a schematic diagram of the circuit board assembly according to an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the chip packaging structure of the 3D packaging according to an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the chip packaging structure of Embodiment 2.5D of this application;

[0038] Figure 4 This is a schematic diagram of a chip packaging structure combining 2.5D packaging and 3D packaging according to an embodiment of this application;

[0039] Figure 5 This is a partial structural diagram of a chip packaging structure used in related technologies.

[0040] Figure 6 This is a partial three-dimensional schematic diagram of the first chip packaging structure in Example 1;

[0041] Figure 7 This is a schematic diagram showing partial parameter annotations for the first chip packaging structure in Example 1;

[0042] Figure 8 This is a partial structural diagram of the second chip packaging structure in Example 1;

[0043] Figure 9 (a), (b), (c), (d), and (e) are schematic diagrams of each step in the fabrication method of the chip packaging structure in Example 2, respectively.

[0044] Figure 10 (a), (b), (c), (d), (e), and (f) are schematic diagrams of each step in the fabrication method of the chip packaging structure in Example 3.

[0045] Figure 11 This is a partial three-dimensional schematic diagram of the chip packaging structure in Example 4;

[0046] Figure 12 (a), (b), (c), (d), and (e) are schematic diagrams of each step in the fabrication method of the chip package structure in Example 5, respectively.

[0047] Figure 13 (a), (b), (c), (d), (e), and (f) are schematic diagrams of each step in the fabrication method of the chip package structure in Example 6.

[0048] Icon labels:

[0049] 1000 - Circuit board assembly; 100 - Circuit board; 200 - Packaging structure; 200S - Chip packaging structure; 10 - Chip stacking structure; 1 - Chip; 1a - First chip; 1b - Second chip; 1c - Third chip; 101a - First wafer; 101b - Second wafer; 101c - Third wafer; 11 - Substrate; 11S - Substrate layer; 1101 - First side; 1102 - Second side; 12a - Dielectric layer; 121 - First dielectric layer; 121S - First dielectric structure; 122 - Second dielectric layer; 122S - Second dielectric structure; 13 - Insulating layer; 14 - Adhesive layer; 2 - Redistribution layer; 2S - Redistribution structure; 3 - Conductive via; 31 - First through-hole; 32 - Blind via; 4 - Intermediate board; 4S - Intermediate board; 20 - Packaging substrate. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0051] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0052] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0053] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can refer to a mechanical or physical connection. It can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. It can also be understood as the physical contact and electrical conduction of components, or as the form of connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as PCB copper foil or wires.

[0054] This application provides an electronic device that may include a controller and a circuit board assembly. The controller is electrically connected to the circuit board assembly. Here, the electronic device may be, for example, a server, consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc., and this application does not limit this. Illustrated, the aforementioned consumer electronics may be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics may be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. Automotive electronic products may be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products may be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products may be servers, storage devices, radar, base stations, and other communication equipment. The embodiments of this application do not impose any special restrictions on the specific form of the above-mentioned electronic devices.

[0055] Reference Figure 1 The aforementioned circuit board assembly 1000 may include a circuit board 100 and a package structure 200 disposed on the circuit board 100. Specifically, the circuit board 100 may be a printed circuit board (PCB). The package structure 200 may be disposed on the circuit board 100. Furthermore, the package structure 200 in this embodiment may be a chip package structure 200S employing various packaging methods. For example, the package structure 200 may employ 2.5D packaging or 3D packaging.

[0056] so, Figure 2 A chip package structure 200S employing 3D packaging is shown. (Refer to...) Figure 2 The chip packaging structure 200S includes a chip stacking structure 10 and a packaging substrate 20. The chip stacking structure 10 includes multiple chips 1 and multiple redistribution layers 2, with the multiple chips 1 stacked vertically along the thickness direction. The multiple redistribution layers 2 are located between adjacent chips 1. Conductive vias are provided between the chips 1 and the redistribution layers 2. Signal transmission occurs between adjacent chip layers 1 through the connected conductive vias and redistribution layers 2. The conductive vias can specifically be through-silicon vias (TSVs). The chip stacking structure 10 is disposed on the packaging substrate 20. It should be noted that the 3D packaging chip packaging structure 200S may also omit the aforementioned packaging substrate 20.

[0057] Figure 3 The chip package structure 200S using 2.5D packaging is shown. (Refer to...) Figure 3 The chip package structure 200S includes multiple chips 1, an interposer 4, and a package substrate 20. The multiple chips 1 are spaced apart on the interposer 4. The interposer 4 is disposed on the package substrate 20. Multiple conductive vias are provided between any chip 1 and the interposer 4. These conductive vias allow electrical signals to be transmitted vertically between the chip 1 and the package substrate 20. The substrate 11 of the chip 1 can be made of silicon. Accordingly, the conductive vias are specifically through-silicon vias (TSVs). It should be noted that the chip package structure 200S using 2.5D packaging may also omit the aforementioned package substrate 20.

[0058] Figure 4 A chip packaging structure 200S combining 2.5D and 3D packaging is shown. (Refer to...) Figure 4The chip packaging structure 200S includes a chip stack structure 10, individual chips 1, an interposer 4, and a packaging substrate 20. The chip stack structure 10 and the individual chips 1 are spaced apart on the interposer 4. The structure of the chip stack structure 10 is the same as that of the chip stack structure 10 in the aforementioned chip packaging structure 200S employing 3D packaging technology. Furthermore, the individual chips 1 and the interposer 4 are electrically connected via conductive vias (such as through-silicon vias). The interposer 4 is disposed on the packaging substrate 20.

[0059] Therefore, in the three chip packaging structures mentioned above (200S), through-silicon vias (TSVs) are one of the core connection structures. TSVs are typically fabricated using an inductively coupled plasma etching (ICP-ADI) machine. The dielectric layer 12a (such as silicon dioxide, SiO2) on top of the substrate 11 of chip 1 can serve as a mask layer for etching the TSVs. (Refer to...) Figure 5 The fabrication process of through-silicon vias (TSVs) is as follows: Using photoresist as a mask, the dielectric layer 12a is etched using an inductively coupled plasma etching (ICP-CPE) machine to transfer the TSV pattern onto the dielectric layer 12a. Then, using photoresist and dielectric layer 12a as a mask layer, or using dielectric layer 12a as a mask layer, dry etching is performed using an ICP-CPE machine to etch the silicon substrate 11, obtaining the TSVs. Next, an insulating layer is formed within the TSVs etched in the dielectric layer 12a. Then, the interposer 4 or redistribution layer 2 is further etched, causing the TSVs to extend and form blind vias. Finally, conductive material is filled into the blind vias to obtain the desired conductive vias 3.

[0060] Taking silicon dioxide (SiO2) as the dielectric layer 12a as an example, due to the low ion energy of the inductively coupled plasma etching (ICP) system, the sidewalls of the dielectric layer 12a are more inclined after etching (i.e., Figure 5 The median angle A ≤ 87° (e.g., angle A is 85°). Therefore, during the etching of the interposer 4 or redistribution layer 2, the etching depth of the insulating layer 13 (used to isolate the silicon substrate 11 and the conductive hole 3) at the interface between the dielectric layer 12a and the silicon substrate 11 within the blind via (which can be formed by filling with conductive material) is relatively large, resulting in a very thin remaining insulating layer 13. Figure 5 The area of ​​insulating layer 13 within the dashed circle. This may cause leakage problems between the silicon substrate 11 and the conductive via 3 at this location.

[0061] Therefore, in order to solve this problem, the chip packaging structure has been improved in the embodiments of this application. The following describes this application with specific examples.

[0062] Example 1

[0063] Continue to refer to Figure 2 This example shows a 3D chip packaging structure, 200S. Figure 6As shown, any chip 1 in this example chip package structure 200S includes a substrate 11, a first dielectric layer 121, and a second dielectric layer 122. The substrate 11 has a first side 1101 and a second side 1102. The first side 1101 and the second side 1102 are opposite to each other. The first dielectric layer 121 and the second dielectric layer 122 are sequentially stacked on the first side 1101 of the substrate 11. A redistribution layer 2 may be disposed on the second side 1102 of the substrate 11.

[0064] The chip stack structure 10 in this example includes multiple layers of conductive vias 3, each layer of conductive vias 3 connecting two adjacent chip layers 1. For example... Figure 6 As shown, any conductive hole 3 can penetrate a portion of the thickness of the second dielectric layer 122, the first dielectric layer 121, the substrate 11, and the adjacent next redistribution layer 2 located in the upper chip 1.

[0065] Each redistribution layer 2 includes an insulating structure and a conductive structure, with the conductive structure disposed within the insulating structure. The conductive structure includes multiple wiring layers and multiple interconnecting vias, with the multiple wiring layers located in different layers within the insulating structure. The multiple interconnecting vias connect to the wiring layers in different layers.

[0066] The conductive via 3 can penetrate and connect to the conductive structure of the lower redistribution layer 2. Thus, the conductive via 3 can electrically connect the chip 1 to the lower redistribution layer 2. Each chip 1 also includes an insulating layer 13, which can wrap around the sidewall of the conductive via 3. Specifically, the insulating layer 13 can be made of silicon dioxide (SiO2).

[0067] Furthermore, referring to Figure 7 On the side away from the conductive hole 3, the angle between the portion of the surface of the first dielectric layer 121 opposite to the hole wall of the conductive hole 3 and the substrate 11 is a first angle α. The first angle α is the tilt angle of the sidewall of the first dielectric layer 121 within the conductive hole 3 after dry etching using an inductively coupled plasma etching machine. In this application, the sidewall tilt angle refers to the tilt angle of the sidewall relative to the plane where the substrate 11 is located.

[0068] On the side away from the conductive hole 3, the angle between the portion of the second dielectric layer 122 surface opposite to the hole wall of the conductive hole 3 and the substrate 11 is a second angle β. The second angle β is the tilt angle of the sidewall of the second dielectric layer 122 within the conductive hole 3 after dry etching using an inductively coupled plasma etching machine.

[0069] The first included angle α is greater than the second included angle β. That is, after dry etching using an inductively coupled plasma etching machine, the tilt angle of the sidewall of the first dielectric layer 121 in the conductive hole 3 is greater than the tilt angle of the sidewall of the second dielectric layer 122 in the conductive hole 3.

[0070] For example, if the second dielectric layer 122 is silicon dioxide (SiO2), the inclination angle of the sidewall of the second dielectric layer 122 within the conductive hole 3 (i.e., the second included angle β) is less than or equal to 87°, such as β being 85°. The inclination angle of the sidewall of the first dielectric layer 121 within the conductive hole 3 (i.e., the first included angle α) must be greater than 87°, such as α being 89°.

[0071] Therefore, in the subsequent fabrication process of etching the redistribution layer 2 (before forming the conductive hole 3), the etching amount of the insulating layer 13 at the junction of the first dielectric layer 121 outside the conductive hole 3 and the substrate 11 will be relatively small, and the thickness of the insulating layer 13 left at this location will be relatively thick. Thus, the thicker insulating layer 13 can prevent leakage between the substrate 11 and the conductive hole 3 at this location.

[0072] It is understandable that if the second dielectric layer 122 is silicon dioxide (SiO2), the etching rate of the second dielectric layer 122 during dry etching is relatively slow, resulting in a smaller sidewall tilt angle of the second dielectric layer 122 within the conductive hole 3. This means the second included angle β is less than or equal to 87°. Therefore, the first dielectric layer 121 needs to be made of a material with a faster etching rate during dry etching to ensure a larger sidewall tilt angle of the first dielectric layer 121 within the conductive hole 3. That is, to ensure the first included angle α is greater than 87°. In other words, in the dry etching process, the etching rate of the material used for the first dielectric layer 121 is greater than the etching rate of the material used for the second dielectric layer 122.

[0073] Based on this, in some embodiments of this example, the first dielectric layer 121 can specifically be silicon nitride (Si3N4) or a low-dielectric-constant material. In this application, a low-dielectric-constant material refers to a material with a dielectric constant lower than that of silicon dioxide (SiO2 has a dielectric constant of 4). The low-dielectric-constant material used in the first dielectric layer 121 can specifically be fluorosilicate glass, BD1 material, BD2 material, BD3 material, or Aurora material, etc. Specifically, BD1, BD2, BD3, and Aurora materials are all low-dielectric-constant materials based on carbon-doped silicon oxide obtained by chemical vapor deposition. These materials all exhibit relatively fast etching rates during dry etching.

[0074] The aforementioned materials may experience issues such as high stress or poor adhesion with the substrate 11. Therefore, in this example embodiment, the chip 1 further includes, for example, Figure 8 The adhesive layer 14 shown is stacked between the substrate 11 and the first dielectric layer 121. The adhesive layer 14 can improve the stress and adhesion between the first dielectric layer 121 and the substrate 11, that is, ensure that the first dielectric layer 121 and the substrate 11 have a strong connection.

[0075] For example, the substrate 11 described above is a silicon substrate. Accordingly, the material of the adhesive layer 14 can be silicon dioxide. Silicon dioxide has good adhesion to both silicon and silicon nitride (first dielectric layer 121).

[0076] Furthermore, to ensure that the insulating layer 13 left at the junction of the first dielectric layer 121 outside the conductive hole 3 and the substrate 11 has sufficient thickness, thus guaranteeing reliable insulation performance at this location, the first included angle α is greater than or equal to 88°, and the second included angle β is less than or equal to 87° in this example embodiment.

[0077] Furthermore, the first dielectric layer 121 also needs to maintain a certain thickness. For example, if the thickness of the first dielectric layer 121 is too thin, the tilt angle (i.e., the sidewall tilt angle) of the portion of the first dielectric layer 121 opposite to the hole wall of the conductive hole 3 will have a relatively small impact on subsequent processes. Therefore, in the embodiment of this example, as... Figure 7 As shown, the thickness T1 of the first dielectric layer 121 is greater than or equal to 1 / 5 of the total thickness T0 of the first dielectric layer 121 and the second dielectric layer 122, so as to ensure a better dry etching effect on the first dielectric layer 121.

[0078] Example 2

[0079] This example illustrates a method for fabricating a chip package structure as shown in Example 1. (Refer to...) Figure 9 The method for fabricating this chip packaging structure includes the following steps:

[0080] S201: A redistribution layer and another chip are stacked sequentially on one chip.

[0081] In some embodiments, such as Figure 9 As shown in (a), the upper surface of the first chip 1a is hybrid bonded to the lower surface of a redistribution layer 2. Then, the upper surface of the redistribution layer 2 is hybrid bonded to the lower surface of the second chip 1b.

[0082] S202: A through-hole is formed in the chip, with at least the sidewalls covered by an insulating layer.

[0083] In some embodiments, the steps for creating the above-mentioned through-holes with at least sidewalls covered by an insulating layer are as follows:

[0084] First, the first via 31 is formed within the second chip 1b using dry etching with an inductively coupled plasma etching machine. For example... Figure 9As shown in (b), the first via 31 penetrates the second dielectric layer 122, the first dielectric layer 121, and the substrate 11 of the second chip 1b. Furthermore, on the side away from the conductive via 3, the angle between the portion of the surface of the first dielectric layer 121 opposite to the wall of the first via 31 and the substrate 11 is the aforementioned first angle α. The angle between the portion of the surface of the second dielectric layer 122 opposite to the wall of the first via 31 and the substrate 11 is the aforementioned second angle β. The first angle α is greater than the second angle β.

[0085] Subsequently, a deposition process is used to form a layer on the inner wall of the first through-hole 31. Figure 9 The insulating layer 13 is shown in (c). The material of the insulating layer 13 can be the same as the material of the dielectric layer in the redistribution layer 2, such as SiO2. Alternatively, the material of the insulating layer 13 can be different from the material of the dielectric layer in the redistribution layer 2, and this application does not impose any restrictions on this.

[0086] S203: Conductive holes are formed in the vias and at positions corresponding to the vias in the redistribution layer to obtain the chip package structure of Example 1 above.

[0087] In some embodiments, the steps for fabricating the above-mentioned conductive hole are as follows:

[0088] First, dry etching is performed on the redistribution layer 2 at the location corresponding to the first via 31 using an inductively coupled plasma etching machine. This extends the etching of the first via 31 to form a shape similar to... Figure 9 The blind via 32 is shown in (d). This blind via 32 penetrates a portion of the thickness of the redistribution layer 2. The depth of the blind via 32 is the location of the connection between the preset conductive via 3 and a certain wiring layer in the redistribution layer 2.

[0089] Then, conductive material is filled into the blind hole 32 to form a shape like... Figure 9 The conductive hole 3 is shown in (e). This yields the chip package structure 200S of Example 1 described above. The conductive hole 3 can be electrically connected to the redistribution layer 2. Furthermore, the insulating layer 13 can be wrapped around the sidewall of the conductive hole 3.

[0090] It is understood that in some embodiments, the chip package structure 200S includes multiple chips 1 and multiple redistribution layers 2. Therefore, steps S201, S202, and S203 are repeated on the stacked structure including two chips 1 and one redistribution layer 2 obtained in step S203. Thus, the desired chip package structure 200S is obtained.

[0091] It should be noted that after the conductive hole 3 is fabricated, the second dielectric layer 122 of the original chip 1 can be ground away (e.g., by using chemical mechanical polishing) to remove part of its thickness, depending on the needs of subsequent processes.

[0092] Example 3

[0093] This example demonstrates another method for fabricating the chip package structure of Example 1. (Refer to...) Figure 10 The method for fabricating this chip packaging structure includes the following steps:

[0094] S301: A redistribution structure and another wafer are sequentially stacked on a wafer to obtain the first stacked structure layer.

[0095] In some embodiments, such as Figure 10 As shown in (a), the upper surface of the first wafer 101a is mixed-bonded to the lower surface of a redistribution structure 2S. Then, the upper surface of the redistribution layer 2 is mixed-bonded to the lower surface of the second wafer 101b.

[0096] S302: Multiple through-holes with at least sidewalls covered by an insulating layer are formed in the upper wafer.

[0097] In some embodiments, Figure 10 Figures (b) to (c) show the fabrication process of forming a plurality of first vias 31 with at least the sidewalls covered by an insulating layer 13 within a second wafer.

[0098] The conductive vias 3 are partially penetrated through the second dielectric structure 122S, the first dielectric structure 121S, the substrate layer 11S, and the redistribution structure 2S in the first wafer 101a, and are electrically connected to the redistribution structure 2S. An insulating layer 13 surrounds the sidewalls of the multiple conductive vias 3.

[0099] On the side away from the conductive hole 3, the angle between the portion of the surface of the first dielectric structure 121S opposite to the hole wall of the first through hole 31 and the substrate layer 11S is the aforementioned first included angle α. The angle between the portion of the surface of the second dielectric structure 122S opposite to the hole wall of the first through hole 31 and the substrate layer 11S is the aforementioned second included angle β. The first included angle α is greater than the second included angle β.

[0100] Therefore, the steps for making insulating layer 13 in this example are the same as those for making insulating layer 13 in Example 2, and will not be repeated here.

[0101] S303: Multiple conductive vias are formed within the vias of the upper wafer and at positions corresponding to the vias in the redistribution structure. This results in the first stacked structure layer.

[0102] In some embodiments, Figure 10 Figures (d) to (e) illustrate the fabrication process of multiple conductive holes 3. Therefore, the fabrication steps of conductive holes 3 in this example are the same as those in Example 2, and will not be repeated here.

[0103] It should be noted that in some embodiments, the chip package structure 200S includes multiple chips 1 and multiple redistribution layers 2. Therefore, steps S301, S302, and S303 need to be repeated on the stacked structure layer including two wafers and a redistribution structure 2S obtained in step S303. Thus, a stacked structure layer including multiple wafers and multiple redistribution structures 2S is obtained.

[0104] S304: Cut the first stacked structure layer to obtain multiple chip package structures including the first stacked structure and conductive holes.

[0105] In some embodiments, the first stacked structure layer can be cut using methods such as mechanical cutting or laser cutting. A first wafer 101a in the first stacked structure layer is cut into multiple first chips 1a, a second wafer 101b is cut into multiple second chips 1b, a redistribution structure 2S is cut into multiple redistribution layers 2, and the first wafer 101a is cut into multiple first chips 1a. The second dielectric structure 122S in the first wafer 101a or the second wafer 101b is cut into multiple second dielectric layers 122, the first dielectric structure 121S is cut into multiple first dielectric layers 121, and the substrate layer 11S is cut into multiple substrates 11. Thus, multiple... Figure 10 The chip packaging structure 200S is shown in (f).

[0106] Therefore, any chip package structure 200S may include a first stacked structure and a conductive via 3. The first stacked structure includes an insulating layer 13, a first chip 1a, a redistribution layer 2, and a second chip 1b stacked sequentially. The insulating layer 13 surrounds the sidewall of the conductive via 3. The conductive via 3 penetrates a portion of the thickness of the second dielectric layer 122, the first dielectric layer 121, the substrate 11, and the redistribution layer 2 in the second chip 1b, and is electrically connected to the redistribution layer 2.

[0107] It is understood that in some other embodiments, the first stacked structure may also include multiple layers of chip 1 and multiple layers of redistribution layer 2, with the multiple layers of chip 1 and multiple layers of redistribution layer 2 being distributed alternately.

[0108] Example 4

[0109] This example demonstrates a 2.5D chip package structure, 200S. Return to reference. Figure 11This example chip package structure 200S includes a chip 1, an interposer 4, and a conductive via 3. The structure, materials, and location of the chip 1 are identical to those of the chip 1 in Example 1. Furthermore, the positional and connection relationships between the chip 1 and the interposer 4 in this example chip package structure 200S are the same as those between the chip 1 and the redistribution layer 2 in Example 1. These will not be repeated here. The only difference is that the conductive via 3 in this example penetrates a portion of the thickness of the second dielectric layer 122, the first dielectric layer 121, the substrate 11, and the interposer 4 of the chip 1, and is electrically connected to the interposer 4. Therefore, this example also avoids the leakage problem that occurs at the junction of the substrate 11 and the first dielectric layer 121 in the chip 1.

[0110] Example 5

[0111] This example illustrates a method for fabricating a chip package structure as described in Example 4, which is similar to the method for fabricating a chip package structure as described in Example 2. Therefore, refer to... Figure 12 The fabrication method of the 200S chip package structure includes the following steps:

[0112] S501: Chips are stacked on an interposer.

[0113] In some embodiments, such as Figure 12 As shown in (a), the upper surface of the interposer 4 is co-bonded with the lower surface of the third chip 1c. It can be understood that there can be multiple chips 1, and the lower surfaces of the multiple chips 1 can be co-bonded with the upper surface of the interposer 4 respectively. The multiple chips 1 are spaced apart.

[0114] S502: A via is formed in the chip with at least one sidewall covered by an insulating layer.

[0115] In some embodiments, Figure 12 Figures (b) to (c) show the fabrication process of forming a first through-hole 31 with at least the sidewalls covered by an insulating layer 13 within the third chip 1c.

[0116] The conductive hole 3 penetrates a portion of the thickness of the second dielectric layer 122, the first dielectric layer 121, the substrate 11, and the interposer 4 in the third chip 1c, and is electrically connected to the interposer 4. The insulating layer 13 is wrapped around the sidewall of the conductive hole 3.

[0117] Furthermore, on the side away from the conductive hole 3, the angle between the portion of the surface of the first dielectric layer 121 opposite to the wall of the first through hole 31 and the substrate layer 11S is the aforementioned first included angle α. The angle between the portion of the surface of the second dielectric layer 122 opposite to the wall of the first through hole 31 and the substrate layer 11S is the aforementioned second included angle β. The first included angle α is greater than the second included angle β.

[0118] Therefore, the steps for making insulating layer 13 in this example are the same as those for making insulating layer 13 in Example 2, and will not be repeated here.

[0119] S503: Conductive holes are fabricated in the aforementioned through holes and at positions corresponding to the through holes in the intermediate plate. Thus, the chip package structure 200S of Example 4 above is obtained.

[0120] In some embodiments, Figure 12 Figures (d) to (e) illustrate the fabrication process of the conductive hole. Therefore, the fabrication steps for conductive hole 3 in this example are the same as those for conductive hole 3 in Example 2, and will not be repeated here.

[0121] Example 6

[0122] This example illustrates another method for fabricating the chip package structure in Example 4, which is similar to the method for fabricating the chip package structure in Example 2. (Refer to...) Figure 13 The fabrication method of the 200S chip package structure includes the following steps:

[0123] S601: Wafers are stacked on an interposer board.

[0124] In some embodiments, such as Figure 13 As shown in (a), the upper surface of the intermediate plate 4 is mixed-bonded with the lower surface of the third wafer 101c.

[0125] S602: A plurality of through-holes are formed in the wafer, with at least the sidewalls covered by an insulating layer.

[0126] In some embodiments, Figure 13 Figures (b) to (c) show the fabrication process of forming a plurality of first vias 31 with at least the sidewalls covered by an insulating layer 13 within a third wafer 101c.

[0127] The conductive holes 3 are partially penetrated through the second dielectric structure 122S, the first dielectric structure 121S, the substrate layer 11S, and the intermediate plate 4S in the third wafer 101c, and are electrically connected to the intermediate plate 4S. The insulating layer 13 is wrapped around the sidewalls of the multiple conductive holes 3.

[0128] On the side away from the conductive hole 3, the angle between the portion of the surface of the first dielectric structure 121S opposite to the hole wall of the first through hole 31 and the substrate layer 11S is the aforementioned first included angle α. The angle between the portion of the surface of the second dielectric structure 122S opposite to the hole wall of the first through hole 31 and the substrate layer 11S is the second included angle β. The first included angle α is greater than the second included angle β.

[0129] Therefore, the steps for making insulating layer 13 in this example are the same as those for making insulating layer 13 in Example 2, and will not be repeated here.

[0130] S603: Conductive vias are formed within multiple vias on the wafer and at positions corresponding to the multiple vias in the interposer plate. This results in a second stacked structure layer.

[0131] In some embodiments, Figure 13 Figures (d) to (e) illustrate the fabrication process of multiple conductive holes 3. Therefore, the fabrication steps of conductive holes 3 in this example are the same as those in Example 2, and will not be repeated here.

[0132] S604: Cut the second stacked structure layer to obtain multiple chip package structures including the second stacked structure and conductive holes.

[0133] In some embodiments, the second stacked structure layer can also be cut using methods such as mechanical cutting or laser cutting. The third wafer 101c in the second stacked structure layer is cut into multiple third chips 1c, and the interposer 4S is cut into multiple interposers 4. The second dielectric structure 122S in the third wafer 101c is cut into multiple second dielectric layers 122, the first dielectric structure 121S is cut into multiple first dielectric layers 121, and the substrate layer 11S is cut into multiple substrates 11. Thus, multiple... Figure 13 The chip packaging structure 200S is shown in (f).

[0134] Therefore, any chip package structure 200S includes a second stacked structure and a conductive via 3. The second stacked structure includes an insulating layer 13, a third chip 1c stacked sequentially, and an interposer 4. The insulating layer 13 surrounds the sidewall of the conductive via 3. The conductive via 3 penetrates a portion of the thickness of the second dielectric layer 122, the first dielectric layer 121, the substrate 11, and the interposer 4 in the third chip 1c, and is electrically connected to the interposer 4.

[0135] It is important to note that during the production process... Figure 4 The chip package structure 200S shown can be combined with any one of the fabrication methods of Example 2 and Example 3, and any one of the fabrication methods of Example 5 and Example 6. Further details are omitted here.

[0136] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A packaging structure, characterized in that, include: A first stacked structure and / or a second stacked structure, wherein the first stacked structure includes at least two chips and at least one redistribution layer, the redistribution layer being stacked between two adjacent chips; the second stacked structure includes an interposer and at least one chip disposed on one side of the interposer; each chip includes a substrate, an insulating layer, and a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate; In the first stacked structure, the conductive via penetrates a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the adjacent next-layer redistribution layer in the chip above, and is electrically connected to the adjacent next-layer redistribution layer; in the second stacked structure, the conductive via penetrates a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the interposer in the chip, and is electrically connected to the interposer; the insulating layer in the chip through which the via penetrates wraps around the sidewall of the conductive via. On the side away from the conductive hole, the angle between the portion of the first dielectric layer surface opposite to the hole wall of the conductive hole and the substrate is a first angle, and the angle between the portion of the second dielectric layer surface opposite to the hole wall of the conductive hole and the substrate is a second angle. The first included angle is greater than the second included angle.

2. The packaging structure according to claim 1, characterized in that, The first included angle is greater than or equal to 88°; the second included angle is less than or equal to 87°.

3. The packaging structure according to claim 1 or 2, characterized in that, The material of the first dielectric layer includes silicon nitride or a material with a dielectric constant less than 4; the material of the second dielectric layer is silicon dioxide.

4. The packaging structure according to any one of claims 1-3, characterized in that, The thickness of the first dielectric layer is greater than or equal to 1 / 5 of the total thickness of the first dielectric layer and the second dielectric layer.

5. The packaging structure according to any one of claims 1-4, characterized in that, In the dry etching process, the etching rate of the first dielectric layer is greater than that of the second dielectric layer.

6. The packaging structure according to any one of claims 1-5, characterized in that, The chip also includes: An adhesive layer is stacked between the substrate and the first dielectric layer.

7. The packaging structure according to claim 6, characterized in that, The substrate is made of silicon; the adhesive layer is made of silicon dioxide.

8. A method for fabricating a packaging structure, characterized in that, Includes the following steps: Fabricating a first stacked structure and / or a first stacked structure: a redistribution layer and a second chip are sequentially stacked on a first chip to obtain a first stacked structure; a third chip is stacked on an interposer to obtain a second stacked structure; wherein, the first chip, the second chip and the third chip each include a substrate, an insulating layer, and a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate; Fabrication of insulating layer and conductive via: A via with at least an insulating layer covering its sidewalls is formed in the second chip in the first stacked structure; conductive vias are formed in the vias and at positions corresponding to the vias in the redistribution layer to obtain a package structure; wherein the conductive vias are disposed through a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate and the redistribution layer in the second chip, and are electrically connected to the redistribution layer; In the third chip of the second stacked structure, a through-hole with at least an insulating layer covering its sidewalls is formed. Conductive holes are formed in the through-hole and at positions corresponding to the through-hole in the interposer to obtain a package structure. The conductive holes are disposed through a portion of the thickness of the second dielectric layer, the first dielectric layer, the substrate, and the interposer in the third chip and are electrically connected to the interposer. Furthermore, for either the first or second stacked structure, on the side away from the conductive hole, the angle between the portion of the surface of the first dielectric layer opposite to the hole wall of the conductive hole and the substrate is a first angle, and the angle between the portion of the surface of the second dielectric layer opposite to the hole wall of the conductive hole and the substrate is a second angle; the first angle is greater than the second angle.

9. A method for manufacturing an encapsulation structure, characterized in that, Includes the following steps: Fabricating a first stacked structure layer and / or a first stacked structure layer: a redistribution structure and a second wafer are sequentially stacked on a first wafer to obtain a first stacked structure layer; a third wafer is stacked on an interposer to obtain a second stacked structure layer; wherein, the first wafer, the second wafer and the third wafer each include a substrate layer and a first dielectric structure and a second dielectric structure sequentially stacked on one side of the substrate layer. Fabrication of an insulating layer and multiple conductive vias: Multiple vias with at least an insulating layer covering their sidewalls are formed in the second wafer within the first stacked structure layer. Multiple conductive vias are formed within the multiple vias of the second wafer and at positions corresponding to the multiple vias in the redistribution structure. The conductive vias penetrate a portion of the thickness of the second dielectric structure, the first dielectric structure, the substrate layer, and the redistribution structure in the first wafer and are electrically connected to the redistribution structure. A plurality of through-holes with at least an insulating layer covering their sidewalls are formed in the third wafer in the second stacked structure layer. A plurality of conductive holes are formed in the plurality of through-holes in the third wafer and at positions corresponding to the plurality of through-holes in the intermediate plate. The conductive holes penetrate a portion of the thickness of the second dielectric structure, the first dielectric structure, the substrate layer and the intermediate plate in the third wafer and are electrically connected to the intermediate plate. Fabricating multiple chip package structures: Cutting the first stacked structure layer to obtain multiple chip package structures including the first stacked structure and conductive holes; wherein, the first stacked structure includes an insulating layer, a first chip, a redistribution layer and a second chip stacked sequentially; And / or, cut the second stacked structure layer to obtain multiple chip package structures including the second stacked structure and conductive holes; wherein, the second stacked structure includes an insulating layer, an interposer and a third chip stacked sequentially; Furthermore, in the first or second stacked structure, the first chip, the second chip, and the third chip all include a substrate, an insulating layer, and a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate; on the side away from the conductive hole, the angle between the portion of the surface of the first dielectric layer opposite to the hole wall of the conductive hole and the substrate is a first angle, and the angle between the portion of the surface of the second dielectric layer opposite to the hole wall of the conductive hole and the substrate is a second angle; the first angle is greater than the second angle.

10. A circuit board assembly, characterized in that, include: Circuit board; The packaging structure according to any one of claims 1-7, wherein the packaging structure is disposed on the circuit board.

11. An electronic device, characterized in that, include: Controller; The circuit board assembly of claim 10 is electrically connected to the controller.

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