Package substrate with molded extensions and z-height reset layer

Abstract

The embodiments disclosed herein include an apparatus comprising a substrate having a first surface and a second surface opposite the first surface. In one embodiment, a first pillar is located on the first surface of the substrate, and a second pillar is located on the first surface of the substrate. In another embodiment, a first layer is located above the first surface of the substrate, and the first layer embeds the first pillar and the second pillar. In another embodiment, a third pillar is located on the second pillar, and a component is located above the first layer. In another embodiment, the component is coupled to the second pillar. In yet another embodiment, a second layer is located above the first layer, wherein the second layer embeds the third pillar and the component.

Description

Background Technology

[0001] High-performance computing is driving the adoption of larger die-on-die composites on a single substrate. This results in an increased overall package form factor, which can lead to higher substrate warpage. High warpage can cause yield losses during surface mount technology (SMT) for ball grid array (BGA) packages, and / or require high compression pressures and expensive mounting mechanisms for contact grid array (LGA) packages.

[0002] Furthermore, there is a significant demand for advanced packaging with high-bandwidth and high-density interconnects for heterogeneous chiplet integration. For example, in the case of accelerator technologies based on graphics processing units (GPUs) and high-bandwidth memory (HBM), there is a need for very large chip complexes on the package. Existing packaging solutions for such technologies have several drawbacks. For instance, variations in dielectric stack thickness and topography across substrate panels cause problems with interlayer interconnects in the Z-direction. Typically, higher solder volumes (e.g., larger bump critical dimensions (CD)) are used to accommodate these thickness variations. This hinders the reduction of bump pitch to the smaller dimensions required for high-bandwidth solutions. In some cases, XY positioning accuracy is also limited. Attached Figure Description

[0003] Figure 1 This is a schematic cross-sectional view of an electronic system having a warped packaging substrate according to an embodiment.

[0004] Figure 2A This is a cross-sectional schematic diagram of an electronic system having a warp reset layer for an LGA packaging solution according to an embodiment.

[0005] Figure 2B This is a cross-sectional schematic diagram of an electronic system having a warp reset layer for a BGA packaging solution according to an embodiment.

[0006] Figure 3A –3C is a schematic illustration depicting some embodiments described in more detail herein, illustrating improved capacitance performance.

[0007] Figure 4A –4G is a schematic cross-sectional view depicting a process flow for forming a packaging substrate with a warp reset layer, according to an embodiment.

[0008] Figure 4H This is a flowchart depicting a process for forming a packaging substrate with a warp reset layer, according to an embodiment.

[0009] Figure 5A and 5B This is a cross-sectional schematic diagram depicting an interconnect architecture for an electronic system according to an embodiment.

[0010] Figure 6A This is a schematic cross-sectional view of a packaging substrate having a molded extension layer for improved interconnect scaling according to an embodiment.

[0011] Figure 6B This is a schematic cross-sectional view of a package substrate having a molded extension layer for improved interconnect scaling, according to an additional embodiment.

[0012] Figure 7A –7H is a schematic cross-sectional view depicting a process flow for forming a packaging substrate with a molded extension layer, according to an embodiment.

[0013] Figure 7I This is a flowchart depicting a process for forming a packaging substrate with a molded extension layer, according to an embodiment.

[0014] Figure 8A –8I is a schematic cross-sectional view depicting a process flow for forming a package substrate with a molded extension layer on the top and bottom surfaces of a package substrate, according to an embodiment.

[0015] Figure 8J This is a flowchart depicting a process for forming a packaging substrate having an upper molding extension layer and a lower molding extension layer, according to an embodiment.

[0016] Figure 9A –9H is a schematic cross-sectional view depicting a process for forming a packaging substrate having a molded extension layer and a Z-height resetting layer, according to an embodiment.

[0017] Figure 9I This is a process flow diagram depicting, according to an embodiment, a process for forming a packaging substrate having a molded extension layer and a Z-height resetting layer.

[0018] Figure 10 This is a schematic cross-sectional view of an electronic system comprising a package-to-package connection having a package substrate including a Z-height reset layer, according to an embodiment.

[0019] Figure 11A –11D is a schematic cross-sectional view of a process for forming a package substrate with a Z-height reset layer and aligned second-level interconnect pads, according to an embodiment.

[0020] Figure 11E This is a flowchart depicting a process for forming a packaging substrate with a Z-height reset layer and aligned second-level interconnect pads, according to an embodiment.

[0021] Figure 12A –12H is a schematic cross-sectional view according to an embodiment depicting a process for forming an electronic system having a packaged substrate including a molded extension layer and a substrate encapsulation layer.

[0022] Figure 12I This is a process flow diagram depicting, according to an embodiment, a process for forming an electronic system having a packaged substrate including a molded extension layer and a substrate encapsulation layer.

[0023] Figure 13 This is a schematic planar view of the substrate, which has a panel substrate that can be used to fabricate multiple devices, such as any electronic system and / or packaging substrate described in more detail herein.

[0024] Figure 14 This is a schematic cross-sectional view of an electronic system having a packaged substrate coupled to a plate, according to an embodiment described in more detail herein.

[0025] Figure 15 This is a schematic diagram of a computing device constructed according to an embodiment. Detailed Implementation

[0026] This document describes processes and structures according to various embodiments for improving warpage and positional variations on a substrate to achieve enhanced pitch scaling. In the following description, terms commonly used by those skilled in the art will be used to describe various aspects of the illustrative embodiments in order to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that this disclosure may be practiced using only some of the aspects described. Specific figures, materials, and configurations are set forth for purposes of explanation in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that this disclosure may be practiced without these specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the illustrative embodiments.

[0027] The various operations will be described sequentially, in a manner most conducive to understanding this disclosure, as multiple discrete operations; however, the order of description should not be construed as implying that these operations are necessarily sequentially dependent. Specifically, these operations need not be performed in the order presented.

[0028] This document describes various embodiments or aspects of this disclosure. In some implementations, different embodiments are practiced individually. However, the embodiments are not limited to those implemented in isolation. For example, two or more different embodiments may be combined together to be implemented as a single device, process, structure, etc. In some instances, all of the various embodiments may be combined together. In other instances, a portion of a first embodiment may be combined with portions of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with portions of a second embodiment and a portion of a third embodiment.

[0029] As described above, the drive for advanced computing toward larger form factor package components has led to warping and alignment issues with interconnect pads in the X, Y, and / or Z planes. Offsets driven by such issues limit the ability to continuously scale interconnect density. Consequently, data bandwidth between dies on the package component and / or between different package components is limited. Therefore, the embodiments disclosed herein provide different package manufacturing assembly processes and / or features that allow for continuous scaling of interconnect density and / or mitigation of substrate warping. In the embodiments disclosed herein, the process flow is primarily focused on individual devices and / or cells. However, it should be understood that the process flow can be implemented at any form factor, such as panel substrate form factor, quarter-panel form factor, etc. However, the process flow can also be implemented at individual device and / or cell form factors. In the case of larger form factor substrates (e.g., panels or quarter-panels), individual devices and / or cells can be fabricated substantially in parallel.

[0030] Now for reference Figure 1 The diagram illustrates a schematic cross-sectional view of an electronic package 100 according to an embodiment. In this embodiment, the electronic package 100 includes a package substrate 110 and a die 105 coupled to a first surface 111 of the package substrate 110. For example, the die 105 may be coupled to the package substrate 110 via an interconnect 106, such as any suitable first-level interconnect (FLI) architecture (e.g., solder balls, copper bumps, hybrid bonding, etc.). In this embodiment, an interconnect 108 may be coupled to a second surface 112 of the package substrate 110. The interconnect 108 may include any suitable second-level interconnect (SLI), such as a ball grid array (BGA), a contact grid array (LGA), etc.

[0031] The packaging substrate 110 may include any suitable packaging substrate structure, such as a core (e.g., a glass core or an organic core) having an organic dielectric layer formed above and / or below the core. In embodiments, the die 105 may include any type of die, such as a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), an XPU, etc.), a memory die (e.g., an HBM), a communication die, etc. Although Figure 1 A single die 105 is shown, but it should be understood that any number of dies 105 may be coupled to the package substrate 110.

[0032] As shown in the figure, the package substrate 110 may experience significant warpage, as indicated by the bent first surface 111 and the bent second surface 112. Warpage may be a result of a mismatch in the coefficient of thermal expansion (CTE) between the die 105 and the package substrate 110. That is, warpage may occur after the die is coupled to the package substrate 110. Warpage of the second surface 112 is particularly problematic in terms of mounting the interconnect 108. As warpage increases, the solder volume must be increased to accommodate the different heights between the second surface 112 and the board (not shown) beneath the package substrate 110. This increases the critical dimension (CD) of the interconnect 108 and hinders the pitch scaling required to achieve higher data transmission bandwidth.

[0033] Significant changes to electronic package design and / or materials have been proposed to mitigate warpage. For example, increasing the core thickness of the package substrate 110, improving the core stiffness of the package substrate 110 (e.g., by using a glass core), and / or adding reinforcements and / or top covers are some options for reducing warpage. However, many assembly and reliability challenges are associated with these changes. From a BGA and surface mount technology (SMT) perspective, low-temperature soldering (LTS) and multi-ball technology are additional options for mitigating warpage risk. However, LTS typically has lower IMAX capability, which limits the use of such interconnects in high-performance computing (HPC) applications, such as those described in this paper. Multi-ball technology has limited capabilities in overcoming high warpage. Furthermore, both options face significant challenges with finer SLI pitches, limiting their scalability. For LGA packages, theoretically, higher compressive forces could overcome the warpage challenge. However, as compressive force requirements increase, loading mechanisms become extremely complex and expensive. As pin counts continue to increase, the massive forces required to overcome warpage may become impractical.

[0034] Therefore, the embodiments disclosed herein may include adding a warp reset layer on a second surface of the package substrate. That is, a warp reset layer may be provided between the package substrate and the underlying board. In such a configuration, the board exhibits a substantially flat surface during assembly. This reduces the need to change mounting conditions and allows for continuous scaling of interconnect pitch to meet desired design goals. As used herein, "substantially flat" may mean a maximum Z-height variation of approximately 20 µm or less, approximately 10 µm or less, or approximately 5 µm or less.

[0035] In an embodiment, the warpage reset layer may include multiple metal vias (sometimes referred to herein as pillars) and a molding layer surrounding the pillars. The molding layer is formed to a thickness fully embedded with the pillars. Subsequently, the molding layer (and portions of one or more pillars) may be polished back to expose the pillars. In the case of an LGA package substrate, since LGA mounting is typically performed at relatively low temperatures, the polished surface of the molding layer may be substantially flat near room temperature. In the case of a BGA package substrate, since BGA mounting is performed at relatively high temperatures, the polished surface may have curvature near room temperature. At the high temperatures of BGA mounting, the surface of the molding layer may be substantially flat.

[0036] In this embodiment, the substantially flat surface of the warp reduction layer offers opportunities for performance improvements and cost reductions compared to existing solutions. For example, LGA solutions may allow for shorter LGA pins, smaller LGA pads, and / or lower compressive force requirements. Furthermore, other SLI technologies that can be attached / detached at room temperature, such as liquid metal carrier arrays, can also benefit from the production of substantially flat substrates. For BGA solutions, higher-temperature solders can be used, reducing the volume of solder balls and the spacing between solder bumps.

[0037] Now for reference Figure 2A A schematic cross-sectional view of an electronic package 200 according to an embodiment is shown. In an embodiment, the electronic package 200 may include a package substrate 210 having a first surface 211 and a second surface 212. In an embodiment, a die 205 may be electrically coupled to the first surface 211 of the package substrate 210 via an interconnect 206. In an embodiment, the first surface 211 and the second surface 212 may be bent due to warping caused by CTE mismatch between the die 205 and the package substrate 210. In an embodiment, the die 205, the interconnect 206, and the package substrate 210 may be as described herein with respect to... Figure 1 The corresponding features are similarly described in more detail.

[0038] In an embodiment, warpage of the substrate 210 can be mitigated by a warpage reduction layer 215 formed on the second surface 212 of the package substrate 210. In an embodiment, the warpage reduction layer 215 may include a molding material, etc. In an embodiment, the bottom surface 217 of the warpage reduction layer 215 may be substantially flat. In an embodiment, pads 213 on the second surface 212 of the package substrate 210 may be electrically coupled to pads 216 on the bottom surface 217 of the warpage reduction layer 215 via pillars 214. In an embodiment, the pillars 214 may have substantially vertical sidewalls. The pillars 214 may be formed by electroplating upwards from the pads 213, or the pillars 214 may be discrete pillars bonded to the pads 213 (e.g., by solder, etc.). In an embodiment, pads 216 may be provided above each pillar 214 on the bottom surface 217 of the warpage reduction layer 215. This embodiment may be useful for LGA interconnect methods, etc.

[0039] Now for reference Figure 2B A schematic cross-sectional view of an electronic package 200 according to an additional embodiment is shown. In the embodiment, Figure 2B The electronic package 200 can be used with Figure 2A The electronic package 200 is similar, except for the warpage reduction layer 215. Instead of having a substantially flat bottom surface 217, the warpage reduction layer can be curved. In an embodiment, the curvature of the bottom surface 217 can be selected to provide the desired amount of warpage control at elevated temperatures. For example, when the electronic package 200 is bonded to a board (not shown) using a BGA process with interconnects 218, the elevated temperature causes additional warpage, making the bottom surface 217 substantially flat. In an embodiment, the curvature of the bottom surface 217 differs from the curvature of the second surface 212 of the package substrate 210.

[0040] In addition to providing warpage mitigation, the embodiments disclosed herein can also improve high-speed input / output (HSIO) performance. For example, Figure 3A This is a schematic diagram of a baseline BGA electronic package 300 (built-in layers are omitted for simplicity). As shown, there is a capacitor 303 between the pads of interconnect structure 301 and the adjacent ground layer 309, and there is also a capacitor 304 between interconnect 308 and the adjacent ground layer 309. In particular, it has been shown that capacitors 303 and 304 are limiting factors for signal bandwidth.

[0041] However, as Figure 3B As shown, adding a warp reduction layer 315 and pillars 314 to interconnect structure 301 allows for significant improvements in capacitances 303 and 304. For example, the improved flatness provided by the warp reduction layer 315 allows for a reduction in the diameter of the pads beneath the pillars 314. Furthermore, the thickness of the warp reduction layer 315 can reduce capacitance because the distance between the signal pads and the ground plane is increased. The dimensions of interconnect 308 (e.g., solder balls) can also be reduced due to improved flatness. This may also reduce capacitance 304.

[0042] Now for reference Figure 3C The figure illustrates an additional configuration of the electronic package 300 according to an embodiment, which further contributes to improving HSIO performance via the BGA method. As shown, interconnects 308 can be directly attached to exposed posts 314, thereby completely eliminating interconnect pads and their associated capacitance. In some embodiments, interconnects 308 are attached to posts 314 prior to bonding to the board. In other embodiments, interconnects 308 are provided on the board, and the exposed posts 314 are inserted into interconnects 308 during bonding.

[0043] Now for reference Figures 4A to 4G The diagram shows a series of cross-sectional schematics depicting the process of forming a warp reduction layer on an electronic package according to an embodiment.

[0044] Now for reference Figure 4A This diagram illustrates a cross-sectional schematic of a portion of an electronic package 400 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 400 may include a package substrate 410 having a first surface 411 and a second surface 412. In this embodiment, a die 405 may be electrically coupled to the first surface 411 of the package substrate 410 via an interconnect 406. In this embodiment, the first surface 411 and the second surface 412 may be bent due to warping caused by a CTE mismatch between the die 405 and the package substrate 410. In this embodiment, the die 405, the interconnect 406, and the package substrate 410 may be as described herein with respect to… Figure 1 The corresponding features are similarly described in more detail.

[0045] Now for reference Figure 4B This illustration shows a cross-sectional schematic of an electronic package 400 after pads 413 and pillars 414 have been formed on a second surface 412 of a package substrate 410 according to an embodiment. In this embodiment, the pads 413 can be formed by any suitable electroplating and / or patterning process. In this embodiment, the pillars 414 can be formed by electroplating upwards from the pads 413, by forming through-holes, by attaching via a bonding via array method, or the pillars 414 can be attached to the pads 413 (e.g., by solder). In this embodiment, pre-formed conductive pillars 414 are coupled to the pads 413 by applying solder to the pads 413, dropping the pillars 414 onto the solder through a mask, and then reflowing the solder. That is, the pillars 414 can be formed in direct contact with the pads 413, or the pillars 414 can be electrically coupled to the pads 413 via solder.

[0046] Now for reference Figure 4C The figure shows a schematic cross-sectional view of an electronic package 400 after a warpage reduction layer 415 has been formed on the second surface 412 of a packaging substrate 410 according to an embodiment. In the embodiment, the warpage reduction layer 415 may be a molding layer or the like. For example, the warpage reduction layer 415 may be applied by a compression molding process, a transfer molding process, or the like. As shown, the warpage reduction layer 415 may be completely embedded in the pillar 414. That is, the ends of the pillar 414 may be covered by the warpage reduction layer 415.

[0047] In an embodiment, Figures 4A to 4C The operations shown can be performed at the panel level or the cell level. Furthermore, die 405 can... Figures 4A to 4CThe operations shown are attached afterward. Subsequent process operations can be performed after dicing and the attachment of the end-of-line unit, as well as any dies 405, reinforcements, integrated heat sinks, etc. This is because including these additional components may alter the warpage of the package substrate 410. In other words, the planarization provided by the subsequent warpage reduction layer 415 can be performed after the warpage of the electronic package 400 has been substantially stabilized.

[0048] Now for reference Figure 4D The figure shows a schematic cross-sectional view of an electronic package 400 after the warp reduction layer 415 has been recessed to expose the ends of the pillars 414, according to an embodiment. In the embodiment, the warp reduction layer 415 is recessed by a polishing process (e.g., chemical mechanical polishing (CMP) process), an etching process, etc. As shown, the ends of the pillars 414 may be substantially coplanar with the bottom surface 417 of the warp reduction layer 415. Using a substantially flat bottom surface 417 may be useful for lower-temperature bonding processes (e.g., LGA process). As shown, the pillars 414 may have a non-uniform height to accommodate the warp of the package substrate 410.

[0049] Now for reference Figure 4E The diagram shows a schematic cross-sectional view of an electronic package 400 after pads 416 have been formed on pillar 414 according to an embodiment. In this embodiment, pads 416 can be formed by any suitable deposition and / or patterning process. Pads 416 can be LGA pads, etc.

[0050] Now for reference Figure 4F The figure shows a schematic cross-sectional view of an electronic package 400 after an alternative recess process for the warp reduction layer 415, according to an embodiment. As shown, the bottom surface 417 of the warp reduction layer 415 may have curvature. The curvature can be selectively implemented to accommodate additional warp during high-temperature bonding processes (e.g., SMT processes, such as BGA attachments). In embodiments, controlled polishing and / or grinding processes, such as scan polishing processes, can be used to provide the desired curvature for the warp reduction layer 415.

[0051] Now for reference Figure 4G The figure shows a schematic cross-sectional view of an electronic package 400 after interconnect 408 is electrically coupled to pillar 414 according to an embodiment. As shown, pillar 414 directly contacts interconnect 408. However, in other embodiments, pads (not shown) may be provided above the ends of pillar 414 (e.g., similar to...). Figure 3B (The example shown).

[0052] Now for reference Figure 4H This illustrates a process flow diagram depicting process 480 for forming a warp reduction layer on a packaging substrate according to an embodiment. In this embodiment, process 480 may be related to the above description... Figures 4A to 4GAny process described is similar. In an embodiment, process 480 may begin with operation 481, which includes mounting a die to a first surface of a substrate. In an embodiment, the die may be mounted to the first surface of the substrate via any suitable interconnect, such as any suitable FLI architecture.

[0053] In one embodiment, process 480 can proceed to operation 482, which includes forming pillars on a second surface of the substrate. In another embodiment, the pillars can be electrically coupled to pads on the substrate. The pillars can be formed by electroplating upwards from the pads, attached to the pads, etc.

[0054] In one embodiment, process 480 may proceed to operation 483, which includes forming a molding layer over the substrate. In one embodiment, the molding layer may be fully embedded with pillars. In one embodiment, process 480 may proceed to operation 484, which includes recessing the molding layer to expose the pillars. In one embodiment, the recessed molding layer may have a substantially flat bottom surface (e.g., for the LGA method), or the recessed molding layer may have a curved surface (e.g., for the SMT method). In some embodiments, operation 481 may be performed after operation 484. In one embodiment, process 480 may continue to form pads on the exposed pillars and / or form solder interconnects on the exposed pillars or pads.

[0055] For high-bandwidth and high-density interconnects used in heterogeneous chiplet integration, large-scale electronic packaging is required. Two options for such electronic packaging include interposer-based solutions, such as... Figure 5A As shown, or based on bridging solutions, such as... Figure 5B As shown. However, both electronic packaging solutions face significant challenges as chiplet-to-chiplet bump spacing decreases and the form factor of the packaging substrate increases.

[0056] Now for reference Figure 5A This diagram illustrates a cross-sectional schematic of an electronic package 500 with an interposer-based solution according to an embodiment. In this embodiment, the electronic package 500 includes a package substrate 510. The package substrate 510 may be similar to any package substrate described in more detail herein. For example, the package substrate 510 may include a core (e.g., a glass core or an organic core) having an organic dielectric built-in layer above and / or below the core. In this embodiment, an interposer 520 may be coupled to the package substrate 510 via an interconnect 522. The interconnect may be solder balls, etc.

[0057] In an embodiment, the interposer 520 may be a molded interposer substrate having components 525 embedded within the interposer 520. In an embodiment, the component 525 may be a bridging substrate with or without vias 526. In an embodiment, pillars 521 may extend through the interposer 520 to electrically couple interconnects 522 to an upper interconnect 506, which in turn electrically couples die 505 to the interposer 520. Although not shown, a built-in layer with electrical wiring may be provided between the interposer 520 and the interconnect 506. In an embodiment, the component 525 may include one or more wiring layers (not shown) configured to electrically couple the dies 505 to each other. An overmolding layer 527 may be provided around the die 505, and a capillary underfill 528 may be provided around the structure above the package substrate 510.

[0058] Regarding, for example, Figure 5A The large form factor of the illustrated electronic package 500 results in a large pitch (e.g., greater than approximately 110 µm) for the package side bump (PSB) interconnects 522. This loose PSB interconnect pitch can be a challenge for external I / O, a capability required to include high pin-count memories (e.g., low-power double data rate (LPDDR) I / O) in next-generation HBM memory technologies.

[0059] Now for reference Figure 5B A schematic cross-sectional view of an electronic package 500 with a bridging-based solution according to an embodiment is shown. In this embodiment, the electronic package 500 includes a package substrate 510. The package substrate 510 is compatible with... Figure 5A The encapsulation substrate 510 is similar, except for the cavity 502 that can be used to accommodate components 525 (e.g., bridging). In this embodiment, interconnect 506 A Die 505 can be electrically coupled to electrical wiring (not shown) in package substrate 510, and interconnect 506 B This can be used to electrically couple die 505 to component 525. Interconnect 506 A and 506 B They can have different diameters. In some embodiments, an interconnect 529 may be provided between the bottom of component 525 and the bottom of cavity 502 to electrically couple the via 526 of component 525 to electrical wiring within the package substrate 510.

[0060] Regarding, for example, Figure 5BThe illustrated electronic package 500 has a package substrate 510 with a laminated dielectric film (e.g., an organic built-in layer material) applied over a component 525. Due to the type of dielectric material and the variations in thickness and morphology across the dielectric stack including the package substrate 510, this dielectric film is not planarized after lamination. The thickness variations occur both within individual cells (e.g., Figure 5B The variations in Z-axis topography, both locally within the package substrate 510 and globally across the entire panel including the package substrate 510, are significantly greater than typical built-in film thickness and via height tolerances. These Z-position variations result in a higher solder volume required for the interconnects 506 between the die 505 and component 525 and / or between the die 505 and package substrate 510. This higher solder volume increases the CD of the interconnects 506 and limits the reduction in bump pitch. Furthermore, component 525 can be coupled to a pad (not shown) on the bottom surface of cavity 502, which is a buried built-in layer. Due to potential layer-to-layer misalignment, the resulting structure may lead to issues with the interconnects 506. B Positional tolerances in the X and / or Y directions between the component and the through-hole pad.

[0061] Therefore, the embodiments disclosed herein may include structures that can be used to improve the X, Y, and / or Z positioning accuracy of bumps used to couple a structure to component 525 (e.g., bridging). Improved positioning accuracy enables further scaling of bump pitch on existing electronic packaging architectures.

[0062] The embodiments disclosed herein can be used for component integration using panel-level processes with a packaging substrate having an organic core or a glass core. Instead of using a carrier panel (or carrier wafer) with a back redistribution layer (RDL) as used in interposer-based architectures, the embodiments disclosed herein may include conductive pillars provided directly on the final packaging substrate. Components having finely pitched pillars embedded in a molding layer (e.g., bridging dies, passive components, etc.) are also coupled (e.g., via solder interconnects) to the same packaging substrate. The panel including the packaging substrate is then reshaped. The pillars above the packaging substrate and components can then be exposed by a panel polishing process (e.g., CMP). In some embodiments, an optional upper side RDL may be added above the molding layer and pillars prior to solder bumps for providing interconnects to the upper die. Thereafter, the panel can be diced and the upper die attached. While panel-level processes are described herein, some embodiments may also include similar processes implemented at the cell and / or device level.

[0063] Now for reference Figure 6A and 6B The diagram shows a cross-sectional schematic of an electronic package 600 incorporating a molded extension layer according to various embodiments. The molded extension layer can be used to improve the positional accuracy of interconnects and enable interconnect pitch scaling. Figure 6AIn this embodiment, the electronic package 600 includes a package substrate 610. In this embodiment, the package substrate 610 may be similar to any package substrate described in more detail herein. For example, the package substrate may include a glass core or an organic core having an organic dielectric built-in layer above and / or below the core.

[0064] In an embodiment, a molding extension layer 630 may be provided on the surface of the package substrate 610. In an embodiment, the molding extension layer 630 (which may sometimes be referred to as the first molding layer) may include an epoxy material, an organic built-in film (having one or more layers), or any other suitable electrically insulating material. In an embodiment, a first pillar 631 may extend upward from the package substrate 610 through the thickness of the molding layer 630. The first pillar 631 may include any suitable conductive material, such as copper. The first pillar 631 may have substantially vertical sidewalls. The first pillar 631 may be electroplated or otherwise mounted to the package substrate 610 (e.g., by solder, etc.). In an embodiment, the first pillar 631 may be electrically coupled to pads (not shown) on the surface of the package substrate 610.

[0065] In embodiments, component 625 may also be embedded within molding layer 630. Where component 625 has a through-hole 626 extending through at least a portion of its thickness, component 625 may be electrically coupled to pads (not shown) on the surface of package substrate 610 via interconnects 629 (e.g., solder bumps, etc.). In embodiments, component 625 may be a bridge configured to electrically couple dies 605 together. For example, a pair of dies 605 may both at least partially overlap with component 625. However, in other embodiments, component 625 may be located below a single die 605 or outside the occupied area of ​​any die 605. In some embodiments, component 625 may be a passive device, such as a capacitor, inductor, etc. In embodiments, component 625 may include a glass layer, silicon layer, etc.

[0066] like Figure 6A As shown, die 605 (which may include capillary bottom filler 628) can be electrically coupled to post 631 and / or component 625 via interconnect 606. In the illustrated embodiment, interconnect 606 may have substantially uniform dimensions. However, as Figure 6B As shown, the interconnection 606 between the die 605 and the post 631 A It may have a first dimension, and the interconnection 606 between the die 605 and the component 625. B It can have a second (smaller) size that allows for finer spacing connections.

[0067] exist Figure 6A and 6B In the embodiment shown, interconnect 606 A and 606 BDirectly on the molding layer 630. However, in other embodiments, one or more RDLs (not shown) may be provided above the top surface of the molding layer 630. This embodiment may allow for more flexible wiring between the die 605 and the post 631. This embodiment may allow for fine-pitch interconnects 606. A Convert to a more spacious spacing for column 631. When not using RDL, Figure 6B The illustrated embodiment may be easier to manufacture because of the connection between pillar 631 and interconnect 606. A No spacing conversion may be required between them.

[0068] Now for reference Figures 7A to 7H The diagram shows a series of cross-sectional schematic diagrams depicting the process for forming an electronic package 700 having a molded extension layer 730 according to an embodiment. Figures 7A to 7H The process flow shown can produce something similar to Figure 6B The electronic package 600 is an electronic package 700. However, it should be understood that, similar to... Figure 6A The electronic system of the electronic package 600 can be manufactured using similar process operations, especially when an RDL is added above the molded extension layer 730.

[0069] Now for reference Figure 7A The image shows a schematic cross-sectional view of a portion of an electronic package 700 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 700 may include a package substrate 710. The package substrate 710 may include a core 709, such as a glass core or an organic core.

[0070] In the case of glass core 709, glass core 709 can be substantially entirely glass. Glass core 709 can be a solid block comprising a glass material having an amorphous crystalline structure, wherein the solid glass core may also include various structures—such as through holes, cavities, channels, or other features—filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.). Thus, glass core 709 can be distinguished from, for example, a “prepreg” or “FR4” core of a printed circuit board (PCB) substrate, which typically comprises glass fibers embedded in a resin organic material (e.g., epoxy resin).

[0071] The glass core 709 can have any suitable dimensions. In a particular embodiment, the glass core 709 can have a thickness of about 50 µm or greater. For example, the thickness of the glass core 709 can be between about 50 µm and about 1.4 mm. However, smaller or larger thicknesses can also be used. The glass core 709 can have an edge dimension (e.g., length, width, etc.) of about 10 mm or greater. For example, the edge dimension can be between about 10 mm and about 250 mm. However, larger or smaller edge dimensions can also be used. More generally, the area dimensions (from a top view) of the glass core 709 can be between about 10 mm x 10 mm and about 250 mm x 250 mm. In an embodiment, the glass core 709 can have a first side perpendicular to or orthogonal to the second side. In a more general embodiment, the glass core 709 can include a rectangular prism volume having a removed portion (e.g., a through-hole) and filled with other materials (e.g., metal, etc.).

[0072] The glass core 709 may comprise a single monolithic glass layer. In other embodiments, the glass core 709 may comprise two or more discrete glass layers stacked on top of each other. The discrete glass layers may be provided in direct contact with each other, or the discrete glass layers may be mechanically coupled to each other by an adhesive or the like. Each discrete glass layer in the glass core 709 may have a thickness of less than about 50 µm. For example, a discrete glass layer in the glass core 709 may have a thickness between about 25 µm and about 50 µm. However, in some embodiments, the discrete glass layers may have a greater or lesser thickness. As used herein, “about” may refer to a range of values ​​within ten percent of a specified value. For example, about 50 µm may refer to a range between 45 µm and 55 µm.

[0073] The glass core 709 can be any suitable glass formulation that has the necessary mechanical robustness and is compatible with semiconductor packaging manufacturing and assembly processes. For example, the glass core 709 may include aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silica, etc. In some embodiments, the glass core 709 may include one or more additives, such as, but not limited to, Al₂O₃, B₂O₃, MgO, CaO, SrO, BaO, SnO₂, Na₂O, K₂O, SrO, P₂O₃, ZrO₂, Li₂O, Ti, or Zn. More generally, the glass core 709 may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In embodiments, the glass core 709 may contain at least 23 weight percent silicon and at least 26 weight percent oxygen. In some embodiments, the glass core 709 may further contain at least 5 weight percent aluminum.

[0074] In one embodiment, the package substrate 710 may include pads 732. Pads 732 may be provided on the surface of the package substrate 710. In another embodiment, pads 732 may be electrically coupled to electrical wiring (not shown) within the package substrate 710 and / or through the core 709. For example, electrical wiring may include pads, traces, vias, etc.

[0075] Now for reference Figure 7B The diagram illustrates a cross-sectional schematic of an electronic package 700 after pillars 731 have been formed above some pads 732 according to an embodiment. In this embodiment, the pillars 731 may be high aspect ratio features (e.g., a height:width ratio of 3:1 or greater, 5:1 or greater, or 10:1 or greater). The pillars 731 may be formed directly upwards from the pads 732 by electroplating. In other embodiments, the pillars 731 may be discrete structures attached to the pads 732 (e.g., by solder, etc.).

[0076] Now for reference Figure 7C This illustration shows a schematic cross-sectional view of an electronic package 700 after component 725 is coupled to package substrate 710 according to an embodiment. In this embodiment, component 725 may include bridging devices. For example, component 725 may include one or more wiring layers (e.g., represented as a horizontal rectangle) that allow lateral electrical wiring. In this embodiment, component 725 may include pads 734 electrically coupled to pads 732 on package substrate 710 via interconnects 733 (e.g., solder bumps). In this embodiment, component pillars 735 may be electrically coupled to and extend upward from the wiring layers. Component pillars 735 may be embedded in component molding layer 739. Component 725 may be surrounded by pillars 731. However, in other embodiments, component 725 may be outside of pillars 731.

[0077] Although Figure 7C The component 725 shown is a bridge, but embodiments may include any type of component useful to the electronic package 700. For example, component 725 may include passive components (e.g., inductors, capacitors, etc.), memory devices, transistor-based devices, etc. Furthermore, although... Figure 7C A single component 725 is shown, but embodiments may include any number of components 725.

[0078] Now for reference Figure 7D This diagram shows a schematic cross-sectional view of an electronic package 700 after a molding extension layer 730 has been formed over a package substrate 710, according to an embodiment. In this embodiment, the molding extension layer 730 (also referred to as a molding layer) can be formed by any molding process. The molding layer 730 may comprise an epoxy material or any other suitable electrically insulating material. In this embodiment, the molding layer 730 may be formed to a thickness sufficient to completely embed the pillar 731 and the component 725. That is, the top surface of the pillar 731 and the sidewall surfaces of the pillar 731 may be covered by the molding layer 730.

[0079] Now for reference Figure 7E The diagram shows a schematic cross-sectional view of an electronic package 700 after the molding layer 730 has been recessed, according to an embodiment. In this embodiment, the molding layer 730 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the molding layer 730 is recessed such that the top surfaces of the pillars 731 and component pillars 735 are exposed and substantially coplanar with each other. In some embodiments, the recessing process may also recess a portion of the molding layer of component 725. The polishing process may give the molding layer 730 a substantially flat surface. More generally, the flatness of the top surface of the molding layer 730 is flatter than the flatness of the top surface of the package substrate 710. Therefore, Z-height variations that limit pitch scaling are avoided.

[0080] Now for reference Figure 7F The diagram illustrates a schematic cross-sectional view of an electronic package 700 after pads 736 and 737 have been formed over exposed pillars 731 and component pillars 735, respectively, according to an embodiment. In the embodiment, pad 736 can be formed by any suitable plating and / or patterning process. Although the pads are shown as being formed directly on the surface of the molding layer 730, embodiments may also include forming one or more RDLs over the molding layer 730. In some embodiments, pad 736 and component pillar 735 over pillar 731 can be formed by a single photolithography process. Therefore, positional variations in the X and Y directions are substantially eliminated. Consequently, positional variations of pads 736 and 737 in the X, Y, and Z directions are reduced or substantially eliminated. This allows for improved pitch scaling of subsequently formed interconnects. For example, a pitch of 10 µm or less can be achieved in some embodiments.

[0081] Now for reference Figure 7G This figure shows a schematic cross-sectional view of an electronic package 700 after an interconnect 706 has been formed over pad 736 according to an embodiment. In this embodiment, the interconnect 706 may include solder bumps, etc. As shown, the interconnect 706 over pad 736 A It may have a first diameter, and the interconnect 706 above the pad 737. B It may have a second (smaller) diameter. However, in other embodiments, the interconnect 706 A and 706 B They can have basically similar diameters.

[0082] Now for reference Figure 7H This illustrates coupling from die 705 to interconnect 706 according to an embodiment. A and 706 BThe following is a cross-sectional schematic diagram of the electronic package 700. In embodiments, die 705 can be any type of die, such as a processor die, memory die, communication die, etc. In some embodiments, capillary underfill 728 may be provided around and / or below die 705. In the case of panel-level assembly, the panel may be diced into individual cells before die 705 is mounted to package substrate 710.

[0083] Now for reference Figure 7I This illustrates a process flow diagram of process 780 for forming an electronic package with a molded extension layer, according to an embodiment. In this embodiment, process 780 may be related to the above description regarding... Figures 7A to 7H The described processes are similar. In an embodiment, process 780 may begin with operation 781, which includes forming a first pillar on the surface of a substrate. In an embodiment, the first pillar may be a high aspect ratio pillar formed by a process such as electroplating. In an embodiment, the substrate may be an encapsulation substrate (e.g., having an organic core or a glass core).

[0084] In one embodiment, process 780 can proceed to operation 782, which includes mounting components (e.g., chiplets, bridges, etc.) onto the surface of a substrate. In one embodiment, the chiplet includes a second pillar. The second pillar may be embedded in a layer, such as an epoxy molding layer.

[0085] In one embodiment, process 780 can proceed to operation 783, which includes forming a molding layer over the substrate, the molding layer being fully embedded with the first and second pillars. In another embodiment, the molding layer can be an epoxy-based material, a built-in film, etc.

[0086] In one embodiment, process 780 may proceed to operation 784, which includes recessing the molding layer to expose the first and second pillars. For example, a CMP process or similar method may be used to recess the molding layer. In some embodiments, the recessing process may remove portions of the first and / or second pillars. The recessed surface of the molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0087] In one embodiment, process 780 can proceed to operation 785, which includes forming a first pad on the first pillar and a second pad on the second pillar. In another embodiment, the first and second pads can be formed using a single patterning process. Therefore, any positional variations in the X and / or Y directions are substantially eliminated. Eliminating positional variations in the X, Y, and Z directions allows for improved pitch scaling.

[0088] In one embodiment, process 780 can proceed to operation 786, which includes mounting the die to a first pad and a second pad. In another embodiment, the die can be mounted to the first and second pads via interconnects (e.g., solder balls). Due to improved pitch scaling, this embodiment allows for increased interconnect density between the die and the substrate.

[0089] The above text is about Figures 7A to 7I In the described embodiments, the planarization process of the molding layer 730 is performed without addressing any Z-height variations (e.g., warpage, built-in layer thickness variations, etc.) on the bottom surface of the package substrate 710. In some instances, such additional Z-height variations may affect the flatness of the top surface of the molding layer 730. Therefore, some embodiments may also include a bottom molding extension layer above the bottom surface of the package substrate 710. This embodiment can further improve overall flatness and enable further scaling of component interconnects and pillar interconnects. Examples of this embodiment are as follows: Figures 8A to 8I As shown.

[0090] Now for reference Figure 8A This diagram illustrates a cross-sectional schematic of a portion of an electronic package 800 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 800 may include a package substrate 810. The package substrate 810 may include a core 809, such as a glass core or an organic core. In this embodiment, the package substrate 810 may be similar to any package substrate described in more detail herein. For example, due to non-uniform thickness of the package substrate 810, the top and / or bottom surfaces of the package substrate 810 may not be substantially flat. In this embodiment, pads 832 may be formed on the top surface of the package substrate 810, and pads 816 may be formed on the bottom surface of the package substrate 810.

[0091] Now for reference Figure 8B The diagram shows a schematic cross-sectional view of an electronic package 800 after a pillar 814 has been formed on pad 816 according to an embodiment. In this embodiment, the pillar 814 may be a high aspect ratio feature (e.g., a height:width ratio of 3:1 or greater, 5:1 or greater, or 10:1 or greater). The pillar 814 may be formed directly upwards from the pad 816 by electroplating. In other embodiments, the pillar 814 may be a discrete structure attached to the pad 816 (e.g., by solder, etc.).

[0092] Now for reference Figure 8C This diagram illustrates a cross-sectional view of an electronic package 800 after a lower molding extension layer 815 has been formed above the bottom surface of a package substrate 810, according to an embodiment. In this embodiment, the lower molding extension layer 815 (also referred to as the bottom molding layer) can be formed using any molding process. The lower molding layer 815 may comprise an epoxy material or any other suitable electrical insulating material. In this embodiment, the lower molding layer 815 may be formed to a thickness fully embedded in the pillar 814. That is, the bottom surface and sidewall surfaces of the pillar 814 may be covered by the lower molding layer 815.

[0093] Now for reference Figure 8DThe diagram shows a schematic cross-sectional view of an electronic package 800 after the lower molding layer 815 has been recessed according to an embodiment. In this embodiment, the lower molding layer 815 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the lower molding layer 815 is recessed, exposing the top surface of the pillars 814. The polishing process gives the bottom molding layer a substantially flat surface 817. Therefore, variations in Z-height that limit pitch scaling (e.g., due to warpage, variations in the thickness of built-in layers in the package substrate 810, etc.) are avoided.

[0094] Now for reference Figure 8E The diagram shows a cross-sectional schematic of an electronic package 800 after pillars 831 and components 825 are provided above some pads 832 according to an embodiment. In the embodiment, pillar 831 may be similar to pillar 731 described in more detail above, and component 825 may be similar to component 725 described in more detail above. For example, component 825 may be a bridge, a passive device, an active device, etc.

[0095] Now for reference Figure 8F This diagram shows a schematic cross-sectional view of an electronic package 800 after an upper molding extension layer 830 has been formed over a package substrate 810 according to an embodiment. In this embodiment, the upper molding extension layer 830 (also referred to as the upper molding layer) can be formed using any molding process. The upper molding layer 830 may comprise an epoxy material or any other suitable electrical insulating material. In this embodiment, the upper molding layer 830 may be formed to a thickness sufficient to completely embed the pillar 831 and the component 825. That is, the upper surface and sidewall surfaces of the pillar 831 may be covered by the molding layer 830.

[0096] Now for reference Figure 8G This diagram shows a schematic cross-sectional view of an electronic package 800 after the upper molding layer 830 has been recessed according to an embodiment. In this embodiment, the upper molding layer 830 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the upper molding layer 830 is recessed such that the top surfaces of the pillars 831 and the component 825 are exposed and substantially coplanar with each other. In some embodiments, the recessing process may also recess a portion of the molding layer of the component 825. The polishing process can give the upper molding layer 830 a substantially flat surface. Furthermore, since the bottom surface of the lower molding layer 815 is planarized, the overall flatness of the electronic package 800 is improved compared to other embodiments. Therefore, Z-height variations that limit pitch scaling are avoided.

[0097] Now for reference Figure 8HThis diagram illustrates a cross-sectional schematic of an electronic package 800 after pads 836 and 837 have been formed on exposed pillars 831 and 825, respectively, according to an embodiment. In this embodiment, pad 836 can be formed by any suitable electroplating and / or patterning process. Although the pads are shown as being formed directly on the surface of the upper molding layer 830, embodiments may also include forming one or more RDLs above the upper molding layer 830. In some embodiments, pad 836 above pillar 831 and pad 837 above component pillar 825 can be formed by a single photolithography process. Therefore, positional variations in the X and Y directions are substantially eliminated. Thus, positional variations of pads 836 and 837 in the X, Y, and Z directions are eliminated. This allows for improved pitch scaling of subsequently formed interconnects. For example, a pitch of 10 µm or less can be achieved in some embodiments.

[0098] Now for reference Figure 8I The figure shows a schematic cross-sectional view of an electronic package 800 after interconnects 806 are formed on pads 836 and 837, and a die 805 is coupled to interconnects 806, according to an embodiment. In the embodiment, interconnects 806 may include solder bumps, etc. As shown, interconnects 806 are located above pads 836. A It may have a first diameter, and the interconnect 806 above the pad 837. B It may have a second (smaller) diameter. However, in other embodiments, the diameter may be the same.

[0099] In some embodiments, die 805 can be any type of die, such as a processor die, memory die, communication die, etc. In some embodiments, capillary underfill 828 may be provided around and / or below die 805. In the case of panel-level assembly, the panel may be diced into individual cells before die 805 is mounted to the package substrate 810.

[0100] Now for reference Figure 8J This illustrates a process flow diagram of process 880 for forming an electronic package with a molded extension layer, according to an embodiment. In this embodiment, process 880 may be related to the above description regarding... Figures 8A to 8I The described processes are similar. In an embodiment, process 880 may begin with operation 881, which includes forming a first pillar on a pad on a first surface of the substrate. In an embodiment, the first pillar may be a high aspect ratio pillar formed by a process such as electroplating. In an embodiment, the substrate may be an encapsulation substrate (e.g., having an organic core or a glass core).

[0101] In one embodiment, process 880 can proceed to operation 882, which includes forming a first molding layer above a first surface of the substrate. In another embodiment, the first molding layer may be fully embedded with the first pillar.

[0102] In one embodiment, process 880 may proceed to operation 883, which includes recessing the first molding layer to expose the first pillar. For example, a CMP process or similar method may be used to recess the molding layer. In some embodiments, the recessing process may remove a portion of the first pillar. The recessed surface of the molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0103] In one embodiment, process 880 may proceed to operation 884, which includes forming a second pillar on a second surface of the substrate. In another embodiment, the second pillar may be a high aspect ratio pillar formed by a process such as electroplating.

[0104] In one embodiment, process 880 can proceed to operation 885, which includes mounting a component (e.g., a chiplet, a bridge, etc.) to a second surface of the substrate. In another embodiment, the component may include a third pillar. The third pillar may be embedded in a layer, such as an epoxy molding layer.

[0105] In one embodiment, process 880 may proceed to operation 886, which includes forming a second molding layer above the second surface of the substrate, the second molding layer being fully embedded with the second pillar and component. In another embodiment, the second molding layer may be an epoxy-based material, a built-in film, etc.

[0106] In one embodiment, process 880 may proceed to operation 887, which includes recessing the second molding layer to expose the second and third pillars. For example, a CMP process or similar method may be used to recess the second molding layer. In some embodiments, the recessing process may remove portions of the second and / or third pillars. The recessed surface of the molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0107] In one embodiment, process 880 can proceed to operation 888, which includes attaching the die to the second post and the component. In another embodiment, pads can be formed on the second and third posts. In yet another embodiment, the pads can be formed using a single patterning process. Therefore, any positional variations in the X and / or Y directions are substantially eliminated. Elimination of positional variations in the X, Y, and Z directions allows for improved pitch scaling. Due to this improved pitch scaling, the embodiment allows for increased interconnect density between the die and the substrate.

[0108] As described in the embodiments above, a front-side molded extension layer on a conventional package substrate can be used to improve the Z-topology of interconnect bumps. However, the Z-thickness variation across the panel including the package substrate, especially in the case of a package substrate with a high dielectric built-in layer count, can exceed 50 µm. Such a high thickness variation can result in very high pillars (e.g., greater than about 70 µm) requiring fine pitch on the components (e.g., from about 15 µm to about 25 µm pitch). Such a high aspect ratio of the pillars is difficult to manufacture and may also negatively impact the thermal bonding (TCB) of the components to the package substrate due to thermal resistance issues, as a thick molded layer needs to be used above the components to surround the pillars.

[0109] Therefore, embodiments may include a front-side Z-reset molding layer between the molding extension layer and the package substrate to provide a uniform Z-thickness across the entire panel. The front-side Z-reset molding layer enables a molding and polishing process that planarizes the substrate panel before attaching the component to the package substrate. That is, the embodiment allows for improved coplanarity of the component and component pillars. This embodiment can be used to achieve finely pitched pillars on the component. After adding the front-side Z-reset molding layer, a previously disclosed molding extension layer (e.g., a front-side molding extension layer and / or a rear-side molding extension layer) can be added using a process similar to that described in more detail herein. Similarly, according to other embodiments described herein, a rear-side Z-reset molding layer may be combined with a front-side Z-reset molding layer. Various molding material properties of any reset layer and / or extension layer can be tuned to manage the inherent warpage of the package substrate and / or the ultimately assembled electronic package. Examples of processes for forming an electronic package with a Z-reset molding layer are provided in […]. Figures 9A to 9H As shown in the image.

[0110] Now for reference Figure 9A This diagram illustrates a cross-sectional schematic of a portion of an electronic package 900 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 900 may include a package substrate 910. The package substrate 910 may include a core 909, such as a glass core or an organic core. In this embodiment, the package substrate 910 may be similar to any package substrate described in more detail herein. In this embodiment, pads 932 may be formed on the top surface of the package substrate 910.

[0111] Now for reference Figure 9B This illustrates the formation of a pillar 931 above a pad 932 according to an embodiment. A and 931 BThe following is a cross-sectional schematic diagram of the electronic package 900. In an embodiment, the pillar 931 may be a high aspect ratio feature (e.g., a height:width ratio of 3:1 or greater, 5:1 or greater, or 10:1 or greater). The pillar 931 may be formed directly upwards from the pad 932 by electroplating. In other embodiments, the pillar 931 may be a discrete structure attached to the pad 932 (e.g., by solder, etc.). In an embodiment, the pillar 931 A This can be used to electrically couple the packaging substrate 910 to the die above (added in a subsequent process operation), and pillar 931 B This can be used to electrically couple the packaging substrate 910 to a component (added in a subsequent process operation). Pillar 931 A and 931 B They can have different widths. For example, column 931. B It can be compared to column 931 A Narrower.

[0112] Now for reference Figure 9C This diagram shows a schematic cross-sectional view of an electronic package 900 after the Z-reset molding layer 930 is formed over the package substrate 910, according to an embodiment. In this embodiment, the Z-reset molding layer 930 (also referred to as the first molding layer) can be formed by any molding process. The first molding layer 930 may comprise an epoxy material or any other suitable electrically insulating material. In this embodiment, the first molding layer 930 may be formed to the point where the pillars 931 are fully embedded. A and 931 B The thickness. That is to say, column 931. A and 931 B The top surface and column 931 A and 931 B The sidewall surface can be covered by the first molding layer 930.

[0113] Now for reference Figure 9D This diagram shows a schematic cross-sectional view of an electronic package 900 after the first molding layer 930 has been recessed according to an embodiment. In this embodiment, the first molding layer 930 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the first molding layer 930 is recessed such that pillars 931... A and 931 B The top surfaces are exposed and are substantially coplanar with each other. A polishing process allows the first molding layer 930 to have a substantially flat surface.

[0114] Now for reference Figure 9E The following is an illustration of column 931 according to an embodiment. A A cross-sectional schematic diagram of the electronic package 900 after the formation of pillar 939. In the illustrated embodiment, pillar 931... AIt has a width that is approximately equal to the width of column 939. That is to say, column 931... A The combination of column 939 and column 931 may appear as a single continuous structure. However, in other embodiments, column 939 may have a different shape than column 931. A The width of the column. For example, column 939 can be wider than column 931. A Narrower. Furthermore, although Figure 9E The image shows a perfect alignment, but embodiments may include post 939 relative to post 931. A Offset. In an embodiment, post 939 may be formed by an electroplating process or mounted onto post 931. A The top surface (e.g., through solder, etc.).

[0115] Now for reference Figure 9F This illustrates the coupling of component 925 to pillar 931 according to an embodiment. B This is a cross-sectional schematic diagram of the electronic package 900 after the molding extension layer 940 (also referred to as the second molding layer) is formed. In an embodiment, component 925 may include bridging devices. For example, component 925 may include one or more wiring layers (e.g., represented as a horizontal rectangle) that allow lateral electrical wiring. In an embodiment, component 925 may include electrical coupling to pillar 931 via interconnects (e.g., solder bumps). B The pads formed above. The formation of the first molding layer 930 after the recess allows for improved pillar 931. B The Z-position uniformity between the pads above allows for a reduction in spacing, as smaller solder interconnects can be used due to the lower Z-height variation. However, in other embodiments, the interconnect to component 925 can fall directly on post 931. B On top, the pads on the first molding layer 930 can be omitted.

[0116] In one embodiment, the component post 938 may extend upward from the wiring layer, and the component post 938 may be embedded in a molding layer (not shown). In other embodiments, the post 938 may be embedded in a second molding layer 940, rather than a dedicated component molding layer.

[0117] Although Figure 9F The component 925 shown is a bridge, but embodiments may include any type of component useful to the electronic package 900. For example, component 925 may include passive components (e.g., inductors, capacitors, etc.), memory devices, transistor-based devices, etc. Furthermore, although... Figure 9F A single component 925 is shown, but embodiments may include any number of components 925.

[0118] In embodiments, the second molding layer 940 can be formed using any molding process. The second molding layer 940 may comprise an epoxy material or any other suitable electrical insulating material. In embodiments, the second molding layer 940 may be formed to a thickness fully embedded in the pillars 939 and 938. That is, the top surfaces and sidewall surfaces of the pillars 939 and 938 may be covered by the second molding layer 940. In embodiments, the first molding layer 930 and the second molding layer 940 may have similar material compositions. In such embodiments, the first molding layer 930 and the second molding layer 940 may appear as a single layer. However, in other embodiments, the first molding layer 930 and the second molding layer 940 may comprise different material compositions.

[0119] Now for reference Figure 9G The diagram shows a schematic cross-sectional view of an electronic package 900 after the second molding layer 940 has been recessed according to an embodiment. In this embodiment, the second molding layer 940 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the second molding layer 940 is recessed such that the top surfaces of pillars 939 and 938 are exposed and substantially coplanar with each other. The polishing process may give the second molding layer 940 a substantially flat surface.

[0120] Now for reference Figure 9H The interconnect 906 is shown according to an embodiment. A and 906 B Electrically coupled to pillars 939 and 938 respectively, and die 905 coupled to interconnect 906. A and 906 B A subsequent cross-sectional schematic diagram of the electronic package 900. In this embodiment, interconnect 906... A and 906 B This may include solder bumps, etc. As shown in the figure, the interconnect 906 above pillar 939... A It may have a first diameter, and the interconnect 906 above the component post 925. B It may have a second (smaller) diameter. However, in other embodiments, the diameter may be the same.

[0121] In some embodiments, die 905 can be any type of die, such as a processor die, memory die, communication die, etc. In some embodiments, capillary underfill 928 may be provided around and / or below die 905. In the case of panel-level assembly, the panel may be diced into individual cells before die 905 is mounted to the package substrate 910.

[0122] Now for reference Figure 9I This illustrates a process flow diagram of process 980 for forming an electronic package having a Z-reset molding layer and a molding extension layer, according to an embodiment. In this embodiment, process 980 may be related to the above description regarding... Figures 9A to 9H The described processes are similar. In an embodiment, process 980 may begin with operation 981, which includes forming a first pillar on a pad on the surface of a substrate. In an embodiment, the first pillar may be a high aspect ratio pillar formed by a process such as electroplating. In an embodiment, the substrate may be an encapsulation substrate (e.g., having an organic core or a glass core). In some embodiments, the first pillar may include a first subgroup having a first diameter and a second subgroup having a second diameter different from the first diameter.

[0123] In one embodiment, process 980 may proceed to operation 982, which includes forming a first molding layer (e.g., a Z-reset molding layer) over the surface of the substrate, the first molding layer being fully embedded with the first pillar. In another embodiment, the first molding layer may be an epoxy-based material, an embedded film, etc.

[0124] In one embodiment, process 980 may proceed to operation 983, which includes recessing the first molding layer to expose the first pillar. For example, a CMP process or similar method may be used to recess the first molding layer. In some embodiments, the recessing process may remove a portion of the first pillar. The recessed surface of the first molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0125] In one embodiment, process 980 may proceed to operation 984, which includes forming a second pillar above the first subgroup of the first pillar. In another embodiment, the second pillar may have a diameter different from the diameter of the first subgroup of the first pillar, or the second pillar may have a diameter substantially equal to the diameter of the first subgroup of the first pillar.

[0126] In one embodiment, process 980 can proceed to operation 985, which includes mounting components (e.g., chiplets, bridges, etc.) onto the first molding layer. In another embodiment, the component may include a third pillar. The third pillar may be embedded in a layer, such as an epoxy molding layer, or the third pillar may be independent and without surrounding molding layers.

[0127] In one embodiment, process 980 may proceed to operation 986, which includes forming a second molding layer (e.g., a molding extension layer) over the first molding layer, the second molding layer being fully embedded with the second and third pillars. In another embodiment, the second molding layer may be an epoxy-based material, a built-in membrane, etc.

[0128] In one embodiment, process 980 may proceed to operation 987, which includes recessing the second molding layer to expose the second and third pillars. For example, a CMP process or similar method may be used to recess the second molding layer. In some embodiments, the recessing process may remove portions of the second and third pillars. The recessed surface of the second molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0129] In one embodiment, process 980 can proceed to operation 988, which includes electrically coupling the die to a second and third post of the component. For example, the die can be mounted to a first pad above the second post and a second pad above the third post of the component via interconnects (e.g., solder balls). Due to the improved pitch scaling, the embodiment allows for increased interconnect density between the die and the substrate.

[0130] The push for HPC products (such as GPUs and HBM accelerators or data center CPUs) is driving larger chip composite sizes. For example, large package sizes (e.g., 120mm x 120mm) and high substrate layer counts (e.g., twenty or more layers) are becoming increasingly common. This results in low yields and high costs for such advanced substrates. Therefore, depackaging is necessary for these products. One solution for depackaging relies on package-to-package (P2P) interconnect bridging between two adjacent packages. In existing solutions, a top-side P2P bridge with approximately 300µm bump pitch (or BGA ball pitch) is required to provide reasonable bandwidth between packages. However, the corresponding P2P pads on GPU (or CPU) packages present solder attachment issues related to the P2P bridging at such a spacing.

[0131] One issue is the X and Y direction positional tolerances of P2P pads on a given package relative to the motherboard (e.g., BGA pads on the bottom side of the package substrate). For high-layer-count package substrates, the tolerance is currently approximately 100 µm or greater per package substrate. Furthermore, the Z direction positional tolerance of P2P pads between two adjacent package substrates can be greater than approximately 150 µm. These poor X, Y, and Z tolerances of the P2P pads at both ends of the P2P interconnect bridge drive complex P2P bridging configurations. For example, P2P interconnect bridges may need to be flexible, and pin alignment may need to account for the X, Y, and Z direction tolerances. In some embodiments, a weighted reflow process may also be required.

[0132] Therefore, the embodiments disclosed herein may include a package substrate with P2P pads and a molding layer, the molding layer correcting X, Y, and / or Z tolerances to simplify P2P interconnect bridging architectures and bonding solutions. In embodiments, a panel-level back molding layer with embedded pillars can be used to reset the Z height of adjacent packages to a fixed, achievable target value. For example, the pillars and molding layer can be polished to achieve the desired Z height target for the BGA pads. Furthermore, large X and / or Y positional tolerances of BGA pads relative to top-side P2P pads can be improved by correcting their X, Y placement relative to the pillars. Larger BGA pad CDs relative to pillar CDs can achieve X and / or Y positional corrections of approximately 100 µm or more.

[0133] Now for reference Figure 10A first electronic package 1000, according to an embodiment, is shown to be electrically coupled to each other via a P2P bridge 1050. A Second electronic package 1000 B A schematic diagram of the cross-section.

[0134] As shown in the figure, each electronic package contains 1000 A and 1000 B It may include a corresponding molding layer 1015 A and 1015 B The encapsulation substrate 1010. In an embodiment, the molding layer 1015. A and 1015 B The heights can vary. Different heights can be adjusted through a polishing process to achieve a generally equal total height of the packaging substrate 1010. In this embodiment, the molding layer 1015 can be controlled. A and 1015 B The thickness is adjusted to achieve a fixed Z-height target while maintaining a low tolerance of approximately 20µm or less across all substrate panels for a given product. This enables Z-height resetting for all packages within and from panel to panel. In the embodiment, pillar 1014 A and 1014 B It can be embedded in each molding layer 1015 respectively. A and 1015 B middle.

[0135] In this embodiment, BGA pad 1016 A and 1016 B The X and / or Y position tolerances can be corrected by placing BGA pads relative to the top side of the package substrate using P2P pad 1052. Backside BGA pad 1016 A and 1016 B Alignment error correction can be achieved by referring to the top side reference mark 1055. A and 1055 B To implement this, in an embodiment, the P2P pad 1052 may be located between the reference mark 1055 and the edge of the package substrate 1010. In some embodiments, alignment may be implemented by using a data feedforward process and / or by laser-marking features (not shown) on the back side of the package substrate 1010 to transfer the top side position information of the package substrate 1010 to the back side of the package substrate 1010. In some embodiments, the transfer of such alignment features may be completed before the BGA pad photomask is repositioned.

[0136] As shown in the figure, the reference mark is 1055. A and / or 1055 B Compatible with BGA pad 1016 Aand / or 1016 B Shared basic common centerline 1056 A and / or 1056 B In addition, BGA pad 1016 A and / or 1016 B Repositioning may cause BGA pad 1016 A and / or 1016 B Centerline 1056 A and / or 1056 B Corresponding column 1014 A and / or 1014 B Centerline 1057 A and / or 1057 B Offset distances A1 and / or A2.

[0137] In this embodiment, improved X, Y, and / or Z alignment allows for simpler P2P bridge 1050 design and integration. For example, rigid bridges (e.g., silicon, glass, etc.) can be coupled to P2P pads 1052 via solder interconnects 1051, etc. This embodiment allows for scaling of the interconnect pitch 1051, thereby enabling improved electronic packaging 1000. A and 1000 B Data transmission bandwidth between them.

[0138] In an embodiment, one or more dies 1005 may be coupled to each package substrate 1010. In an embodiment, die 1005 may include any type of die, such as a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU), XPU, etc.), a memory die (e.g., HBM), a communication die, etc. Although Figure 10 A pair of dies 1005 are shown on each package substrate 1010, but it should be understood that any number of dies 1005 may be coupled to each package substrate 1010.

[0139] Now for reference Figures 11A to 11D The diagram illustrates a series of cross-sectional schematics depicting a process for forming an electronic package 1100 for P2P interconnects according to an embodiment. The electronic package 1100 includes a molding layer 1115 beneath a package substrate 1110 and precisely aligned BGA pads 1116. In this embodiment, the molding layer 1115 sets the overall thickness of the electronic package 1100 and mitigates thickness variations across the package substrate 1110. The precisely aligned BGA pads 1116 allow for improved X and Y positional tolerances for coupling the package substrate 1110 to the substrate. Consequently, interconnect bridging between electronic packages 1100 can have higher interconnect density and simplified manufacturing and / or assembly processes.

[0140] Now for reference Figure 11A This diagram illustrates a schematic cross-sectional view of an electronic package 1100 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 1100 may include a package substrate 1110. The package substrate 1110 may be similar to any package substrate described in more detail herein. For example, the package substrate 1110 may include a core (e.g., a glass core or an organic core) having an organic dielectric built-in layer above and / or below the core. In this embodiment, P2P pads 1152 may be formed on the top surface of the package substrate 1110. In this embodiment, reference marks 1155 may also be formed on the top surface of the package substrate 1110.

[0141] In one embodiment, pad 1113 may be formed on the bottom surface of package substrate 1110. In another embodiment, pillar 1114 may be electrically coupled to pad 1113. In another embodiment, pillar 1114 may be similar to any pillar described in more detail herein. For example, a pillar may be a high aspect ratio conductive pillar (e.g., a copper pillar) formed or mounted to pad 1113 by electroplating upwards from pad 1113 (e.g., by solder, etc.).

[0142] Now for reference Figure 11B This diagram illustrates a schematic cross-sectional view of an electronic package 1100 after a molding layer 1115 has been formed over a package substrate 1110, according to an embodiment. In this embodiment, the molding layer 1115 can be formed using any molding process. The molding layer 1115 may comprise an epoxy material or any other suitable electrically insulating material. In this embodiment, the molding layer 1115 may be formed to a thickness sufficient to completely embed the pillar 1114. That is, the top surface and sidewall surfaces of the pillar 1114 may be covered by the molding layer 1115.

[0143] Now for reference Figure 11C The diagram shows a schematic cross-sectional view of an electronic package 1100 after the molding layer 1115 has been recessed according to an embodiment. In this embodiment, the molding layer 1115 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the molding layer 1115 is recessed such that the top surfaces of the pillars 1114 are exposed and substantially coplanar with each other. The polishing process allows the molding layer 1115 to have a substantially flat surface and precisely controlled thickness.

[0144] Now for reference Figure 11DThis diagram shows a cross-sectional view of the electronic package 1100 after BGA pads 1116 have been formed above pillar 1114. The width of the BGA pads 1116 may be greater than the width of the reference mark 1155 and / or the P2P pad 1152. In an embodiment, the photolithography process for forming the BGA pads 1116 is informed by the placement position of the reference mark 1155 on the opposite side of the package substrate 1110. In an embodiment, alignment can be implemented by using a data feedforward process and / or by laser marking features (not shown) on the back side of the package substrate 1110 to transfer the top side position information of the package substrate 1110 to the back side of the package substrate 1110. In some embodiments, the transfer of such alignment features can be completed before the BGA pad 1116 photolithography mask is repositioned.

[0145] As shown in the figure, the alignment process brings the centerline 1156 of the reference mark 1155 and the BGA pad 1116 to substantially aligned. For example, the BGA pad 1116 and the reference mark 1155 may have aligned centerlines (e.g., substantially shared centerlines within 20µm of each other). Because the BGA pad 1116 needs to be aligned with the reference mark 1155, the post 1114 and the corresponding BGA pad 1116 may be offset from each other. For example, the centerline 1156 of the BGA pad 1116 may be offset by a distance A from the centerline 1157 of the post 1114.

[0146] Now for reference Figure 11E This illustration shows a process flow diagram depicting process 1180 for forming BGA pads with molded layers and precise alignment to achieve P2P interconnects, according to an embodiment. In this embodiment, process 1180 may proceed to operation 1181, which includes forming pillars on the pads on a first surface of the substrate. In this embodiment, the substrate may be a package substrate similar to any package substrate described in more detail herein. The pillars may be high aspect ratio pillars formed by electroplating upwards from the pads or otherwise coupled to the pads.

[0147] In one embodiment, process 1180 may proceed to operation 1182, which includes forming a molding layer above a first surface of the substrate, the molding layer being fully embedded with the first pillar. In another embodiment, the molding layer may be similar to any molding layer described in more detail herein. For example, the molding layer may include epoxy resin, etc.

[0148] In one embodiment, process 1180 may proceed to operation 1183, which includes recessing the molding layer to expose the pillars. For example, a CMP process or similar method may be used to recess the molding layer. In some embodiments, the recessing process may remove a portion of the pillars. The recessed surface of the molding layer can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated, and / or the total height of the electronic package 1100 can be precisely set.

[0149] In one embodiment, process 1180 may proceed to operation 1184, which includes forming pads on the pillar. In one embodiment, the pillar may be aligned with a reference mark on a second surface of the substrate. In one embodiment, the centerline of the reference mark may be substantially centered with the centerline of one of the pads on the pillar. For example, alignment can be implemented by using a data feedforward process and / or by laser-marking features on a first surface of the package substrate 1110 to transfer positional information of the second surface of the substrate to the first surface of the substrate. In some embodiments, the transfer of such alignment features may be completed before the photolithographic mask used to form the substrate is repositioned. In one embodiment, the pad may be a BGA pad for electrically coupling the substrate to a substrate, etc.

[0150] As in other embodiments herein, bridging-based electronic packages can use a diced packaging substrate for top die assembly. Therefore, the top die is difficult to mold and planarize. This can result in an uneven outer contour of the electronic package. Such a non-planar outer contour can lead to poor thermal contact with the system's thermal solution. In the preceding embodiments, the integration of components (e.g., interconnect bridging) in a panel-level process using molded extension layers has been described. The improved Z-height uniformity from such molded extension layers allows for finer pitch interconnects. However, the outer contour may still be uneven due to variations in die thickness. Therefore, the embodiments disclosed herein can further extend the panel-level process to attach, mold, and planarize the top die. Such processes can allow the molded layer extension to further provide a flat outer contour for the top die. Therefore, the integration of the molding process and / or thermal solution can be improved. Figures 12A to 12H These are examples of embodiments that include such processes.

[0151] Now for reference Figure 12A This illustration shows a schematic cross-sectional view of an electronic package 1200 during the manufacturing stage according to an embodiment. In this embodiment, the electronic package 1200 includes a package substrate 1210. In this embodiment, the package substrate 1210 may be similar to any package substrate described in more detail herein. For example, the package substrate 1210 may include a core 1209 (e.g., a glass core or an organic core) having built-in layers above and / or below the core 1209.

[0152] In an embodiment, the electronic package 1200 may further include a Z-reset molding layer 1230 (which may be referred to herein as a first molding layer). In an embodiment, the first molding layer 1230 may include a first pillar 1231 provided above the pad 1232. A and 1231 B First molding layer 1230 and first pillar 1231 A and 1231 BIt can be formed by a process similar to any process described in more detail herein. For example, a high aspect ratio first pillar 1231 can be formed on pad 1232, a molding layer 1230 can be formed to fully embed the first pillar 1231, and the molding layer 1230 can be recessed to expose the top surface of the first pillar 1231.

[0153] Now for reference Figure 12B A schematic cross-sectional view of an electronic package 1200 after a second pillar 1239 is formed above a first pillar 1231A, according to an embodiment, is shown. In the illustrated embodiment, the first pillar 1231... A It has a width that is approximately equal to the width of the second pillar 1239. That is to say, the first pillar 1231... A The combination of the second column 1239 may appear as a single continuous structure. However, in other embodiments, the second column 1239 may have a different structure than the first column 1231. A The width of the width. For example, the second column 1239 can be wider than the first column 1231. A Narrower. Furthermore, although Figure 12B The image shows a perfect alignment, but embodiments may include post 1239 relative to post 1231. A Offset. In an embodiment, the second post 1239 may be formed by an electroplating process or mounted to the top surface of the first post 1231A (e.g., by solder, etc.).

[0154] Now for reference Figure 12C This illustrates the coupling of component 1225 to the first post 1231 according to an embodiment. B This is a cross-sectional schematic of the electronic package 1200 after the molding extension layer 1240 (also referred to as the second molding layer) is formed. In an embodiment, component 1225 may include bridging devices. For example, component 1225 may include one or more wiring layers (e.g., represented as a horizontal rectangle) that allow lateral electrical wiring. In an embodiment, component 1225 may include components electrically coupled to the first pillar 1231 via interconnects (e.g., solder bumps). B The pads formed above. The formation of the first molding layer 1230 after the recess allows for improvement of the first pillar 1231. B The uniformity of the Z-position between the pads above. Therefore, the interconnect spacing can be reduced because smaller solder interconnects can be used (due to the lower Z-height variation). However, in other embodiments, the interconnect to component 1225 can fall directly on the first post 1231. B On top, the pads on the first molding layer 1230 can be omitted.

[0155] In one embodiment, component post 1238 may extend upward from the wiring layer, and component post 1238 may be embedded in a molding layer (not shown). In other embodiments, component post 1238 may be embedded in a second molding layer 1240, rather than a dedicated component molding layer.

[0156] Although Figure 12C The component 1225 shown is a bridge, but embodiments may include any type of component useful to the electronic package 1200. For example, component 1225 may include passive components (e.g., inductors, capacitors, etc.), memory devices, transistor-based devices, etc. Furthermore, although... Figure 12C A single component 1225 is shown, but embodiments may include any number of components 1225.

[0157] In an embodiment, the second molding layer 1240 can be formed using any molding process. The second molding layer 1240 may comprise an epoxy material or any other suitable electrical insulating material. In an embodiment, the second molding layer 1240 may be formed to a thickness fully embedded in the second pillar 1239 and component pillar 1238. That is, the top surfaces of the second pillar 1239 and component pillar 1238 and the sidewall surfaces of the second pillar 1239 and component pillar 1238 may be covered by the second molding layer 1240. In an embodiment, the first molding layer 1230 and the second molding layer 1240 may have similar material compositions. In this embodiment, the first molding layer 1230 and the second molding layer 1240 may appear as a single layer. However, in other embodiments, the first molding layer 1230 and the second molding layer 1240 may comprise different material compositions.

[0158] Now for reference Figure 12D The diagram shows a schematic cross-sectional view of an electronic package 1200 after the second molding layer 1240 has been recessed according to an embodiment. In this embodiment, the second molding layer 1240 may be recessed by a polishing or grinding process (e.g., CMP process). In this embodiment, the second molding layer 1240 is recessed such that the top surfaces of the second pillar 1239 and the component pillar 1238 are exposed and substantially coplanar with each other. A polishing process may give the second molding layer 1240 a substantially flat surface.

[0159] Now for reference Figure 12E The following is an illustration of die 1205 according to an embodiment. A and 1205 B A cross-sectional view of the electronic package 1200 after being mounted to the second molding layer 1240. For example, pads may be formed on the second pillar 1239 and component pillar 1238, and interconnects 1206 may be formed. A and 1206 B These pads can be electrically coupled to die 1205. A and 1205 BIn this embodiment, the die can be any type of die, such as any type of die described in more detail herein. In this embodiment, die 1205 A and 1205 B They can have different thicknesses. Therefore, at this point in the process flow, the electronic package 1200 does not have a flat outer contour.

[0160] Now for reference Figure 12F This shows the 1205 die. A and 1205 B A cross-sectional schematic diagram of the electronic package 1200 after the formation of the third molding layer 1270. In the illustrated embodiment, the bottom of the molding layer 1270 is filled with a die 1205. A and 1205 B However, in other embodiments, die 1205 can be used. A and 1205 B The lower part provides capillary bottom filler, etc. In an embodiment, the third molding layer 1270 may have a shape that allows the die 1205 to be formed. A and 1205 B The thickness is fully embedded in the third molding layer 1270.

[0161] Now for reference Figure 12G This diagram shows a cross-sectional view of the electronic package 1200 after the third molding layer 1270 has been recessed, according to an embodiment. In this embodiment, the third molding layer 1270 may be recessed using a CMP process or the like. In this embodiment, the recessing process may also result in polishing or grinding of the die 1205. A and 1205 B The back surface of the die 1205 is planarized. Therefore, the outer contour of the electronic package 1200 is flattened. This allows for improved thermal control, as thermal solutions can be provided in conjunction with the die 1205. A and 1205 B Better thermal coupling.

[0162] Now for reference Figure 12H A schematic cross-sectional view of an electronic package 1200 according to an additional embodiment is shown. As shown in the figure, Figure 12H The electronic package 1200 can be used with Figure 12G Similar to the electronic package 1200, except that the first molding layer 1230 is removed. As shown, the second molding layer 1240 can be formed directly above the top surface of the package substrate 1210. That is, there may be no pillars between the component 1225 and the package substrate 1210.

[0163] Now for reference Figure 12IA flowchart of process 1280 for forming an electronic system with a planarized die encapsulation layer to improve the flatness of the outer contour, according to an embodiment, is shown. In the embodiment, process 1280 may be related to the above description... Figures 12A to 12H The described processes are similar. In an embodiment, process 1280 may begin with operation 1281, which includes forming a first pillar on the surface of a substrate. In an embodiment, the pillar may be a high aspect ratio pillar formed by a process such as electroplating. In an embodiment, the substrate may be an encapsulation substrate (e.g., having an organic core or a glass core).

[0164] In one embodiment, process 1280 may proceed to operation 1282, which includes mounting components (e.g., chiplets, bridges, etc.) onto the surface of a substrate. In another embodiment, the components may include component pillars. Component pillars may be embedded in a layer, such as an epoxy molding layer.

[0165] In one embodiment, process 1280 may proceed to operation 1283, which includes forming a first molding layer over the substrate, the first molding layer being fully embedded with pillars and component pillars. In another embodiment, the first molding layer may be an epoxy-based material, an embedded film, or the like.

[0166] In one embodiment, process 1280 may proceed to operation 1284, which includes recessing the first molding layer to expose the pillars and component pillars. For example, a CMP process or similar method may be used to recess the first molding layer. In some embodiments, the recessing process may remove portions of the pillars and / or component pillars. The surface of the first molding layer after recessing can be substantially flat. Therefore, any Z-height variation of the substrate can be substantially eliminated.

[0167] In one embodiment, process 1280 can proceed to operation 1285, which includes attaching the die to the posts and component posts. In another embodiment, pads can be formed on the posts and component posts using a single patterning process. Therefore, any positional variations in the X and / or Y directions are substantially eliminated. Eliminating positional variations in the X, Y, and Z directions allows for improved pitch scaling. In another embodiment, interconnects can electrically couple the die to the posts and component posts.

[0168] In one embodiment, process 1280 can proceed to operation 1286, which includes forming a second molding layer over the first molding layer. In another embodiment, a die is embedded in the second molding layer. The second molding layer may be similar to the first molding layer. However, in other embodiments, the first and second molding layers may use different materials.

[0169] In one embodiment, process 1280 may proceed to operation 1287, which includes recessing the second molding layer to expose the back side of the die. In another embodiment, the recessed back side may include the use of a CMP process, etc. In the case of multiple dies, the dies may be planarized to have substantially flat surfaces, which is advantageous for thermally coupling the dies to a heatsink or other temperature control system.

[0170] As described in the various embodiments herein, the process flow for manufacturing various electronic packages can be implemented at the panel level, quarter panel level, cell level, etc. For example, the various molding layers described herein can be formed at a larger form factor (e.g., panel form factor). Figure 13 This is a schematic plan view of a panel 1390 that can be used to form multiple electronic packages 1300.

[0171] exist Figure 13 In this embodiment, multiple electronic packages 1300 are arranged across panel 1390. In one embodiment, the individual electronic packages 1300 may be spaced apart from each other by cutaways or the like. In another embodiment, the individual electronic packages 1300 may be similar to any electronic package described more specifically herein. In another embodiment, the electronic packages 1300 may be formed on a common packaging substrate having the form factor of panel 1390. The common packaging substrate may be similar to any packaging substrate described more specifically herein. For example, the packaging substrate may include a glass core or an organic core having a dielectric built-in layer above and / or below the core. In another embodiment, one or more molded layers having embedded conductive pillars may be provided above and / or below the common packaging substrate.

[0172] As shown in the figure, in each electronic package 1300, one or more dies 1305 A and 1305 B It can be electrically coupled to a common package substrate. In some embodiments, component 1325 may be embedded in one or more dies 1305. A and 1305 B In the underlying molded layer. In the illustrated embodiment, component 1325 may include a die 1305 A and 1305 B Bridge tube cores electrically coupled together.

[0173] Now for reference Figure 14This diagram illustrates a cross-sectional schematic of an electronic system 1495 according to an embodiment. In this embodiment, the electronic system 1495 may include an electronic package 1400 electrically coupled to a board 1496 (e.g., a motherboard, printed circuit board (PCB), etc.) via interconnects 1497 (e.g., BGA solder balls). In this embodiment, the electronic package 1400 may be similar to any electronic package disclosed in more detail herein. For example, the electronic package 1400 may include a package substrate 1410 having a core 1409 and one or more molding layers 1430 having embedded pillars 1431. Components 1425 may also be embedded within the molding layers 1430. Components 1425 may be embedded via interconnects (e.g., solder balls) and / or via pillars embedded in the molding layers 1430. Figure 14 (Not shown in the image) Electrically coupled to the packaging substrate 1410.

[0174] In an embodiment, one or more dies 1405 A and 1405 B 1406 can be interconnected A and / or 1406 B Electrically coupled to post 1431 and / or component 1425. Capillary bottom filler 1428 may surround the die 1405. A and / or 1405 B In some embodiments, the molding layer (not shown) may also embed the die 1405. A and / or 1405 B This is to provide a flat outer contour for the electronic system 1495.

[0175] Figure 15 A computing device 1500 according to one embodiment of the present disclosure is shown. The computing device 1500 houses a board 1502. The board 1502 may include multiple components, including but not limited to a processor 1504 and at least one communication chip 1506. The processor 1504 is physically and electrically coupled to the board 1502. In some embodiments, at least one communication chip 1506 is also physically and electrically coupled to the board 1502. In a further embodiment, the communication chip 1506 is part of the processor 1504.

[0176] These other components include, but are not limited to: volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, encryption processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, optical disc (CD), digital versatile optical disc (DVD), etc.).

[0177] Communication chip 1506 implements wireless communication for transmitting data to and from computing device 1500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that can communicate data using modulated electromagnetic radiation over a non-solid medium. This term does not imply that the associated device does not contain any wires, although they may be absent in some embodiments. Communication chip 1506 can implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. Computing device 1500 may include multiple communication chips 1506. For example, the first communication chip 1506 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 1506 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0178] The processor 1504 of computing device 1500 includes an integrated circuit die packaged within the processor 1504. In some embodiments of this disclosure, the processor's integrated circuit die may be part of an electronic packaging system that includes a packaging substrate having one or more molded layers with embedded pillars according to embodiments herein to provide a flat surface for enhanced pitch scaling. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0179] The communication chip 1506 also includes an integrated circuit die packaged within the communication chip 1506. According to another embodiment of this disclosure, the integrated circuit die of the communication chip may be part of an electronic packaging system comprising a packaging substrate having one or more molded layers with embedded pillars, according to embodiments herein, to provide a flat surface for enhanced pitch scaling.

[0180] In this embodiment, computing device 1500 can be part of any device. For example, computing device can be part of a personal computer, server, mobile device, tablet computer, automobile, etc. That is, computing device 1500 is not limited to any particular type of system, and computing device 1500 can be included in any device that can benefit from computing capabilities.

[0181] The foregoing description of illustrative embodiments of this disclosure, including the description in the abstract, is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications can be made within the scope of this disclosure, as will be recognized by those skilled in the art.

[0182] These modifications may be made to this disclosure based on the above detailed description. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of this disclosure should be fully defined by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

[0183] Example: Example 1: An apparatus comprising: a substrate having a first surface and a second surface opposite to the first surface; a first pillar on the first surface of the substrate; a second pillar on the first surface of the substrate; a first layer above the first surface of the substrate, wherein the first layer has the first pillar and the second pillar embedded therein; a third pillar on the second pillar; a component above the first layer, wherein the component is coupled to the second pillar; and a second layer above the first layer, wherein the second layer has the third pillar and the component embedded therein.

[0184] Example 2: According to the apparatus of Example 1, the component includes: a wiring layer; and a plurality of fourth posts above the wiring layer, wherein the second layer is embedded with the plurality of fourth posts.

[0185] Example 3: According to the apparatus of Example 2, the surface of the third pillar is substantially coplanar with the surface of at least one of the plurality of fourth pillars.

[0186] Example 4: The apparatus according to Example 2 or Example 3 further includes: a first die coupled to a first fourth post among a third post and a plurality of fourth posts; and a second die coupled to a second fourth post among a plurality of fourth posts.

[0187] Example 5: According to the apparatus of Example 4, the wiring layer couples the first die to the second die.

[0188] Example 6: The apparatus according to Examples 1-5, wherein the first layer and the second layer are molded layers.

[0189] Example 7: The apparatus according to Examples 1-6, wherein the substrate comprises: a core; and an organic dielectric layer above the core.

[0190] Example 8: The apparatus according to Example 7, wherein the core includes a glass layer.

[0191] Example 9: The apparatus according to Examples 1-8, wherein the component is a passive component.

[0192] Example 10: The apparatus according to Examples 1-9, wherein the component is coupled to the second post via solder bumps.

[0193] Example 11: A method comprising: forming a plurality of first pillars on a first surface of a substrate; forming a first molding layer over the substrate, wherein the first molding layer has the plurality of first pillars embedded therein; recessing the first molding layer to expose the plurality of first pillars; forming a plurality of second pillars on respective first pillars of the plurality of first pillars; attaching a component to the first molding layer; forming a second molding layer over the first molding layer, wherein the second molding layer has the plurality of second pillars and the component embedded therein; recessing the second molding layer to expose the plurality of second pillars; and attaching a die to the second molding layer, wherein the die is coupled to the plurality of second pillars and the component.

[0194] Example 12: According to the method of Example 11, the component includes: a plurality of third pillars, wherein the second molding layer is embedded with the plurality of third pillars.

[0195] Example 13: According to the method of Example 12, the die is coupled to the component through a plurality of third posts.

[0196] Example 14: According to the method of Examples 11-13, wherein the first molding layer and the second molding layer contain substantially similar material compositions.

[0197] Example 15: According to the method of Examples 11-14, the component includes a wiring layer.

[0198] Example 16: Following the method of Examples 11-15, where the component is a passive component.

[0199] Example 17: According to the method of Examples 11-16, wherein the substrate is a panel-level substrate, and wherein multiple devices are fabricated substantially in parallel on the panel-level substrate.

[0200] Example 18: An apparatus comprising: a plate; an encapsulation substrate coupled to the plate, wherein the encapsulation substrate includes: a substrate; a first plurality of pillars above a surface of the substrate; a first molding layer surrounding the first plurality of pillars; a second plurality of pillars on the first plurality of pillars; a component on the first molding layer; and a second molding layer surrounding the second plurality of pillars and the component; and a die coupled to the encapsulation substrate, wherein the die is coupled to at least one of the first plurality of pillars.

[0201] Example 19: The apparatus according to Example 18, wherein the component is coupled to the die.

[0202] Example 20: The apparatus according to Example 19 further includes: a second die coupled to a packaging substrate and coupled to a component, wherein the component couples the die to the second die.

Claims

1. An apparatus comprising: A substrate having a first surface and a second surface opposite to the first surface; A first pillar is located on the first surface of the substrate; A second pillar is located on the first surface of the substrate; A first layer is situated above the first surface of the substrate, wherein the first layer has the first pillar and the second pillar embedded therein; The third pillar is located on top of the second pillar; Components, located above the first layer, wherein said components are coupled to the second pillar; and The second layer is located above the first layer, wherein the third column and the component are embedded in the second layer.

2. The apparatus according to claim 1, wherein, The component includes: Wiring layer; and A plurality of fourth posts are located above the wiring layer, and wherein the second layer is embedded with the plurality of fourth posts.

3. The apparatus according to claim 2, wherein, The surface of the third pillar is substantially coplanar with the surface of at least one of the plurality of fourth pillars.

4. The apparatus according to claim 2, further comprising: A first die, which is coupled to the third post and the first fourth post of the plurality of fourth posts; as well as The second die is coupled to the second fourth post of the plurality of fourth posts.

5. The apparatus according to claim 4, wherein, The wiring layer couples the first die to the second die.

6. The apparatus according to claim 1, 2 or 3, wherein, The first layer and the second layer are molded layers.

7. The apparatus according to claim 1, 2 or 3, wherein, The substrate includes: Core; and An organic dielectric layer is located above the core.

8. The apparatus according to claim 7, wherein, The core includes a glass layer.

9. The apparatus according to claim 1, 2 or 3, wherein, The component is a passive component.

10. The apparatus according to claim 1, 2 or 3, wherein, The component is coupled to the second post via solder bumps.

11. A method comprising: Multiple first pillars are formed on the first surface of the substrate; A first molding layer is formed over the substrate, wherein the first molding layer has the plurality of first pillars embedded therein; The first molding layer is recessed to expose the plurality of first pillars; A plurality of second columns are formed on a corresponding first column among the plurality of first columns; Attach the component to the first molding layer; A second molding layer is formed above the first molding layer, wherein the second molding layer embeds the plurality of second pillars and the component; The second molding layer is recessed to expose the plurality of second pillars; and The die is attached to the second molding layer, wherein the die is coupled to the plurality of second posts and the component.

12. The method according to claim 11, wherein, The component includes: Multiple third pillars, wherein the second molding layer has the multiple third pillars embedded therein.

13. The method according to claim 12, wherein, The die is coupled to the component via the plurality of third posts.

14. The method according to claim 11, 12 or 13, wherein, The first molding layer and the second molding layer have substantially similar material compositions.

15. The method according to claim 11, 12 or 13, wherein, The component includes a wiring layer.

16. The method according to claim 11, 12 or 13, wherein, The component is a passive component.

17. The method according to claim 11, 12 or 13, wherein, The substrate is a panel-level substrate, and multiple devices are fabricated substantially in parallel on the panel-level substrate.

18. An apparatus comprising: plate; An encapsulation substrate coupled to the plate, wherein the encapsulation substrate comprises: Substrate; The first plurality of pillars are located above the surface of the substrate; A first molding layer surrounds the first plurality of pillars; The second plurality of columns are located on the first plurality of columns; Components, which are on the first molding layer; and A second molding layer surrounds the second plurality of pillars and the component; and A die coupled to the packaging substrate, wherein the die is coupled to at least one of the first plurality of pillars.

19. The apparatus according to claim 18, wherein, The component is coupled to the die.

20. The apparatus of claim 19, further comprising: A second die is coupled to the packaging substrate and to the component, wherein the component couples the die to the second die.

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