Semiconductor device and method for manufacturing semiconductor device
Patent Information
- Application Number
- CN202511223157.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-19
- Filing Date
- 2025-08-29
- Publication Date
- 2026-09-29
Smart Images
Figure CN122847232A_ABST
Abstract
Description
Technical Field
[0001] This embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] In semiconductor packaging, multiple chips are sometimes stacked by bonding them together. Summary of the Invention
[0003] Semiconductor devices and methods for manufacturing semiconductor devices that provide improved reliability of chip bonding.
[0004] The semiconductor device of this embodiment includes: a first semiconductor element having a first dummy pattern and a first active pattern on its surface; and a second semiconductor element having a second dummy pattern on its surface facing the first dummy pattern and bonded to the first semiconductor element. The first dummy pattern includes a first region. The second dummy pattern includes a second region. The first region and the second region face each other. The size of the first region is larger than the average area of the pads included in the first active pattern. The pattern coverage of the first region is different from that of the second region. Attached Figure Description
[0005] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.
[0006] Figure 2 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0007] Figure 3 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0008] Figure 4 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0009] Figure 5 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0010] Figure 6 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0011] Figure 7 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0012] Figure 8 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0013] Figure 9 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0014] Figure 10 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0015] Figure 11 These are schematic diagrams of the first and second dummy patterns of the implementation method.
[0016] Figure 12 This is a schematic cross-sectional view of the first semiconductor element in the first dummy pattern portion and the second semiconductor element in the second dummy pattern portion of the embodiment.
[0017] Figure 13 This is a schematic cross-sectional view of the first semiconductor element in the first dummy pattern portion and the second semiconductor element in the second dummy pattern portion of the embodiment.
[0018] Figure 14 This is a schematic cross-sectional view of the first semiconductor element in the first dummy pattern portion and the second semiconductor element in the second dummy pattern portion of the embodiment.
[0019] Figure 15 This is a schematic diagram of the surfaces of the first semiconductor element and the second semiconductor element in the embodiment.
[0020] Figure 16 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment.
[0021] Figure 17 This is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment.
[0022] Figure 18 This is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment.
[0023] Figure 19 This is a schematic diagram of a method for manufacturing a semiconductor device according to an implementation method.
[0024] Figure 20 This is a schematic diagram of a method for manufacturing a semiconductor device according to an implementation method.
[0025] Figure 21 This is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment.
[0026] Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.
[0027] Figure 23 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.
[0028] Label Explanation
[0029] 1: First semiconductor element
[0030] 1A: 1st substrate
[0031] 2: Second semiconductor element
[0032] 2A: Second substrate
[0033] 3: First dummy pattern
[0034] 3A: Area 1
[0035] 3B: Area 3
[0036] 3C: Zone 5
[0037] 3D: Area 7
[0038] 4: Second dummy pattern
[0039] 4A: Area 2
[0040] 4B: Area 4
[0041] 4C: Region 6
[0042] 4D: Area 8
[0043] 5: Solder pads
[0044] 6: Solder pads
[0045] 7: Solder pads
[0046] 8: Solder pads
[0047] 9: Solder pads
[0048] 10: Solder pads
[0049] 11: First insulating film
[0050] 12: Second insulating film
[0051] 20: First valid pattern
[0052] 21: Second valid pattern
[0053] 25: Insulating film
[0054] 26: Wiring layer
[0055] 40: First semiconductor layer
[0056] 41: First wiring layer
[0057] 42: First Insulation Layer
[0058] 43: First electrode layer
[0059] 50: Second semiconductor layer
[0060] 51: Second wiring layer
[0061] 52: Second Insulation Layer
[0062] 53: Second electrode layer
[0063] 61: Contact plug
[0064] 62: Word Line Wiring Layer
[0065] 63: Contact plug
[0066] 64: Back gate wiring layer
[0067] 65: Contact plug
[0068] 66: Select the gate wiring layer
[0069] 67: Plug
[0070] 69: Interlayer insulation layer
[0071] 73: Memory-side wiring layer
[0072] 74a: Bonding metal
[0073] 74b: Joining metal
[0074] 76: Circuit-side wiring layer
[0075] 77: Transistor
[0076] 78: Gate electrode
[0077] 79: Plug
[0078] 80: Interlayer insulation layer
[0079] 96: Stepped structure section
[0080] 100: Semiconductor devices
[0081] 200: Semiconductor devices
[0082] BG: Back gate
[0083] BL: Bitline
[0084] CL: columnar part
[0085] RDL: Rerouting Layer
[0086] SG: Select Gate
[0087] SL: Source Line
[0088] W1: First Chip
[0089] W2: Second Chip
[0090] WL: Electrode layer Detailed Implementation
[0091] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0092] This embodiment is not intended to limit the invention. The accompanying drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, the same reference numerals are used for elements that are described with respect to the parts already shown in the drawings, and detailed descriptions are omitted where appropriate.
[0093] (First Embodiment)
[0094] The first embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device. Figure 1 This is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a first semiconductor element 1 and a second semiconductor element 2. The first semiconductor element 1 and the second semiconductor element 2 are connected, for example, by means of electrodes such as Cu provided on the surface of the first semiconductor element 1 facing the second semiconductor element 2 and electrodes such as Cu provided on the surface of the second semiconductor element 2 facing the first semiconductor element 1, without the use of bumps. The first semiconductor element 1 and the second semiconductor element 2 are in contact.
[0095] Figure 1 The figure shows three directions: X, Y, and Z. The XY plane of the first semiconductor element 1 and the XY plane of the second semiconductor element 2 are stacked in the Z direction. The X, Y, and Z directions of the figure indicate the orientation and positional relationship of the cross-section.
[0096] The first semiconductor element 1 and the second semiconductor element 2 have different circuit configurations. The first semiconductor element 1 and the second semiconductor element 2 are different types of elements, therefore the junction of the first semiconductor element 1 and the second semiconductor element 2 is called a hybrid junction.
[0097] A pad or solder ball is provided on the side opposite to the bonding surface of the first semiconductor element 1 or the second semiconductor element 2, which can be electrically connected to external passive or / or active components.
[0098] Semiconductor device 100 is, for example, a memory device or a computing device. The computing device may also include a memory device.
[0099] Semiconductor device 100 is preferably a storage device. The type of storage device in semiconductor device 100 is not limited; for example, it can be a non-volatile memory chip or a volatile memory chip. As a non-volatile memory chip, NAND flash memory chips, magnetoresistive variable memory chips, resistive variable memory chips, and phase-change memory chips are preferred, for example. As a volatile memory chip, examples include DDR (Double Data Rate) memory, HBM (High Bandwidth Memory), and GDDR (Graphics Double Data Rate) memory, as well as DRAM (Dynamic Random Access Memory).
[0100] The type of computing device in the semiconductor device 100 is not limited, such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array), etc.
[0101] The first semiconductor element 1 has a first dummy pattern 3. The first dummy pattern 3 may not be electrically connected to a first circuit element included in the first semiconductor element 1. The first circuit element includes transistors, etc. The first dummy pattern 3 includes, for example, a pad made of a conductive component such as Cu or Al. The first circuit element is electrically connected to a first active pattern 20. The first semiconductor element 1 includes, for example, a first semiconductor layer containing the first circuit element and a first wiring layer containing the first dummy pattern 3 and the first active pattern 20.
[0102] The second semiconductor element 2 has a second dummy pattern 4. The second dummy pattern 4 is not electrically connected to a second circuit element contained in the second semiconductor element 2. The second circuit element includes transistors, etc. The second dummy pattern 4 includes, for example, a pad made of a conductive component such as Cu or Al. A portion of the second dummy pattern 4 is preferably electrically connected to the first dummy pattern 3. The second circuit element is electrically connected to the second active pattern 21. The second semiconductor element 2 includes, for example, a second semiconductor layer containing the second circuit element and a second wiring layer containing the second dummy pattern 4 and the second active pattern 21. The semiconductor device 100 is a semiconductor device formed by connecting the first wiring layer of the first semiconductor element 1 and the second wiring layer of the second semiconductor element 2 towards each other.
[0103] The first dummy pattern 3 and the second dummy pattern 4 are facing each other.
[0104] The area of the first valid pattern 20 includes multiple pads. These pads are conductive, such as Cu or Al. The pads in the first valid pattern 20 are electrically connected to the pads in the second valid pattern 21. The first valid pattern 20 is not electrically connected to the first dummy pattern 3 or the second dummy pattern 4.
[0105] The area of the second valid pattern 21 contains multiple pads. The multiple pads contained in the second valid pattern 21 are conductive pads such as Cu or Al. The second valid pattern 21 is not electrically connected to the first dummy pattern 3 and the second dummy pattern 4.
[0106] The size of the region of the first dummy pattern 3 is preferably approximately the same as the size of the region of the second dummy pattern 4. The size of the region of the first dummy pattern 3 is preferably 90% or more and 110% or less of the size of the region of the second dummy pattern 4, more preferably 95% or more and 105% or less, and even more preferably 98% or more and 102% or less.
[0107] Figure 2 The diagram shows a first dummy pattern 3 and a second dummy pattern 4. The first dummy pattern 3 includes a first region 3A as a marked region. The second dummy pattern 4 includes a second region 4A as a marked region. Figure 2 The dashed lines of the second dummy pattern 4 indicate the outer perimeter of the second region 4A. Figure 2 In the schematic diagram, the outer perimeters of region 3A (1) and region 4A (2) are common. Region 3A (1) and region 4A (2) face each other. Figure 2 The underlined A, B, C and D indicate the positions shared with the first dummy pattern 3 in the second dummy pattern 4.
[0108] Figure 2 The schematic diagram shows the location of the second region 4A of the second dummy pattern 4, which overlaps with the first dummy pattern 3. Additionally, Figure 2 The schematic diagram shows the position of the first region 3A of the first dummy pattern 3, which overlaps with the second dummy pattern 4. That is, the schematic diagram of the first dummy pattern 3 shows the position of the second region 4A, which is opposite to the first region 3A. Furthermore, the schematic diagram of the second dummy pattern 4 shows the position of the first region 3A, which is opposite to the second region 4A.
[0109] exist Figure 2The schematic diagram shows that a circular pad 5 is provided in the first region 3A, and the area outside the first region 3A also includes regular dummy pattern areas (e.g., non-marked areas) with pads 6 of the same size arranged regularly. The pattern in the first region 3A is different from the regular dummy pattern areas. Even if the first dummy pattern 3 is not present, there is no obstacle to the operation of the first semiconductor device 1. However, if the first dummy pattern 3 is not present, it becomes a large convex surface, which may sometimes become a three-dimensional obstacle during bonding. Therefore, it is preferable to have the first dummy pattern 3, and it is preferable to set the first dummy pattern 3 as the reference position for positioning when forming the wiring layer of the first semiconductor device 1.
[0110] The size of the first region 3A is preferably larger than the average area of the pads contained in the first effective pattern 20.
[0111] The size of the first region 3A is preferably larger than the average area of the pads included in the first dummy pattern 3, excluding the marking area.
[0112] The size of the first region 3A is preferably larger than the maximum area of the pads contained in the first effective pattern 20.
[0113] The shape of the pads 5 within region 1 3A is selected from one or more of the following shapes: circular, elliptical, quadrilateral, polygonal, and cross-shaped, or similar to these shapes. There are more than one pad 5 within region 1 3A, and each pad is arranged separately and / or connected to ground. The pads 5 within region 1 3A are arranged in a full-film or high-density manner.
[0114] When the shape of the pad 5 in the first region 3A is a circle, an ellipse, a rounded polygon, or a circled shape, a portion of the outer periphery of the pad 5 can be joined with the pad 7 in the second region 4A or the pad contained in the region directly adjacent to the second region 4A.
[0115] Region 3A exists at any position in the first dummy pattern 3.
[0116] exist Figure 2 The schematic diagram shows that region 4A contains a pattern composed of multiple pads 7, and the area outside region 4A also includes regular dummy pattern areas (e.g., non-marked areas) with pads 8 of the same size arranged regularly. The pattern in region 4A is different from the regular dummy pattern areas.
[0117] The shape of pad 7 in region 2, 4A, is selected from one or more of the following shapes: circular, elliptical, quadrilateral, polygonal, and cross-shaped, or similar. There is one or more pads 5 in region 1, 3A, which are arranged separately and / or connected to ground. No pads 7 are configured in region 2, 4A, or the pads 7 are configured at a lower density compared to region 1, 3A.
[0118] Region 4A exists at any position in the second dummy pattern 4.
[0119] A marked region is a region with irregular pad patterns relative to a regular dummy pattern region. A marked region is a region with pads of the same shape (or substantially the same shape) arranged at equal (or substantially equal) intervals within a regular dummy pattern region. The boundaries of regions within the marked region (e.g., region 3A, region 4A) are obtained by dividing the region based on the characteristics of the pad patterns. Using regions with high pattern coverage as a reference, portions opposite to regions with high pattern coverage can be designated as paired regions, for example, region 4A relative to region 3A. The marked region can be divided into multiple regions based on characteristics such as the shape and density of the patterns.
[0120] The pattern coverage of region 3A is preferably different from that of region 4A. Pattern coverage refers to the area ratio of a pattern formed by a conductive component such as Cu on the surface of the first semiconductor element 1 or the second semiconductor element 2. Pattern coverage is not evaluated in a small area, but rather, for example, in a region containing two pads horizontally and two pads vertically within a regularly defined dummy pattern area. Figure 2 Using the rectangular area enclosed by the double-dotted long dashed line as a reference, the pattern coverage rate can be calculated, and its average value can be set as the pattern coverage rate. Alternatively, based on the patterns of the first dummy pattern 3 and the second dummy pattern 4, the region can be divided into marked and unmarked regions to calculate the pattern coverage rate for each region. For example, by detecting the edges of the pads, the regularity of the pattern's shape, arrangement, and density can be evaluated based on the edges to divide the region into multiple regions.
[0121] exist Figure 2 The outer periphery of region 3A (first region) and region 4A (second region) in the schematic diagram has areas without pads. The areas without pads are common to both the first dummy pattern 3 and the second dummy pattern 4, and the pattern coverage is zero. Therefore, the areas without pads can be considered as regular dummy pattern areas of the first dummy pattern 3 and the second dummy pattern 4.
[0122] The pattern coverage of region 3A is preferably higher than that of region 4A. The pattern coverage of region 4A is preferably 0% or more and 80% or less of the pattern coverage of region 3A, more preferably 0% or more and 50% or less of the pattern coverage of region 3A, and even more preferably 0% or more and 20% or less of the pattern coverage of region 3A.
[0123] The pattern coverage of the first region 3A is preferably higher than the overall pattern coverage of the first dummy pattern 3. The pattern coverage of the first region 3A is preferably 120% or more of the overall pattern coverage of the first dummy pattern 3, more preferably 150% or more of the overall pattern coverage of the first dummy pattern 3, and even more preferably 200% or more of the overall pattern coverage of the first dummy pattern 3.
[0124] The pattern coverage of the second region 4A is preferably different from the overall pattern coverage of the second dummy pattern 4. The pattern coverage of the second region 4A is preferably lower than the overall pattern coverage of the second dummy pattern 4. The pattern coverage of the second region 4A is preferably 80% or less of the overall pattern coverage of the second dummy pattern 4, more preferably 50% or less, and even more preferably 20% or less.
[0125] When the surface of the first semiconductor element 1 is subjected to CMP (Chemical Mechanical Polishing), the surface of the first region 3A with high pattern coverage is easily removed. The first region 3A is preferably concave. The surface of the first region 3A relative to the first effective pattern 20 is preferably concave.
[0126] When CMP is performed on the surface of the second semiconductor element 2, the surface of the second region 4A with low pattern coverage is not easily removed. It becomes a convex surface. The second region 4A is preferably a convex surface. The surface of the second region 4A relative to the second effective pattern 21 is preferably a convex surface.
[0127] The first dummy pattern 3 is, for example, a mark indicating a reference position when forming the wiring layer on the surface of the first semiconductor element 1. The second dummy pattern 4 is a mark indicating a reference position when forming the wiring layer on the surface of the second semiconductor element 2. Most of these marks are formed by large pads, but large pads are easier to polish with CMP than the SiO2 insulating film surrounding them, making them prone to becoming concave. When both opposing surfaces are concave, gaps in the bonding surfaces are easily created. Conversely, if both surfaces are convex, bonding becomes difficult. Therefore, by setting the mark on the wiring layer of the surface of the first semiconductor element 1 to be concave and the mark on the wiring layer of the surface of the second semiconductor element 2 to be convex, and by having the convex surface opposite to the concave surface enter the gap of the concave surface, the function of the mark and the generation of gaps in the bonding surfaces can be achieved.
[0128] Preferably, the volume of the protruding portion of the convex surface of the second region 4A is larger than the volume of the gap of the concave surface of the first region 3A. The volume of the gap of the concave surface of the first region 3A is preferably 50% or more and 80% or less, more preferably 80% or more and 90% or less, and even more preferably 90% or more and 100% or less.
[0129] exist Figure 2 In the schematic diagram, the marked pattern consists of one region, but the marked pattern can also consist of multiple regions. When the first semiconductor element 1 contains two or more regions with high pattern coverage, and when the second semiconductor element 2 contains one or more regions with high pattern coverage, it is preferable that each of the regions with high pattern coverage faces a region with low pattern coverage.
[0130] The pattern coverage of the regular dummy pattern area of the first dummy pattern 3 is preferably 0% or more and 50% or less, more preferably 10% or more and 40% or less, and even more preferably 20% or more and 30% or less. The flatness of the regular dummy pattern area of the first dummy pattern 3 is preferably higher than that of the first region 3A.
[0131] The pattern coverage of the regular dummy pattern area of the second dummy pattern 4 is preferably 0% or more and 50% or less, more preferably 10% or more and 40% or less, and even more preferably 20% or more and 30% or less. The flatness of the regular dummy pattern area of the second dummy pattern 4 is preferably higher than that of the second region 4A.
[0132] The patterns in region 3A and region 4A are different, and preferably the pattern in region 3A is not similar to the pattern in region 4A.
[0133] like Figure 2As shown in the schematic diagram, the pattern in region 3A is composed of a single circular pad, and the pattern in region 4A is composed of multiple rectangular pads.
[0134] exist Figures 3 to 11 The schematic diagram shows the first dummy pattern 3 and the second dummy pattern 4. Figures 3 to 11 The schematic diagram is Figure 2 A variation of the schematic diagram.
[0135] Figure 3 In the schematic diagram shown, in the first dummy pattern 3 of the first semiconductor element 1, a full-area pad 5 is provided in a rectangular shape in the first region 3A. In the second region 4A of the second dummy pattern 4 of the second semiconductor element 2, no pad 7 is provided. The first region 3A with high pattern coverage is opposite to the second region 4A with low pattern coverage. Figure 3 The schematic diagram illustrates an example where the difference in pattern coverage between region 1 (3A) and region 2 (4A) is significant.
[0136] When the pad 5 in the first region 3A is polygonal, two or more portions including the corners of the pad 5, preferably three or more portions including the corners of the pad 5, and more preferably four or more portions including the corners of the pad 5, are bonded to the pad 7 contained in the second region 4A or the pad contained in the region directly adjacent to the second region 4A.
[0137] Figure 4 In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 with a full-surface film is circularly arranged in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage where pads 7 are densely arranged. A portion of the pads 7 or a portion of the pads within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A.
[0138] Alternatively, region 3B could be a region with a higher pattern coverage than region 1A, and region 4B could be a region with a lower pattern coverage than region 2A.
[0139] Figure 5In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 of the entire film is arranged in a ring shape in the first region 3A. The third region 3B is a region where small pads 9 are arranged at low density, and the pattern coverage of the third region 3B is lower than that of the first region 3A and lower than that of the fourth region 4B. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage where large pads 7 are arranged at high density. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A and the pads 9 of the third region 3B.
[0140] Figure 6 In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 of the entire film is circularly arranged in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage where small pads 7 are densely arranged. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A.
[0141] Figure 7 In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 of the entire film is circularly arranged in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with a full film and high pattern coverage. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A. The marking area of the first dummy pattern 3 has a pattern that is the reverse of the pattern of the marking area of the second dummy pattern 4.
[0142] Figure 8In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 with a full-surface film is provided in a circular pattern in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage where pads 7 are arranged in a grid pattern. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A.
[0143] When the pattern coverage in region 3B is low, the pattern coverage, etc., is the same as that in region 2A. Furthermore, when a dummy pattern with low pattern coverage, not electrically connected to the first circuit element and / or the second circuit element, is included in the first dummy pattern 3 and / or the second dummy pattern 4, the coverage, size, relative size relationship to the opposing region with high pattern coverage, pad shape, and surface roughness of the dummy pattern with low pattern coverage are the same as those in region 2A.
[0144] When the pattern coverage in region 4B is high, the pattern coverage and other parameters are the same as those in region 1A. Furthermore, when a dummy pattern with high pattern coverage but not electrically connected to the first circuit element and / or the second circuit element is included in the first dummy pattern 3 and / or the second dummy pattern 4, the coverage, size, relative size relationship to the opposite region with low pattern coverage, pad shape, and surface roughness of the dummy pattern with low pattern coverage are the same as those in region 1A.
[0145] In the case of including region 3A, region 4A, region 3B, and region 4B, for the first dummy pattern 3 of the first semiconductor element 1, region 3A is concave and region 3B surrounding the concave surface has a convex surface. That is, the surface of the first dummy pattern 3 has a concave surface and a continuous convex surface surrounding the concave surface. Similarly, for the second dummy pattern 4 of the second semiconductor element 2, region 4A is convex and region 4B surrounding the convex surface is concave. That is, the surface of the second dummy pattern 4 has a convex surface and a continuous concave surface surrounding the convex surface. In this case, the convex and concave surfaces face each other, with the convex surface entering the concave surface. The same concave or convex surface may also exist on the outer periphery of region 3B and region 4B, respectively.
[0146] Figure 9 In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 of a full-surface film without a specific shape is provided in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage where small pads 7 are arranged in a grid pattern. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A.
[0147] Figure 10In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage, a third region 3B with low pattern coverage outside the first region 3A, a fifth region 3C with high pattern coverage outside the third region 3B, and a seventh region 3D with low pattern coverage outside the fifth region 3C. A circular pad 5 is provided in the first region 3A. The third region 3B is a region without pads. The fifth region 3C is a region with an annular pad 9. The seventh region 3D is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage, and a fourth region 4B with high pattern coverage, a sixth region 4C with low pattern coverage, and an eighth region 4D with high pattern coverage outside the second region 4A. The second region 4A is a region without pads. The fourth region 4B is a region with high pattern coverage and an annular pad 7. Region 6, 4C, is an area without pads. Region 8, 4D, is an area with square-shaped annular pads 10. Region 1, 3A, and Region 2, 4A are opposite each other. Region 3, 3B, and Region 4B are opposite each other. Region 5, 3C, and Region 6, 4C are opposite each other. Region 7, 3D, and Region 8, 4D are opposite each other.
[0148] Figure 11 In the schematic diagram shown, the first dummy pattern 3 of the first semiconductor element 1 includes a first region 3A with high pattern coverage and a third region 3B with low pattern coverage outside the first region 3A. A pad 5 with a full-surface film is provided in a cross shape in the first region 3A. The third region 3B is a region without pads. The second dummy pattern 4 of the second semiconductor element 2 includes a second region 4A with low pattern coverage and a fourth region 4B with high pattern coverage outside the second region 4A. The second region 4A is a region with pads 7 with low pattern coverage. A portion of the pads 7 within the second dummy pattern 4 can be bonded to the pads 5 of the first region 3A.
[0149] Next, the cross-section of the faces of the first dummy pattern 3 and the second dummy pattern 4 facing each other will be described. Figure 12 The diagram shows a schematic cross-sectional view of a first semiconductor element 1 with a portion of a first dummy pattern 3 and a second semiconductor element 2 with a portion of a second dummy pattern 4. The first region 3A of the first dummy pattern 3 of the first semiconductor element 1 is concave due to its high pattern coverage. The regular dummy pattern regions of the first dummy pattern 3 are flat relative to the concave surface. The second region 4A of the second dummy pattern 4 of the second semiconductor element 2 is convex due to its low pattern coverage. The regular pattern regions of the second dummy pattern 4 are flat relative to the convex surface.
[0150] From the viewpoint of suppressing the situation that hinders the bonding of the mating surfaces by the gap between the convex surface and the concave surface, when the semiconductor device 100 includes a first insulating film 11 and a second insulating film 12, the area of the first region 3A is preferably 150% or more and 200% or less of the area of the second region 4A, more preferably 120% or more and 150% or less of the area of the second region 4A, and even more preferably 100% or more and 120% or less of the area of the second region 4A.
[0151] exist Figure 12 In the schematic diagram, the opposing surfaces of the first dummy pattern 3 and the second dummy pattern 4 separate, and the convex surface of the second region 4A enters the concave surface of the first region 3A. The surfaces of the first dummy pattern 3 and the second dummy pattern 4 can also be... Figure 13 The first semiconductor element 1 of the first dummy pattern 3 and the second semiconductor element 2 of the second dummy pattern 4 are connected as shown in the schematic diagram.
[0152] In addition, such as Figure 14 As shown in the schematic diagram of the first semiconductor element 1 with the first dummy pattern 3 and the second semiconductor element 2 with the second dummy pattern 4, a first insulating film 11 may be provided on the surface of the first semiconductor element 1 including the surface of the first dummy pattern 3, and a second insulating film 12 may be provided on the surface of the second semiconductor element 2 including the surface of the second dummy pattern 4. When the first insulating film 11 is provided on the surface where the first dummy pattern 3 is provided, the first dummy pattern 3 is not provided on the outermost surface of the first semiconductor element 1. When the second insulating film 12 is provided on the surface where the second dummy pattern 4 is provided, the second dummy pattern 4 is not provided on the outermost surface of the second semiconductor element 2.
[0153] The first insulating film 11 on the first dummy pattern 3 has a concave surface corresponding to the first region 3A, and the second insulating film 12 on the second dummy pattern 4 has a convex surface corresponding to the second region 4A. Furthermore, the generation of gaps in the bonding surface can be suppressed by the convex surface of the second insulating film 12, which faces the concave surface, entering the gap of the concave surface of the first insulating film 11.
[0154] Alignment marks (not shown) may also be provided on the surfaces of the first insulating film 11 and the second insulating film 12. The alignment marks are preferably smaller than the pattern areas of the first dummy pattern 3 and the second dummy pattern 4. The alignment marks may include, for example, pairs of marks representing nested structures not included in the first dummy pattern 3 and the second dummy pattern 4 of the embodiment.
[0155] Next, refer to Figure 15A schematic diagram of the surfaces of the first semiconductor element 1 and the second semiconductor element 2 is provided, illustrating the positions of the first dummy pattern 3 and the second dummy pattern 4. The first semiconductor element 1 is electrically connected to a first circuit element contained within the first semiconductor element 1, outside of the first dummy pattern 3.
[0156] exist Figure 15 In the schematic diagram, the first dummy pattern 3 and the second dummy pattern 4 are disposed on the outer periphery of the first semiconductor element 1 and the second semiconductor element 2, preferably at the corner periphery. The first dummy pattern 3 and the second dummy pattern 4 may also be disposed on the center side of the first semiconductor element 1 and the second semiconductor element 2.
[0157] The first semiconductor element 1 has one or more first dummy patterns 3. When two or more first dummy patterns 3 are provided on the first semiconductor element 1, the first dummy patterns 3 may have the same pattern shape or different pattern shapes. The first dummy pattern 3 is preferably provided at a position opposite to the surface where the second dummy pattern 4 is provided.
[0158] The second semiconductor element 2 has one or more second dummy patterns 4. When two or more second dummy patterns 4 are provided on the second semiconductor element 2, the second dummy patterns 4 may have the same pattern shape or different pattern shapes.
[0159] Next, the manufacturing method of the semiconductor device 100 will be described. The manufacturing method of the semiconductor device 100 also applies to the description of the semiconductor device 100. Figure 16 The flowchart illustrates a method for manufacturing a semiconductor device 100. The method includes: forming a first wiring layer on a first semiconductor layer having a first dummy pattern 3 and a first active pattern 20 electrically connected to the first circuit element; performing CMP processing on the first wiring layer to obtain a first semiconductor element; forming a second wiring layer on a second semiconductor layer having a second circuit element having a second wiring layer having a second dummy pattern 4 and a second active pattern 21 electrically connected to the second circuit element; performing CMP processing on the second wiring layer to obtain a second semiconductor element 2; and bonding the first semiconductor element 1 and the second semiconductor element 2 to bond the pads of the first active pattern 20 and the pads of the second active pattern 21.
[0160] Reference Figures 17-21 A schematic diagram of a method for manufacturing a semiconductor device 100 is provided to illustrate the method for manufacturing the semiconductor device 100.
[0161] Reference Figure 17The schematic diagram related to the manufacturing method of the semiconductor device 100 describes the process of forming a first wiring layer 41 containing a first dummy pattern 3 and a first effective pattern 20 electrically connected to the first circuit element on a first semiconductor layer 40 on which the first circuit element is formed. Figure 17 The schematic diagram mainly shows either the first dummy pattern 3 or the second dummy pattern 4. A first insulating layer 42, such as SiO2, is formed on the first semiconductor layer 40 where the first circuit element is formed. A first electrode layer 43, containing the first dummy pattern 3 and the first effective pattern 20, is formed at the opening, resulting in a component with a first wiring layer 41 formed on the first semiconductor layer 40. The first electrode layer 43 may also be provided up to the depth of the first semiconductor layer 40.
[0162] Next, refer to Figure 18 A schematic diagram of a method for manufacturing a semiconductor device 100 illustrates the process of obtaining a first semiconductor element 1 by performing CMP processing on the first wiring layer. The CMP process... Figure 17 The first electrode layer 43 of the component in the schematic diagram is polished until the surface of the first insulating layer 42 is removed, resulting in... Figure 18 The component is shown in the schematic diagram. Because a pad with high pattern coverage is provided in part of the first region 3A, part of the first region 3A becomes concave relative to other surfaces, such as the surface of the first effective pattern 20.
[0163] Reference Figure 19 The schematic diagram of a method for manufacturing a semiconductor device 100 illustrates the process of forming a second wiring layer 51, including a second dummy pattern 4 and a second active pattern 21 electrically connected to the second circuit element, on a second semiconductor layer 50 on which the second circuit element is formed. A second insulating layer 52, such as SiO2, is formed on the second semiconductor layer 50 on which the second circuit element is formed, and a second electrode layer 53, containing the second dummy pattern 4 and the second active pattern 21, is formed at the opening to obtain a component having a second wiring layer 51 formed on the second semiconductor layer 50. The second electrode layer 53 can be provided up to the depth of the second semiconductor layer 50.
[0164] Next, refer to Figure 20 A schematic diagram of a method for manufacturing a semiconductor device 100 illustrates the process of obtaining a second semiconductor element 2 by performing CMP processing on a second wiring layer. The CMP process... Figure 19 The second electrode layer 53 of the component in the schematic diagram is polished until the surface of the second insulating layer 52 is removed, resulting in... Figure 20 The component is shown in the schematic diagram. Because a pad with high pattern coverage is provided in part of the second region 4A, part of the second region 4A becomes a convex surface relative to other surfaces, such as the surface of the second effective pattern 21.
[0165] Next, refer to Figure 21 A schematic diagram of a method for manufacturing a semiconductor device 100 illustrates the process of bonding a first semiconductor element 1 and a second semiconductor element 2 to join the pads of a first effective pattern 20 and a second effective pattern 21. Figure 18 The schematic diagram shows the first semiconductor element 1 and Figure 20 The second semiconductor element 2 is attached to the schematic diagram. The pads of the first effective pattern 20 and the second effective pattern 21 are directly joined without using solder or the like. The first semiconductor element 1 and the second semiconductor element 2 are joined by facing the concave surface of the first region 3A and the convex surface of the second region 4A, thereby suppressing the situation where the first dummy pattern 3 and the second dummy pattern 4 hinder the joining of the first effective pattern 20 and the second effective pattern 21.
[0166] Furthermore, before the process of bonding the first effective pattern 20 and the second effective pattern 21 by bonding the first semiconductor element 1 and the second semiconductor element 2, a first insulating film 11 is provided on the surface of the first semiconductor element 1 where the first dummy pattern 3 is provided, and a second insulating film 12 is provided on the surface of the second semiconductor element 2 where the second dummy pattern 4 is provided, and then the first semiconductor element 1 and the second semiconductor element 2 are bonded together, it is possible to obtain... Figure 22 The schematic cross-sectional view of the semiconductor device 100 is shown.
[0167] (Second Implementation)
[0168] The second embodiment relates to a semiconductor device. Figure 23 The diagram shows a schematic cross-sectional view of the semiconductor device 200. Figure 23 The schematic cross-sectional view shows the main portion of a region of the semiconductor device 200. The semiconductor device 200 is a specific example of the semiconductor device 100 and an example of a memory device. The semiconductor device 200 includes a first semiconductor element 1, a second semiconductor element 2, and a redistribution layer RDL. The configuration of the semiconductor device 200 will be described below, but the specific example of the semiconductor device 100 is not limited to a memory device.
[0169] The first semiconductor element 1 includes a first substrate 1A and a first semiconductor layer 40. The first semiconductor layer 40 is disposed on the surface of the first substrate 1A facing the second semiconductor layer 50. The first semiconductor element 1 is an element obtained by monolithically processing a first wafer W1. The first substrate 1A is, for example, a Si substrate. The first semiconductor layer 40 includes a memory cell array containing a plurality of memory cells. A stepped structure portion 96 of an electrode layer WL is formed at the end of the memory cell array region in which the plurality of memory cells are disposed.
[0170] The second semiconductor element 2 includes a second substrate 2A and a second semiconductor layer 50. The second semiconductor layer 50 is formed on the circuit forming surface (the surface facing the first semiconductor layer 40) of the second substrate 2A. The second semiconductor element 2 is an element obtained by monolithically processing a second wafer. The second substrate 2A is, for example, a Si substrate. The second semiconductor layer 50 includes control circuitry for controlling the reading, writing, and erasing of memory cells. The memory cell array has multiple memory strings. The memory cell array has a stack of multiple layers, consisting of alternating electrode layers WL and insulating layers. This stack is disposed on a back gate BG, which serves as a gate layer. Furthermore, the number of electrode layers WL shown in the figure is an example, and the number of electrode layers WL is arbitrary.
[0171] The back gate (BG) and electrode layer (WL) are layers containing silicon as the main component. Furthermore, the back gate (BG) and electrode layer (WL) may contain, for example, boron as an impurity to impart conductivity to the silicon layer. Additionally, the electrode layer (WL) may also contain metal silicides.
[0172] A memory string is formed, for example, in a U-shape, having a pair of columnar portions CL extending in the stacking direction of the electrode layer WL and a connecting portion connecting the ends of the pair of columnar portions CL. The columnar portions CL are formed, for example, in a cylindrical or elliptical cylindrical shape, penetrating the stack to reach the back gate BG.
[0173] In a U-shaped memory string, a drain-side select gate is provided at the upper end of one of a pair of columnar portions CL, and a source-side select gate is provided at the upper end of the other portion. The drain-side select gate and the source-side select gate are disposed on the uppermost electrode layer WL via an interlayer insulating layer.
[0174] In the stepped structure section 96, the X-direction ends of each electrode layer WL are formed in a stepped shape. Multiple contact plugs 61 are provided in the stepped structure section 96 to connect with the stepped electrode layers WL. The contact plugs 61 penetrate the interlayer insulating layer 69 and connect to the stepped electrode layers WL.
[0175] Additionally, in the stepped structure section 96, the back gate BG is connected to the contact plug 63. The select gate SG (drain-side select gate, source-side select gate) is connected to the contact plug 65.
[0176] Contact plug 61, which is connected to electrode layer WL, is connected to word line wiring layer 62. Contact plug 63, which is connected to back gate BG, is connected to back gate wiring layer 64. Contact plug 65, which is connected to select gate SG, is connected to select gate wiring layer 66.
[0177] The word line routing layer 62, the back gate routing layer 64, and the select gate routing layer 66 are disposed on the same layer. In addition, the source lines (not shown) are also disposed on the same layer as the word line routing layer 62, the back gate routing layer 64, and the select gate routing layer 66.
[0178] The word line wiring layer 62, the back gate wiring layer 64, the select gate wiring layer 66, and the source line SL are formed by a pattern of the same material layer (e.g., a metal layer). Therefore, the word line wiring layer 62, the back gate wiring layer 64, the select gate wiring layer 66, and the source line SL are formed simultaneously in the same layer with the same material and the same thickness.
[0179] The word line wiring layer 62 is also connected to the surface wiring layer 73 formed on the junction side of the first semiconductor layer 40 and the second semiconductor layer 50 via other plugs and / or wiring layers.
[0180] The back gate wiring layer 64, the select gate wiring layer 66, and the source line SL are also connected to the surface wiring layer 73 via other plugs and / or wiring layers.
[0181] In addition, the channel body of the columnar portion CL and the bit line BL are connected via plug 67, and the bit line BL is connected to the surface wiring layer 73 via other plugs and / or wiring layers.
[0182] The first semiconductor element 1 has a memory-side wiring layer for electrically connecting the memory cell array to the second semiconductor element 2. The memory-side wiring layer is formed as a multilayer wiring including the aforementioned word line wiring layer 62, back gate wiring layer 64, select gate wiring layer 66, surface wiring layer 73, etc.
[0183] The surface wiring layer 73 is connected to the circuit-side wiring layer 76 of the second semiconductor device 2 via bonding metals 74a and 74b. The second semiconductor device 2 includes a second substrate 2A. The second substrate 2A is, for example, a silicon substrate.
[0184] The control circuit of the second semiconductor layer 50 is formed as a semiconductor integrated circuit including a transistor 77. The transistor 77 has, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure having a gate electrode 78, source / drain regions, etc. The source / drain regions of the MOSFET are connected to the circuit-side wiring layer 76 via plugs 79.
[0185] The circuit-side wiring layer 76 is formed as a multilayer wiring layer on the circuit formation surface via the interlayer insulating layer 80.
[0186] Bonding metals 74a and 74b are provided between the surface wiring layer 73 of the first semiconductor layer 40 and the wiring layer 76 of the circuit-side wiring layer 76 of the second semiconductor layer 50, which is closest to the first semiconductor layer 40. Bonding metals 74a and 74b are, for example, copper or a copper alloy containing copper as a main component. Bonding metals 74a and 74b are formed by annealing the bonding metals of each wafer during the bonding of the first wafer W1 and the second wafer W2. Before the wafers are bonded, a first insulating layer 42, a second insulating layer 52, and bonding metals 74a and 74b are respectively provided on the first wafer W1 and the second wafer W2.
[0187] The surface wiring layer 73 of the first semiconductor layer 40 and the uppermost circuit-side wiring layer 76 of the second semiconductor layer 50 are bonded to bonding metals 74a and 74b. A first insulating layer 42 and a second insulating layer 52 are disposed between the first semiconductor layer 40 and the second semiconductor layer 50, surrounding the bonding metals 74a and 74b. The first insulating layer 42 and the second insulating layer 52 are, for example, inorganic films formed by CMP polishing.
[0188] The first semiconductor element 1 and the second semiconductor element 2 are bonded together via bonding metals 74a and 74b, the first insulating layer 42, and the second insulating layer 52. The memory-side wiring layer 73 of the first semiconductor layer 40 and the circuit-side wiring layer 76 of the second semiconductor layer 50 are electrically connected via bonding metals 74a and 74b.
[0189] Therefore, the memory cell array is connected to the control circuit of the second semiconductor layer 50 via the memory-side wiring layer 73, bonding metals 74a and 74b, and circuit-side wiring layer 76.
[0190] Furthermore, according to an embodiment, a redistribution layer RDL, including an insulating film 25 and a wiring layer 26, is provided on the first substrate 1A side. The redistribution layer RDL is electrically connected to the first semiconductor layer 40 and / or the second semiconductor layer. The wiring layer 26 has pads (not shown) on the surface side of the semiconductor device 100 that are capable of being electrically connected to an external source. For example, the redistribution layer RDL is connected to the first semiconductor layer 40 and / or the second semiconductor layer via a through electrode (not shown) penetrating the first substrate 1A.
[0191] A plurality of bonding metals 74a and 74b are disposed at the junction between the first semiconductor layer 40 and the second semiconductor layer 50. The plurality of bonding metals 74a and 74b mainly include a plurality of bit line leads 74a electrically connected to the bit line BL and a plurality of word line leads 74b electrically connected to the electrode layer WL.
[0192] Bit line lead-out portion 74a is disposed in a region that overlaps with a memory cell array region in the stacking direction.
[0193] The word line lead-out portion 74b is disposed in a region that overlaps with a region in the stacking direction that has a stepped structure portion 96, etc., located on the outer side of the memory cell array region. Figure 1 In the middle, multiple word line leads 74b are arranged in the area below the stepped structure section 96 and in the area to the lower right of the stepped structure section 96.
[0194] The bonding metal (bit line lead-out portion) 74a and the bonding metal (word line lead-out portion) 74b are metals obtained by bonding the first effective pattern 20 and the second effective pattern 21.
[0195] The first dummy pattern 3 is electrically insulated from the first circuit element formed on the first semiconductor layer 40, and is coupled to the second dummy pattern 4, which is electrically insulated from the second circuit element formed on the second semiconductor layer 50.
[0196] The technical solution of the invention is described below.
[0197] Technical Solution 1
[0198] A semiconductor device comprising:
[0199] A first semiconductor device includes a first dummy pattern and a first active pattern on its surface; and
[0200] The second semiconductor element has a second dummy pattern on its surface that faces the first dummy pattern and is bonded to the first semiconductor element.
[0201] The first dummy pattern includes a first region.
[0202] The second dummy pattern includes a second region.
[0203] The first region and the second region are opposite to each other.
[0204] The size of the first region is larger than the average area of the pads contained in the first effective pattern.
[0205] The pattern coverage of the first region is different from that of the second region.
[0206] Technical Solution 2
[0207] The semiconductor device according to technical solution 1
[0208] The pattern coverage of the second region is more than 0% and less than 80% of the pattern coverage of the first region.
[0209] Technical Solution 3
[0210] The semiconductor device according to technical solution 1 or 2
[0211] The pattern coverage of the second region is more than 0% and less than 20% of the pattern coverage of the first region.
[0212] Technical Solution 4
[0213] The semiconductor device according to any one of technical solutions 1 to 3
[0214] The pattern coverage of the first region is higher than that of the second region.
[0215] The pattern coverage of the first region is above 20% and below 100%.
[0216] The pattern coverage of the second region is above 0% and below 50%.
[0217] Technical Solution 5
[0218] The semiconductor device according to any one of technical solutions 1 to 4
[0219] The pattern coverage of the first region is higher than the overall pattern coverage of the first dummy pattern.
[0220] The pattern coverage of the second region is lower than the overall pattern coverage of the second dummy pattern.
[0221] Technical Solution 6
[0222] The semiconductor device according to any one of technical solutions 1 to 5
[0223] The first region is a concave surface.
[0224] The second region is a convex surface.
[0225] Technical Solution 7
[0226] The semiconductor device according to any one of technical solutions 1 to 6
[0227] The first region is a concave surface.
[0228] The second region is a convex surface.
[0229] The convex surface, which is opposite to the concave surface, enters the gap of the concave surface.
[0230] Technical Solution 8
[0231] The semiconductor device according to technical solution 6 or 7
[0232] A first insulating film is provided on the first dummy pattern.
[0233] A second insulating film is provided on the second dummy pattern.
[0234] The first insulating film on the first dummy pattern has a concave surface corresponding to the first region.
[0235] The second insulating film on the second dummy pattern has a convex surface corresponding to the second region.
[0236] The convex surface of the second insulating film, which is opposite to the concave surface of the first insulating film, enters the gap of the concave surface of the first insulating film.
[0237] Technical Solution 9
[0238] The semiconductor device according to any one of technical solutions 1 to 8
[0239] The first dummy pattern is not electrically connected to the circuit elements within the first semiconductor element.
[0240] The second dummy pattern is not electrically connected to the circuit elements within the second semiconductor element.
[0241] Technical Solution 10
[0242] The semiconductor device according to any one of technical solutions 1 to 9
[0243] The first region is provided with solder pads either on a whole surface or at a high density.
[0244] The second region has no pads or has pads with a lower density compared to the first region.
[0245] Technical Solution 11
[0246] The semiconductor device according to any one of technical solutions 1 to 10
[0247] Pads are configured in the first region.
[0248] Pads are provided in the second region.
[0249] The pads in the first region are bonded to a portion of the pads in the second region.
[0250] Technical Solution 12
[0251] The semiconductor device according to any one of technical solutions 1 to 11
[0252] The outer region of the first region includes a third region with low pattern coverage.
[0253] A fourth region with high pattern coverage is located outside the second region.
[0254] The third region is opposite to the fourth region.
[0255] Technical Solution 13
[0256] The semiconductor device according to any one of technical solutions 1 to 12
[0257] Pads are provided in the third region.
[0258] Pads are provided in the fourth region.
[0259] The pads in the third region are bonded to a portion of the pads in the fourth region.
[0260] Technical Solution 14
[0261] A method for manufacturing a semiconductor device includes:
[0262] The process of forming a first wiring layer including a first dummy pattern and a first effective pattern electrically connected to the first circuit element in a first semiconductor layer where a first circuit element is formed;
[0263] The process of performing CMP processing on the first wiring layer to obtain the first semiconductor device;
[0264] The process of forming a second wiring layer including a second dummy pattern and a second valid pattern electrically connected to the second circuit element in a second semiconductor layer where the second circuit element is formed;
[0265] The process of performing CMP processing on the second wiring layer to obtain the second semiconductor device; and
[0266] The process of bonding the first semiconductor element and the second semiconductor element to join the pads of the first effective pattern and the second effective pattern.
[0267] The first region contained in the first dummy pattern and the second region contained in the second dummy pattern are opposite to each other.
[0268] The size of the first region is larger than the average area of the pads contained in the first effective pattern.
[0269] The pattern coverage of the first region is different from that of the second region.
[0270] Technical Solution 15
[0271] The method for manufacturing a semiconductor device according to technical solution 14
[0272] The surface of the first region relative to the first effective pattern is concave.
[0273] The surface of the second region relative to the second effective pattern is convex.
[0274] The concave surface of the first region and the convex surface of the second region face each other.
[0275] Technical Solution 16
[0276] The method for manufacturing a semiconductor device according to technical solution 14 or 15
[0277] The pattern coverage of the second region is more than 0% and less than 80% of the pattern coverage of the first region.
[0278] Technical Solution 17
[0279] The method for manufacturing a semiconductor device according to any one of technical solutions 14 to 16
[0280] The pattern coverage of the second region is more than 0% and less than 20% of the pattern coverage of the first region.
[0281] Technical Solution 18
[0282] The method for manufacturing a semiconductor device according to any one of technical solutions 14 to 17
[0283] The pattern coverage of the first region is above 20% and below 100%.
[0284] The pattern coverage of the second region is above 0% and below 50%.
[0285] Technical Solution 19
[0286] The method for manufacturing a semiconductor device according to any one of technical solutions 14 to 18
[0287] The pattern coverage of the first region is higher than the overall pattern coverage of the first dummy pattern.
[0288] The pattern coverage of the second region is lower than the overall pattern coverage of the second dummy pattern.
[0289] Technical Solution 20
[0290] The method for manufacturing a semiconductor device according to any one of technical solutions 14 to 19
[0291] The outer region of the first region includes a third region with low pattern coverage.
[0292] A fourth region with high pattern coverage is located outside the second region.
[0293] The third region is opposite to the fourth region.
[0294] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.
Claims
1. A semiconductor device comprising: A first semiconductor device includes a first dummy pattern and a first active pattern on its surface; and The second semiconductor element has a second dummy pattern on its surface that faces the first dummy pattern and is bonded to the first semiconductor element. The first dummy pattern includes a first region. The second dummy pattern includes a second region. The first region and the second region are opposite to each other. The size of the first region is larger than the average area of the pads contained in the first effective pattern. The pattern coverage of the first region is different from that of the second region.
2. The semiconductor device according to claim 1, The pattern coverage of the second region is more than 0% and less than 80% of the pattern coverage of the first region.
3. The semiconductor device according to claim 1, The pattern coverage of the second region is more than 0% and less than 20% of the pattern coverage of the first region.
4. The semiconductor device according to claim 1, The pattern coverage of the first region is higher than that of the second region. The pattern coverage of the first region is above 20% and below 100%. The pattern coverage of the second region is above 0% and below 50%.
5. The semiconductor device according to claim 1, The pattern coverage of the first region is higher than the overall pattern coverage of the first dummy pattern. The pattern coverage of the second region is lower than the overall pattern coverage of the second dummy pattern.
6. The semiconductor device according to claim 1, The first region is a concave surface. The second region is a convex surface.
7. The semiconductor device according to claim 1, The first region is a concave surface. The second region is a convex surface. The convex surface, which is opposite to the concave surface, enters the gap of the concave surface.
8. The semiconductor device according to claim 6, A first insulating film is provided on the first dummy pattern. A second insulating film is provided on the second dummy pattern. The first insulating film on the first dummy pattern has a concave surface corresponding to the first region. The second insulating film on the second dummy pattern has a convex surface corresponding to the second region. The convex surface of the second insulating film, which is opposite to the concave surface of the first insulating film, enters the gap of the concave surface of the first insulating film.
9. The semiconductor device according to claim 1, The first dummy pattern is not electrically connected to the circuit elements within the first semiconductor element. The second dummy pattern is not electrically connected to the circuit elements within the second semiconductor element.
10. The semiconductor device according to claim 1, The first region is provided with solder pads either on the entire surface or at high density. The second region has no pads or has pads with a lower density compared to the first region.
11. The semiconductor device according to claim 1, Pads are provided in the first region. Pads are provided in the second region. The pads in the first region and a portion of the pads in the second region are joined.
12. The semiconductor device according to claim 1, The outer region of the first region includes a third region with low pattern coverage. A fourth region with high pattern coverage is located outside the second region. The third region is opposite to the fourth region.
13. The semiconductor device according to claim 1, Pads are provided in the third region. Pads are provided in the fourth region. The pads in the third region and a portion of the pads in the fourth region are joined.
14. A method for manufacturing a semiconductor device, comprising: The process of forming a first wiring layer including a first dummy pattern and a first effective pattern electrically connected to the first circuit element in a first semiconductor layer where a first circuit element is formed; The process of performing CMP processing on the first wiring layer to obtain the first semiconductor device; The process of forming a second wiring layer including a second dummy pattern and a second valid pattern electrically connected to the second circuit element in a second semiconductor layer where the second circuit element is formed; The process of performing CMP processing on the second wiring layer to obtain the second semiconductor device; as well as The process of bonding the first semiconductor element and the second semiconductor element to join the pads of the first effective pattern and the second effective pattern. The first region contained in the first dummy pattern and the second region contained in the second dummy pattern are opposite to each other. The size of the first region is larger than the average area of the pads contained in the first effective pattern. The pattern coverage of the first region is different from that of the second region.
15. The method for manufacturing a semiconductor device according to claim 14, The surface of the first region relative to the first effective pattern is concave. The surface of the second region relative to the second effective pattern is convex. The concave surface of the first region is opposite to the convex surface of the second region.
16. The method for manufacturing a semiconductor device according to claim 14, The pattern coverage of the second region is more than 0% and less than 80% of the pattern coverage of the first region.
17. The method for manufacturing a semiconductor device according to claim 14, The pattern coverage of the second region is more than 0% and less than 20% of the pattern coverage of the first region.
18. The method for manufacturing a semiconductor device according to claim 14, The pattern coverage of the first region is above 20% and below 100%. The pattern coverage of the second region is above 0% and below 50%.
19. The method for manufacturing a semiconductor device according to claim 14, The pattern coverage of the first region is higher than the overall pattern coverage of the first dummy pattern, and the pattern coverage of the second region is lower than the overall pattern coverage of the second dummy pattern.
20. The method for manufacturing a semiconductor device according to claim 14, The outer region of the first region includes a third region with low pattern coverage. A fourth region with high pattern coverage is located outside the second region. The third region is opposite to the fourth region.