Semiconductor package structure

Abstract

This application discloses a semiconductor packaging structure, comprising: a substrate; a plurality of chips disposed above the substrate, including at least one first chip and at least one second chip, wherein the top surfaces of the first chip and the second chip are not flush; a frame structure disposed on the substrate, surrounding at least a portion of the plurality of chips and extending above at least one second chip; and a heat sink disposed above the frame structure and connected to at least one first chip and the frame structure, wherein the corresponding frame structure or heat sink above the lower of the top surfaces of the at least one first chip and the at least one second chip has a protrusion. The above technical solution can at least suppress warping, improve structural stability, and achieve efficient heat dissipation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] With the rapid development of artificial intelligence (AI) and high-performance computing (HPC) applications, semiconductor packaging structures are evolving towards higher power and larger sizes to meet the demands of high computing density and high integration. However, the increase in packaging size also brings problems such as heat dissipation difficulties, warpage caused by material thermal expansion mismatch, and insufficient overall structural strength, which in turn affect assembly yield and long-term reliability.

[0003] Furthermore, as package structures become increasingly larger, the thermal interface material (TIM) in current microchannel cold plate technology is becoming thicker to overcome assembly tolerances. Since TIM itself is not a good thermal conductor, this leads to increasingly poor heat dissipation as power increases. Therefore, how to simultaneously achieve efficient heat dissipation, warpage suppression, and structural stability in large-size package structures is a pressing issue that needs to be addressed. Summary of the Invention

[0004] To address the above issues, this application proposes a semiconductor packaging structure that can at least suppress warping, improve structural stability, and provide efficient heat dissipation.

[0005] According to one aspect of this application, a semiconductor package structure is provided, the semiconductor package structure comprising: a substrate; a plurality of chips disposed above the substrate, including at least one first chip and at least one second chip, the top surfaces of the first chip and the second chip being non-flush; a frame structure disposed on the substrate, surrounding at least a portion of the plurality of chips and extending above at least one second chip; and a heat sink disposed above the frame structure and connected to at least one first chip and the frame structure, wherein the corresponding frame structure or heat sink above the lower of the top surfaces of the at least one first chip and the at least one second chip has a protrusion.

[0006] In some embodiments, the frame structure includes a vertical extension connected to a substrate and a lateral extension connected to the vertical extension and located above at least one second chip, wherein the lateral extension and at least one first chip are both connected to a heat sink.

[0007] In some embodiments, the top surface of at least one first chip is higher than the top surface of at least one second chip, the bottom surface of the heat sink spanning multiple chips is flat, the lateral extension of the frame structure has a bottom surface facing at least one second chip, the bottom surface of the lateral extension has a protrusion connected to a corresponding second chip in at least one second chip, and the thickness of the protrusion is associated with the height difference between at least one first chip and at least one second chip.

[0008] In some embodiments, the top surface of at least one second chip is higher than the top surface of at least one first chip, the bottom surface of the lateral extension of the frame structure facing at least one second chip is flat, and the bottom surface of the heat sink is provided with a protrusion that passes through the frame structure and connects to a corresponding first chip among at least one first chip.

[0009] In some embodiments, the heat generation of each of the at least one first chip is higher than the heat generation of each of the at least one second chip.

[0010] In some embodiments, the heat sink includes a heat sink body disposed above the frame structure and a support foot connected to the heat sink body. The support foot is located on the outer side of the frame structure facing away from the multiple chips, and the support foot is fixedly connected to the frame structure by a locking structure.

[0011] In some embodiments, the locking structure includes either a snap-fit ​​connection structure or a bolt connection structure; wherein the locking structure includes at least one snap-fit ​​protrusion disposed on the inner side of the support leg and a corresponding snap-fit ​​groove disposed on the outer side of the frame structure.

[0012] In some embodiments, the semiconductor package structure further includes a molding layer that covers the outer side of the support portion and the inner side of the frame structure, and covers multiple chips, wherein the top surface of the molding layer is higher than the top surface of the frame structure to cover the locking structure.

[0013] In some embodiments, each of the at least one first chip is connected to a heat sink via a first thermal interface material (TIM) layer, and each of the at least one second chip is connected to a frame structure via a second thermal interface material layer, wherein the thickness of the first thermal interface material layer is the same as the thickness of the second thermal interface material layer.

[0014] In some embodiments, the heat sink has a fluid channel for containing coolant, and an inlet and an outlet communicating with the fluid channel.

[0015] In some embodiments, the semiconductor package structure further includes an interposer layer located on a substrate, a plurality of chips located on the interposer layer, and a frame structure that at least partially surrounds the interposer layer.

[0016] According to another aspect of this application, a semiconductor package structure is provided, the semiconductor package structure comprising: a substrate; a plurality of chips disposed above the substrate, including at least one first chip and at least one second chip, the top surfaces of the at least one first chip and at least one second chip being non-flush; a frame structure disposed on the substrate and laterally surrounding at least a portion of the plurality of chips, the frame structure including a lateral extension located above the plurality of chips, wherein the lateral extension has at least one opening, each opening being located above a corresponding first chip among the at least one first chip; and a heat sink connected above the frame structure, wherein the heat sink and the corresponding first chip are connected to each other through the corresponding opening in the at least one opening.

[0017] In some embodiments, the lateral extension of the frame structure is disposed above the gap between at least one first chip to separate a plurality of openings.

[0018] In some embodiments, the lateral extension is located above and connected to at least one second chip.

[0019] In some embodiments, from a top-down view, at least one first chip is disposed on the opposite side of at least one second chip, or, from a top-down view, at least one second chip is disposed on the opposite side of at least one first chip.

[0020] In some embodiments, the top surface of at least one first chip is higher than the top surface of at least one second chip, and the frame structure further includes a vertical extension connected between the substrate and the lateral extension. The lateral extension includes a first portion located above a corresponding second chip in the at least one second chip, and a second portion connected between the first portion and the vertical extension, wherein the first portion protrudes toward the corresponding second chip relative to the second portion.

[0021] In some embodiments, the thickness of the first portion is the same as the height difference between at least one first chip and at least one second chip.

[0022] In some embodiments, the top surface of at least one second chip is higher than the top surface of at least one first chip, and the heat sink is provided with at least one protrusion, the at least one protrusion passing through a corresponding opening in at least one opening and protruding toward a corresponding first chip in at least one first chip.

[0023] In some embodiments, the thickness of the protrusion is equal to the sum of the thickness of the lateral extension and the height difference between at least one first chip and at least one second chip.

[0024] In some embodiments, the plurality of chips further includes at least one third chip, with the lateral extension located above and vertically spaced apart from the at least one third chip. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1A and Figure 1B These are cross-sectional schematic diagrams of semiconductor packaging structures according to embodiments of this application.

[0027] Figure 2A and Figure 2B These are cross-sectional schematic diagrams of semiconductor packaging structures according to other embodiments of this application.

[0028] Figure 3A and Figure 3B These are cross-sectional schematic diagrams of semiconductor packaging structures according to other embodiments of this application.

[0029] Figure 4A This is a top view schematic diagram of the planar layout of multiple chips in a semiconductor packaging structure according to an embodiment of this application.

[0030] Figure 4B and Figure 4C They are in Figure 4A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed.

[0031] Figure 4D Is Figure 4C A three-dimensional schematic diagram of the semiconductor packaging structure after a heat sink is installed on top of the structure shown.

[0032] Figure 4E yes Figure 4D A cross-sectional schematic diagram of the semiconductor packaging structure.

[0033] Figure 5A It shows Figure 4E A cross-sectional schematic diagram of the heat sink in the image.

[0034] Figure 5B and Figure 5C Two heat dissipation devices that can be used in the heat sink according to other embodiments are shown respectively.

[0035] Figure 6A This is a top view schematic diagram of a planar layout of multiple chips in a semiconductor packaging structure according to another embodiment of this application.

[0036] Figure 6B and Figure 6C They are in Figure 6A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed.

[0037] Figure 6D Is Figure 6C The diagram shows a three-dimensional representation of the semiconductor packaging structure with a heat sink 500 mounted on top.

[0038] Figure 6E yes Figure 6D A cross-sectional schematic diagram of the semiconductor packaging structure.

[0039] Figure 7A This is a top view schematic diagram of a planar layout of multiple chips in a semiconductor packaging structure according to another embodiment of this application.

[0040] Figure 7B and Figure 7C They are in Figure 7A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed.

[0041] Figure 7D Is Figure 7C A three-dimensional schematic diagram of the semiconductor packaging structure after a heat sink is installed on top of the structure shown.

[0042] Figure 7E yes Figure 7D A cross-sectional schematic diagram of the semiconductor packaging structure.

[0043] Figure 8A This is a top view schematic diagram of a planar layout of multiple chips in a semiconductor packaging structure according to another embodiment of this application.

[0044] Figure 8B and Figure 8C They are in Figure 8A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed.

[0045] Figure 8D Is Figure 8C A three-dimensional schematic diagram of the semiconductor packaging structure after a heat sink is installed on top of the structure shown.

[0046] Figure 8E yes Figure 8D A cross-sectional schematic diagram of the semiconductor packaging structure. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0048] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0049] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0050] An embodiment of this application provides a semiconductor packaging structure. Figure 1A This is a schematic cross-sectional view of a semiconductor package structure 1000A according to an embodiment of this application. See also... Figure 1A The semiconductor package structure 1000A may include a substrate 110 and a plurality of chips 200 disposed on the substrate 110. The plurality of chips 200 includes at least one first chip 210 and at least one second chip 220. Such a semiconductor package structure including a plurality of chips 200 may be referred to as a large-size semiconductor package structure.

[0051] The semiconductor package structure 1000A also includes a frame structure 400 and a heat sink 500. The frame structure 400 is disposed on a substrate, surrounding at least a portion of a plurality of chips 200, and extending over at least one second chip. In some embodiments, the frame structure 400 may surround each of the plurality of chips 200. The frame structure 400 is laterally spaced from both the first chip 210 and the second chip 220, without directly contacting the first chip 210 and the second chip 220. In some embodiments, the frame structure 400 may be made of a metallic material to provide high rigidity and a low coefficient of thermal expansion.

[0052] A heat sink 500 is disposed above the frame structure 400 and connected to each first chip 210 and the frame structure 400. In some embodiments, the first chip 210 is the hottest core area (i.e., hot spot) of the semiconductor package structure 1000A.

[0053] In some embodiments, the top surfaces of the first chip 210 and the second chip 220 are not flush. Figure 1A In the illustrated embodiment, the top surface of the first chip 210 is higher than the top surface of the second chip 220. In this embodiment, the frame structure 400 above each second chip 220 has a protrusion 405 protruding toward the second chip 220. The frame structure 400 is engaged to the second chip 220 through the protrusion 405.

[0054] A frame structure 400 is disposed on the substrate 110 and surrounds at least a portion of the chip 200. A heat sink 500 is disposed on the frame structure 400. The frame structure 400 provides mechanical support for the large-size semiconductor package structure 1000A and effectively reduces warpage caused by material thermal expansion mismatch. This is particularly important in large-area package structures, improving assembly yield and long-term reliability. The frame structure 400 also provides heat dissipation for the second chip 220. Furthermore, the mechanical load applied by the heat sink 500 can be transferred from the chip to the surrounding frame structure 400, preventing the chip from cracking or deteriorating in reliability due to direct pressure. Therefore, by providing a rigid and warpage-suppressing frame structure 400 around multiple chips 200, this application avoids excessive warpage. The integrated heat sink 500 quickly and effectively removes the heat generated by the first chip 210 (hot spot), optimizing the heat transfer path and significantly reducing the interface temperature of the first chip 210, ensuring stable and reliable thermal management performance under high-power operation.

[0055] Specifically, the frame structure 400 includes a vertical extension 420 connected to the substrate, and a lateral extension 440 connected to the top of the vertical extension 420 and extending laterally. The lateral extension 440 can extend laterally above each second chip 220. Both the lateral extension 440 and each first chip 210 are connected to the heat sink 500. This frame structure 400 effectively prevents the second chip 220 from being subjected to excessive pressure during the packaging process, thereby reducing the risk of chip damage.

[0056] In this embodiment, where the top surface of the first chip 210 is higher than the top surface of the second chip 220, the lateral extension 440 may include a first portion 441 located above the second chip 220, and a second portion 442 connecting the first portion 441 and the vertical extension 420. The first portion 441 protrudes relative to the second portion 442 toward the corresponding second chip 220. Thus, the bottom surface of the lateral extension 440 facing the second chip 220 has a protrusion 405. In this embodiment, the bottom surface of the heat sink 500 spanning multiple chips 200 (including the first chip 210 and the second chip 220) is flat. The frame structure 400, with this non-uniform thickness design, can be adjusted for the first chip 210 and the second chip 220 at different heights, providing flexibility and maintaining structural stability under different thermal expansion conditions, further enhancing the reliability of the packaging structure.

[0057] The lateral extension 440 may have at least one opening 445, each opening 445 being located above a corresponding first chip 210. The first chip 210 and the heat sink 500 can be connected to each other through the openings 445. A portion of the first chip 210 may be located in the opening 445 for connection to the heat sink 500.

[0058] In some embodiments, the first chip 210 is an ASIC (Application Specific Integrated Circuit) chip. The second chip 220 is a memory chip, such as an HBM (High Bandwidth Memory) chip.

[0059] In some embodiments, the heat generated by the first chip 210 is higher than that of the second chip 220. That is, an opening 445 is provided above the first chip 210, which generates more heat. By making localized openings 445 for hot spots, and connecting to the heat sink 500 via the openings 445, the heat dissipation effect is improved.

[0060] Each first chip 210 can be connected to the heat sink 500 via a first thermal interface material (TIM) layer 610. Each second chip 220 can be connected to the frame structure 400 via a second TIM layer 620. The combination of the first chip 210 and the first TIM layer 610 passes through a corresponding opening 445 and connects to the bottom surface of the heat sink body 520. In some embodiments, the thickness of the first TIM layer 610 is the same as the thickness of the second TIM layer 620. In some embodiments, the first TIM layer 610 is a single interface layer directly disposed between the heat sink 500 and the first chip 210. In large-size semiconductor package structures, the first TIM layer 610 being a single interface layer directly disposed between the heat sink 500 and the first chip 210 can ensure efficient heat conduction.

[0061] This application utilizes a frame structure 400 surrounding the chip, integrated with a heat sink 500, to quickly and effectively dissipate heat generated by hot spots. Specifically, the heat transfer path for the first chip 210 is from the first chip 210 to the first TIM layer 610, and then to the heat sink 500; the heat transfer path for the second chip 220 is from the second chip 220 to the second TIM layer 620, to the frame structure 400, and then to the heat sink 500. Through high thermal conductivity materials and optimized heat transfer paths, the chip's interface temperature can be significantly reduced, ensuring stable and reliable thermal management performance under high-power operation and improving thermal management efficiency. Furthermore, with the trend of high-power operation and continuous increases in future power density, the thickness of the TIM layer will inevitably move towards ultra-thinness to reduce thermal resistance. However, in traditional structures, the clamping force of heat sinks or cold plates often acts directly on the chip surface. When the TIM thickness is reduced, it is easy to cause chip damage due to pressure or stress concentration, a problem that is particularly critical when using thin TIM layers. In this application, the mechanical load applied by the heat sink 500 can be transferred from the chip to the surrounding frame structure 400, which can prevent the chip from cracking or deteriorating in reliability due to direct pressure, thus providing good mechanical safety and supporting the application of ultra-thin TIM layers.

[0062] In some embodiments, the thickness of the protrusion 405 is associated with the height difference between the first chip 210 and the second chip 220. In some embodiments, the thickness of the first portion 441 is the same as the height difference between the first chip 210 and the second chip 220. The first portion 441 has this predetermined thickness, which allows it to be disposed above the second chip 220 and has a top surface flush with the top surface of the first TIM layer 610.

[0063] The heat sink 500 includes a heat sink body 520 disposed above the frame structure 400, and a support portion 540 connected to the heat sink body 520. The heat sink body 520 may be made of metal. The support portion 540 is located on the outer side of the frame structure 400 opposite to the first chip 210 and the second chip 220. The support portion 540 can expose the lower portion of the vertical extension 420.

[0064] In some embodiments, the heat sink body 520 may have a fluid channel 524 for containing coolant inside, and may also have an inlet 525 and an outlet 526 communicating with the fluid channel. Coolant enters the fluid channel 524 inside the heat sink body 520 from the inlet 525, flows through the fluid channel 524, absorbs the heat generated by the first chip 210, and then flows out from the outlet 526, carrying the heat away from the heat sink 500. By adding a fluid channel 524 inside the heat sink 500, heat dissipation performance can be improved, thermal management performance can be enhanced, and the stability of the chip under high-performance operation can be ensured.

[0065] In some embodiments, the support leg 540 and the frame structure 400 are fixedly connected by a locking structure 480. In some embodiments, the locking structure 480 is a snap-fit ​​connection structure. In such embodiments, the locking structure 480 may include at least one snap-fit ​​protrusion 481 disposed on the inner side of the support leg 540, and at least one snap-fit ​​groove 483 disposed on the outer side of the frame structure 400, each corresponding to the snap-fit ​​protrusion 481. The snap-fit ​​protrusion 481 and the snap-fit ​​groove 483 cooperate to fix them together. In other embodiments, the locking structure 480 may be a bolted connection structure. In such embodiments, the locking structure 480 may include screw holes located in the support leg 540 and the vertical extension 420, and bolts passing through the screw holes. When the heat sink 500 cannot effectively remove heat by directly pressing the first chip 210 through the first TIM layer 610, the heat sink 500 with fluid channel 524 and the design of locking structure 480 can further improve the heat removal efficiency to ensure the stable operation and performance of the system.

[0066] The semiconductor package structure 1000A may further include an interposer 140 located on a substrate 110. Both the first chip 210 and the second chip 220 are located on the interposer 140. The frame structure 400 also at least partially surrounds the interposer 140.

[0067] Specifically, a first chip 210 is electrically connected to an interposer 140 via its connector 219, and a first underfill 722 is formed between the first chip 210 and the interposer 140 to laterally surround each connector 219. A second chip 220 is electrically connected to the interposer 140 via its connector 229, and a second underfill 724 is formed between the second chip 220 and the interposer 140 to laterally surround each connector 229. The interposer 140 is electrically connected to the substrate 110 below it via connectors 149, and a third underfill 726 is formed between the interposer 140 and the substrate 110 to laterally surround each connector 149. Additional connectors 119 may be provided below the substrate 110. The connectors 119 can be used for electrical connection with other components.

[0068] Figure 1B This is a cross-sectional schematic diagram of a semiconductor packaging structure 1000B according to an embodiment of this application. Figure 1B Several aspects of the illustrated embodiments are related to the above references. Figure 1A The semiconductor package structure described below is the same as or similar to that of 1000A; only the following description is provided. Figure 1B The differences of the semiconductor package structure 1000B shown.

[0069] See Figure 1B The semiconductor package structure 1000B may further include a molding layer 180. The molding layer 180 covers the outer side of the foot portion 540 and the inner side of the frame structure 400, and covers each of the first chip 210 and the second chip 220. In some embodiments, the top surface 180t of the molding layer 180 may be higher than the top surface 400t of the frame structure 400, thereby ensuring that the molding layer 180 can cover the locking structure 480.

[0070] Figure 2A This is a cross-sectional schematic diagram of a semiconductor package structure 2000A according to an embodiment of this application. Figure 2A Several aspects of the illustrated embodiments are related to the above references. Figure 1A The semiconductor package structure described below is the same as or similar to that of 1000A; only the following description is provided. Figure 2A The differences of the semiconductor package structure 2000A shown.

[0071] See Figure 2A As shown, the top surface of the second chip 220 can be higher than the top surface of the first chip 210. In this embodiment, the bottom surface of the lateral extension 440 of the frame structure 400 facing the second chip 220 is flat.

[0072] The bottom surface of the heat sink 500 may have at least one protrusion 505. The protrusion 505 protrudes toward the corresponding first chip 210. The protrusion 505 passes through a corresponding opening 445 in the lateral extension 440 of the frame structure 400, so that the protrusion 505 can pass through the frame structure 400 and connect to the corresponding first chip 210. The frame structure 400 has this non-uniform thickness design, which can be adjusted for the first chip 210 and the second chip 220 with different heights, providing not only flexibility, but also maintaining structural stability under different thermal expansion conditions, further enhancing the reliability of the package structure.

[0073] In some embodiments, the thickness of the protrusion 505 may be equal to the sum of the thickness of the lateral extension 440 and the height difference between at least one first chip 210 and at least one second chip 220. The protrusion 505 having this predetermined thickness allows it to connect to the underlying first TIM layer 610.

[0074] Figure 2B This is a cross-sectional schematic diagram of a semiconductor packaging structure 2000B according to an embodiment of this application. Figure 2B Several aspects of the illustrated embodiments are related to the above references. Figure 2A The semiconductor package structure described is the same as or similar to that of the 2000A; only the following description is provided. Figure 2B The differences between the semiconductor package structure 2000B shown are as follows.

[0075] See Figure 2B The semiconductor package structure 2000B may further include a molding layer 180. The molding layer 180 covers the outer side of the foot portion 540 and the inner side of the frame structure 400, and covers each of the first chip 210 and the second chip 220. In some embodiments, the top surface 180t of the molding layer 180 may be higher than the top surface 400t of the frame structure 400, thereby ensuring that the molding layer 180 can cover the locking structure 480.

[0076] Figure 3A This is a cross-sectional schematic diagram of a semiconductor package structure 3000A according to an embodiment of this application. Figure 3A Several aspects of the illustrated embodiments are related to the above references. Figure 2A The semiconductor package structure described is the same as or similar to that of the 2000A; only the following description is provided. Figure 3A The differences in the semiconductor package structure 3000A shown.

[0077] See Figure 3A As shown, in this embodiment, the top surface of the second chip 220 can be higher than the top surface of the first chip 210. The bottom surface of the lateral extension 440 of the frame structure 400 facing the second chip 220 is flat. The bottom surface of the heat sink body 520 of the heat sink 500, spanning the first chip 210 and the second chip 220, is also flat. The thickness of the first TIM layer 610 is greater than the thickness of the second TIM layer 620. The thickness of the first TIM layer 610 can be greater than the sum of the thicknesses of the second TIM layer 620 and the lateral extension 440. The gap between the flat bottom surface of the heat sink body 520 and the first chip 210 is filled by the thicker first TIM layer 610.

[0078] Figure 3B This is a cross-sectional schematic diagram of a semiconductor packaging structure 3000B according to an embodiment of this application. Figure 3B Several aspects of the illustrated embodiments are related to the above references. Figure 3A The semiconductor package structure described below is the same as or similar to that of the 3000A; only the following description is provided. Figure 3B The differences in the semiconductor package structure 3000B shown.

[0079] See Figure 3BThe semiconductor package structure 3000B may further include a molding layer 180. The molding layer 180 covers the outer side of the foot portion 540 and the inner side of the frame structure 400, and covers each of the first chip 210 and the second chip 220. In some embodiments, the top surface 180t of the molding layer 180 may be higher than the top surface 400t of the frame structure 400, thereby ensuring that the molding layer 180 can cover the locking structure 480.

[0080] Figures 4A to 4E These are multiple illustrations of a semiconductor packaging structure 4000 according to an embodiment of this application. Figure 4A This is a top view of the planar layout of multiple chips in a semiconductor package structure 4000. Figure 4B and Figure 4C They are in Figure 4A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed. Figure 4D Is Figure 4C The diagram shows a three-dimensional view of the semiconductor packaging structure 4000 after the heat sink 500 is installed on top of the structure shown. Figure 4E This is a cross-sectional schematic diagram of the semiconductor package structure 4000. Figure 4E The cross-sectional schematic diagram can correspond to Figure 4D The section at section line C1-C1. It should be understood that for... Figures 4A to 4E The above references Figures 1A to 3B The same reference numerals are used for similar components.

[0081] See Figure 4A Multiple chips 200 are disposed on an interposer layer 140 above a substrate 110. The multiple chips 200 include multiple first chips 210 and multiple second chips 220. In this embodiment, four first chips 210 and eight second chips 220 are shown as an example. The four first chips 210 are arranged adjacent to each other, forming two rows along direction X and two columns along direction Y. Direction X is perpendicular to direction Y. The eight second chips 220 are disposed along direction X on opposite sides of the four first chips 210. Specifically, four second chips 220 are disposed along direction X on one side of the four first chips 210, and another four second chips 220 are disposed along direction X on the other side of the four first chips 210.

[0082] Furthermore, in this embodiment, the plurality of chips 200 also includes at least one third chip 230. In this embodiment, four third chips 230 are shown as an example. The four third chips 230 are arranged along the Y direction on opposite sides of the four first chips 210. Specifically, two third chips 230 are arranged along the Y direction on one side of the four first chips 210, and the other two third chips 230 are arranged along the Y direction on the other side of the four first chips 210. The plurality of second chips 220 and the plurality of third chips 230 are arranged around the plurality of first chips 210.

[0083] In some embodiments, the first chip 210 is an ASIC chip. The second chip 220 is an HBM chip. In some embodiments, the third chip 230 is an I / O (input / output) chip. In some embodiments, the heat generated by the third chip 230 is lower than that of each of the first chip 210 and the second chip 220.

[0084] See Figure 4B and Figure 4C The frame structure 400 is connected to the substrate 110 and surrounds a plurality of first chips 210, a plurality of second chips 220, and a plurality of third chips 230. The frame structure 400 includes a vertical extension 420 connected to the substrate and a lateral extension 440 connected to the top of the vertical extension 420 and extending laterally. The lateral extension 440 can pass through a second TIM layer 620 (see...). Figure 4E ) is connected to each second chip 220.

[0085] The lateral extension 440 may have a plurality of openings 445 spaced apart from each other. The lateral extension 440 of the frame structure 400 may be disposed above the spacing between the plurality of first chips 210 to separate the plurality of openings 445. The plurality of openings 445 are respectively located above the respective first chip 210. In a top view, the first chip 210 is exposed through the openings 445.

[0086] See Figure 4D Place the heat sink 500 on the frame structure 400. For more details, see... Figure 4E In this embodiment, the top surface of each first chip 210 is higher than the top surface of each second chip 220. The bottom surface of the lateral extension 440 facing the second chip 220 has a protrusion 405. The protrusion 405 is connected to the second chip 220 through the second TIM layer 620.

[0087] The heat sink 500 includes a heat sink body 520 disposed above the frame structure 400, and a support portion 540 connected to the heat sink body 520. The support portion 540 is fixedly connected to the vertical extension portion 420 of the frame structure 400 by the aforementioned locking structure 480. Each first chip 210 is connected to the heat sink body 520 of the heat sink 500 via a first TIM layer 610. The combination of the first chip 210 and the first TIM layer 610 passes through a corresponding opening 445 and connects to the flat bottom surface of the heat sink body 520.

[0088] Furthermore, in embodiments where the heat generation of the third chip 230 is lower than that of the first chip 210 and the second chip 220, the lateral extension 440 is located above at least one third chip 230 and is perpendicularly spaced from it. That is, in embodiments where the heat generation of the third chip 230 is lower than that of the first chip 210 and the second chip 220, the third chip 230 is not connected to the frame structure 400, nor is it connected to the heat sink 500.

[0089] Figure 5A It shows Figure 4E A cross-sectional schematic diagram of the heat sink 500 is shown. The heat sink 500 includes a heat sink body 520 disposed above the frame structure 400, and a support leg 540 connected to the heat sink body 520. A snap-fit ​​protrusion 481 is provided on the inner side of the support leg 540.

[0090] It should be understood that in other embodiments, other types of heat dissipation devices may also be used as heat dissipation cover 500. Figure 5B and Figure 5C Two heat dissipation devices that may be used in the heat sink 500 according to other embodiments are shown respectively.

[0091] See Figure 5B As shown, a cold plate 500A can be used to replace the aforementioned heat sink 500. The cold plate 500A can be obtained from an external system manufacturer. The cold plate 500A includes a main body 520A and a plurality of connecting parts 550A connected to the main body 520A. The main body 520A and the plurality of connecting parts 550A can both extend in the lateral direction. The main body 520A may have a fluid channel for containing coolant inside. The main body 520A may also have an inlet 525A and an outlet 526A communicating with the fluid channel. The cold plate 500A does not have the aforementioned support leg 540. The cold plate 500A can be connected to the aforementioned frame structure 400 through the plurality of connecting parts 550A. Each connecting part 550A may have a through hole 552, which can be used for bolts to pass through for fixed connection with the frame structure 400.

[0092] See Figure 5CAs shown, a vapor chamber 500B can also be used to replace the heat sink 500. A vapor chamber 582 is provided on the back of the vapor chamber 500B, and a wick 584 is provided between the inner wall of the vapor chamber 500B and the vapor chamber 582. Heat 588 from a heat source (e.g., from the first chip 210) causes the liquid in the wick 584 to boil and turn into steam. The steam can rapidly diffuse to the surrounding area in the direction shown by arrow 589. The diffused steam condenses back into liquid upon cooling, and the condensed liquid flows back to the area above the heat source along the wick 584 in the direction shown by arrow 591.

[0093] Figures 6A to 6E These are multiple illustrations of a semiconductor package structure 5000 according to another embodiment of this application. Figure 6A This is a top view of the planar layout of multiple chips in a semiconductor package structure 5000. Figure 6B and Figure 6C They are in Figure 6A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed. Figure 6D Is Figure 6C The diagram shows a three-dimensional view of the semiconductor packaging structure 5000 after a heat sink 500 is installed on top of the structure shown. Figure 6E This is a cross-sectional schematic diagram of the semiconductor package structure 5000. Figure 6E The cross-sectional schematic diagram can correspond to Figure 6D The section at section line C2-C2. It should be understood that for... Figures 6A to 6E The above references Figures 1A to 4E The same reference numerals are used for similar components.

[0094] See Figure 6A Multiple chips 200 are disposed on an interposer layer 140 above the substrate 110. The multiple chips 200 include multiple first chips 210, multiple second chips 220, and multiple third chips 230. In this embodiment, the arrangement of the multiple chips 200 is similar to that described above. Figure 4A The described layouts are similar.

[0095] See Figure 6B and Figure 6C The frame structure 400 is connected to the substrate 110. The frame structure 400 includes a vertical extension 420 connected to the substrate and a lateral extension 440 connected to the top of the vertical extension 420 and extending laterally. The lateral extension 440 can pass through the second TIM layer 620 (see...). Figure 6E The lateral extension 440 is connected to each of the second chips 220. The lateral extension 440 may have a plurality of openings 445 spaced apart from each other, as referenced above. Figure 4B and Figure 4C As described.

[0096] See Figure 6D Place the heat sink 500 on the frame structure 400. For more details, see... Figure 6E In this embodiment, the top surface of each second chip 220 is higher than the top surface of each first chip 210. The bottom surface of the lateral extension 440 facing the second chip 220 is flat. The second chip 220 is connected to the lateral extension 440 via a second TIM layer 620.

[0097] The heat sink 500 includes a heat sink body 520 disposed above the frame structure 400, and a support portion 540 connected to the heat sink body 520. The bottom surface of the heat sink body 520 is flat. The support portion 540 can be fixedly connected to the vertical extension portion 420 of the frame structure 400 by the aforementioned locking structure 480. Each first chip 210 is connected to the heat sink body 520 of the heat sink 500 by a first TIM layer 610. The gap between the flat bottom surface of the heat sink body 520 and the first chip 210 is filled by a relatively thick first TIM layer 610. The thickness of the first TIM layer 610 can be greater than the sum of the thicknesses of the second TIM layer 620 and the lateral extension portion 440.

[0098] Other aspects of the semiconductor package structure 5000 can be found in the above references. Figures 4A to 4E The semiconductor package structure described is the same as or similar to 4000.

[0099] Figures 7A to 7E These are multiple illustrations of a semiconductor package structure 6000 according to another embodiment of this application. Figure 7A This is a top view of the planar layout of multiple chips in the semiconductor package structure 6000. Figure 7B and Figure 7C They are in Figure 7A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed. Figure 7D Is Figure 7C The diagram shows a three-dimensional view of the semiconductor packaging structure 6000 after the heat sink 500 is installed on top of the structure shown. Figure 7E This is a cross-sectional schematic diagram of the 6000 semiconductor package structure. Figure 7E The cross-sectional schematic diagram can correspond to Figure 7D The section at section line C3-C3. It should be understood that for... Figures 7A to 7E The above references Figures 1A to 6E The same reference numerals are used for similar components.

[0100] See Figure 7AMultiple chips 200 are disposed on an interposer layer 140 above a substrate 110. The multiple chips 200 include multiple first chips 210, multiple second chips 220, and multiple third chips 230. In this embodiment, four first chips 210, eight second chips 220, and four third chips 230 are shown as an example. The four first chips 210 are arranged in two rows along direction X and two columns along direction Y. The eight second chips 220 are arranged in two columns along direction Y, with the two columns of second chips 220 adjacent along direction X. The four first chips 210 are disposed on opposite sides of the eight second chips 220. Specifically, two first chips 210 are disposed on one side of the eight second chips 220 along direction X, and the other two first chips 210 are disposed on the other side of the eight second chips 220 along direction X.

[0101] Furthermore, in this embodiment, the plurality of chips 200 also includes at least one third chip 230. In this embodiment, four third chips 230 are shown as an example. The four third chips 230 are arranged along the Y direction on opposite sides of the four first chips 210. Specifically, two third chips 230 are arranged along the Y direction on one side of the four first chips 210, and the other two third chips 230 are arranged along the Y direction on the other side of the four first chips 210. The plurality of second chips 220 and the plurality of third chips 230 are arranged around the plurality of first chips 210.

[0102] See Figure 7B and Figure 7C The frame structure 400 is connected to the substrate 110. The frame structure 400 includes a vertical extension 420 connected to the substrate and a lateral extension 440 connected to the top of the vertical extension 420 and extending laterally. The vertical extension 420 of the frame structure 400 surrounds a plurality of first chips 210, a plurality of second chips 220 and a plurality of third chips 230. The lateral extension 440 can pass through the second TIM layer 620 (see...). Figure 7E The lateral extension 440 is connected to each second chip 220. The lateral extension 440 may have a plurality of openings 445 spaced apart from each other. The plurality of openings 445 are respectively located above the respective first chip 210. In a top view, each first chip 210 is exposed through the openings 445.

[0103] See Figure 7D Place the heat sink 500 on the frame structure 400. For more details, see... Figure 7E In this embodiment, the top surface of each first chip 210 is higher than the top surface of each second chip 220. The bottom surface of the lateral extension 440 has a protrusion 405 that protrudes towards the second chip 220. The protrusion 405 is connected to the second chip 220 through the second TIM layer 620.

[0104] Other aspects of the semiconductor package structure 6000 can be found in the above references. Figures 4A to 4E The semiconductor package structure described is the same as or similar to 4000.

[0105] Figures 8A to 8E These are multiple illustrations of a semiconductor package structure 7000 according to another embodiment of this application. Figure 8A This is a top view of the planar layout of multiple chips in the 7000 semiconductor package structure. Figure 8B and Figure 8C They are in Figure 8A The diagram shows a top view and a three-dimensional view of the structure above it after a frame structure has been installed. Figure 8D Is Figure 8C The diagram shows a three-dimensional view of the semiconductor packaging structure 7000 after the heat sink 500 is installed on top of the structure shown. Figure 8E This is a cross-sectional schematic diagram of the 7000 semiconductor package structure. Figure 8E The cross-sectional schematic diagram can correspond to Figure 8D The section at section line C4-C4. It should be understood that for... Figures 8A to 8E The above references Figures 1A to 7E The same reference numerals are used for similar components.

[0106] See Figure 8A Multiple chips 200 are disposed on an interposer layer 140 above the substrate 110. The multiple chips 200 include multiple first chips 210, multiple second chips 220, and multiple third chips 230. In this embodiment, the arrangement of the multiple chips 200 is similar to that described above. Figure 7A The described layouts are similar.

[0107] See Figure 8B and Figure 8C The frame structure 400 is connected to the substrate 110. The frame structure 400 includes a vertical extension 420 connected to the substrate and a lateral extension 440 connected to the top of the vertical extension 420 and extending laterally. The lateral extension 440 can pass through the second TIM layer 620 (see...). Figure 8E The lateral extension 440 is connected to each of the second chips 220. The lateral extension 440 may have a plurality of openings 445 spaced apart from each other, as referenced above. Figure 7B and Figure 7C As described.

[0108] See Figure 8D Place the heat sink 500 on the frame structure 400. For more details, see... Figure 8EIn this embodiment, the top surface of each second chip 220 is higher than the top surface of each first chip 210. The bottom surface of the lateral extension 440 facing the second chip 220 is flat. The second chip 220 is connected to the lateral extension 440 via a second TIM layer 620.

[0109] The bottom surface of the heat sink body 520 of the heat sink 500 is flat. Each first chip 210 is connected to the heat sink body 520 of the heat sink 500 via a first TIM layer 610. In this embodiment, the gap between the flat bottom surface of the heat sink body 520 and the first chip 210 is filled by a relatively thick first TIM layer 610. The thickness of the first TIM layer 610 can be greater than the sum of the thicknesses of the second TIM layer 620 and the lateral extension 440.

[0110] Other aspects of the semiconductor package structure 7000 can be found in the above references. Figures 4A to 4E The semiconductor package structure described is the same as or similar to 4000.

[0111] In summary, by setting the frame structure 400 and the heat sink 500 on the frame structure 400, the frame structure 400 can provide mechanical support and suppress warpage, thereby improving packaging reliability. The mechanical load applied by the heat sink 500 can be transferred from the chip to the surrounding frame structure 400, preventing the chip from cracking or deteriorating in reliability due to direct pressure, and ensuring the mechanical safety of the chip. Therefore, this application can avoid excessive warpage by setting a rigid and warpage-suppressing frame structure 400 around multiple chips 200, and then quickly and effectively remove the heat generated by the first chip 210 (hot spot) through the integrated heat sink 500, optimizing the heat transfer path and significantly reducing the interface temperature of the first chip 210, ensuring stable and reliable thermal management performance under high power operation, and improving thermal management performance. The frame structure 400 can have this non-uniform thickness design, which can be adjusted for the first chip 210 and the second chip 220 with different heights, providing flexibility and further enhancing the reliability of the packaging structure. The technical solution of this application can meet the needs of future high-power, large-area chip packaging structures. The technical solution of this application can be applied to a variety of application products, such as high-performance computing (HPC) servers, artificial intelligence (AI) accelerators and graphics processing units (GPUs), and also to embedded systems and consumer electronics products.

[0112] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; Multiple chips are disposed above the substrate, including at least one first chip and at least one second chip, wherein the top surfaces of the first chip and the second chip are not flush. A frame structure is disposed on the substrate, surrounds at least a portion of the plurality of chips, and extends over the at least one second chip; A heat sink is disposed above the frame structure and connected to the at least one first chip and the frame structure. The corresponding frame structure or heat sink above the lower of the top surface of the at least one first chip and the at least one second chip has a protrusion.

2. The semiconductor packaging structure according to claim 1, characterized in that, The frame structure includes a vertical extension connected to the substrate and a lateral extension connected to the vertical extension and located above the at least one second chip, wherein the lateral extension and the at least one first chip are both connected to the heat sink.

3. The semiconductor packaging structure according to claim 2, characterized in that, The top surface of at least one first chip is higher than the top surface of at least one second chip, and the bottom surface of the heat sink spanning the plurality of chips is flat. The lateral extension of the frame structure has a bottom surface facing the at least one second chip, the bottom surface of the lateral extension having a protrusion connected to a corresponding second chip in the at least one second chip, the thickness of the protrusion being related to the height difference between the at least one first chip and the at least one second chip.

4. The semiconductor packaging structure according to claim 2, characterized in that, The top surface of the at least one second chip is higher than the top surface of the at least one first chip, and the bottom surface of the lateral extension of the frame structure facing the at least one second chip is flat. The bottom surface of the heat sink cover is provided with the protrusion, which passes through the frame structure and connects to the corresponding first chip in the at least one first chip.

5. The semiconductor packaging structure according to claim 1, characterized in that, The heat generated by each of the at least one first chip is higher than the heat generated by each of the at least one second chip.

6. The semiconductor packaging structure according to claim 1, characterized in that, The heat sink includes a heat sink body disposed above the frame structure, and a support foot connected to the heat sink body. The support foot is located on the outer side of the frame structure opposite to the plurality of chips, and the support foot is fixedly connected to the frame structure by a locking structure.

7. The semiconductor packaging structure according to claim 6, characterized in that, The locking structure includes either a snap-fit ​​connection structure or a bolt connection structure. The locking structure includes at least one snap-fit ​​protrusion disposed on the inner side of the support leg and a corresponding snap-fit ​​groove disposed on the outer side of the frame structure.

8. The semiconductor packaging structure according to claim 6, characterized in that, Also includes: A molding layer covers the outer side of the support legs and the inner side of the frame structure, and also covers the plurality of chips. The top surface of the sealing layer is higher than the top surface of the frame structure to cover the locking structure.

9. The semiconductor packaging structure according to claim 1, characterized in that, Each of the at least one first chip is connected to the heat sink via a first thermal interface material layer, and each of the at least one second chip is connected to the frame structure via a second thermal interface material layer, wherein the thickness of the first thermal interface material layer is the same as the thickness of the second thermal interface material layer.

10. The semiconductor packaging structure according to claim 1, characterized in that, The heat dissipation cover has a fluid channel for containing coolant, and an inlet and an outlet connected to the fluid channel.

11. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: An interposer layer is located on the substrate, the plurality of chips are located on the interposer layer, and the frame structure also at least partially surrounds the interposer layer.

12. A semiconductor packaging structure, characterized in that, include: substrate; Multiple chips are disposed above the substrate, including at least one first chip and at least one second chip, wherein the top surfaces of the at least one first chip and the at least one second chip are not flush. A frame structure is disposed on the substrate and laterally surrounds at least a portion of the plurality of chips. The frame structure includes a lateral extension located above the plurality of chips, wherein the lateral extension has at least one opening, each of the openings being located above a corresponding first chip in the at least one first chip. A heat sink is attached above the frame structure, wherein the heat sink and the corresponding first chip are connected to each other through corresponding openings in the at least one opening.

13. The semiconductor packaging structure according to claim 12, characterized in that, The lateral extension of the frame structure is disposed above the interval between the at least one first chip to separate the plurality of openings.

14. The semiconductor packaging structure according to claim 12, characterized in that, The lateral extension is located above and connected to the at least one second chip.

15. The semiconductor packaging structure according to claim 14, characterized in that, From a top-down view, the at least one first chip is disposed on the opposite side of the at least one second chip, or From a top-down view, the at least one second chip is disposed on the opposite side of the at least one first chip.

16. The semiconductor packaging structure according to claim 12, characterized in that, The top surface of the at least one first chip is higher than the top surface of the at least one second chip. The frame structure further includes a vertical extension connecting the substrate and the lateral extension, the lateral extension including a first portion located above a corresponding second chip in the at least one second chip, and a second portion connecting the first portion and the vertical extension. The first portion protrudes toward the corresponding second chip relative to the second portion.

17. The semiconductor packaging structure according to claim 16, characterized in that, The thickness of the first portion is the same as the height difference between the at least one first chip and the at least one second chip.

18. The semiconductor packaging structure according to claim 12, characterized in that, The top surface of the at least one second chip is higher than the top surface of the at least one first chip. The heat sink cover has at least one protrusion, which passes through a corresponding opening in the at least one opening and protrudes toward a corresponding first chip in the at least one first chip.

19. The semiconductor packaging structure according to claim 18, characterized in that, The thickness of the protrusion is equal to the sum of the thickness of the lateral extension and the height difference between the at least one first chip and the at least one second chip.

20. The semiconductor packaging structure according to claim 12, characterized in that, The plurality of chips also includes at least one third chip, the lateral extension being located above the at least one third chip and vertically spaced apart from the at least one third chip.

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