A stacked package method of a memory chip

Abstract

The application belongs to the technical field of semiconductor packaging, and particularly relates to a laminated packaging method for a memory chip, which comprises the following steps: performing plasma activation treatment on the surface of the chip to form a self-assembled monolayer modification film; depositing a polyimide base dielectric layer and a nano heat-conducting composite layer to construct a low-thermal-resistance composite dielectric layer; depositing an organic silicon-acrylate hybrid polymer stress relaxation layer to construct a gradient elastic modulus distribution feature; constructing a molecular scale interface fusion layer through a hot-press bonding process; and finally performing overall plastic encapsulation packaging; the self-assembled monolayer modification film is constructed on the surface of the chip, and the polyimide base dielectric layer and the nano heat-conducting composite layer are deposited, so that the effective thermal resistance of the dielectric layer and the chip interface is effectively reduced, the heat-conducting network formed by the nano heat-conducting filler improves the effective thermal conductivity of the dielectric layer compared with the thermal conductivity of the traditional organic dielectric layer material, and the heat management performance of the chip is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically a method for stacked packaging of memory chips. Background Technology

[0002] Bumpless stacked packaging technology abandons the solder bump interconnect structure of traditional flip chips, which can effectively reduce the stacked loop inductance of chips, alleviate internal thermomechanical stress, reduce circuit parasitic effects, and improve the overall working performance of microprocessor chips. It is the core research and development direction in the field of high-performance semiconductor device packaging. Existing bumpless stacked packaging processes generally use organic dielectric layers to achieve chip stacking interconnection and structural packaging, which can complete the stacking and basic interconnection fabrication of semiconductor chips and meet the packaging production and basic use requirements of conventional performance devices.

[0003] Existing organic dielectric layer filling encapsulation solutions have fundamental material compatibility defects. The large difference in thermal expansion coefficients between organic dielectrics and silicon wafers can easily lead to thermal stress concentration inside the package, inducing the initiation and propagation of microcracks at the dielectric layer interface, degrading the long-term electrical reliability of the device, and at the same time, insufficient thermal resistance control capability affects chip stacking density.

[0004] Therefore, the present invention provides a method for stacked packaging of memory chips. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0006] The technical solution adopted by this invention to solve its technical problem is: a stacked packaging method for memory chips, comprising the following steps: Step 1: Wafer-level chip pretreatment. The surface of the memory chip wafer is subjected to plasma activation treatment using oxygen plasma bombardment. The plasma bombardment power is set to 150 to 200 watts, and the duration is set to 30 to 60 seconds. The plasma treatment can generate a high density of hydroxyl functional groups on the chip surface, improving the wettability and chemical activity of the chip surface. Subsequently, a self-assembled monolayer modified film is formed on the chip surface. The self-assembled monolayer modified film is prepared using an amino-containing silane coupling agent solution. The silane coupling agent is 3-aminopropyltriethoxysilane. The thickness of the self-assembled monolayer modified film is controlled within the range of 1 to 3 nanometers. This modified film forms a uniform and dense molecular-level coating layer on the chip surface, providing a chemical anchoring interface with high surface energy for subsequent dielectric layer deposition, effectively enhancing the interfacial adhesion strength between the dielectric layer and the chip surface.

[0007] Step 2: Preparation and deposition of a low thermal resistance composite dielectric layer. A polyimide substrate dielectric layer and a nano-thermal conductive composite layer are sequentially formed on the surface of the modified chip. The polyimide substrate dielectric layer is prepared by spin coating. The spin coating speed is set to 800 to 1500 rpm, the spin coating duration is set to 20 to 40 seconds, the solid content of the polyimide precursor solution is controlled within the range of 15 to 25% (by weight), and the viscosity is controlled within the range of 500 to 3000 cm⁻¹. After spin coating, a pre-baking treatment is performed. The pre-baking temperature is set to 80 to 100 degrees Celsius, and the pre-baking time is set to 3 to 5 minutes. High-temperature curing is performed, with the curing temperature set at 250 to 300 degrees Celsius and the curing time set at 60 to 120 minutes. The final film thickness of the polyimide substrate dielectric layer is controlled within the range of 5 to 15 micrometers. The nano-thermal conductive composite layer is formed by dispersing nano-thermal conductive fillers in the polyimide matrix and then coating them. The nano-thermal conductive filler is made of spherical nano-silica particles or spherical nano-alumina particles. The particle size of the nanoparticles is controlled within the range of 50 to 200 nanometers. The amount of nano-thermal conductive filler added to the polyimide matrix is ​​controlled within the range of 15 to 25% (by weight). The thickness of the nano-thermal conductive composite layer is controlled within the range of 2 to 8 micrometers. The nano-thermal conductive filler forms a three-dimensional thermal conductive network structure in the polyimide matrix, improving the effective thermal conductivity of the dielectric layer to the range of 0.3 to 0.8 W / m Kelvin.

[0008] Step 3: Construct a gradient elastic modulus stress relaxation layer. Deposit a stress relaxation layer on the surface of the composite dielectric layer. The stress relaxation layer is prepared using an organosilicon-acrylate hybrid polymer material. This hybrid polymer material is prepared by the sol-gel method. Its molecular structure contains both organosilicon segments and acrylate segments. The organosilicon segments provide excellent flexibility and low elastic modulus characteristics, while the acrylate segments provide good adhesion and process adjustability. The stress relaxation layer was prepared by spin coating, with the spin coating speed set to 500 to 800 rpm and the spin coating duration set to 30 to 50 seconds. The wet film thickness of the stress relaxation layer was controlled within the range of 3 to 8 micrometers. After deposition, partial cross-linking curing was performed. The partial cross-linking curing temperature was set to 120 to 150 degrees Celsius and the partial cross-linking curing time was set to 10 to 20 minutes. The degree of partial cross-linking curing was precisely controlled within the range of 40 to 60%. The partial cross-linking treatment enabled the stress relaxation layer to form a gradient elastic modulus distribution, with the surface elastic modulus being higher than that of the underlying layer. This gradient modulus distribution can effectively absorb and relax the thermal mismatch stress between the dielectric layer and the chip interface during the subsequent hot-press bonding process.

[0009] Step 4: Perform chip stacking, thermo-press bonding, and interface fusion. Multiple chip layers are stacked on the surface of the chip after the stress relaxation layer has been prepared. A thermo-press bonding process is used to achieve interface fusion and reliable adhesion between the chip and the dielectric layer. The heating temperature for the thermo-press bonding process is set to 180 to 220 degrees Celsius, the bonding pressure is set to 0.5 to 2 MPa, the bonding duration is set to 30 to 60 minutes, and the thermo-press bonding heating rate is set to 2 to 5 degrees Celsius per second. During the thermo-press bonding process, the stress relaxation layer undergoes further cross-linking under thermo-press conditions. Simultaneously, the organosilicon segments in the stress relaxation layer undergo segmental movement and stress relaxation behavior, causing the dielectric layer material to soften and produce plastic flow, filling the microscopic gaps between the chip and the dielectric layer. Under thermo-press conditions, the polymer segments on both sides of the interface diffuse and entangle with each other, forming a molecular-scale interface fusion layer. The formation of this interface fusion layer eliminates the risk of microcrack initiation caused by interface stress concentration in traditional packaging processes.

[0010] Step 5: Perform overall molding and post-curing. On the substrate where the chips have been stacked and bonded, perform overall molding. The molding is done using epoxy molding compound for transfer molding. The transfer molding temperature is set to 170 to 190 degrees Celsius, the transfer molding pressure is set to 5 to 15 MPa, the molding duration is set to 2 to 5 minutes, and the epoxy molding compound filling rate is controlled to be no less than 99.5% (by weight). The molding compound is a special encapsulation material with low coefficient of thermal expansion and low shrinkage. After molding, post-curing treatment is performed. The post-curing temperature is set to 175 to 185 degrees Celsius, and the post-curing time is set to 4 to 8 hours. The post-curing treatment ensures that both the epoxy resin molding compound and the polyimide dielectric layer are fully cured. The degree of curing is controlled within a range of not less than 95%. After the post-curing treatment, the material is allowed to cool naturally to room temperature. During the cooling process, the internal temperature gradient of the encapsulation is strictly controlled to avoid generating secondary thermal stress.

[0011] Preferably, in the specific implementation of the nano-thermal conductive filler dispersion treatment, the nano-thermal conductive filler is dispersed in the polyimide precursor solution using an ultrasonic dispersion process. The ultrasonic dispersion power is set to 200 to 400 watts, and the ultrasonic dispersion duration is set to 15 to 30 minutes. During the dispersion process, low-speed magnetic stirring is used for assistance, and the stirring speed is set to 100 to 300 revolutions per minute. After dispersion, the composite system is subjected to vacuum degassing treatment, with the vacuum degree set to -0.08 to -0.1 MPa and the degassing duration set to 10 to 20 minutes. The dispersion uniformity of the nano-thermal conductive filler in the polyimide matrix is ​​characterized by dynamic light scattering particle size analysis. The agglomerate particle size is controlled within the range of no more than 500 nanometers, and the agglomerate content is controlled within the range of no more than 5% (by weight).

[0012] Preferably, in the specific implementation of preparing the organosilicon-acrylate hybrid polymer material, an acrylate prepolymer containing reactive silanol groups is first synthesized. The number-average molecular weight of the acrylate prepolymer is controlled within the range of 8,000 to 15,000, and the silanol content is controlled within the range of 0.5% to 2% (by weight). Subsequently, the acrylate prepolymer is subjected to an addition reaction with a hydrogen-containing silicone oil to obtain the hybrid polymer. The hydrogen content of the hydrogen-containing silicone oil is controlled within the range of 0.1% to 0.5% (by weight). During the reaction, the content of organosilicon segments in the hybrid polymer is adjusted by adjusting the mass ratio of the acrylate prepolymer to the hydrogen-containing silicone oil. The mass fraction of organosilicon segments is controlled within the range of 30% to 50% (by weight), the weight-average molecular weight of the hybrid polymer is controlled within the range of 20,000 to 50,000, and the molecular weight distribution index is controlled within the range of 1.5 to 2.5.

[0013] Preferably, in the specific implementation of optimizing the hot-press bonding process parameters, the temperature curve in the hot-press bonding process is set to a multi-segment temperature control mode. The first stage is the heating stage, with the heating rate set at 2 to 5 degrees Celsius per second, to raise the temperature to a bonding temperature of 180 to 220 degrees Celsius. The second stage is the heat preservation and pressure holding stage, where the heat preservation and pressure holding time is set to 30 to 60 minutes, and the bonding pressure remains constant throughout the heat preservation stage; The third stage is a slow cooling stage, with a cooling rate set at 1 to 3 degrees Celsius per second. The temperature is slowly reduced to below 100 degrees Celsius before air cooling. During the bonding process, the softening degree and fluidity of the dielectric layer material are monitored online. The energy storage modulus of the dielectric layer material is controlled within 5 to 20% of its original value at the bonding temperature.

[0014] Preferably, the overall process flow of the stacked packaging method for memory chips of the present invention follows a technical synergy mechanism as follows: Through plasma activation and self-assembly monolayer modification in step one, a high-energy chemical anchoring interface is established on the chip surface. This interface provides a reliable chemical bonding basis for subsequent dielectric layer deposition. The amino functional groups on the chip surface can react chemically with the carboxyl or anhydride groups in the polyimide precursor to form covalent bonds, thereby enhancing the interfacial adhesion strength. By depositing the polyimide substrate dielectric layer and the nano-thermal conductive composite layer in step two, a composite dielectric layer with high thermal conductivity is constructed on the chip surface. The three-dimensional thermal conductive network formed by the nano-thermal conductive filler in the polyimide matrix can effectively reduce the effective thermal resistance at the interface between the dielectric layer and the chip, providing an efficient channel for the conduction of chip heat to the outside of the package. The addition of the nano-filler also reduces the thermal expansion coefficient of the polyimide substrate dielectric layer, narrowing the difference in thermal expansion coefficient between the dielectric layer material and the chip material. By constructing the gradient elastic modulus stress relaxation layer in step three, a stress absorption layer with gradient modulus distribution characteristics is established on the surface of the composite medium layer. This stress relaxation layer continues to play the function of absorbing and relaxing thermal stress during the subsequent hot-press bonding and encapsulation process. Through thermal bonding and overall plastic encapsulation in steps four and five, reliable stacking of multilayer chips and construction of the overall package structure are completed.

[0015] The beneficial effects of this invention are as follows: 1. The stacked packaging method for memory chips described in this invention effectively reduces the effective thermal resistance at the interface between the dielectric layer and the chip by constructing a self-assembled monolayer modified thin film on the chip surface and depositing a polyimide substrate dielectric layer and a nano-thermal conductive composite layer. The thermally conductive network formed by the nano-thermal conductive filler improves the effective thermal conductivity of the dielectric layer compared with the thermal conductivity of traditional organic dielectric layer materials, which is beneficial to improving the thermal management performance of the chip. 2. The stacked packaging method for memory chips described in this invention constructs an organosilicon-acrylate hybrid polymer stress relaxation layer on the surface of a composite dielectric layer. The gradient elastic modulus distribution characteristics of this stress relaxation layer can effectively absorb and relax the thermal mismatch stress between the dielectric layer and the chip interface during chip stacking and package operation, reduce the peak stress at the interface, and help prevent cracks from forming or increasing at the dielectric layer interface. 3. The stacked packaging method for memory chips described in this invention optimizes the hot-press bonding process parameters to achieve further cross-linking of the stress relaxation layer and softening and flow of the dielectric layer material at the bonding temperature, thereby promoting mutual diffusion and entanglement of polymer chain segments on both sides of the interface to form a molecular-scale interface fusion layer, which helps to reduce the generation of cracks. 4. The stacked packaging method for memory chips described in this invention uses epoxy resin molding compound with low thermal expansion coefficient for overall plastic encapsulation and controls the post-curing process parameters to ensure that the materials of each layer inside the package are fully cured and that thermal stress is fully released, which is beneficial to improving the electrical performance of the device. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings.

[0017] Figure 1 This is a flowchart of a method for stacked packaging of a memory chip according to the present invention; Figure 2 This is a schematic diagram of the process flow framework for chip stacking thermal bonding and molecular-scale interface fusion in this invention. Detailed Implementation

[0018] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0019] Example 1: like Figure 1 and Figure 2 As shown, the present invention provides a method for stacked packaging of a memory chip, comprising: In step one, wafer-level chip preprocessing is performed, and plasma activation treatment is performed on the surface of the memory chip wafer. When the plasma activation treatment is carried out by oxygen plasma bombardment, the plasma treatment equipment is selected as a radio frequency plasma cleaner, the working frequency of the plasma generator is set to 13.56 MHz, and the plasma bombardment power is set to 150 to 200 watts, preferably 180 watts. The plasma density generated by the glow discharge is controlled within the range of 10⁹ to 10¹¹ ions per cubic centimeter, and the duration is set to 30 to 60 seconds, preferably 45 seconds. The oxygen flow rate is precisely controlled within the range of 20 to 50 standard cubic centimeters per minute, preferably 35 standard cubic centimeters per minute, and the chamber vacuum is set within the range of 50 to 200 Pa. During plasma treatment, high-energy oxygen ions bombard the silicon oxide layer or metal wiring layer on the chip surface, generating a high density of hydroxyl functional groups on the chip surface. The hydroxyl density is characterized as 15 to 25 hydroxyl sites per square nanometer. Plasma treatment improves the wettability of the chip surface, reducing the contact angle from 60 to 80 degrees before treatment to 5 to 15 degrees after treatment, and enhancing the chemical activity of the chip surface.

[0020] Subsequently, a self-assembled monolayer modified film is formed on the chip surface. The self-assembled monolayer modified film is prepared using an amino-containing silane coupling agent solution. The silane coupling agent selected is 3-aminopropyltriethoxysilane, whose molecular structure is H2N(CH2)3Si(OC2H5)3. The purity of 3-aminopropyltriethoxysilane is controlled to be no less than 98% (by weight). The specific preparation process of self-assembled monolayer modified thin films includes the following operations: 3-Aminopropyltriethoxysilane is dissolved in anhydrous ethanol to obtain a silane coupling agent solution. The mass fraction of the silane coupling agent is controlled in the range of 0.5% to 2% (by weight), preferably 1% (by weight). The solution preparation process is carried out in a dry glove box with a humidity of less than 5% relative humidity to prevent silane hydrolysis. The plasma-activated chip is immersed in a silane coupling agent solution for a time of 30 to 120 seconds, preferably 60 seconds, with the chip surface facing upwards during immersion to ensure uniform wetting of the solution. After immersion, a lifting operation is performed at a speed of 2 to 10 millimeters per second, preferably 5 millimeters per second. After the pulling process is completed, an annealing treatment is performed. The annealing temperature is set to 100 to 130 degrees Celsius, and the annealing time is set to 10 to 30 minutes. The annealing treatment allows the silane coupling agent molecules to complete self-assembly and arrangement on the chip surface and undergo partial condensation reaction. The thickness of the self-assembled monolayer modified film is controlled in the range of 1 to 3 nanometers, preferably 2 nanometers. This thickness is accurately measured by an elliptic polarization spectrometer, and the surface coverage of the film is controlled in the range of not less than 95%. The modified film forms a uniform and dense molecular-level coating layer on the chip surface. The amino functional groups in the self-assembled monolayer are oriented on the outer surface of the film, providing a chemical anchoring interface with high surface energy for subsequent dielectric layer deposition, effectively enhancing the interfacial adhesion strength between the dielectric layer and the chip surface.

[0021] In step two, a low thermal resistance composite dielectric layer is prepared and deposited, and a polyimide substrate dielectric layer and a nano-thermal conductive composite layer are sequentially formed on the surface of the chip after surface modification. The polyimide substrate medium layer is prepared by spin coating. The polyimide precursor solution is selected from the polyamic acid system, and its solid content is controlled in the range of 15 to 25% (by weight), preferably 20% (by weight), and its viscosity is controlled in the range of 500 to 3000 centipoise, preferably 1500 centipoise. The specific operation process of spin coating includes the following steps: The chip is fixed on the vacuum chuck of the spin coater, and the chip surface must be kept horizontal with the tilt angle controlled within 0.5 degrees. Spin coating is performed using a spin coater, with the coating speed set to 800 to 1500 rpm, preferably 1200 rpm, and the spin coating duration set to 20 to 40 seconds, preferably 30 seconds. During the spin coating process, the droplet speed is set to be fast at first and then slow to ensure uniform film thickness. After spin coating, a pre-baking process is performed on a hot plate. The pre-baking temperature is set to 80 to 100 degrees Celsius, preferably 90 degrees Celsius, and the pre-baking time is set to 3 to 5 minutes, preferably 4 minutes. The purpose of pre-baking is to remove residual solvent from the polyamic acid solution. High-temperature curing is performed in a nitrogen protective atmosphere. The curing temperature is set to 250 to 300 degrees Celsius, preferably 280 degrees Celsius, the curing time is set to 60 to 120 minutes, preferably 90 minutes, and the heating rate is set to 2 to 5 degrees Celsius per second. During the curing process, polyamic acid undergoes an imide reaction to transform into polyimide. The final film thickness of the polyimide substrate dielectric layer is controlled within the range of 5 to 15 micrometers, preferably 10 micrometers, and the film thickness uniformity is controlled within ±5%.

[0022] The nano-thermal conductive composite layer is formed by dispersing nano-thermal conductive fillers in a polyimide matrix and then coating it. The nano-thermal conductive fillers are selected from spherical nano-silica particles or spherical nano-alumina particles, and their particle size distribution is characterized by transmission electron microscopy. The average particle size of the nanoparticles is controlled in the range of 50 to 200 nanometers, preferably 100 nanometers, and the particle size distribution index is controlled in the range of 1.2 to 1.5. The amount of nano-thermal conductive fillers added to the polyimide matrix is ​​controlled in the range of 15 to 25% (by weight), preferably 20% (by weight). If the amount added is too low, the thermal conductive network will be difficult to form; if the amount added is too high, it will affect the mechanical strength and adhesion properties of the dielectric layer. The specific preparation process of the nano-thermal conductive composite layer includes the following operations: The nano-thermal conductive filler was mixed with the polyimide precursor solution in a planetary centrifugal mixer at a speed of 500 to 1000 rpm for 10 to 20 minutes. Ultrasonic dispersion is performed to break up the soft agglomeration of nanoparticles. The ultrasonic dispersion power is set to 200 to 400 watts, preferably 300 watts, and the ultrasonic dispersion duration is set to 15 to 30 minutes, preferably 20 minutes. Low-speed magnetic stirring is used to assist in the dispersion process. The stirring speed is set to 100 to 300 revolutions per minute, preferably 200 revolutions per minute. The purpose of magnetic stirring is to prevent the temperature gradient generated by the ultrasonic action from causing excessively high local concentrations. After dispersion, the composite system is subjected to vacuum degassing treatment. The vacuum degree is set to -0.08 to -0.1 MPa, preferably -0.095 MPa, and the degassing duration is set to 10 to 20 minutes, preferably 15 minutes. The dispersion uniformity of the nano-thermal conductive filler in the polyimide matrix was characterized by dynamic light scattering particle size analysis. The agglomerate particle size was controlled within the range of no more than 500 nm, preferably no more than 300 nm, and the agglomerate content was controlled within the range of no more than 5% (by weight), preferably no more than 3% (by weight). The coating of the nano-thermal conductive composite layer is carried out by spin coating process. The spin coating speed is set to 1000 to 2000 revolutions per minute, preferably 1500 revolutions per minute, and the spin coating duration is set to 20 to 40 seconds. After spin coating, the same pre-baking and high-temperature curing treatment as the polyimide substrate medium layer is performed. The thickness of the nano-thermal conductive composite layer is controlled within the range of 2 to 8 micrometers, preferably 5 micrometers; The nano-thermal conductive filler forms a three-dimensional thermally conductive network structure in the polyimide matrix. This thermally conductive network is verified by thermal conductivity testing. The effective thermal conductivity of the nano-thermal conductive composite layer at 25 degrees Celsius is improved to the range of 0.3 to 0.8 W / m Kelvin, preferably 0.5 W / m Kelvin, which is at least twice that of the thermal conductivity of pure polyimide material, which is 0.15 W / m Kelvin.

[0023] In step three, a gradient elastic modulus stress relaxation layer is constructed by depositing a stress relaxation layer on the surface of the composite dielectric layer. The stress relaxation layer is prepared using an organosilicon-acrylate hybrid polymer material, which is prepared by the sol-gel method and contains both organosilicon segments and acrylate segments in its molecular structure. The specific preparation process of organosilicon-acrylate hybrid polymer materials includes the following steps: An acrylate prepolymer containing reactive silanol groups is synthesized. The acrylate prepolymer is prepared by free radical polymerization. The reactive monomers are a mixture of butyl acrylate, hydroxyethyl acrylate, and glycidyl methacrylate, with a mass ratio of 60 to 80:10 to 20:5 to 15. The polymerization initiator is azobisisobutyronitrile (AIBN), and its addition amount is 0.1 to 0.5% (by weight) of the total monomer mass. The polymerization temperature is set to 60 to 80 degrees Celsius, and the reaction time is 4 to 8 hours. After the reaction is completed, unreacted monomers are removed by vacuum distillation. The number average molecular weight of the acrylate prepolymer is controlled in the range of 8,000 to 15,000, preferably 12,000. The silanol content is controlled in the range of 0.5 to 2% (by weight), preferably 1.2% (by weight). The silanol groups are introduced through silanol propyl methacrylate monomer. An acrylate prepolymer is added to a hydrogen-containing silicone oil to obtain a hybrid polymer. The hydrogen content of the hydrogen-containing silicone oil is controlled within the range of 0.1 to 0.5% (by weight), preferably 0.3% (by weight), and the viscosity of the hydrogen-containing silicone oil is controlled within the range of 50 to 200 centipoise. The addition reaction is catalyzed by a platinum catalyst, specifically a Karstedt catalyst, added at an amount of 50 to 100 ppm of the total mass of the reactants. The reaction temperature is controlled within the range of 60 to 100 degrees Celsius, and the reaction time is 2 to 4 hours. During the reaction, the content of organosilicon segments in the hybrid polymer is adjusted by regulating the mass ratio of the acrylate prepolymer to the hydrogen-containing silicone oil. The mass fraction of organosilicon segments is controlled within the range of 30 to 50% (by weight), preferably 40% (by weight). The weight-average molecular weight of the hybrid polymer is controlled within the range of 20,000 to 50,000, preferably 35,000, and the molecular weight distribution index is controlled within the range of 1.5 to 2.5, preferably 2.0.

[0024] Silicone segments offer excellent flexibility and low elastic modulus, with their glass transition temperature controlled within the range of -60 to -80 degrees Celsius. Acrylic segments provide good adhesion and process adjustability. The stress relaxation layer is prepared by spin coating. The specific operation process includes the following steps: First, the hybrid polymer is dissolved in an organic solvent to obtain a stress relaxation layer coating solution. The organic solvent is a mixture of ethyl acetate and isopropanol with a mass ratio of 7 to 3. The mass fraction of the hybrid polymer is controlled within the range of 10 to 20% (by weight), preferably 15% (by weight). The solution is dropped onto the surface of the composite medium layer, the spin coating speed is set to 500 to 800 revolutions per minute, preferably 600 revolutions per minute, the spin coating duration is set to 30 to 50 seconds, preferably 40 seconds; the wet film thickness of the stress relaxation layer is controlled in the range of 3 to 8 micrometers, preferably 5 micrometers; After deposition, partial cross-linking and curing treatment is performed. The partial cross-linking and curing temperature is set to 120 to 150 degrees Celsius, preferably 135 degrees Celsius. The partial cross-linking and curing time is set to 10 to 20 minutes, preferably 15 minutes. The degree of partial cross-linking and curing is precisely controlled within the range of 40% to 60%, preferably 50%. The degree of partial cross-linking curing was monitored by Fourier transform infrared spectroscopy, and the degree of cross-linking was calculated by the change in the area of ​​characteristic absorption peaks. The partial cross-linking treatment resulted in a gradient elastic modulus distribution in the stress relaxation layer, with the surface elastic modulus being higher than that of the underlying layer. The surface elastic modulus was controlled within the range of 200 to 500 MPa, and the underlying elastic modulus was controlled within the range of 20 to 80 MPa. This gradient modulus distribution can effectively absorb and relax the thermal mismatch stress between the dielectric layer and the chip interface during the subsequent hot-press bonding process.

[0025] In step four, chip stacking hot-press bonding and interface fusion are performed. Multi-layer chip stacking is performed on the chip surface after the stress relaxation layer is prepared. Hot-press bonding process is used to achieve interface fusion and reliable bonding between the chip and the dielectric layer. The heating temperature of the hot-press bonding process is set to 180 to 220 degrees Celsius, preferably 200 degrees Celsius; the bonding pressure is set to 0.5 to 2 MPa, preferably 1.2 MPa; the bonding duration is set to 30 to 60 minutes, preferably 45 minutes; and the hot-press bonding heating rate is set to 2 to 5 degrees Celsius per second, preferably 3 degrees Celsius per second.

[0026] The temperature profile during the hot-press bonding process is set to a multi-segment temperature control mode: The first stage is the heating stage, with the heating rate set at 2 to 5 degrees Celsius per second, to raise the temperature to a bonding temperature of 180 to 220 degrees Celsius. The second stage is the heat preservation and pressure holding stage, where the heat preservation and pressure holding time is set to 30 to 60 minutes, and the bonding pressure remains constant throughout the heat preservation stage; The third stage is a slow cooling stage, with a cooling rate set at 1 to 3 degrees Celsius per second. The temperature is slowly reduced to below 100 degrees Celsius before air cooling is performed. During the bonding process, the softening degree and fluidity of the dielectric layer material are monitored online. The energy storage modulus of the dielectric layer material is controlled within 5% to 20% of its original value at the bonding temperature, preferably 10%, indicating that the dielectric layer is in a highly elastic state and has excellent fluidity at the bonding temperature.

[0027] During the hot-press bonding process, the stress relaxation layer undergoes a further cross-linking reaction under hot-press conditions, and its degree of cross-linking increases from 50% to 80 to 95%. At the same time, the organosilicon segments in the stress relaxation layer undergo segment movement and stress relaxation behavior, and the segment relaxation time is controlled within the range of 10 to 100 seconds. The low glass transition temperature of organosilicon segments gives them excellent segmental mobility at bonding temperatures, enabling them to respond quickly to stress changes and undergo stress relaxation. The stress relaxation behavior of organosilicon segments can be described by the following formula: , where σ(t) represents the relationship between stress and time, σ0 represents the initial stress, τ represents the stress relaxation time constant, and t represents time; It can represent the characteristic that the stress of organosilicon segments decays exponentially with time under constant strain conditions.

[0028] The softening of the stress relaxation layer causes the dielectric material to soften and generate plastic flow, filling the micro gaps between the chip and the dielectric layer. The size of the filled micro gaps ranges from 1 to 500 nanometers. Under hot-pressing conditions, the polymer chain segments on both sides of the interface diffuse and entangle with each other, forming a molecular-scale interface fusion layer. The thickness of the interface fusion layer is controlled within the range of 10 to 50 nanometers. The formation of this interface fusion layer eliminates the risk of microcrack initiation caused by interface stress concentration. The hot-press bonding process is carried out using specialized hot-press bonding equipment, which has precise temperature and pressure control functions. The temperature control accuracy is set to ±2 degrees Celsius, and the pressure control accuracy is set to ±0.05 MPa.

[0029] In step five, overall molding and post-curing are performed. Overall molding is performed on the substrate after chip stacking and bonding. The molding process uses epoxy resin molding compound for transfer molding. The epoxy resin molding compound is a special packaging material with low coefficient of thermal expansion and low shrinkage. Its coefficient of thermal expansion is controlled in the range of 10 to 20 ppm per degree Celsius, preferably 15 ppm per degree Celsius. The glass transition temperature of the molding compound is controlled in the range of 150 to 170 degrees Celsius. The filling rate of the molding compound is controlled in the range of not less than 99.5% (by weight), preferably 99.8% (by weight). The transfer molding temperature is set to 170 to 190 degrees Celsius, preferably 180 degrees Celsius, the transfer molding pressure is set to 5 to 15 MPa, preferably 10 MPa, and the molding duration is set to 2 to 5 minutes, preferably 3 minutes. During the molding process, the epoxy resin molding compound fills the encapsulation cavity and covers the chip stack structure under the action of heating and pressure. After molding, post-curing treatment is performed. The post-curing temperature is set to 175 to 185 degrees Celsius, preferably 180 degrees Celsius, and the post-curing time is set to 4 to 8 hours, preferably 6 hours. Post-curing treatment ensures that both the epoxy resin molding compound and the polyimide medium layer are fully cured, with the degree of curing controlled within a range of not less than 95%, preferably 98%. The degree of curing is determined by Fourier transform infrared spectroscopy or differential scanning calorimetry. After the post-curing process is completed, the contents are allowed to cool naturally to room temperature. During the cooling process, the internal temperature gradient of the encapsulation is strictly controlled to avoid generating secondary thermal stress, and the cooling rate is controlled within the range of 1 to 3 degrees Celsius per second.

[0030] In the specific implementation of the stacked packaging method for memory chips, the overall process technology coordination mechanism follows the following technical process: through the plasma activation and self-assembly monolayer modification treatment in step one, a high-energy chemical anchoring interface is established on the chip surface. This interface provides a reliable chemical bonding basis for subsequent dielectric layer deposition. The amino functional groups on the chip surface can react chemically with the carboxyl or anhydride groups in the polyimide precursor to form covalent bonds, thereby enhancing the interface adhesion strength. By depositing the polyimide substrate dielectric layer and the nano-thermal conductive composite layer in step two, a composite dielectric layer with high thermal conductivity is constructed on the chip surface. The three-dimensional thermal conductive network formed by the nano-thermal conductive filler in the polyimide matrix can effectively reduce the effective thermal resistance at the interface between the dielectric layer and the chip, providing an efficient channel for the conduction of chip heat to the outside of the package. The addition of the nano-filler also reduces the thermal expansion coefficient of the polyimide substrate dielectric layer, narrowing the difference in thermal expansion coefficient between the dielectric layer material and the chip material. Furthermore, through the construction of the gradient elastic modulus stress relaxation layer in step three, a stress absorption layer with gradient modulus distribution characteristics is established on the surface of the composite dielectric layer. This stress relaxation layer continues to play the function of absorbing and relaxing thermal stress during the subsequent hot-press bonding and encapsulation process. Finally, through the hot-press bonding and overall plastic encapsulation in steps four and five, the reliable stacking of multilayer chips and the construction of the overall encapsulation structure are completed.

[0031] Example 2: Embodiment 2 of the present invention takes the multi-layer stacked packaging of 128-layer 3D NAND flash memory chips as a specific application example.

[0032] When performing multi-layer stacked packaging of 128-layer 3D NAND flash memory chips, a memory chip wafer is selected as the substrate to be packaged. The wafer diameter is 300 mm and the chip thickness is 50 to 100 micrometers, preferably 75 micrometers. The wafer surface undergoes chemical mechanical polishing, and the surface roughness is controlled within 0.5 nanometers root mean square value. The thickness of the oxide layer on the wafer surface is 100 to 500 nanometers.

[0033] The surface of the memory chip wafer is subjected to plasma activation treatment; the plasma treatment equipment selected is a domestic ZEP-800 radio frequency plasma cleaner with a working frequency of 13.56 MHz and a maximum output power of 500 watts. The process parameters for plasma activation treatment were set as follows: bombardment power 180 watts, duration 45 seconds, oxygen flow rate 35 standard cubic centimeters per minute, and chamber vacuum degree 100 Pa. After plasma treatment, the contact angle of the chip surface was measured by a contact angle meter, which showed that the contact angle decreased from 72 degrees before treatment to 8 degrees after treatment, confirming that the surface wettability was improved. X-ray photoelectron spectroscopy analysis confirmed that hydroxyl functional groups were successfully introduced into the chip surface, and the oxygen-carbon atom ratio increased from 0.5 before treatment to 1.2 after treatment.

[0034] A self-assembled monolayer modified film is formed on the chip surface; 3-aminopropyltriethoxysilane is dissolved in anhydrous ethanol to prepare a 1% (by weight) silane coupling agent solution; the plasma-activated chip is immersed in the solution for 60 seconds. The lifting process is carried out at a lifting speed of 5 mm per second, and after the lifting is completed, it is annealed at 120 degrees Celsius for 15 minutes to complete the self-assembly process; The thickness of the self-assembled monolayer modified film was determined to be 2.1 nm using elliptic polarization spectroscopy, with a surface coverage of 97.5%. The surface morphology of the thin film was observed using atomic force microscopy, confirming that the root mean square roughness of the thin film surface was 0.3 nanometers.

[0035] Preparation and deposition of low thermal resistance composite dielectric layers; The polyimide substrate dielectric layer is spin-coated using a polyamic acid precursor solution with a solid content of 20% (by weight) and a viscosity of 1500 centipoise. The spin coating speed is set to 1200 rpm, and the spin coating time is 30 seconds. Set the pre-baking temperature to 90 degrees Celsius and the time to 4 minutes; The high-temperature curing temperature is set to 280 degrees Celsius, the time is 90 minutes, the heating rate is 3 degrees Celsius per second, and the curing atmosphere is nitrogen. After curing, the thickness of the polyimide substrate dielectric layer was measured to be 10.2 micrometers, and the film thickness uniformity was ±4%. The film thickness was measured using a stylus profilometer.

[0036] The nano-thermal conductive composite layer uses spherical nano-alumina particles as thermal conductive fillers. The average particle size of the nanoparticles is 100 nanometers, and the particle size distribution index is 1.3. Nano-alumina particles were mixed with a polyimide precursor solution and dispersed using an ultrasonic dispersion process. The ultrasonic dispersion power was 300 watts and the time was 20 minutes. During the dispersion process, magnetic stirring at 200 revolutions per minute was used for assistance. After dispersion, vacuum degassing was performed at a vacuum degree of -0.095 MPa for 15 minutes. The average particle size of the agglomerates was determined to be 280 nm by dynamic light scattering particle size analysis, and the agglomerate content was 2.5% (by weight); the amount of nano thermally conductive filler added was 20% (by weight); the spin coating speed was 1500 rpm and the time was 30 seconds. The same pre-baking and curing process as the base dielectric layer is performed; the thickness of the nano-thermal conductive composite layer is 5.1 micrometers, and the effective thermal conductivity is 0.52 W / m Kelvin as measured by a laser thermal conductivity meter, which is about 3.5 times higher than the thermal conductivity of pure polyimide material of 0.15 W / m Kelvin.

[0037] The gradient elastic modulus stress relaxation layer was constructed. In the preparation of the organosilicon-acrylate hybrid polymer, the number average molecular weight of the acrylate prepolymer was 12,000, the silanol content was 1.2% (by weight), the hydrogen content of the hydrogen-containing silicone oil was 0.3% (by weight), the amount of platinum catalyst added was 80 ppm, the reaction temperature was 80 degrees Celsius, and the reaction time was 3 hours. The mass fraction of organosilicon segments is 40% (by weight), the weight-average molecular weight of the hybrid polymer is 35,000, and the molecular weight distribution index is 2.0; the solid content of the stress relaxation layer coating liquid is 15% (by weight), the spin coating speed is 600 rpm, the time is 40 seconds, and the wet film thickness is 5 micrometers. The partial cross-linking curing temperature was 135 degrees Celsius, the time was 15 minutes, and the degree of cross-linking was 50%. After curing, the gradient elastic modulus distribution of the stress relaxation layer was measured by a nanoindenter. The elastic modulus of the surface layer was 350 MPa, and the elastic modulus of the bottom layer was 45 MPa.

[0038] Perform chip stacking, thermal bonding, and interface fusion; Four chips with completed stress relaxation layers were stacked and bonded using a hot-press bonding process. The hot-press bonding temperature curve adopts a multi-stage temperature control mode. During the heating stage, the heating rate is 3 degrees Celsius per second, and the temperature is raised to 200 degrees Celsius for bonding. During the heat preservation and pressure preservation stage, the bonding pressure is 1.2 MPa and the heat preservation time is 45 minutes. During the cooling phase, the cooling rate is 2 degrees Celsius per second. After the temperature drops below 100 degrees Celsius, air cooling is performed. During the bonding process, the storage modulus of the dielectric layer material was monitored online using a rheometer. The storage modulus at the bonding temperature was 10% of the original value at room temperature, indicating that the dielectric layer was in a highly elastic state and had excellent fluidity. After the bonding was completed, the interface state was observed using a scanning acoustic microscope to confirm that the interface fusion layer had formed and that there were no voids or microcracks on the interface.

[0039] The epoxy molding compound undergoes overall plastic encapsulation and post-curing treatment; its coefficient of thermal expansion is 15 ppm per degree Celsius, its glass transition temperature is 160 degrees Celsius, and its filler content is 99.8% (by weight). The transfer molding temperature was 180 degrees Celsius, the pressure was 10 MPa, and the time was 3 minutes; the post-curing temperature was 180 degrees Celsius, the time was 6 hours, and the degree of curing was 98%. The cooling rate during natural cooling is 2 degrees Celsius per second.

[0040] After packaging, reliability testing was conducted. The test results showed that the chip's operating junction temperature was reduced by 20 degrees Celsius compared to traditional packaging solutions, the interface peak stress was reduced by 60%, and the interface defect rate was 0.08% (by weight) after 260 reflow soldering tests.

[0041] Example 3: Embodiment 3 of the present invention uses the multi-layer stacked packaging of 256-layer 3D NAND flash memory chips as an application example of an alternative technical solution to further illustrate the memory chip stacked packaging method of the present invention.

[0042] When performing multi-layer stacking packaging of 256-layer 3D NAND flash memory chips, the chip thickness is further reduced to 50 to 60 micrometers to achieve higher stacking density. In this embodiment, a chip with a thickness of 50 micrometers is selected.

[0043] The plasma activation treatment parameters were optimized to a bombardment power of 200 watts, a duration of 50 seconds, an oxygen flow rate of 40 standard cubic centimeters per minute, a chamber vacuum of 80 Pa, and a contact angle reduced to 6 degrees after treatment. The self-assembled monolayer modified film was prepared by using 3-aminopropyltriethoxysilane in a 2% (by weight) solution to enhance the film coverage. The immersion time was extended to 90 seconds, the annealing temperature was 130 degrees Celsius, the annealing time was 20 minutes, the film thickness was 2.8 nm, and the surface coverage was increased to 98.5%.

[0044] The polyimide substrate dielectric layer uses a high-concentration precursor solution with a solid content of 25% (by weight) to obtain a thicker dielectric layer. The spin coating speed is reduced to 800 rpm to increase the film thickness, the spin coating time is 40 seconds, the pre-baking temperature is 100 degrees Celsius and the time is 5 minutes, and the high-temperature curing temperature is 300 degrees Celsius and the time is 120 minutes to ensure sufficient imidization. The dielectric layer thickness is increased to 15 micrometers to meet the stress buffering requirements of thinner chips.

[0045] The nano-thermal conductive composite layer uses spherical nano-silica particles as thermal conductive fillers, with a particle size of 75 nanometers to enhance the formation efficiency of the thermal conductive network. The amount of nano thermally conductive filler added was increased to 25% (by weight) to maximize thermal conductivity, the spin coating speed was increased to 2000 rpm to control film thickness, and the composite layer thickness was controlled at 8 micrometers. The effective thermal conductivity test result is 0.78 W / m Kelvin, which is more than 5 times higher than that of traditional packaging solutions.

[0046] The content of organosilicon segments in the organosilicon-acrylate hybrid polymer is increased to 50% (by weight) to enhance the stress relaxation effect, and the weight-average molecular weight of the hybrid polymer is increased to 50,000 to improve mechanical properties. The wet film thickness of the stress relaxation layer was increased to 8 micrometers to adapt to more complex stress environments; the partial crosslinking curing temperature was increased to 150 degrees Celsius, and the degree of crosslinking was precisely controlled at 60% to obtain a more optimized gradient modulus distribution; The surface elastic modulus is increased to 500 MPa, while the underlying elastic modulus is controlled at 80 MPa to obtain a larger modulus gradient.

[0047] Hot-press bonding employs a higher bonding temperature of 220 degrees Celsius and a bonding pressure of 1.5 MPa to accommodate an 8-micron thick stress-relaxation layer, and the bonding time is extended to 60 minutes to ensure full interface fusion.

[0048] At the bonding temperature, the energy storage modulus of the dielectric layer material is controlled at 5% of its original value to achieve maximum softening flow.

[0049] The package reliability test results show that the chip operating junction temperature decreased by 25 degrees Celsius, the interface peak stress decreased by 70%, and the interface defect rate of the package was controlled below 0.05% (by weight) after 260 reflow soldering tests.

[0050] Comparative example: This comparative example is a conventional memory chip stacked packaging scheme that uses a single organic dielectric layer to achieve bumpless chip stacking interconnection. The process differs from that of the present invention in that the chip pretreatment stage only performs conventional surface cleaning, does not perform plasma activation treatment, and does not prepare self-assembled monolayer modified films. The dielectric layer adopts a pure polyimide single-layer structure, without doping with nano thermally conductive fillers, and does not construct a low thermal resistance composite dielectric layer; No separate silicone-acrylate hybrid polymer stress relaxation layer is provided, and no gradient elastic modulus adjustment is performed; Hot-press bonding uses a conventional constant temperature and pressure process, without setting up a multi-stage temperature control process, and does not actively induce the formation of a molecular-scale interface fusion layer; after molding and curing, conventional process parameters are used, without controlling the degree of curing or the cooling rate.

[0051] The following is a comparison table of the embodiments of the present invention and the prior art: Table 1: Comparison of Embodiments of the Invention with Comparative Examples As can be seen, the multifunctional packaging interface technology solution of the present invention, which adopts self-assembled monolayer modification, nano-thermal conductive filler doping and gradient modulus stress relaxation layer synergistic integration, is superior to the traditional packaging comparison solution that does not adopt the above modification and gradient structure in terms of various indicators such as effective thermal conductivity of dielectric layer, reduction of chip working junction temperature, reduction of interface peak stress, interface defect rate after reflow soldering, gradient modulus ratio of stress relaxation layer and compatibility with hot pressing bonding process. The third embodiment of this invention (0.78 W / (m·K) thermal conductivity, 2.8 nm self-assembled layer, 25 wt% nanofiller, 50 wt% stress relaxation layer silicon content and 6.3 gradient modulus) achieves a 25°C reduction in chip junction temperature, a 70% reduction in interface stress, and a defect rate of only 0.05% after 260 reflow soldering cycles, demonstrating the best overall performance. Compared with Example 1, Example 2 demonstrates the synergistic effect of three factors: self-assembled monolayer nanoscale thickness control, effective construction of thermally conductive pathways by nano-thermal fillers, and efficient buffering of thermal mismatch stress by gradient modulus stress relaxation layer. Combined with optimized hot-press bonding temperature and post-curing treatment, this improves the heat dissipation performance, reliability, and process compatibility of power device packaging.

[0052] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for stacked packaging of a memory chip, comprising the following steps: Step 1: Perform plasma activation treatment on the surface of the memory chip wafer; Step 2: Form a self-assembled monolayer modified film on the chip surface; A polyimide substrate dielectric layer and a nano-thermal conductive composite layer are sequentially formed on the chip surface; Step 3: Deposit a stress relaxation layer on the surface of the composite dielectric layer; Step 4: Use a hot-press bonding process to achieve chip stacking and interface fusion; Step 5: Use transfer molding process to perform overall plastic encapsulation and post-curing treatment.

2. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The nano-thermal conductive filler was dispersed in a polyimide precursor solution using an ultrasonic dispersion process aided by low-speed magnetic stirring. After dispersion, vacuum degassing was performed.

3. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The agglomerate particle size of the nano-thermal conductive filler in the polyimide matrix is ​​controlled to be within the range of no more than 500 nanometers.

4. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The organosilicon-acrylate hybrid polymer material was prepared by the sol-gel method, and its molecular structure contains organosilicon segments and acrylate segments.

5. The method for stacked packaging of a memory chip according to claim 4, characterized in that, In the organosilicon-acrylate hybrid polymer material, the mass fraction of organosilicon segments is controlled within the range of 30% to 50% (by weight).

6. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The stress relaxation layer undergoes partial cross-linking and curing treatment, which gives the stress relaxation layer a gradient elastic modulus distribution characteristic, with the surface elastic modulus being higher than the bottom elastic modulus.

7. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The hot-press bonding process adopts a multi-stage temperature control mode, including a heating stage, a heat preservation and pressure holding stage, and a slow cooling stage. The heating rate was set to 2 to 5 degrees Celsius per second, the bonding pressure was set to 0.5 to 2 MPa, and the bonding duration was set to 30 to 60 minutes.

8. The method for stacked packaging of a memory chip according to claim 1, characterized in that, The composite dielectric layer includes a polyimide substrate dielectric layer and a nano-thermal conductive composite layer; Nano-thermal conductive fillers form a three-dimensional thermally conductive network structure in a polyimide matrix; The polyimide substrate medium layer is prepared by spin coating, and after spin coating, it undergoes pre-baking and curing treatment.

9. The method for stacked packaging of a memory chip according to claim 1, characterized in that, Under hot-press bonding conditions, the polymer chain segments on both sides of the interface diffuse and entangle with each other, forming a molecular-scale interface fusion layer. The interface fusion layer is formed when the stress relaxation layer undergoes a cross-linking reaction under hot-pressing conditions, while the organosilicon segments in the stress relaxation layer undergo segment movement and stress relaxation behavior, and the dielectric layer material undergoes softening and flow.

10. A method for stacked packaging of a memory chip according to claim 1, characterized in that, The transfer molding uses epoxy resin molding compound; after molding, post-curing treatment is performed to cure the epoxy resin molding compound and the polyimide medium layer.

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