Low temperature hybrid bonded multilayer 3D package structure and fabrication process

Abstract

This invention discloses a low-temperature hybrid bonding multilayer 3D stacked packaging structure and its fabrication process. The structure, from top to bottom, includes a top functional chip array, a first TSV interposer, a second TSV interposer, and a bottom substrate. Both the first and second TSV interposers have vertically penetrating TSV vias, which are filled with conductive metal material to achieve vertical electrical conduction between layers. The upper and lower surfaces of the TSV vias in the first TSV interposer are provided with gold-plated pads. The low-temperature hybrid bonding multilayer 3D stacked packaging structure and fabrication process disclosed in this invention solves the defects of existing technologies, such as high multilayer stacking process temperatures, easy remelting and short circuits at the top chip solder joints, low solder joint mechanical strength, high package warpage stress, and high production costs.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor 3D stacked packaging technology, specifically relating to low-temperature hybrid bonding multilayer 3D stacked packaging structure and its fabrication process. Background Technology

[0002] With the continuous development of multi-chip high-density integration technology, three-layer and above 3D stacked packaging is being used more and more widely in the semiconductor field. Currently, mainstream multilayer hybrid stacking processes have many technical shortcomings: Top-level multi-chip horizontal arrays typically use flip-chip solder connections. Due to the wide variety of chips, flip-chip operations need to be performed in batches. Adjacent chips and interconnect structures within the same module will be repeatedly subjected to heating processes, making the solder joints prone to remelting, which can lead to short circuits and open circuits.

[0003] According to Appendix 5.3.6 of the IPC International Electronic Packaging Standard (IPC / JEDECJ-STD-020D) <Reflow Temperature Specifications for Humidity-Sensitive Devices, and Temperature Margin Requirements for Multi-Level Rework / Step-by-Step Reflow>, when a device or solder joint undergoes a second / subsequent step-by-step reflow process, the peak temperature of the subsequent reflow should be at least 35°C lower than the solidus temperature of the preceding solder. A safety margin of 40°C is recommended for mass production to compensate for reflow oven temperature fluctuations, localized temperature differences in the device, and deviations in solder alloy composition. Therefore, when using high- and low-temperature solder balls in a graded reflow stack with two or more layers, to avoid secondary melting of the solder joints, the interlayer temperature difference needs to be at least 35-40°C. The more layers stacked, the higher the top layer soldering temperature, which can easily damage the chip's optical structure. Simultaneously, high temperatures can cause package warpage and excessive internal stress.

[0004] Furthermore, the solder joints of pure tin ball reflow bonding lack a rigid support structure, making them prone to collapse and bridging short circuits after the solder melts. This results in low interconnect mechanical strength and poor reliability under long-term thermal cycling conditions. While the copper pillar tin cap structure commonly used in the industry can achieve rigid support, its fabrication requires complex processes such as photolithography and electroplating, leading to high production costs. Moreover, it is not compatible with existing conventional bonding equipment, resulting in poor mass production applicability. Summary of the Invention

[0005] The main objective of this invention is to provide a low-temperature hybrid bonding multilayer 3D stacked packaging structure and fabrication process, addressing the shortcomings of existing technologies such as high process temperatures in multilayer stacking, easy remelting and short circuits at the top-layer chip solder joints, low solder joint mechanical strength, high package warpage stress, and high production costs. This invention employs a composite stacking scheme involving top-layer gold ball thermo-ultrasonic bonding, mid-layer medium-temperature solder ball reflow, and bottom-layer low-temperature solder ball reflow. The maximum process temperature throughout does not exceed 200°C, making it suitable for various high-temperature-sensitive optoelectronic chips. Gold ball bumps serve as rigid supports, forming embedded, encapsulated solder joints with the solder balls, improving interconnect reliability. Simultaneously, it is compatible with existing production equipment, simplifying the process flow and reducing mass production costs.

[0006] To achieve the above objectives, this invention provides a low-temperature hybrid bonding multilayer 3D stacked packaging structure, which, from top to bottom, comprises a top functional chip array, a first TSV interposer, a second TSV interposer, and a bottom carrier substrate, wherein: Both the first TSV interposer and the second TSV interposer have vertically penetrating TSV vias inside, and the TSV vias are filled with a metal conductive material to achieve vertical electrical conduction between layers. The upper surface of the TSV via of the first TSV interposer is provided with gold-plated pads, and the lower surface is provided with gold-plated pads; the upper surface of the TSV via of the second TSV interposer is provided with gold-plated pads, and the lower surface is provided with a metal redistribution layer. Each chip in the top-level functional chip array has a first gold ball bump at its bottom, which is interconnected with the gold-plated pads on the upper surface of the first TSV interposer layer by thermo-ultrasonic bonding. The gold-plated pads on the lower surface of the first TSV interposer are provided with first solder balls, and the gold-plated pads on the upper surface of the second TSV interposer are provided with second gold ball bumps. After the first solder ball melts, it wraps around the corresponding second gold ball bump to form an embedded wrapping solder joint. The metal redistribution layer on the lower surface of the second TSV interposer is implanted with a second solder ball, and the bottom substrate pad is provided with a third gold ball bump. After the second solder ball melts, it wraps around the corresponding third gold ball bump to form an embedded wrapping solder joint.

[0007] As a further preferred embodiment of the above technical solution, the first gold ball protrusion is an irregular cylindrical structure with a diameter of 50μm.

[0008] As a further preferred embodiment of the above technical solution, the first solder ball has a composition of Sn90Zn7Bi3 and a reflow peak temperature of 200℃; the second solder ball has a composition of Sn58Bi and a reflow peak temperature of 160℃.

[0009] As a further preferred technical solution to the above technical solution, filler adhesive is provided between the interconnection areas of each layer to enhance the overall structural strength of the encapsulation.

[0010] To achieve the above objectives, the present invention also provides a fabrication process for a low-temperature hybrid bonding multilayer 3D stacked packaging structure, characterized by comprising the following steps: Step S1: Prepare the first TSV interposer layer, fabricate TSV through-silicon vias inside a substrate and complete metallization filling, and prepare gold-plated pads on the upper and lower surfaces of the substrate to obtain the first TSV interposer layer; Step S2: Prepare a second TSV interposer, fabricate TSV through-silicon vias inside another substrate and complete metallization filling, prepare gold-plated pads on the upper surface of the substrate and prepare a metal redistribution layer on the lower surface to obtain the second TSV interposer. Step S3: Fabricate the first gold ball bump on the bonding surface of each top-level functional chip; Step S4: Using an ultrasonic flip-chip device, multiple top-level functional chips with first gold ball bumps are sequentially thermo-ultrasonic bonded to the gold-plated pads on the upper surface of the first TSV interposer to form a top-level functional chip array. Step S5: Fabricate the first solder ball on the gold-plated pad on the lower surface of the first TSV interposer layer; Step S6: Prepare a second gold ball bump on the gold-plated pad on the upper surface of the second TSV interposer layer; Step S7: The product obtained in step S5 is subjected to formic acid heating pretreatment, and then aligned and pressed with the second TSV interlayer under vacuum. The first solder ball is melted by vacuum reflow, and the second gold ball bump is wrapped to form an embedded wrapped solder joint, thus obtaining a multi-layer composite structure. Step S8: Fabricate a second solder ball on the metal redistribution layer pad on the lower surface of the second TSV interposer; Step S9: Fabricate a third gold ball bump on the pads of the bottom carrier substrate; Step S10: The product obtained in step S8 is subjected to formic acid heating pretreatment, and then aligned and pressed with the bottom substrate under vacuum. The second solder ball is melted by vacuum reflow, and the third gold ball bump is wrapped to form an embedded encapsulation solder joint, thus completing the multi-layer 3D stacked packaging.

[0011] As a further preferred technical solution to the above technical solution, the thermo-ultrasonic bonding process parameters in step S4 are: temperature 180℃, ultrasonic power 8W, and bonding time 800ms.

[0012] As a further preferred technical solution to the above technical solution, the vacuum reflux curve in step S7 is as follows: the temperature is increased from room temperature to 150℃ at a heating rate of 2℃ / s for 75s; the temperature is held at 150℃ for 80s; the temperature is then increased to 200℃ at a heating rate of 2℃ / s for 20s; the temperature is held at 200℃ for 30s; and finally the temperature is reduced to room temperature at a cooling rate of 2℃ / s for 300s. The vacuum reflux curve in step S10 is as follows: the temperature is increased from room temperature to 110℃ at a rate of 2℃ / s for 40s; the temperature is held at 110℃ for 80s; the temperature is then increased to 160℃ at a rate of 2℃ / s for 15s; the temperature is held at 160℃ for 30s; and finally the temperature is reduced to room temperature at a rate of 2℃ / s for 200s.

[0013] As a further preferred technical solution to the above technical solution, in steps S5 and S8, the solder balls are prepared by laser ball implantation or electroplating ball implantation; in steps S3, S6 and S9, the gold ball bumps are processed and formed by gold ball bonding equipment.

[0014] As a further preferred technical solution to the above technical solution, after the stacked packaging is completed, filler glue is provided in the interconnection gaps of each layer to enhance the overall structural strength of the packaging.

[0015] The beneficial effects of this invention are as follows: 1. Completely solve the problem of solder joint remelting: The top-layer chip array adopts gold ball thermo-ultrasonic bonding process. The subsequent middle and bottom layer reflow processes will not have a thermal impact on the top-layer interconnect structure, completely avoiding the risk of solder joint remelting, short circuit, and open circuit caused by multiple heating.

[0016] 2. Low-temperature process throughout to protect the thermal chip: The highest temperature of the entire process is only 200℃, abandoning the traditional multi-layer stacking and step-by-step heating mode, which greatly reduces package warpage and internal stress, and can be adapted to various high-temperature resistant optoelectronic chips and humidity-sensitive devices.

[0017] 3. Reliable solder joint structure and long service life: The gold ball bumps serve as a rigid support structure, preventing the solder balls from collapsing and bridging short circuits after melting; the solder balls wrap around the gold balls to form embedded interlocking solder joints, resulting in high interconnect strength, excellent vibration resistance and thermal cycling resistance, and significantly improved reliability over long-term use.

[0018] 4. Strong process compatibility and low mass production cost: Gold ball bumps and thermo-ultrasonic bonding can be directly processed using existing conventional equipment in the industry, without the need to introduce complex and high-cost processes such as photolithography and electroplating copper pillars. The equipment modification cost is low and it is compatible with existing mass production lines.

[0019] 5. Complementary advantages of process combination: Thermo-ultrasonic bonding has high positioning accuracy and low-temperature non-damage; gradient solder ball reflow solder joint has good toughness and strong load-bearing capacity. The combination of the two processes can adapt to the interconnection needs of different levels, and the process is highly flexible.

[0020] 6. Clear functional division of the interposer layer and strong integration capability: The two-level TSV interposer layer has a clear division of labor. The first interposer layer realizes the integration of large-volume small chip arrays, and the second interposer layer realizes the amplification and dispersion of signal pins, which can meet the needs of high-density, large-size multi-layer stacked packaging. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the first TSV intermediary layer of the present invention.

[0022] Figure 2 This is a schematic diagram of the second TSV intermediary layer of the present invention.

[0023] Figure 3This is a schematic diagram of the top-level functional chip of the present invention.

[0024] Figure 4 This is a schematic diagram of the present invention bonding the functional chip to the first TSV interposer layer.

[0025] Figure 5 This is a schematic diagram of the fabrication of the first solder ball in the first TSV interposer layer according to the present invention.

[0026] Figure 6 This is a schematic diagram of the fabrication of the second gold ball bump in the second TSV interposer layer according to the present invention.

[0027] Figure 7 This is a schematic diagram of the multilayer composite structure of the present invention.

[0028] Figure 8 This is a schematic diagram of the present invention, showing the fabrication of a second solder ball in the second TSV interposer layer and the preparation of a third gold ball bump in the bottom carrier substrate.

[0029] Figure 9 This is a schematic diagram of the final multi-layer 3D stacked package of the present invention.

[0030] Figure 10 This is a schematic diagram of the preparation method of the present invention. Detailed Implementation

[0031] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0032] In the preferred embodiments of the present invention, those skilled in the art should note that the top-level functional chip, ultrasonic flip-chip device, etc. involved in the present invention can be regarded as prior art.

[0033] Preferred embodiment.

[0034] like Figure 1-9 As shown, this invention discloses a low-temperature hybrid bonding multilayer 3D stacked packaging structure, which, from top to bottom, includes a top functional chip array, a first TSV interposer, a second TSV interposer, and a bottom carrier substrate, wherein: Both the first TSV interposer and the second TSV interposer have vertically penetrating TSV vias inside, and the TSV vias are filled with a metal conductive material to achieve vertical electrical conduction between layers. The upper surface of the TSV via of the first TSV interposer is provided with gold-plated pads, and the lower surface is provided with gold-plated pads; the upper surface of the TSV via of the second TSV interposer is provided with gold-plated pads, and the lower surface is provided with a metal redistribution layer. Each chip in the top-level functional chip array has a first gold ball bump at its bottom, which is interconnected with the gold-plated pads on the upper surface of the first TSV interposer layer by thermo-ultrasonic bonding. The gold-plated pads on the lower surface of the first TSV interposer are provided with first solder balls, and the gold-plated pads on the upper surface of the second TSV interposer are provided with second gold ball bumps. After the first solder ball melts, it wraps around the corresponding second gold ball bump to form an embedded wrapping solder joint. The metal redistribution layer on the lower surface of the second TSV interposer is implanted with a second solder ball, and the bottom substrate pad is provided with a third gold ball bump. After the second solder ball melts, it wraps around the corresponding third gold ball bump to form an embedded wrapping solder joint.

[0035] Specifically, the first gold ball protrusion is an irregular cylindrical structure with a diameter of 50μm.

[0036] More specifically, the first solder ball has a Sn90Zn7Bi3 composition and a reflow peak temperature of 200℃; the second solder ball has a Sn58Bi composition and a reflow peak temperature of 160℃.

[0037] Furthermore, filler adhesive is provided between the interconnection areas of each layer to enhance the overall structural strength of the package.

[0038] like Figure 10 As shown, this invention also discloses a fabrication process for a low-temperature hybrid bonding multilayer 3D stacked packaging structure, which includes the following steps: Step S1: As Figure 1 As shown, a first TSV interposer is prepared, a TSV through-silicon via is fabricated inside a substrate and metallized and filled, and gold-plated pads are prepared on the upper and lower surfaces of the substrate to obtain the first TSV interposer. Step S2: As Figure 2 As shown, a second TSV interposer is prepared, a TSV through-silicon via is fabricated inside another substrate and metallized and filled, a gold-plated pad is prepared on the upper surface of the substrate, and a metal redistribution layer is prepared on the lower surface to obtain the second TSV interposer. Step S3: As Figure 3 As shown, a first gold ball bump is fabricated on the bonding surface of each top-level functional chip; Step S4: As Figure 4As shown, using an ultrasonic flip-chip device, multiple top-level functional chips with first gold ball bumps are sequentially thermo-ultrasonic bonded to the gold-plated pads on the upper surface of the first TSV interposer to form a top-level functional chip array. Step S5: As Figure 5 As shown, the first solder ball is fabricated on the gold-plated pad on the lower surface of the first TSV interposer layer; Step S6: As Figure 6 As shown, a second gold ball bump is fabricated on the gold-plated pad on the upper surface of the second TSV interposer layer; Step S7: As Figure 7 As shown, the product obtained in step S5 is subjected to formic acid heating pretreatment, and then aligned and pressed with the second TSV interlayer under vacuum. The first solder ball is melted by vacuum reflow, and the second gold ball bump is wrapped to form an embedded wrapped solder joint, resulting in a multi-layer composite structure. Step S8: As Figure 8 As shown, a second solder ball is fabricated on the metal redistribution layer pad on the lower surface of the second TSV interposer; Step S9: Fabricate a third gold ball bump on the pads of the bottom carrier substrate; Step S10: The product obtained in step S8 is subjected to formic acid heating pretreatment, and then aligned and pressed with the underlying substrate under vacuum. The second solder ball is melted by vacuum reflow, wrapping the third gold ball bump to form an embedded encapsulated solder joint, completing the multi-layer 3D stacked package, as shown below. Figure 9 As shown.

[0039] Specifically, the thermal ultrasonic bonding process parameters in step S4 are: temperature 180℃, ultrasonic power 8W, and bonding time 800ms.

[0040] More specifically, the vacuum reflux curve in step S7 is as follows: the temperature is increased from room temperature to 150°C at a rate of 2°C / s for 75s; the temperature is held at 150°C for 80s; the temperature is then increased to 200°C at a rate of 2°C / s for 20s; the temperature is held at 200°C for 30s; and finally, the temperature is reduced to room temperature at a rate of 2°C / s for 300s. The vacuum reflux curve in step S10 is as follows: the temperature is increased from room temperature to 110℃ at a rate of 2℃ / s for 40s; the temperature is held at 110℃ for 80s; the temperature is then increased to 160℃ at a rate of 2℃ / s for 15s; the temperature is held at 160℃ for 30s; and finally the temperature is reduced to room temperature at a rate of 2℃ / s for 200s.

[0041] Furthermore, in steps S5 and S8, the solder balls are prepared using laser ball implantation or electroplating ball implantation methods; in steps S3, S6, and S9, the gold ball bumps are formed using gold ball bonding equipment.

[0042] Furthermore, after the stacked packaging is completed, filler glue is placed in the gaps between the interconnects of each layer to enhance the overall structural strength of the package.

[0043] In this embodiment of the invention, a two-layer interposer is used as an example. The highest process temperature throughout the process is 200°C, which is much lower than the temperature of traditional multilayer stacking processes. The optical structure of the optoelectronic chip is undamaged, and the packaging warpage and internal stress are significantly reduced. The top layer adopts thermo-ultrasonic bonding, and there is no solder joint remelting phenomenon throughout the process. The embedded solder joints formed by the gold balls and solder balls are tightly bonded. After thermal cycling and vibration reliability tests, there are no short circuits, delamination, or breakage problems. The entire process is fully compatible with existing ultrasonic bonding, ball planting, and reflow equipment, without the need for additional complex processes, and the mass production cost is controllable.

[0044] It is worth mentioning that the technical features such as the top-level functional chip and ultrasonic flip-chip device involved in this patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement of these technical features can be adopted by conventional choices in the field and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0045] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A low-temperature hybrid bonding multilayer 3D stacked packaging structure, characterized in that, From top to bottom, it includes a top-level functional chip array, a first TSV interposer layer, a second TSV interposer layer, and a bottom-level carrier substrate, wherein: Both the first TSV interposer and the second TSV interposer have vertically penetrating TSV vias inside, and the TSV vias are filled with a metal conductive material to achieve vertical electrical conduction between layers. The upper surface of the TSV via of the first TSV interposer is provided with gold-plated pads, and the lower surface is provided with gold-plated pads; the upper surface of the TSV via of the second TSV interposer is provided with gold-plated pads, and the lower surface is provided with a metal redistribution layer. Each chip in the top-level functional chip array has a first gold ball bump at its bottom, which is interconnected with the gold-plated pads on the upper surface of the first TSV interposer layer by thermo-ultrasonic bonding. The gold-plated pads on the lower surface of the first TSV interposer are provided with first solder balls, and the gold-plated pads on the upper surface of the second TSV interposer are provided with second gold ball bumps. After the first solder ball melts, it wraps around the corresponding second gold ball bump to form an embedded wrapping solder joint. The metal redistribution layer on the lower surface of the second TSV interposer is implanted with a second solder ball, and the bottom substrate pad is provided with a third gold ball bump. After the second solder ball melts, it wraps around the corresponding third gold ball bump to form an embedded wrapping solder joint.

2. The low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 1, characterized in that, The first gold ball protrusion is an irregular cylindrical structure with a diameter of 50 μm.

3. The low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 1, characterized in that, The first solder ball has a composition of Sn90Zn7Bi3 and a reflow peak temperature of 200℃; the second solder ball has a composition of Sn58Bi and a reflow peak temperature of 160℃.

4. The low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 1, characterized in that, Filler adhesive is provided between the interconnection areas of each layer to enhance the overall structural strength of the package.

5. A fabrication process for a low-temperature hybrid bonding multilayer 3D stacked packaging structure, used to fabricate the low-temperature hybrid bonding multilayer 3D stacked packaging structure according to any one of claims 1-4, characterized in that, Includes the following steps: Step S1: Prepare the first TSV interposer layer, fabricate TSV through-silicon vias inside a substrate and complete metallization filling, and prepare gold-plated pads on the upper and lower surfaces of the substrate to obtain the first TSV interposer layer; Step S2: Prepare a second TSV interposer, fabricate TSV through-silicon vias inside another substrate and complete metallization filling, prepare gold-plated pads on the upper surface of the substrate and prepare a metal redistribution layer on the lower surface to obtain the second TSV interposer. Step S3: Fabricate the first gold ball bump on the bonding surface of each top-level functional chip; Step S4: Using an ultrasonic flip-chip device, multiple top-level functional chips with first gold ball bumps are sequentially thermo-ultrasonic bonded to the gold-plated pads on the upper surface of the first TSV interposer to form a top-level functional chip array. Step S5: Fabricate the first solder ball on the gold-plated pad on the lower surface of the first TSV interposer layer; Step S6: Prepare a second gold ball bump on the gold-plated pad on the upper surface of the second TSV interposer layer; Step S7: The product obtained in step S5 is subjected to formic acid heating pretreatment, and then aligned and pressed with the second TSV interlayer under vacuum. The first solder ball is melted by vacuum reflow, and the second gold ball bump is wrapped to form an embedded wrapped solder joint, thus obtaining a multi-layer composite structure. Step S8: Fabricate a second solder ball on the metal redistribution layer pad on the lower surface of the second TSV interposer; Step S9: Fabricate a third gold ball bump on the pads of the bottom carrier substrate; Step S10: The product obtained in step S8 is subjected to formic acid heating pretreatment, and then aligned and pressed with the bottom substrate under vacuum. The second solder ball is melted by vacuum reflow, and the third gold ball bump is wrapped to form an embedded encapsulation solder joint, thus completing the multi-layer 3D stacked packaging.

6. The fabrication process of a low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 5, characterized in that, The thermo-ultrasonic bonding process parameters in step S4 are: temperature 180℃, ultrasonic power 8W, and bonding time 800ms.

7. The fabrication process of a low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 5, characterized in that, The vacuum reflux curve in step S7 is as follows: the temperature is increased from room temperature to 150℃ at a rate of 2℃ / s for 75s; the temperature is held at 150℃ for 80s; the temperature is then increased to 200℃ at a rate of 2℃ / s for 20s; the temperature is held at 200℃ for 30s; and finally the temperature is reduced to room temperature at a rate of 2℃ / s for 300s. The vacuum reflux curve in step S10 is as follows: the temperature is increased from room temperature to 110℃ at a rate of 2℃ / s for 40s; the temperature is held at 110℃ for 80s; the temperature is then increased to 160℃ at a rate of 2℃ / s for 15s; the temperature is held at 160℃ for 30s; and finally the temperature is reduced to room temperature at a rate of 2℃ / s for 200s.

8. The fabrication process of a low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 5, characterized in that, In steps S5 and S8, the solder balls are prepared by laser ball placement or electroplating ball placement; in steps S3, S6 and S9, the gold ball bumps are formed by gold ball bonding equipment.

9. The fabrication process of a low-temperature hybrid bonding multilayer 3D stacked packaging structure according to claim 5, characterized in that, After the stacked packaging is completed, filler glue is placed in the gaps between the interconnects of each layer to enhance the overall structural strength of the package.

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