Conversion of identifiers

Abstract

An apparatus, a method, and a computer program are provided. The apparatus includes a conversion circuit configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating a requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information defining a mapping between identifiers in the first and second domains. The first identifier is omitted from the output resource access request.

Description

[0001] This disclosure relates to data processing. Furthermore, this disclosure relates to an apparatus, a method, and a computer program.

[0002] Some devices use identifiers to indicate the requester of a resource access request. This identifier allows the requester to be identified from the resource access request and can be used for resource allocation purposes, such as resource partitioning.

[0003] In some configurations, an apparatus is provided that includes:

[0004] A conversion circuit is configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process that generated the input resource access request in the first domain, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first and second domains.

[0005] The first identifier is omitted from the output resource access request.

[0006] In some configurations, a system is provided that includes:

[0007] Device;

[0008] A first processing circuit, configured to implement a first domain; and

[0009] A second processing circuit, configured to implement a second domain.

[0010] The conversion circuit is configured at the interface between the first domain and the second domain.

[0011] In some configurations, a method is provided that includes:

[0012] An input resource access request received from a first domain is converted into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process that generated the input resource access request in the first domain, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first and second domains.

[0013] The first identifier is omitted from the output resource access request.

[0014] In some configurations, a computer program is provided for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0015] A conversion program logic is configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process that generated the input resource access request in the first domain, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first and second domains.

[0016] The first identifier is omitted from the output resource access request.

[0017] In some configurations, the computer program is stored on a computer-readable storage medium. In some configurations, the computer-readable storage medium is a non-transitory computer-readable storage medium.

[0018] The present invention will be further described by way of example only, with reference to the configuration of the invention illustrated in the accompanying drawings, wherein:

[0019] Figure 1 The apparatus is illustrated schematically with some configurations according to the present technology;

[0020] Figure 2 The processing circuitry according to some configurations of the present technology is illustrated schematically;

[0021] Figure 3 The illustrations illustrate some configurations of CPU clusters according to this technology;

[0022] Figure 4 The apparatus is illustrated schematically with some configurations according to the present technology;

[0023] Figure 5 The apparatus is illustrated schematically with some configurations according to the present technology;

[0024] Figure 6 The apparatus is illustrated schematically with some configurations according to the present technology;

[0025] Figure 7 The use of lookup tables according to some configurations of this technology is illustrated schematically;

[0026] Figure 8 The conversion of identifiers according to some configurations of this technology is illustrated schematically;

[0027] Figure 9 The conversion of identifiers according to some configurations of this technology is illustrated schematically;

[0028] Figure 10 The sequence of steps performed by the device according to some configurations of the present technology is illustrated schematically; and

[0029] Figure 11 The simulator code for some configurations according to this technology is illustrated schematically.

[0030] At least some configurations provide an apparatus including a conversion circuit configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating a requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first and second domains, wherein the first identifier is omitted from the output resource access request.

[0031] A resource access request can be issued from a requesting process, which can be, for example, a virtual machine (VM), operating system (OS), or application executing within a first domain of the device. The requesting process can be a process running on a processor in a multiprocessor environment. To allow the requester to be identified, for example, by the process or device receiving the resource access request, the resource access request includes a first identifier that identifies the requesting process in the first domain. The first identifier is defined within the first domain such that any process or device within the first domain that receives multiple resource access requests within that domain can identify resource access requests originating from the same requesting process (requested by the same requesting process).

[0032] The setting of the first identifier in the first domain of the device can be defined during manufacturing and can vary between different domains. For example, the first identifier in the first domain may not be defined in the second domain (where the second domain is a different domain from the first domain and may have been manufactured to use an alternatively configured identifier) ​​and / or may be alternatively assigned in the second domain.

[0033] The inventors have recognized that in situations where two such domains need to communicate with each other, difficulties may arise due to the use of different identifiers in the first and second domains. For example, if the two domains are coupled to each other within a device, and a requesting process in the first domain issues a request for access to a resource in the second domain, the first identifier included in the resource access request may not be in a format that can be interpreted in the second domain. While it is possible to implement a device in which a second identifier assigned in the second domain is included in the resource access request in addition to the first identifier, such an implementation would require the transmission of a larger amount of data, potentially increasing overhead and power consumption. Furthermore, the method does not scale well in the case of multiple domains. Therefore, the device is provided with a conversion circuit to convert the first identifier received as part of an input resource access request in the first domain into the second identifier included in an output resource access request in the second domain. The conversion between the first and second identifiers is handled within the conversion circuit, and the conversion circuit is configured to omit (e.g., exclude and / or withhold) the first identifier from the output resource access request. Providing such a conversion circuit reduces the overhead associated with setting alternative identifiers in each of the first and second domains and improves scalability.

[0034] In some configurations, the number of identifiers available for allocation in the first identifier space and the second identifier space is defined independently of each other. The independence of the definition of identifiers available in each domain means that the number of identifiers provided in one domain can be determined without utilizing knowledge of the number of identifiers provided in the other domain. For example, identifiers may be assigned at manufacturing time by different manufacturers who do not need to communicate with each other regarding the number of identifiers. Alternatively, the allocation of identifiers in the first and second domains may be based on different specific implementation standards, without considering the specific implementation standards in the other domain. The number of identifiers available in the first domain and the number of identifiers available in the second domain may differ from each other. For example, the first domain may be a large domain including multiple processors, while the second domain may be a much smaller domain including a single processor and supporting far fewer identifiers than the first domain. For example, identifiers in the first domain may be represented using 8 digits, while identifiers in the second domain may be represented using 4 digits. Alternatively, the number of identifiers available in the first and second domains may happen to be the same. However, in this case, the allocation and application of these identifiers in each of the first and second domains may be different.

[0035] In some configurations, the conversion information is dynamically configurable. While setting a fixed conversion between the first and second domains can provide the reduced overhead and improved scalability discussed above, this approach requires prior knowledge of identifiers available in both the first and second domains. Such information may not be available during system assembly, for example, because the first domain is built by a first manufacturer, the second domain is built independently by a second manufacturer, and these domains are combined by a third manufacturer. By allowing the conversion information to be dynamically configurable, greater flexibility is provided, and incompatibilities, such as those between domains manufactured by different manufacturers, can be reduced.

[0036] In some configurations, the conversion circuitry includes one or more registers, and the conversion information is defined based on data stored in the registers. For example, registers may identify one or more rules that allow the conversion of identifiers between a first domain and a second domain. Registers may be configured by one or more processes executing in the first and / or second domain, thereby allowing either the first or second domain to configure the conversion circuitry.

[0037] In some configurations, one or more registers are memory-mapped registers. Memory-mapped registers can be mapped to memory regions accessible by processes running in one or both of the domain. Memory-mapped registers allow processes that wish to modify them to write data to the memory-mapped location (e.g., to the address in memory corresponding to the memory-mapped register). This approach provides an efficient way to offer dynamic configurability of translation information.

[0038] In some configurations, the device includes control circuitry configured to maintain translation information by modifying one or more registers. In addition to using memory-mapped registers, control circuitry can be provided, thus offering multiple methods for dynamically updating registers. The control circuitry can be configured to respond to one or more architecture-defined instructions that may form part of an instruction set architecture.

[0039] While transformation data can be stored in any format, in some configurations, transformation information includes one or more transformation lookup tables. Transformation lookup tables can be arranged as a direct-mapped storage structure (e.g., a direct-mapped cache), a set-associative storage structure, or a fully associative storage structure. Transformation tables can be arranged in a hierarchical structure that requires transformation table traversal to map between a first identifier and a second identifier. Transformation tables can be arranged to transform a portion of an identifier (e.g., the most significant part of the identifier), while another portion of the identifier, such as the least significant part of the identifier, is mapped unchanged between the first and second identifiers.

[0040] In some configurations, the transformation information includes one or more transformation functions configured to map identifiers in a first field to identifiers in a second field. Transformation functions may include one or more hash functions, one or more bit reduction functions, and / or one or more bit swapping functions. One or more transformation tables may be combined to provide the transformation functions, wherein the transformation functions are provided for mapping between the most significant portion of the first identifier and the most significant portion of the second identifier, and the transformation tables are provided for mapping between the least significant portion of the first identifier and the least significant portion of the second identifier. Alternatively, transformation tables may be provided for mapping between the most significant portions, while transformation functions map between the least significant portions. Furthermore, in some configurations, a combination of transformation functions, transformation tables, and direct mappings can be used to map different portions of the identifier. In some configurations, transformation tables can be used to identify the function used to perform the identifier transformation from a plurality of possible functions.

[0041] In some configurations, the conversion circuit is set at the boundary between the first and second domains. Where multiple communication paths exist between the first and second domains, multiple instances of the conversion circuit can be provided; for example, one instance of the conversion circuit can be provided at each of the communication paths.

[0042] In some configurations, the boundary is the outer boundary of both the first and second domains. In alternative configurations, the boundary can be the inner boundary of at least one of the first and second domains.

[0043] In some configurations, identifiers in each of the first and second domains are assigned by the corresponding instance of management software running in the respective domain. The assignment of identifiers can be handled by the management software. In such configurations, the management software in the second domain may be unaware of the identifiers assigned by the management software operating in the first domain. The management software running in the first domain may be able to communicate with the management software running in the second domain to define a region of the identifier space in one domain that can be utilized by a requester device in the other domain. Where one domain has a greater number of available identifiers than the other, a subset of these identifiers can be mapped to identifiers in the other domain for cross-domain resource access requests, while the remaining identifiers are reserved for intra-domain resource access requests.

[0044] In some configurations, identifiers in each of the corresponding domains in the first and second domains are used for resource allocation control to regulate the performance level perceived by resource access in the corresponding domain. In some configurations, resource allocation may include resource partitioning. For example, identifiers can be used to help provide the desired Quality of Service (QoS) for requesting processes and / or to help ensure fair use policies among different requesting processes. In some configurations, the identifier is a Partition Identifier (PARTID), also known as a partition number, which references a specific partition within a partition ID space. The numerical value of a partition number has no inherent meaning. As a use case, a unique partition identifier may be assigned to different VMs, OSes, or applications by the associated PARTID space manager. Alternatively or additionally, the identifier may include a Partition Monitoring Group (PMG), which can be used to group access requests and can provide coarser-grained grouping than using PARTIDs; for example, two or more requesting devices may share the same PMG identifier and each assign its own PARTID. QoS can then be provided to two or more requesters based on the PMG identifier, PARTID, or a combination of both. Furthermore, PMGs allow for finer-grained partitioning, where multiple requester devices in different PMGs can use the same PARTID, thus providing a wider range of PARTIDs available for a single requester. It will be apparent to those skilled in the art that PARTID and PMG are examples of identifiers, and alternative identifiers may be used in alternative configurations.

[0045] In some configurations, the first identifier is independent of the memory address specified in the input resource access request. The first identifier (e.g., PARTID) can be used as a tag to distinguish memory requests originating from different execution environments (e.g., software execution environments executed by processing circuitry). The first identifier does not affect which addresses in memory are allowed to be accessed by a particular execution environment, but can be used for resource allocation control to adjust the performance level perceived by memory accesses originating from a particular execution environment.

[0046] In some configurations, an input memory access request specifies a security state identifier indicating the input security state associated with the input memory access request; and the conversion circuitry is configured to set the output security state of the output conversion request based on the input security state. The first field can support operation under multiple different security states, which can be associated with different permissions, such as access to information stored in registers or memory. A resource access request can specify a security state identifier indicating the security state associated with the resource access request. The conversion circuitry can convert the security state identifier during identifier conversion.

[0047] In some configurations, the conversion circuitry is configured to set the output security state based on security conversion information defined in the conversion information. Security conversions may be provided by a set of tables and / or functions independent of identifier conversions. In some configurations, the number of security states in the first domain may differ from the number of security states provided in the second domain. In some configurations, a different set of conversion tables and / or conversion functions may be provided for each security domain within the security domains. For example, where multiple security domains are provided in the first domain, each security domain may be mapped to a different portion of the identifier space in the second domain, which provides only a single security domain.

[0048] In some configurations, the conversion circuitry is configured to perform conversion of access requests input from a second domain to be output to a first domain. In other words, the conversion circuitry may be able to perform bidirectional conversion, i.e., receiving an input resource access request from either domain and outputting it to the other of the two domains.

[0049] According to some configurations, a system is provided, comprising: the means as described above; a first processing circuit configured to implement a first domain; and a second processing circuit configured to implement a second domain, wherein the conversion circuit is disposed at an interface between the first and second domains. The first and second domains may include any components of a data processing system. For example, each of the first and second domains may include any number of CPUs, GPUs, caches, data processing pipelines, etc.

[0050] In some configurations, the system includes a third processing circuit configured to implement a third domain; and a second translation circuit arranged at the boundary between the third domain and at least one of the first and second domains, wherein the translation circuit is unaware of the identifier assigned in the third domain. In this way, three or more domains can be connected to each other, with each domain independently assigning its own identifier, as described above. The translation circuit is positioned between the first and second domains, and the second translation circuit is positioned between the second and third domains. In some configurations, the third translation circuit may be positioned between the first and third domains. Providing multiple address translation circuits, each capable of translating between the two domains to which they are connected, provides a highly flexible system that does not require any additional overhead as the number of domains increases.

[0051] A specific configuration will now be described with reference to the accompanying drawings.

[0052] Figure 1A device 30 according to some configurations of the present technology is schematically illustrated. Device 30 includes a conversion circuit 34 disposed between a first domain 32 and a second domain 36. The conversion circuit 34 stores conversion information 42 indicating a conversion between an input resource access request issued from one of the first domain 32 and the second domain 34 and an output resource access request issued to the other of the first domain 32 and the second domain 34.

[0053] In the illustrated configuration, the first domain 32 includes a plurality of central processing units (CPUs) 38, each of which is an example of processing circuitry. A process (e.g., a virtual machine or operating system running on one or more of the CPUs 38) may issue a resource access request. Each resource access request is assigned an identifier indicating the requesting process (e.g., the virtual machine or operating system that generated (initiated) the resource access request). When resource access requests are implemented within the first domain 32, this can be accomplished using identifiers to ensure that the requesting process generating the resource access request receives a predefined or dynamically configurable quality of service.

[0054] In the illustrated configuration, the second domain 36 includes a single CPU 46. CPU 46 can respond to resource access requests by satisfying those requests based on identifiers contained within them. The identifiers that can be assigned by the first domain 32 and the second domain 36 can be defined independently, for example, at manufacturing time or when those domains are designed. Therefore, identifiers that can be processed by each of the two domains may be incompatible with each other.

[0055] When a resource access request is issued by the first domain 32 and is to be satisfied by the second domain 36, the resource access request, as input resource access request 40, is transmitted from the first domain 32 to the second domain 36 via conversion circuit 34. Conversion circuit 34 receives the input resource access request 40, which is a 12-bit identifier in the illustrated configuration, and performs a conversion to transform the identifier of the input resource access request 40 into an identifier in the output resource access request 44, which is a 4-bit identifier in the illustrated configuration. The conversion is performed by conversion circuit 34 based on conversion information 42. The output resource access request 44 is then transmitted to the second domain 36 to satisfy the resource access request. The 12-bit identifier of the first domain 32 is omitted from the output resource access request 44.

[0056] While the specific examples illustrated in the accompanying drawings refer to PARTID as an identifier, it will be apparent to those skilled in the art that the use of PARTID is for illustrative purposes only, and any identifier that indicates a requester process may be used. For example, the identifier may be PARTID, PMG, a combination of PARTID and PMG, or any other identifier that can be used to identify a requester process.

[0057] Figure 2 An example of a data processing device 2 is schematically illustrated, which may be an example of a first domain 32 and / or a second domain 36. Device 2 is provided with processing circuitry 4 and a cache 6. For example, cache 6 may be an instruction cache for caching instructions, a data cache for caching data, or a shared cache that caches both instructions to be retrieved for processing and data accessed from memory in response to load / store instructions processed by processing circuitry 4. Cache 6 may be at any level of the cache hierarchy. For example, cache 6 may be a level 1, level 2, level 3, or system cache. Although cache 6 is shown as separate from processing circuitry 4, in some specific implementations (particularly if the cache is a level 1 or level 2 cache), cache 6 may be considered part of the processing circuitry. If cache 6 is at a level of the cache hierarchy other than level 1, there may also be a higher-level cache 8 accessible to processing circuitry 4, from which information can be evicted from higher-level cache 8 to cache 6 at a lower level of the cache hierarchy.

[0058] Processing circuit 4 includes a fetch circuit 10 for fetching instructions from cache 6, 8 or memory, a decode circuit 12 for decoding the fetched instructions, and an execution circuit 14 for executing the instructions to perform data processing operations. The operands of the instructions can be read from register 16 by execution circuit 14, and the result of the executed instructions can be written to register 16.

[0059] Register 16 includes one or more partition identifier control registers 18 for setting the partition identifier specified by a cache request 19 (an example of a resource access request) sent by processing circuitry 4 to cache 6 to request access to information that can be stored in cache 6. Processing circuitry 4 has a partition identifier selection circuit 17 that selects which partition identifier is specified by cache request 19 based on information stored in the one or more partition identifier control registers 18. The partition identifier (PARTID) acts as a tag to distinguish resource requests issued representing different execution environments (e.g., the software execution environment executed by processing circuitry 4). The partition identifier does not affect which addresses in memory are allowed to be accessed by a particular execution environment, but is used for resource allocation control to regulate the performance level perceived by memory accesses issued by a particular execution environment.

[0060] As an illustrative example, cache 6 includes storage circuitry 20 for storing cache information and associated tags (used to determine whether a cache entry is associated with the target address of a cache request during a cache lookup). Cache 6 also has cache replacement control circuitry 22 for controlling the replacement of cache entries in storage circuitry 20. Cache 6 can use partition identifiers to influence the cache replacement strategy used by cache replacement control 22 to select the sacrifice cache entry to be reallocated for a new address to be allocated in the cache. However, partition identifiers can also be used for other aspects of resource allocation, such as controlling the amount of memory system bandwidth allowed for a particular execution environment, or setting a maximum percentage of cache capacity that a given execution environment is allowed to allocate for its own information. Such resource allocation control can help prevent “noisy” execution environments (those that generate frequent memory access requests) from monopolizing a large portion of available memory system resources (which could otherwise impair the performance of other execution environments with less frequent requests, which might not have access to sufficient memory system resources if the amount of resources used by the “noisy” execution environment is unrestricted). It should be understood that partition identifiers can be used for other purposes and can be appended to resource access requests other than cache access requests, such as regarding... Figure 1 The resource access requests discussed can be served in domains other than the domain from which the resource access requests originate.

[0061] In a specific case of a software execution environment executed by processing circuit 4, each software execution environment can be a different process or thread executed by processing circuit 4, or a sub-part of instructions executed within such a process or thread (therefore, in some examples, different parts of the same process or thread can be assigned different partition identifiers). By setting partition identifier control information in one or more partition identifier control registers 18, the software itself controls how the set of software executed by processing circuit 4 is partitioned into different software execution environments assigned different partition identifiers.

[0062] Partition identifiers can also be assigned to specific hardware execution environments within the system. For example, resource access requests originating from different hardware units can be assigned different partition identifiers.

[0063] In some examples, the assignment of partition identifiers can be fixed and chosen by the hardware. For example, partition identifiers used for requests originating from different hardware execution environments can be hardwired in the circuit design (e.g., during circuit fabrication), or partition identifiers used for a specific software execution environment can be derived from software execution environment identifiers such as thread identifiers or process identifiers in a way that does not allow the software itself to change the partition identifiers used.

[0064] Providing software with the ability to program which partition identifiers are used for a specific execution environment can be useful. Therefore, partition identifier control register 18 can be provided with information to allow software configuration to control the selection of partition identifiers for a specific memory access request 19.

[0065] The partition identifier control register 18 may comprise a single register into which the partition identifier can be written by software. In such an implementation, a memory access request, such as cache access request 19, issued by processing circuitry 4 specifies the partition identifier currently specified in register 18. When switching between different parts of software that need to differentiate their resource access requests for resource control purposes (e.g., during a context switch), the software updates the partition identifier control register 18 to specify the partition identifier of the new software to be executed after the switch, and then subsequent resource access requests will specify the new partition identifier.

[0066] Other examples may implement multiple partition identifier control registers 18 that specify partition identifiers associated with different operating states (e.g., privilege levels or exception levels associated with processing circuitry 4), and when a resource access request (e.g., cache request 19) is issued, the current operating state of processing circuitry 4 can be used to select which partition identifier control register 18 is selected by partition identifier selection circuitry 17, and thus which partition identifier is specified in the resource access request. For example, this can help avoid the need for software to rewrite the partition identifier control register 18 every time a supervisor call occurs or an exception occurs that leads to a higher privilege operating state or an exception returns to a lower privilege operating state (which can be a relatively frequent event).

[0067] Some specific implementations may provide architectural mechanisms for specifying different partition identifiers for different types of memory access requests issued within the same software execution environment. For example, a field may exist in the partition identifier control register 18 for specifying different partition identifiers for: data cache requests issued in response to load / store instructions executed by execution circuitry 14, instruction fetch cache requests issued in response to instruction fetch requests made by fetch circuitry 10, and / or page table traversal cache requests issued by processing circuitry 4 requesting access to page table information used to translate the addresses of cache / memory access requests.

[0068] Furthermore, in some cases, the partition identifier specified in the memory access request may not be exactly the same as the partition identifier value stored in the partition identifier control register 18. Some specific implementations of the partition identifier selection circuit 17 can support a partition identifier virtualization scheme, where a virtual partition identifier written by software to the partition identifier control register 18 is remapped to a physical partition identifier appended to the cache request 19 based on software-defined partition identifier remapping information. This allows multiple different lower-privileged software programs (e.g., operating systems) to coexist on the system while independently setting partition identifiers for different software execution environments managed by the lower-privileged software, where higher-privileged software (e.g., a hypervisor) defines the partition identifier remapping information such that conflicting partition identifiers set by different operating systems can be mapped to different partition identifiers as seen in cache 6.

[0069] Therefore, it should be understood that there are multiple ways in which the partition identifier of a resource access request can be determined by the partition identifier selection circuit 17, but in some examples, the processing circuit 4 has circuitry for selecting the partition identifier to be associated with the memory access request based on information specified by the software in at least one software-writable architecture register 18.

[0070] In some implementations, processing circuit 4 also supports operation under different security states, which can be associated with different access permissions to execute instructions and / or access information in memory, caches 6, 8, or register 16. A security state identifier associated with the current security state can also be specified by cache request 19. Cache request 19 also specifies the target address of the information to be accessed in the cache.

[0071] It will be obvious to those skilled in the art that Figure 2 The circuitry shown may form part of the first domain 32 and the second domain 36, or may be split up, with some circuitry (e.g., processing circuitry 4) provided in the first domain 32 and others (e.g., cache 6) provided in the second domain. In such a configuration, a conversion circuitry 34 provided between the first and second domains is used to convert the partition identifier identified in a resource access request issued by the first domain into a partition identifier that can be recognized / managed by the second domain.

[0072] Figure 3Details of another example of a data processing apparatus are schematically illustrated, which may be an example of the first domain 32 and / or an example of the second domain. The system includes a CPU (Central Processing Unit) cluster 200 and a GPU 202. This example also features a DMA (Direct Memory Access) controller 210 for performing memory accesses based on configuration data set by software executed on the CPU cluster 200 or GPU 202. It should be understood that other processing circuitry (e.g., a neural processing unit (NPU) or other types of hardware accelerators for accelerating neural network processing) may also be included.

[0073] CPU cluster 200 includes multiple CPUs 201, each CPU 201 having processing circuitry 4 and at least one higher-level (e.g., Level 1 and / or Level 2) cache 8, as described above. Although Figure 3 An example with two CPUs 201 in cluster 200 is shown, but other examples may have only a single CPU 201 or more than two CPUs 201. Although Figure 3 A single CPU cluster 200 is shown, but other examples may have more than one CPU cluster 200. Although in Figure 3 Not shown in the example, but in addition to any cache 8 dedicated to a specific CPU 201, there may be another level of cache shared among the CPUs 201 of cluster 200, but this other level of cache is not accessible by GPU 202 or other CPU clusters.

[0074] GPU 202 also features a processing circuit 4 similar to those previously mentioned and at least one cache 8. The architecture and microarchitecture of the processing circuit 4 in GPU 202 can differ from those of the processing circuit 4 in CPU 201—for example, the GPU can support different instructions and have different hardware designs for parallel processing of graphics threads. Although Figure 3 A single GPU 202 is shown, but other examples may have more than one GPU 202.

[0075] CPU cluster 200 and GPU 202 share access to a shared memory system including shared cache 6. For example, shared cache 6 may be a system cache that is part of a system interconnect 204 used to manage communication between CPU cluster 200, GPU 202, and memory 206, or alternatively, the shared system cache may be separate from interconnect 204. Interconnect 204 may be a coherent interconnect that applies a coherence protocol to manage the coherence of data cached at corresponding cache locations 8 in CPU cluster 200 and GPU 202.

[0076] Each processing circuit 4 in CPU 201 and GPU 202 assigns a partition identifier to each outgoing memory access request sent to interconnect 204, wherein the partition identifier is selected by partition identifier selection circuit 17 based on information stored in partition identifier control register 18, as described above. The partition identifier flows through the memory system along with the request, reaching any memory system node having resource allocation circuitry for making resource allocation decisions based on the partition identifier. Therefore, cache requests made to system cache 6 also specify a partition identifier selected by one of the sources of the corresponding memory access request in CPU 201 and GPU 202.

[0077] Access from DMA controller 210 to system cache 6 can similarly be marked with a partition identifier selected by partition identifier selection circuit 17 based on information in at least one partition identifier control register 18. However, in the case of DMA controller 210 (which itself does not execute instructions), the information specified in partition identifier control register 18 of DMA controller 210 is set based on instructions executed by processing circuitry 4 running on CPU cluster 200 or GPU 202, rather than based on DMA controller 210 itself. Alternatively, DMA access can be assigned a fixed partition identifier selected in hardware, which cannot be configured based on software executed by CPU cluster 200 or GPU 202.

[0078] Such as about Figure 2 The device 2 shown in the diagram is discussed. Figure 3 The apparatus shown can be provided in the first domain 32, the second domain 34, or can be partitioned among multiple domains. For example, the CPU cluster 200 can be provided as a first domain capable of managing the allocation of its own partition identifiers, and the GPU 202 can be provided as a second domain capable of managing the allocation of its own identifiers. Advantageously, this will allow the architects of the CPU cluster 200 and the GPU 202 to independently determine the format of the partition identifiers used by the respective domains. Conversion circuitry can then be provided at the interface between the CPU cluster 200 and the interconnect 204, and at the interface between the GPU 202 and the interconnect 204. It will be apparent to those skilled in the art that… Figure 2 and Figure 3 The example device described herein can contain any number of independently designed subdomains, and each subdomain operates using its own mechanism for defining and assigning partition identifiers. Providing conversion circuitry at the interface to these domains eliminates the need for designers of components within the system to agree on a standard approach for partition identifiers, thereby allowing each designer to customize the approach for the provided circuitry.

[0079] Figure 4A device 50 with some configurations according to the present technology is illustrated schematically. The device 50 is provided with a conversion circuit 54 for performing a conversion on a partition identifier received from one of the first domain 52 and the second domain 56, so as to output it in the other of the first domain 52 and the second domain 56.

[0080] The first field 52 includes hardware running a management process 58, which is configured to receive a resource access request 62 and, in response to receiving the resource access request, select an N-bit partition identifier using a partition identifier selection circuit 64. Here, N is any positive integer. The management process 58 is based on, for example, information about... Figure 2 The described technique is used to assign partition identifiers and output resource access requests with N-bit partition identifiers (70 bits).

[0081] The second field 56 includes hardware running a management process 60, which is configured to receive resource access requests 66 and, in response to receiving a resource access request, select an M-bit partition identifier using a partition identifier selection circuit 68. Here, M is any positive integer. The management process 60 is based on, for example, regarding... Figure 2 The described technique is used to assign partition identifiers and output resource access requests with M-bit partition identifiers (72 bits).

[0082] In the event that a resource access request in a first domain 52 with an N-bit partition identifier 70 requires access to a resource in a second domain 56, or in the event that a resource access request in a second domain 56 with an M-bit identifier 72 requires access to a resource in a first domain 52, the partition identifier assigned to the resource access request needs to be converted to make the partition identifier compatible with the other domain. The conversion circuit 54 includes conversion information 74, which includes a mapping between at least one subset of N-bit partition identifiers and at least one subset of M-bit partition identifiers.

[0083] Upon receiving a conversion request with an N-bit partition identifier 70 from the first domain 52, the conversion circuit 54 performs the conversion of the N-bit partition identifier using the conversion information 74, and outputs a resource access request with an M-bit identifier obtained from the mapping stored in the conversion information 74 to the second domain. Similarly, upon receiving a conversion request with an M-bit partition identifier 72 from the first domain 56, the conversion circuit 54 performs the conversion of the M-bit partition identifier using the conversion information 74, and outputs a resource access request with an N-bit identifier obtained from the mapping stored in the conversion information 74 to the second domain.

[0084] Figure 5Details of a device 80 according to some configurations of the present technology are schematically illustrated. The device 80 is provided with a conversion circuit 84 configured to perform identifier conversion between a first domain 82 and a second domain 86. The identifier conversion by the conversion circuit can be performed as described above. The conversion is performed with reference to conversion information stored in a register 92 included in the conversion circuit 84. Register 92 is a memory-mapped register mapped to a region of memory 90 included in the first domain 82. The conversion information can be modified by a control process 88 in the first domain 82 by writing to the mapped region of memory 90. The mapped region of memory can also be modified by a control process 94 running in the second domain 86. The control process 94 in the second domain 86 can modify the mapped region of memory 90 in the first domain by sending a memory access request 102. The memory access request 102 is received by a partition identifier management process 98 in the second domain, which uses a partition identifier selection circuit 100 to select a partition identifier. The selected partition identifier, as an M-bit partition identifier, is associated with access request 102 and is passed as input resource access request 96 to conversion circuit 84. The conversion circuit converts the partition identifier from an M-bit partition identifier in second domain 86 to an N-bit partition identifier in first domain 82, then allows control process 94 to access the mapped region of memory 90 to modify the conversion information stored in the memory mapping register 92 included in conversion circuit 84. It will be apparent to those skilled in the art that, in an alternative configuration, the mapped region of memory may be hosted in second domain 86 instead of first domain 82, or may include memory regions from both first domain 82 and second domain 86.

[0085] Figure 6 A system 110 comprising multiple domains 112 is schematically illustrated, each domain being connected to two other domains via conversion circuits 114. The system includes: a first domain 112(1) housing a set of CPUs 116; a second domain 112(2) housing a set of CPUs 118; a third domain 112(3) housing a set of CPUs 120; and a fourth domain 112(4) housing a set of CPUs 122. The first domain 112(1) is coupled (connected) to the second domain 112(2) via conversion circuits 114(1-2), the second domain 112(2) is coupled to the fourth domain 112(4) via conversion circuits 114(2-4), the fourth domain 112(4) is coupled to the third domain 112(3) via conversion circuits 114(3-4), and the third domain 112(3) is coupled to the first domain 112(1) via conversion circuits 114(1-3). Each field in field 112 can be independently assigned a partition identifier, wherein the conversion between different identifiers is handled by the corresponding conversion circuit 114, as described above.

[0086] It will be apparent to those skilled in the art that additional switching circuitry may be provided between the first domain 112(1) and the fourth domain 112(4) and / or between the second domain 112(2) and the third domain 112(3). Furthermore, although each of the illustrated domains 112 comprises a set of four CPUs, the arrangement of each domain may vary in both the size of the domain and the type and arrangement of the circuitry provided.

[0087] Figure 7 The conversion of partition identifiers according to some configurations of the present technology is illustrated schematically. The conversion circuitry receives an input access request 130 from a first field specifying a first partition identifier. The conversion circuitry stores a set of lookup tables (LUTs) 134 that indicate conversions between a first partition identifier defined in the first field and a second partition identifier in the second field. The conversion circuitry performs a lookup in lookup table 134 based on the first partition identifier. For example, a lookup can be performed by indexing into lookup table 134 based on the partition identifier. The conversion circuitry identifies the second partition identifier from an entry in the lookup table and outputs the access request as an output access request 132 with the second partition identifier.

[0088] Figure 8 The arrangement of a lookup table according to some configurations of the present technology is schematically illustrated. The lookup table is arranged as a set-associative memory structure 146. A translation circuit receives a memory request 140 including a memory address and a first partition identifier. The partition identifier indicated in the memory request 140 is fed to a hash circuit 144, which generates a hash of the first partition identifier. The hash of the first partition identifier is used to index into the set-associative memory structure 146. Each unique index of the set-associative memory structure 146 identifies a set of entries, which, in the illustrated configuration, includes two entries, and each entry includes a first partition identifier and a second partition identifier. Once the set of entries is identified based on the hash of the first partition identifier, the identified set 148 is passed to a tag comparison circuit 150. The tag comparison circuit 150 compares the partition identifier in the memory access request 140 with the first partition identifier stored in each entry of the identified set 148. If the tag comparison circuit 150 identifies a match between the first partition identifier included in the memory access request 140 and the first partition identifier in one of the entries included in the identified set 148, the tag comparison circuit 150 signals the multiplexer 152 or 154 to forward the matching second identifier from the entry with the matching first partition identifier. The second partition identifier is included in the output memory access request 142 along with the memory address specified in the input memory access request 140.

[0089] It will be apparent to those skilled in the art that, in an alternative configuration, the group-associative storage structure 146 may contain a greater number of entries (paths) per group. Furthermore, the partition identifier may be based solely on a subset of the bits of the first partition identifier, with the remaining bits either forwarded without translation or omitted from the translation.

[0090] Figure 9 The arrangement of conversion circuitry according to some configurations of the present technology is illustrated schematically. The conversion circuitry receives an input memory access request 160 from a first field specifying a first partition identifier. The first partition identifier is passed to an identifier conversion circuit 168, which stores a logic function 166 to convert the most significant portion of the first identifier to the most significant portion of a second identifier, for example, through a combination of two or more bits of the first partition identifier. The least significant portion of the first identifier is passed without conversion and used as the second partition identifier. The second partition identifier is output to be combined with the resource access request to generate an output resource access request 162 passed to the second field.

[0091] Figure 10 A sequence of steps performed by a conversion circuit according to some configurations of the present technology is illustrated schematically. The process begins at step S100, where it is determined whether an input resource access request with a specified first identifier has been received from a first domain. If it is determined at step S100 that no input resource access request with a specified first identifier has been received, the process remains at step S100. If it is determined at step S100 that an input resource access request with a specified first identifier has been received, the process proceeds to step S102. At step S102, based on conversion information defining the mapping between identifiers in the first and second domains, a conversion from the first identifier to the second identifier, indicating the requester process in the first domain, is performed. Then, the process proceeds to step S104, where a converted access request including the second identifier is output. The converted access request output omits the first identifier.

[0092] Figure 11Examples of emulator implementations that can be used are illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as emulators, in part because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the emulator implementation can run on a host processor 730, which optionally runs a host operating system 720, thereby supporting the emulator program 710. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide emulator implementations that execute at a reasonable speed, but such approaches may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the emulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0093] With respect to embodiments previously described with reference to specific hardware constructions or features, equivalent functionality may be provided in simulated embodiments by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. Where one or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 730), some simulated embodiments may utilize the host hardware where appropriate.

[0094] The simulator program 710 can be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 700 (which may include applications, operating systems, and management programs). This program interface is identical to the interface of the hardware architecture modeled by the simulator program 710. Therefore, the simulator program 710 can be used to execute the program instructions of the target code 700 from within the instruction execution environment, enabling a host computer 730, which does not actually possess the hardware features of device 2 discussed above, to emulate these features. In some configurations, the simulator code includes conversion program logic 740 for emulating the features of the conversion circuit described above.

[0095] In general, an apparatus, a method, and a computer program are provided. The apparatus includes a conversion circuit configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating a requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information defining a mapping between identifiers in the first and second domains. The first identifier is omitted from the output resource access request.

[0096] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0097] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features may be provided independently or in combination. For example, “at least one of [A], [B], and [C]” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0098] While exemplary configurations of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise configurations, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of the dependent claims can be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus, the apparatus comprising: A conversion circuit is configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first domain and the second domain. The first identifier is omitted from the output resource access request.

2. The apparatus of claim 1, wherein the number of identifiers available for allocation in the first identifier space and the second identifier space are defined independently of each other.

3. The apparatus according to claim 1 or claim 2, wherein the conversion information is dynamically configurable.

4. The apparatus according to any of the preceding claims, wherein the conversion circuitry includes one or more registers, and the conversion information is defined based on data stored in the one or more registers.

5. The apparatus of claim 4, wherein the one or more registers are memory-mapped registers.

6. The apparatus of claim 4 or claim 5, wherein the apparatus includes control circuitry configured to maintain the conversion information by modifying the one or more registers.

7. The apparatus according to any of the preceding claims, wherein the conversion information comprises one or more conversion lookup tables.

8. The apparatus according to any preceding claim, wherein the conversion information includes one or more conversion functions configured to map an identifier in the first domain to an identifier in the second domain.

9. The apparatus according to any of the preceding claims, wherein the conversion circuit is configured to be disposed at the boundary between the first domain and the second domain.

10. The apparatus of claim 9, wherein the boundary is the outer boundary of both the first domain and the second domain.

11. The apparatus according to any of the preceding claims, wherein the identifier in each of the first and second domains is assigned by a corresponding instance of management software running in the corresponding domain.

12. The apparatus according to any of the preceding claims, wherein the identifier in each of the first and second domains is used for resource allocation control to adjust the performance level perceived by resource access in the respective domain.

13. The apparatus according to any of the preceding claims, wherein the first identifier is independent of the memory address specified in the input resource access request.

14. The apparatus according to any of the preceding claims, wherein: The input memory access request specifies a security status identifier that indicates the input security status associated with the input memory access request; and The conversion circuit is configured to set the output security state of the output conversion request based on the input security state.

15. The apparatus of claim 14, wherein the conversion circuit is configured to set the output security state according to security conversion information defined in the conversion information.

16. The apparatus according to any of the preceding claims, wherein the conversion circuit is configured to perform an access request conversion from the second domain input to the first domain.

17. A system comprising: The apparatus according to any of the preceding claims; A first processing circuit, configured to implement the first domain; and A second processing circuit, configured to implement the second domain. The conversion circuit is configured at the interface between the first domain and the second domain.

18. The system of claim 17, wherein the system comprises: A third processing circuit, configured to implement a third domain; and A second conversion circuit is disposed at the boundary between the third domain and at least one of the first and second domains. The conversion circuit is unaware of the identifier assigned in the third domain.

19. A method comprising: An input resource access request received from a first domain is converted into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first domain and the second domain. The first identifier is omitted from the output resource access request.

20. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: A conversion program logic is configured to convert an input resource access request received from a first domain into an output resource access request for a second domain. The input resource access request includes a first identifier indicating the requester process in the first domain that generated the input resource access request, and the output resource access request includes a second identifier converted from the first identifier based on conversion information that defines a mapping between identifiers in the first domain and the second domain. The first identifier is omitted from the output resource access request.

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