High bandwidth memory buffer bridge die in a wiring substrate

Abstract

Memory systems and assembly methods are described, where the memory systems include a wiring substrate, a processor located on a first side of the wiring substrate, a memory die stack located on the first side of the wiring substrate, and a buffer bridge die embedded in the wiring substrate and electrically connecting the memory die stack with the processor.

Description

Related applications

[0001] This application claims the benefit of priority to U.S. Patent Application No. 19 / 063,131, filed February 25, 2025, and U.S. Provisional Application No. 63 / 571,805, filed March 29, 2024, each of which is incorporated herein by reference. Technical Field

[0002] The implementation schemes described herein relate to memory systems, and more specifically, to high-bandwidth memory systems.

[0003] Background Information Memory storage devices are an integral part of electronic devices such as personal computers, servers, game consoles, and mobile devices. Memory storage devices can be particularly important components in high-performance computing (HPC) and highly segmented, specialized workloads requiring high bandwidth and high-speed data access, such as artificial intelligence, analytics, and edge computing. While double data rate (DDR) memory solutions can meet most practical needs, the recent introduction of high-bandwidth memory (HBM) provides a memory platform that achieves even higher bandwidth while using less power and a much smaller form factor than DDR. This is achieved by vertically stacking multiple dynamic random access memory (DRAM) dies onto a logic die, which typically includes buffer circuitry and test logic and is often referred to as a buffer die. Compared to DDR, HBM has a wider memory bus with a larger number of channels driven at lower data rates, enabling lower power consumption compared to DDR. HBM also exhibits a significantly higher cost compared to DDR due to the inclusion of an interposer layer for accommodating a larger number of channels and finer-density routing. Summary of the Invention

[0004] A memory system, particularly an HBM system, and an assembly method are described, wherein the memory system includes a wiring substrate, a processor located on a first side of the wiring substrate, a stack of memory dies (e.g., a DRAM die stack) located on the first side of the wiring substrate, and a first buffer bridge die embedded in the wiring substrate and electrically connecting the memory die stack to the processor. The first buffer bridge die may include circuitry common to HBMs, including serialization / deserialization (SerDes) circuitry, buffer circuitry, error correction circuitry, and test circuitry. The memory die stack may include any suitable number of memory dies, such as 8 or 12, depending on the memory system generation. According to an embodiment, the memory die stack does not include logic dies; instead, this circuitry is offloaded to the first buffer bridge die. The memory system configuration according to the embodiment also expands the type of wiring substrate available, which does not necessarily require a silicon substrate. However, the wiring substrate can be mounted on a system substrate similar to a conventional HBM configuration.

[0005] The memory die stacks can also be arranged in rows and columns adjacent to the edge of the processor. In one embodiment, the memory die stack is one of a first plurality of memory die stacks in a first column. Each memory die stack in the first plurality of memory die stacks can be connected to the processor via a corresponding buffer bridge die. In an alternative configuration, each memory die stack in the plurality of memory die stacks can be connected to the processor via a first buffer bridge die. In one embodiment, a second plurality of memory die stacks can be arranged in a second column adjacent to the first column. In such a configuration, the second buffer bridge die can also be embedded in the wiring substrate and electrically connected to a second memory die stack in the second plurality of memory die stacks.

[0006] A bridging wiring chip can be additionally embedded in a wiring substrate to connect individual buffer bridging die. In one embodiment, the bridging wiring chip connects channel wiring from a second buffer bridging die to a first buffer bridging die. Furthermore, the bridging wiring chip can be completely passive, without active components, or alternatively, it can be an active die, in which case it may include repeaters and / or re-drivers / re-timers. Such repeaters and / or re-drivers / re-timers can optionally be added to the bridging wiring chip closer to the processor. According to one embodiment, both the first and second buffer bridging dies may include circuitry such as serialization / deserialization (SerDes) circuitry, buffer circuitry, error correction circuitry, and test circuitry. In one embodiment, the first buffer bridging die includes repeaters and / or re-drivers / re-timers coupled to channel wiring from the second buffer bridging die. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional side view of a conventional HBM system.

[0008] Figure 2A This is a schematic cross-sectional side view of a memory system including an embedded buffer bridge housing, according to an implementation scheme.

[0009] Figure 2B This is a schematic bottom-top view illustration of a memory system including an embedded buffer bridge housing according to an implementation scheme.

[0010] Figures 2C to 2D This is a schematic bottom-top view illustration of a memory system with embedded buffer bridge tubes and bridging wiring chips of different sizes according to the implementation scheme.

[0011] Figures 3A to 3E This is a schematic cross-sectional side view of the process of forming a memory system using a wiring substrate prefabrication method according to the implementation plan.

[0012] Figures 4A to 4D This is a schematic cross-sectional side view of the process of forming a memory system using a wiring substrate fabrication method according to the implementation plan.

[0013] Figure 5 This is a schematic cross-sectional side view of a heterogeneous memory system including an embedded buffer bridge housing, according to an implementation scheme.

[0014] Figure 6 This is a schematic cross-sectional side view of a heterogeneous memory system including an embedded buffer bridge housing, according to an implementation scheme.

[0015] Figure 7 This is a schematic cross-sectional side view of a memory system including an embedded buffer bridge housing, according to an implementation scheme. Detailed Implementation

[0016] The embodiments describe memory systems such as HBM systems and methods of manufacturing them. The memory system includes a memory die stack, a processor, a wiring substrate, and buffer bridging dies embedded in the wiring substrate. Specifically, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, a neural network processor, a system-on-a-chip (SoC), or other units that process data. The wiring substrate can be formed from various materials, such as a redistribution layer (RDL), a silicon interposer, a glass interposer, a printed circuit board, etc. The memory die stack according to the embodiments may be strictly limited to memory dies, without underlying logic (buffer) dies. Specifically, the memory die stack may be a DRAM die stack for HBM. Depending on the generation of the memory system, the number of memory dies may be 8, 12, etc. The buffer bridging dies according to the embodiments may include circuitry for conventional HBM, including serialization / deserialization (SerDes), buffering, error correction, and testing. Additionally, the buffer bridging dies may include die-to-die routing for die-to-die connections between the memory die stack and the processor. In some implementations, the buffer bridge core may include repeaters and / or re-drivers / re-timers for longer channel reach distances.

[0017] In one aspect, the implementation decouples the buffer / logic dies from supplier HBM and embeds circuitry for buffering, serialization / deserialization, error correction, etc., into the wiring substrate (e.g., RDL, interposer). This enables longer channels, additional rows of memory die stacks, greater control over memory management, and the fabrication of heterogeneous memory solutions (e.g., HBM and DDR). The buffer bridging die can be passive or active and can include repeater / retimer circuitry to enable longer routes from the processor to memory. Including channel routing in the buffer bridging die can additionally leverage the fine processing conditions and capabilities associated with the active silicon fab used to manufacture the buffer bridging die.

[0018] In another approach, implementations can reduce the overall cost of a memory system by minimizing the area of ​​active silicon. For example, one or more buffer bridging dielets can replace the silicon interposers present in a conventional HBM system, thereby significantly reducing the amount of active silicon required. Furthermore, one or more buffer bridging dielets can be partitioned into passive or active bridging wiring chips for signal relay, which can provide the fine routing required at a lower cost by completely eliminating active silicon or using cheaper processing nodes for specific circuits. The buffer bridging dielets according to the implementation can be further customized to minimize energy and maximize data rates, bandwidth, and channel length. The cost of active silicon can be attributed to the time and expense associated with fabricating active devices in silicon, as well as the time and cost of fabricating stacked wiring structures, which typically consist of low-dielectric-constant materials deposited using time-consuming vapor deposition techniques. Wiring for passive bridging chiplets and / or wiring substrates can be performed outside the active silicon fab, saving processing time and cost.

[0019] When multiple buffer bridge receivers are integrated into a memory system, these receivers may be identical in shape and circuitry, or they may have different shapes and / or circuitry. Core circuitry such as buffering, serialization / deserialization, and error correction may be similar across different sets of buffer bridge receivers. Some circuitry may optionally reside in one buffer bridge receiver and be shared by multiple buffer bridge receivers. One set of buffer bridge receivers may have additional circuitry not present in another set of buffer bridge receivers within the same memory system, such as repeaters and / or re-drivers / re-timers for longer channel transmission distances.

[0020] Various embodiments are described with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, numerous specific details, such as particular configurations, dimensions, and processes, are set forth to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, construction, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the repeated use of the phrase "in an embodiment" throughout the specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] As used herein, the terms “above,” “to,” “between,” “across,” and “on” can refer to the relative position of a layer with respect to other layers. A layer being “above,” “across,” or “on” another layer, or in combination with “to” another layer, or “in contact with” another layer, can mean directly contacting another layer or may have one or more interlayers. A layer “between” multiple layers can mean directly contacting those multiple layers or may have one or more interlayers.

[0022] Now for reference Figure 1 This diagram provides a cross-sectional side view of a conventional HBM system. As shown, the diagram may include a silicon interposer 102, which includes a base silicon substrate 104 and a wiring layer 106 above the base silicon substrate. The wiring layer may include multiple metal redistribution lines 108, vias 110, and a dielectric layer 112. The respective wiring layers and vias may additionally form die-to-die wiring 115 between a memory die stack 120 and a processor 116, both of which may be flip chips mounted on the same side of the silicon interposer 102 using solder bumps 114 (e.g., microbumps). The memory die stack 120 may include multiple memory dies 118 (such as DRAM dies) and buffer dies 122.

[0023] The silicon interposer 102 may additionally include vias 101, such as through-silicon vias (TSVs), for back-side connection to the system substrate 130 (such as a printed circuit board (PCB)). For example, the connection may be to a plurality of solder bumps 171, pins, etc. The system substrate may be a package substrate or a substrate for a larger module (including additional components mounted thereon). As shown, electrical wiring within the silicon interposer 102 may provide direct connections between the system substrate 130 and the processor 116 and / or memory die stack 120 (e.g., HBM), as well as die-to-die wiring 115 corresponding to channels.

[0024] Now for reference Figures 2A to 2B , Figure 2A This is a schematic cross-sectional side view of an HBM system including an embedded buffer bridge tube core, according to the implementation scheme. Figure 2BThis is a schematic bottom-top view illustration of an HBM system including embedded buffer bridging die according to an embodiment. As shown, the memory system 100 may include a wiring substrate 140 including one or more embedded buffer bridging dies 142A, 142B embedded therein. In the presence of multiple embedded buffer bridging dies 142A, 142B, they may be electrically connected to a bridging wiring chiplet 144 also embedded within the wiring substrate 140. As shown, memory die stacks 120A, 120B include multiple memory dies 118 (e.g., DRAM) and do not include stacked buffer dies. Thus, memory die stacks 120A, 120B include only memory dies 118. Memory die stacks 120A, 120B may be electrically connected to a processor 116 via one or more embedded buffer bridging dies 142A, 142B and bridging wiring chiplet 144.

[0025] The embedded buffer bridge terminals 142A and 142B according to the implementation scheme may include conventional buffer die circuitry for serialization / deserialization (SerDes), buffering, error correction, and testing. Additionally, the buffer bridge terminals may include die-to-die routing for die-to-die connections between memory die stacks and processors. In some implementations, the buffer bridge terminals may include repeaters and / or re-drivers / re-timers for longer channel transmission distances.

[0026] Offloading the buffer circuitry from the memory die stack to the wiring substrate 140 further reduces the channel length and facilitates custom circuit designs separate from the memory die stack, potentially resulting in additional efficiency when interfaced with the processor 116. The reduced channel length, along with the inclusion of repeaters and / or re-drivers / re-timers, facilitates longer channel lengths and includes multiple columns (A, B) of the memory die stacks 120A, 120B, thereby further increasing the potential bandwidth of the memory system 100.

[0027] For details, please refer to the following: Figure 2BThe figure illustrates two columns (A, B) of memory die stacks 120A and 120B, where each column comprises multiple rows of memory die stacks, for a total of six illustrated memory die stacks. While two columns are illustrated, it should be understood that embodiments may include a single column of memory die stacks adjacent to the edge of processor 116, but embodiments may also facilitate the expansion of memory columns. As shown, even when a single column of memory die stack 120A is arranged adjacent to processor 116, multiple rows of embedded buffer bridge duct dies 142A can electrically connect multiple memory die stacks 120A to processor 116. Therefore, not only can significant silicon cost reductions be achieved by removing the conventional silicon interposer 102, but silicon area savings can also be achieved in the row and column segmentation of embedded buffer bridge duct dies. In other embodiments, a single embedded buffer bridge duct die 142A can connect multiple embedded buffer bridge duct dies 142A in the same column to processor 116.

[0028] Still referencing Figures 2A to 2B The bridging wiring chip 144 can be purely passive and primarily used for channel routing, or it can be active and include repeaters and / or re-drivers / re-timers to facilitate longer channel lengths. It should be understood that the passive bridging wiring chip 144 can reduce costs by eliminating the need for active silicon. Including any repeaters and / or re-drivers / re-timers in an embedded buffered bridging chip where the cost of active silicon has already been reduced may be more cost-effective.

[0029] Depending on the memory die stacking layout, cost, and bandwidth requirements, the arrangement of buffer bridge dies and bridging wiring chips can have various configurations. (Reference) Figure 2C In the illustrated implementation, a single bridging wiring chip 144 can connect multiple rows and columns of buffer bridging diodes. This configuration can be cost-effective, especially when there is no active silicon in the bridging wiring chip 144. Figure 2D In the illustrated implementation, the buffer bridging connector die can span multiple rows of a memory die stack. Similarly, a single buffer bridging wiring chip 144 can be used to connect larger buffer bridging connector dies 142A, 142B.

[0030] In the case where multiple buffer bridge dies are integrated into a memory system, the multiple buffer bridge dies can be identical in shape and circuitry, or they can have different shapes and / or circuitry. Core circuitry such as buffering, serialization / deserialization, and error correction can be similar in different groups of buffer bridge dies. Some circuitry may optionally exist in one buffer bridge die and be shared by multiple buffer bridge dies. One group of buffer bridge dies may have additional circuitry not present in another group of buffer bridge dies in the same memory system, such as repeaters and / or re-drivers / re-timers for longer channel transmission distances. In an embodiment, the first embedded buffer bridge die 142A includes repeaters and / or re-drivers / re-timers for channels from the second memory die stack 120B.

[0031] Figures 3A to 3E This is a schematic cross-sectional side view illustrating the process of forming a memory system (e.g., an HBM system) using a wiring substrate prefabrication method according to an embodiment. It should be understood that this significantly simplifies the processing steps and anticipates process variations. Reference is now made to... Figure 3A The diagram shows a partially fabricated wiring substrate 140, which includes a substrate 104 such as silicon or glass, the substrate including a plurality of vias 101 and a wiring layer 106 above the substrate 104. The wiring layer may include a plurality of dielectric layers 112, vias 110, and metal redistribution lines 108. Additionally, a first trench 150 may be formed in the wiring layer 106 using suitable techniques.

[0032] The substrate 104 can be integrated to provide structural stability for the wiring substrate 140, but the substrate 104 is not required. Figure 3B An alternatively manufactured wiring substrate 140 is illustrated, which includes similar components. Figure 3A The diagram shows multiple dielectric layers 112, vias 110, metal redistribution lines 108, and a first trench 150. Figures 3A to 3B The dielectric layer 112, vias 110, and metal redistribution lines 108 can be fabricated using suitable techniques, such as thin-film deposition techniques commonly used to form package redistribution layers (RDLs). For example, the dielectric layer 112 can be formed using liquid solution techniques (such as spin coating, slot coating, etc.), lamination techniques, or more time-consuming techniques (such as chemical vapor deposition (CVD) or physical vapor deposition (PVD)). Suitable techniques such as electroplating, chemical vapor deposition, or lamination can be used to form the metal vias and redistribution lines. Various coarser fabrication techniques can optionally be used for the redistribution lines 108 because the channel traces exhibited in the die-to-die traces in the embedded buffer bridging die and the optional bridging wiring chiplet 144 can have finer spacing, smaller linewidth, and higher density than the surrounding redistribution lines 108.

[0033] Now for reference Figures 3C to 3E Examples of continuing in Figure 3A The structural processing steps, however, should be understood that the same processing steps can also be continued in Figure 3B The structure. For clarity and brevity, only regarding... Figure 3A The illustrated processing steps are shown. For example... Figure 3C As shown, an optional bridging wiring chip 144 can be placed into an optional first trench 150, which can then be filled with a gap-filling material 152, such as epoxy resin or other materials. The bridging wiring chip 144 can be positioned face-up, with the landing pad 158 facing upwards. The bridging wiring chip 144 can be formed of a variety of materials. For example, the bridging wiring chip 144 may include a substrate 151 (e.g., silicon) and one or more dielectric layers 153 and metal trace layers 156 and vias (not shown). The metal trace layers 156 and vias together can provide die-to-die wiring for multiple channels. According to embodiments, the bridging wiring chip 144 may be passive and therefore does not include active devices. In other embodiments, the bridging wiring chip 144 may optionally include active devices, such as repeaters and / or re-drivers / re-timers, at a certain cost.

[0034] After placing the bridging wiring chip 144, an additional layer of gap filler 152 is applied and formed on the wiring substrate 141. One or more second trenches 159 can then be formed in the wiring substrate 140 to expose the bridging wiring chip 144 and optionally expose any redistribution lines 108 (or contact pads connected thereto). One or more buffer bridging die 142 can then be mounted into one or more second trenches 159, for example, using flip-chip bonding and solder bumps 164 (microbumps). As shown, the buffer bridging die 142 may include a back-side landing pad 162 coupled to the solder bump 164, a substrate 161 (e.g., silicon), and one or more dielectric layers 163 and metal routing layers 166 and vias (not shown). Furthermore, a plurality of vias 165 (e.g., through-silicon vias) may extend through the substrate 161 for back-side connections. The metal routing layers 166 and vias together can provide die-to-die wiring and additional logic wiring for multiple channels. According to embodiments, the buffer bridging die 142 may be an active die, wherein active devices are formed in the substrate 161 according to standard processes. The buffer bridging die according to embodiments may include circuitry for conventional HBM, including serialization / deserialization (SerDes), buffering, error correction, and testing. Additionally, the buffer bridging die may include channel wiring for die-to-die connections between memory die stacks and processors. In some embodiments, one or more buffer bridging dies may include repeaters and / or re-drivers / re-timers for longer channel transmission distances.

[0035] Now for reference Figure 3E A gap filler material 170 may be formed around one or more buffer bridge cores 142 in one or more second trenches 159 to embed the buffer bridge cores 142 into the wiring substrate 140. This may be followed by additional processing, such as using solder bumps 114, to flip-chip attach one or more memory die stacks 120A, 120B and processor 116 to the same side of the wiring substrate 140. As shown, solder bumps may be mounted on landing pads 168 of the embedded buffer bridge cores 142 and landing pads coupled to redistribution lines 108 of the wiring substrate 140. Multiple solder bumps 171 may be additionally placed on landing pads on the back side of the wiring substrate 140 opposite to the mounted memory die stacks 120A, 120B and processor 116.

[0036] According to the implementation scheme, the electrical wiring path can extend directly from the solder bump 171 to the processor 116, and also directly to one or more memory die stacks 120A, 120B. As shown, the electrical wiring path can also extend from the solder bump 171 to the buffer bridging die 142, and optionally to the bridging wiring chiplet 144.

[0037] The memory system 100 according to the implementation scheme can also be manufactured using a wiring substrate post-fabrication method. Figures 4A to 4D This is a schematic cross-sectional side view illustrating the process of forming a memory system (e.g., an HBM system) using a post-fabrication method based on a wiring substrate, according to an embodiment. It should be understood that this significantly simplifies the processing steps and anticipates process variations. Figure 4A As shown, a reconfigured structure is illustrated, in which processor 116 and one or more memory die stacks 120A, 120B are encapsulated in molding compound layer 180, wherein processor 116 landing pad 182 and memory die stack landing pad 184 are exposed. One or more buffer bridge die 142 can then be mounted onto the exposed landing pads using solder bumps 114. Figure 4B As shown, the first buffer bridge connector die 142 is mounted on both the landing pad 182 of the processor 116 and the landing pad 184 of one or more of the innermost column memory die stacks 120A. The second buffer bridge connector die 142 is also mounted on the landing pad 184 of one or more memory die stacks 120B in the second column, and so on for additional column extensions.

[0038] Then, the wiring substrate dielectric layer 112, vias 110, and redistribution lines 108 can be partially fabricated to expose the landing pads 162 of the buffer bridge connector core 142, such as... Figure 4CAs shown. This can then be followed by using solder bumps 164 to mount the optional bridging wiring chip 144 onto the landing pad 184, as... Figure 4D As shown, the next step is to complete the wiring substrate 140 and place the solder bumps 171.

[0039] While the implementations to date have been illustrated with respect to homogeneous memory die stacks, multi-row memory die stacks, and multiple bridging wiring chips 144, various alternative configurations are envisioned.

[0040] See now Figures 5 to 6 A schematic cross-sectional side view illustration of a heterogeneous memory system including an embedded buffer bridge housing die, according to an embodiment, is provided. Figure 5 In the illustrated embodiment, a second column of memory dies 119 may be provided adjacent to the first column of the memory die stack 120A, wherein the type of memory dies 119 is different from the type of memory dies 118 forming the memory die stack 120A. For example, the memory die stack 120A may be designed for HBM, while the memory dies 119 may be designed for DDR memory. Figure 6 In the illustrated embodiments, the memory die stack 120B may include fewer memory dies 118 or lower quality memory dies than the memory die stack 120A.

[0041] Figure 7 This is a schematic cross-sectional side view of a memory system including an embedded buffer bridge die according to an embodiment. As shown, a single embedded buffer bridge die 142 may span beneath and be electrically connected to a multi-row memory die stack 120A, 120B. The single embedded buffer bridge die 142 may include separate circuitry (e.g., serialization / deserialization (SerDes), buffering, error correction, and testing) for buffering the individual memory die stacks 120A, 120B, and may also include some shared circuitry for the individual memory die stacks 120A, 120B. Additionally, the buffer bridge die may include die-to-die channel wiring for die-to-die connections between the memory die stacks 120A, 120B and the processor. In some embodiments, the buffer bridge die may include repeaters and / or re-drivers / re-timers for longer channel transmission distances.

[0042] When utilizing the various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming memory systems with embedded buffer bridges controlling the die. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments of the claims used for illustrative purposes.

Claims

1. A memory system, the memory system comprising: Wiring substrate; A processor, the processor being located on a first side of the wiring substrate; A memory die stack, wherein the memory die stack is located on the first side of the wiring substrate; as well as The first buffer bridge connector is embedded in the wiring substrate and electrically connects the memory die stack to the processor.

2. The memory system according to claim 1, wherein the first buffer bridge receiver includes a serialization / deserialization (SerDes) circuit, a buffer circuit, an error correction circuit, and a test circuit.

3. The memory system of claim 1, wherein the memory die stack comprises eight or more memory dies.

4. The memory system of claim 1, wherein the memory die stack does not include logic dies.

5. The memory system of claim 1, wherein the wiring substrate does not include a silicon substrate.

6. The memory system of claim 1, wherein the wiring substrate is mounted on the system substrate.

7. The memory system of claim 1, wherein the memory die stack is one of a first plurality of memory die stacks in a first column.

8. The memory system of claim 7, wherein each of the first plurality of memory die stacks is connected to the processor via a corresponding buffer bridge.

9. The memory system of claim 7, wherein each of the plurality of memory die stacks is connected to the processor via a die using the first buffer bridge.

10. The memory system of claim 7, further comprising a second plurality of memory die stacks arranged in a second column adjacent to the first column.

11. The memory system of claim 10, further comprising a second buffer bridge connector embedded in the wiring substrate and electrically connected to a second memory die stack in the second plurality of memory die stacks.

12. The memory system of claim 11, further comprising a bridging wiring chip embedded in the wiring substrate, the bridging wiring chip connecting a channel wiring from the second buffer bridging connector to the first buffer bridging connector.

13. The memory system of claim 12, wherein the bridging wiring chiplet is passive and does not include active devices.

14. The memory system of claim 12, wherein the second buffer bridge receiver includes a serialization / deserialization (SerDes) circuit, a buffer circuit, an error correction circuit, and a test circuit.

15. The memory system of claim 14, wherein the first buffer bridge connector includes a repeater coupled to the channel wiring from the second buffer bridge connector.

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