Reference image for distortion correction

Abstract

This invention relates to a method for generating a distortion-reduced image of a wafer having a periodic semiconductor structure. The method involves determining a reference image of the wafer showing a reference region of the wafer having at least one reference feature representing a portion of the periodic semiconductor structure; determining a plurality of additional images of the wafer, each additional image showing the reference region having the at least one reference feature and a milled region obtained by milling the top surface of the wafer, wherein the plurality of additional images differ from each other in the depth of the milled region; calculating a first position of the at least one reference feature in the reference image; and calculating a second position of the at least one reference feature in each of the additional images; determining a transformation by which the second position is matched to the first position; and applying the transformation to the additional images to obtain a distortion-reduced image in the milled region.

Description

Technical Field

[0001] This disclosure relates to a method for operating an ion beam apparatus and a corresponding ion beam apparatus. Background Technology

[0002] Semiconductor structures are among the most sophisticated man-made structures, yet various defects still exist. Devices for quantitative 3D metrology, defect detection, or defect review are currently used to locate these defects. The fabricated semiconductor structures are based on existing technologies. Semiconductor structures are made from a series of layers parallel to the substrate. For example, in logic-type samples, metal lines extend parallel to the metal layers or in high aspect ratio (HAR) structures, and metal vias extend perpendicular to the metal layers. The angles between metal lines in different layers are either 0° or 90°. On the other hand, for 3D NAND-type structures, their cross-section is known to be approximately circular.

[0003] Semiconductor wafers can reach diameters of up to 300 millimeters and comprise multiple sections, known as dies, each containing at least one integrated circuit pattern, such as those used in memory chips or processor chips. During manufacturing, a semiconductor wafer undergoes approximately 1000 process steps, forming approximately 100 or more parallel layers within it, including transistor layers, intermediate circuit layers, interconnect layers, and multiple 3D array memory cells in a memory device. The size, shape, and placement of the semiconductor structure and pattern are influenced by a variety of factors. Currently, etching and deposition are the key processes in 3D memory manufacturing. Other involved process steps (such as photolithography or implantation) also affect the characteristics of the IC device.

[0004] The aspect ratio and number of layers in integrated circuits are constantly increasing, and the structure is evolving towards three-dimensional (vertical) dimensions. Currently, the height of memory stacks exceeds five micrometers, and will likely reach tens of micrometers in the future. Conversely, feature sizes are becoming increasingly smaller. The smallest feature size, or critical size, is below 10 nm, such as 7 nm or 5 nm, and will approach 3 nm in the near future; for 3D NANDS, this is 150 nm, and for vertical DRAMS, it is around 30 nm. The thickness of semiconductor layers is approximately 10 nm or less. As the complexity and size of semiconductor structures increase towards three dimensions, the lateral dimensions of integrated semiconductor structures are becoming increasingly smaller. Therefore, high-precision measurement of the shape, size, orientation, and superposition of 3D features and patterns is becoming increasingly challenging.

[0005] As the requirements for the three-dimensional resolution of charged particle imaging systems continue to increase, the inspection and three-dimensional analysis of integrated circuits in wafers are becoming increasingly challenging.

[0006] 3D volumetric information of a wafer can be obtained based on a single wedge-cut slice image. For this purpose, a single wedge-cut slice image of the sample under study and a 3D-Tomo dataset are required, along with a reference sample containing devices manufactured using the same design and process. The necessary information, such as mesh parameters, can be determined from the corresponding 3D-Tomo dataset. However, this method is highly dependent on the consistency between the two datasets and the accurate determination of the mesh parameters. All deviations, such as imaging distortion, will affect the quality of the reconstruction. WO 2021 / 180600 A1 describes a method for reconstructing the examination volume based solely on two cross-sectional measurements, without requiring further knowledge of the mesh parameters.

[0007] Therefore, further improvements are needed in the distortion correction of images generated by the chip. Summary of the Invention

[0008] This requirement is met by the features of the independent claim. Further aspects are described by the dependent claims.

[0009] According to a first aspect, a method is provided for generating a distortion-reduced image of a wafer, wherein the data has a periodic semiconductor structure, wherein the method includes the step of determining a reference image of the wafer, the reference image showing a reference region of the wafer, wherein at least one reference feature represents a portion of the periodic semiconductor structure. Furthermore, a plurality of additional images of the wafer are determined, each of said additional images showing a reference region having at least one reference feature and a milled region obtained by milling the top surface of the wafer, wherein the plurality of additional images differ from each other in the depth of the milled region. A first position of at least one reference feature is calculated in the reference image, and for each of said additional images, a second position of at least one reference feature is calculated in the additional images. A transformation is determined, the second position is matched with the first position using the transformation, and the transformation is applied to the additional images to obtain a distortion-reduced image of the milled region.

[0010] In addition, a corresponding processing device is also provided, which includes a memory and at least one processing unit, wherein the processing device is configured to perform the method as described above or the method discussed in further detail below.

[0011] The generation of additional images of the wafer (especially when the images are used to generate 3D tomographic scans of the wafer) is very time-consuming. During this time, the equipment used to generate the images (such as a dual-beam setup using scanning electron microscopy techniques) may drift. This variation or any other variation in the imaging equipment during the image generation process can be accounted for and eliminated using the reference image and the additional images, as well as the reference features present in the reference images. Since the reference images and additional images include reference regions with reference features, transformations can be calculated to correct distortion differences between images acquired at different times.

[0012] It should be understood that the foregoing features and the features to be explained below can be used not only in the corresponding combinations indicated, but also in other combinations or alone, without departing from the scope of this disclosure. Attached Figure Description

[0013] Other features and advantages will become apparent to those skilled in the art from the following detailed description, which is taken in conjunction with the accompanying drawings, in which the same reference numerals denote the same elements.

[0014] Figure 1 A schematic diagram of the wafer configuration is shown, including a reference area for calculating the distortion reduction of the wafer and a milled area.

[0015] Figure 2 A schematic diagram showing a top view reference image and additional images including the milled area and reference features.

[0016] Figure 3 Show Figure 2 A schematic diagram illustrating how an image with reference features can be used to find a transformation for obtaining a distortion-reduced image.

[0017] Figure 4 As shown Figure 3 A more detailed schematic diagram of a portion of the image shown.

[0018] Figure 5 This diagram illustrates how images of the same sample taken at different orientations can be used to determine the image transformation used to determine distortion reduction.

[0019] Figure 6 It shows in more detail how the channels present in the chip are affected by different possible distortions.

[0020] Figure 7 A more detailed schematic diagram shows how different orientations can be used to reduce the effects of distortion.

[0021] Figure 8 Further examples of different sample orientation choices are shown for determining the image with reduced distortion.

[0022] Figure 9A schematic diagram of a flowchart is shown, which includes steps for determining the distortion reduction of an image.

[0023] Figure 10 A schematic diagram of a dual-beam system that can be used to inspect the semiconductor structure of a wafer is shown.

[0024] Figure 11 A schematic diagram of a channel provided in the wafer that can be used as a reference feature is shown.

[0025] Figure 12 A schematic diagram of a processing apparatus is shown, which can use reference features to determine the distortion reduction of an image. Detailed Implementation

[0026] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described below should not be considered limiting. The scope of this disclosure is not limited to the embodiments or illustrations described below, which are for illustrative purposes only.

[0027] The illustrations should be considered schematic, and the elements shown are not necessarily to scale. Rather, those skilled in the art will understand the function and general purpose of the various elements. Any connection or coupling between functional blocks, devices, components, or other entities or functional units shown in the illustrations or described herein may also be implemented through indirect connection or coupling. Coupling between multiple components may also be established wirelessly. Functional blocks may be implemented using hardware, firmware, software, or a combination thereof.

[0028] Examples of this disclosure are generally provided for use with multiple circuits or other electrical devices. All references to circuits and other electrical devices and the functions provided by each device are not intended to limit the scope of what is illustrated and described herein. Although certain reference numerals may be assigned to the various circuits or other electrical devices disclosed, these reference numerals are not intended to limit the scope of operation of the circuits and other electrical devices. Such circuits and other electrical devices may be combined and / or separated in any way based on the desired type of electrical implementation. It is understood that any circuit or other electrical device disclosed herein may include any number of microcontrollers, graphics processing units (GPUs), integrated circuits, memory devices (e.g., FLASH, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or other suitable variations), and software that cooperates to perform the operations disclosed herein. Furthermore, any one or more of the electrical devices may be configured to execute program code specifically implemented in a non-transitory computer-readable medium, said medium being programmed to perform any number of functions as disclosed.

[0029] The following section will discuss in more detail how to correct distortion differences between wafer images obtained at different times. Using... Figure 10The system shown can take several hours, or even a whole day, to generate a 3D tomographic scan. During this time, the dual-beam device may drift.

[0030] As described below, top-view image portions are used to determine distortion. Based on the top-view portions contained in all images, a transformation can be determined to correct distortion differences between images acquired at different times.

[0031] refer to Figure 10 A system is shown that can be used to inspect the structure of a semiconductor sample 20 and generate an image of the sample (wafer) that can be used to inspect for distortions that occur during the generation of the wafer image. The inspection system 100 is configured to perform slicing and imaging methods using a dual-beam device 1 in a wedge-cut geometry. For the wafer 20, multiple measurement sites, including measurement sites 21 and 22, are defined in a position image or inspection list generated by the inspection tool or design information. The wafer 20 is placed on a wafer support 10. The wafer support 10 is mounted on a wafer platform 90 having actuators and a position controller. Actuators and mechanisms (such as laser interferometers) for precise control of the wafer platform are known in the art. A control unit 80 is configured to control the wafer platform 90 and adjust the wafer 20 to the measurement site 21 at the intersection 43 of the dual-beam device 1. The dual-beam device 1 includes an FIB generation unit 50 with a FIB optical axis 48 and a charged particle beam (CPB) imaging system 40 with an optical axis 42. At the intersection 43 of the two optical axes of the FIB and CPB imaging systems, the wafer surface is configured to be tilted at an angle α to the FIB axis 48. An angle β is formed between the FIB axis 48 and the CPB imaging system axis 42, and an angle GE is formed between the CPB imaging system axis and the normal to the wafer surface 55. Figure 1 In the coordinate system, the normal to the wafer surface 24 is provided by the z-axis. A focused ion beam (FIB) 51 is generated by the FIB generation unit 50 and impacts the surface 55 of the wafer 20 at an angle α. At the inspection or measurement location 21, an inclined profile surface is milled into the wafer by ion beam milling, with an inclination angle or milling angle approximately alpha (α). Figure 10 In this example, the incident angle alpha (α) is approximately 30°. Using a charged particle beam imaging system 40, tilted at an angle α to the wafer normal, an image of the milled surface can be obtained. Figure 2 In this example, the angle GE is approximately 15°. However, other configurations are also possible, such as GE = alpha, which makes the CPB imaging system axis 42 perpendicular to the FIB axis 48, or GE = 0°, which makes the CPB imaging system axis 42 perpendicular to the wafer surface 55.

[0032] During imaging, a charged particle beam 44 scans the cross-sectional surface of the wafer at the measurement location 21 along the scanning path using the scanning unit of the charged particle beam imaging system 40, generating secondary and scattered particles. A particle detector 30 collects at least some of the secondary and scattered particles and transmits the particle count to the control unit 60. Other detectors of other types of interactive products may also be present. The control unit 60 controls the charged particle beam imaging system 40, the FIB generation unit 50, and is connected to a further control unit 80 to control the position of the wafer mounted on the wafer support via the wafer platform 90. The control unit 60 communicates with an operation control unit 70, which triggers the placement and alignment of the wafer 20, for example, the measurement location 21, at the intersection 43 via wafer platform movement, and repeatedly triggers FIB milling, image acquisition, and platform movement operations.

[0033] Each new intersecting surface is milled by FIB beam 51 and can be imaged by charged particle imaging beam 44, which is, for example, a scanning electron beam or a helium ion beam of a helium ion microscope (HIM).

[0034] Figure 11 A schematic diagram of a semiconductor sample is shown, in which a region of interest or measurement site 21 in wafer 20 is examined to determine whether the desired structure, particularly the appearance of the semiconductor structure, is provided for any semiconductor structure implemented in wafer 20. In the example shown, measurement site 21 includes multiple structures 81, 82, and 83 extending along the sample thickness direction, wherein these structures may represent channels or other high aspect ratio, HAR structures. It can be assumed that measurement site 21 contains N different channels.

[0035] Figure 1 A schematic diagram of the measuring area 21 is shown. The measuring area 21 includes a reference area 25 and a milling area 26. Ideally, reference areas 25a, 25b, and 25c form the framework of the entire milling area 26. The purpose of reference area 25b is to allow for a clear measurement of the relationship between the boundaries of the left side 25a and the right side 25c, which is performed on a completely flat area. In this case, area 26 is flat.

[0036] To correct different image distortions between images, the transformation between reference portions of the images can be determined. For this purpose, features in the reference regions, such as... Figure 11 The channels shown, for example, can be detected using cross-correlation calculations with the template. Corresponding features in the image reference region are identified. This identification is feasible because the distortion between the two images is relatively small compared to the distance between the reference features.

[0037] Figure 2 A more detailed view of reference image 200, showing the top surface of wafer 20, is provided, and this reference image is shown in top view. Figure 11 Reference feature 210 of the channel. Furthermore, channels 221-223 located in the milling region 220 generated using an ion beam apparatus are shown. Figure 2 The right side shows an additional image produced after milling began. Figure 2 To the right, the additional image also shows channels 321, 322, and 323 as shown in the structure of reference feature 310 and milled region 320. Reference image 200 and the additional image, wedge image 300, can be scaled or cropped in slightly different ways. Using the reference feature locations of superimposed images 200 and 300, features 210 and 310 here can be used to determine a transformation, which can be used to determine a distortion-reduced image, such as... Figure 3 The lower part shows the image 400 with reduced distortion. This transformation can be determined by fitting an affine transformation, for example, mapping the coordinates of the features detected in region 25 of the reference image to the corresponding coordinates in region 25 of the image obtained from the measurement site.

[0038] Figure 4 More detailed views of reference area 25 and milling area 26 are provided. Reference features such as channel locations on the top surface of the wafer can be overlaid, such as... Figure 4 As shown on the left. By applying a transformation based on features 210 and 310, the positions of channels 321 and 322 are transformed to new positions 321' and 322'. After this transformation, the channels can be reconstructed. To determine the centroid positions of the reconstructed channels, the new positions 321' and 322' are compared with the general positions 221 and 222. Using the transformation, the correction positions of reference features 210 and / or 310 can be calculated, and the new positions of channel positions 221', 222' and 321' and 322' can be used to determine the correction positions of the channels.

[0039] Because 3D reconstruction based on a single wedge image is sensitive to any small scaling or shearing effects, this procedure can be used to improve the accuracy of the reconstruction results. Co-pending application DE 102023115975 A1 discloses the generation of a representative reference standard structure for channels extending in the wafer thickness direction, where this reference standard structure is used to determine the transformation of other channels that can be adapted. For reconstruction based on calibration of a single reference wedge image, the single wedge image to be analyzed can be matched with a reference image of this method. Co-pending application DE 102023115975 describes a method for obtaining semiconductor structure measurements from a single wedge of the examined volume. For reconstruction based on reference coordinates extracted directly from the image, as discussed in co-pending application DE 102023120462, it is important that the relationship between the coordinates in the reference image and the wedge image is not affected by scaling or shearing issues. For such reconstruction or any other reconstruction, it is recommended to record the reference area of ​​all images. [The following text appears to be incomplete and requires further context:] Figure 2The top view shown, and the reconstruction of the image with reduced distortion, may include the following steps: The first step is to record or obtain a top-view image from a database (such as image 200, which includes region 25 used as a reference area). Additionally, region 26 exists in image 200, which will later become the milling area, including the wedge-shaped region, as shown in image 300. This image should be obtained once for each sample type or wafer type.

[0040] The second step is to process each sample site (such as...) Figure 10 Image 300 is generated by milling a wedge-shaped cut at portions 21 and 22 (shown), and recording an image containing the wedge-shaped region of interest and a reference region for distortion correction. Reference features 210 and 310 (channel representations), as well as 221-223 and 321-323, are detected in the third step. In the next step, the reference regions in the two images are matched, and corresponding features in the two sets of images are identified. This process is accomplished by assigning the detection results on each image to points in an idealized grid, and setting an appropriate grid origin. Detections assigned to the same grid points in the same two datasets are then considered as corresponding features.

[0041] In a further step, a transformation is determined based on the coordinates of the corresponding features. For example, an affine transformation can be fitted to convert the coordinates of reference feature 310 in image 300 and the additional image to coordinates determined for reference image 200. This transformation can then be applied to all the different additional images produced from the wafer at different milling stages. Appropriate selection of transformations (such as affine transformations) can also compensate for potential misorientations between image sets. Here, channel representations in images 200 and 300 can be detected. The coordinates of channel positions, such as center positions, can then be removed from the channel positions determined in the additional image 300. These coordinate differences are then interpreted as the xzy coordinates of the reconstructed channel. Since multiple data points may exist for a channel within a small height interval, the data points within the height interval can be clustered to establish a single channel, as disclosed in co-pending application DE 102023115975 A1.

[0042] In summary, if an image suffers from different distortions, it can be corrected numerically because it shares the same content within the outer frame (i.e., the reference area).

[0043] As related Figure 5 The discussion suggests that distortion can be eliminated and reduced by acquiring images of the wafer 20 with wedge-shaped or milled regions 26 using different orientations of the wafer and wedge portions relative to the imaging system. Information from these images can then be combined to determine the average conversion. Figure 5 As shown, with Figure 5After obtaining the first image using the orientation shown on the left, the sample can be rotated 180° to obtain another image. Distortion can lead to… Figure 5 The right y-direction offset shown depends on the depth z, and the two images will be affected by different distortions.

[0044] This will combine Figure 6 A more detailed explanation follows. Here is shown a first 3D characterization 400 of the wafer, where the wedge-shaped portion or milled region 26 has a first orientation. The true sample coordinates are shown as 410, where a distorted coordinate system 415 is also shown. The centroid positions of the actual channels are indicated by labels 430 and 431, while the distorted centroid positions of the channels are indicated by labels 420 and 421. The same applies to the 3D characterization with another orientation of the sample; dataset 500 has a distorted coordinate system 515 and a true coordinate system 510. Here, the distorted centroid position of the vertical channel is shifted to the right side of the image, thus corresponding to the true centroid positions 530 and 531. Figure 6 Compared to samples with other orientations, the distorted centroid positions 520 or 521 are... Figure 6 The degree of shift to the right is greater.

[0045] Figure 7 This is further summarized, showing channel positions 541 and 542 on the top surface, and undistorted wedge positions 551 and 552, while 561 and 562 are distorted wedge positions. Therefore, depth-related image offsets exist, such as... Figure 7 The lower part, shown below, provides the observed offsets. When the sample orientation changes by 180°, the corresponding top surface positions are 441 and 442, the distortion-free wedge positions are 451 and 452, and the distorted channel positions are 461 and 462. The true channel offset and image offset in the real sample can be calculated using the following formula:

[0046] (1) Differences in distortion directly affect the reconstruction results of each dataset. The channel tilt changes in the two datasets have opposite signs. Therefore, combining the two datasets can be used to extract or eliminate the effects of distortion. For example, the two datasets can be analyzed separately, and then the results averaged. This leads to the elimination of distortion effects. After reconstruction, image shift causes the two reconstructions to produce opposite tilts, while in both cases, the true channel stitch blocks are oriented in the same direction. Therefore, averaging is used to eliminate image shift.

[0047] For other distortions, different sample orientations can be selected, such as those related to... Figure 8 The discussion focuses on, for example, image datasets from two orthogonal directions (such as...). Figure 8The datasets 600 and 700 can detect distortion that causes the magnification in the y-direction to change with the z-direction. If the wedge surface is oriented in the x-direction of the SEM, this will cause the sample x-coordinate to fan out. A 90-degree rotation is taken into account here. The geometry of the sample does not change, so the wedge descends along the y-direction of the sample in both cases. The ideal coordinates are shown here. Figure 8 The grid lines on the right. The dashed lines show how SEM distortion affects the coordinates in the measurement. In this case, the y-scaling varies with z, while x is unaffected. The top column shows how this distortion causes curvature in the y-coordinate of the reconstructed channels, as indicated by the dashed lines in the upper right. In the bottom column, the sample is rotated 90 degrees. The image distortion remains the same. If you move along the wedge from top to bottom, you can see that the distance between features at the same depth increases with depth.

[0048] Figure 9 This paper summarizes some of the steps performed in the aforementioned methods to determine the image with reduced distortion.

[0049] In step S81, a reference image of the wafer is determined, which may be an image of the top surface of the wafer, including a reference region, such as region 25, which shows reference features such as channel locations. In step S82, multiple additional images of the wafer are generated. These additional images also show the reference region and the milled region obtained by bombarding the top surface with an ion beam. The different images thus show the milled surface, wherein the amount of surface removed from the wedge portion gradually increases with each image. These additional images also show the reference region, and each additional image also includes the milled region 26. In step S83, a first position of at least one reference feature is determined in the reference image, and in step S84, a second position of the reference feature is determined in the additional images. Based on the first and second positions, a transformation that matches the positions in the reference regions to each other can be determined. After the transformation is determined in step S85, the transformation can be applied to the additional images in step S86 to obtain an image with reduced distortion of the wafer and the milled region.

[0050] Figure 12 A schematic architectural diagram of a processing device 1000 is shown, which can perform the transformation calculations discussed above and the applications to further images. The processing device 1000 can... Figure 10The processing device 1000 may be implemented in any of the entities shown, such as unit or entity 60, 70, or 80, but may also be implemented as a standalone unit. The processing device 1000 includes an interface 1100 provided for transmitting and receiving data, such as receiving and transmitting images, and, if necessary, corrected images after application conversion. The processing device 1000 includes a processing unit 1200 responsible for operating the processing device 1000. The processing unit 1200 includes one or more processors and is capable of executing instructions stored in memory 1300, wherein the memory may include read-only memory, random access memory, mass storage, hard disk, etc. The memory may include appropriate program code executed by the processing unit 1200 to implement the aforementioned functions of the processing device. The processing device may be implemented in a single node or distributed across multiple nodes or entities in a cloud-based implementation.

[0051] Several conclusions can be drawn from the above discussion.

[0052] Additional images can be used for 3D tomography of a wafer, and the periodic semiconductor structure may include channels extending in the wafer along a thickness direction substantially perpendicular to the wafer surface, wherein a distortion-reduced 3D tomography is determined based on a transformation, and wherein the distortion-reduced 3D tomography is used to determine the location of the channels in the wafer.

[0053] The reference region may be located on the top surface of the wafer outside the milled area, and at least one reference feature may include a channel characterization.

[0054] In addition, the grid of channels present in the reference region of the reference image can be matched with the grid of channels present in the reference region of the attached image to determine the transformation.

[0055] Reference images and additional images can be generated using a dual-beam setup and scanning electron microscopy.

[0056] The reference image and the supplementary image each may show at least four reference features, and the at least four reference features may be distributed across the reference image and the supplementary image such that the minimum spacing between two reference features located at their maximum distance relative to each other is greater than half the diagonal of the supplementary image. In other words, this means that the reference features are distributed across the image, making it possible to determine position-related distortions across the entire image range.

[0057] In addition, at least four reference features may be distributed on the reference image and the additional image, such that the reference features are located on both sides of the milling area.

[0058] This conversion can be used to correct distortions such as image scaling, trapezoidal distortion, cropping, or warping.

[0059] Furthermore, at least some or both of the additional images can be generated based on different wafer orientations, and a first distortion is determined using one of the additional images and a reference image, wherein the wafer has the first orientation. A second distortion is determined using another, or a further additional image, and a reference image, wherein the wafer has a different orientation than the first orientation. An average transformation can then be calculated based on the first and second distortions, wherein a distortion-reduced image is generated based on the average transformation. This has been previously combined with... Figures 6 to 8 discuss.

[0060] The orientations of different images can differ from each other by 180° or 90°.

[0061] In summary, by using reference images with the same orientation, or even wafers with different orientations, imaging distortion can be obtained and eliminated, thus improving the calculation of channel positions.

Claims

1. A method for generating a distortion-reduced image of a wafer having a periodic semiconductor structure, the method comprising performing the following steps on a processing apparatus: A reference image of the wafer is determined, the reference image showing a reference region of the wafer having at least one reference feature representing a portion of the periodic semiconductor structure; Multiple additional images of the wafer are determined, each additional image showing the reference region having the at least one reference feature and the milled region obtained by milling the top surface of the wafer, wherein the multiple additional images differ from each other in the depth of the milled region; Calculate the first position of the at least one reference feature in the reference image; For each additional image, calculate the second position of the at least one reference feature in that additional image; Determine a transformation by which the second position is matched to the first position; and The conversion is applied to the additional image to obtain an image with reduced distortion in the milled area.

2. The method of claim 1, wherein the additional image is used for 3D tomographic imaging of the wafer, and the periodic semiconductor structure includes channels in the wafer extending in a thickness direction substantially perpendicular to the surface of the wafer, the method further comprising: Based on this transformation, 3D tomography with reduced distortion is determined; as well as The distortion-reduced 3D tomography was used to determine the location of the channel in the wafer.

3. The method of claim 1 or 2, wherein the reference region is located on the upper top surface of the wafer outside the milling region.

4. The method of claim 2 or 3, wherein the at least one reference feature includes a characterization of the channel.

5. The method of any one of claims 2 to 4, wherein the grid of channels present in the reference region of the reference image is matched with the grid of channels present in the reference region of the additional image to determine the transformation.

6. The method of any of the preceding claims, wherein at least two additional images are generated at different orientations of the wafer; wherein a first distortion is determined using one of the additional images and the reference image of the wafer having a first orientation, and a second distortion is determined using the other of the additional images and the reference image of the wafer having a second orientation different from the first orientation; wherein an average conversion is calculated based on the first distortion and the second distortion; wherein the distortion-reduced image is generated based on the average conversion.

7. The method of claim 6, wherein the first orientation of the wafer differs from the second orientation by 180 degrees from the first orientation by rotating about an axis, and the axis extends perpendicular to the reference region.

8. The method of claim 6, wherein the first orientation of the wafer is 90 degrees different from the second orientation and rotates about an axis, and the axis extends perpendicular to the reference region.

9. The method of any of the preceding claims, wherein at least the additional image is generated using a dual-beam apparatus and scanning electron microscopy techniques.

10. The method of any of the preceding claims, wherein both the reference image and the additional image display at least four reference features distributed on the reference image and the additional image such that the minimum distance between the two reference features that are most distant from each other is greater than half the diagonal of the additional image.

11. The method of any of the preceding claims, wherein both the reference image and the additional image display at least four reference features distributed on the reference image and the additional image such that the reference features are located on both sides of the milling area.

12. The method of any of the preceding claims, wherein the conversion is used to correct at least one of the following in the image with the reduced distortion: Image scale; Trapezoidal distortion; Cutting; and Deformation.

13. A processing apparatus (1000) comprising a memory (1300) and at least one processing unit (1200), the memory including instructions executable by the processing unit, wherein when the at least one processing unit executes the instructions, the processing apparatus causes to perform the following operations: A reference image of the wafer is determined, the reference image showing a reference region of the wafer having at least one reference feature representing a portion of the periodic semiconductor structure; Multiple additional images of the wafer are determined, each additional image showing the reference region having the at least one reference feature and the milled region obtained by milling the top surface of the wafer, wherein the multiple additional images differ from each other in the depth of the milled region; Calculate the first position of the at least one reference feature in the reference image; For each additional image, calculate the second position of the at least one reference feature in that additional image; Determine a transformation by which the second position is matched to the first position; and The conversion is applied to the additional image to obtain a less distorted image in the milled area.

14. The processing apparatus of claim 13, wherein when the at least one processing unit executes the instruction, the processing apparatus performs the method of any one of claims 1 to 12.

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