LED driving circuit and driving method thereof

Abstract

An LED driving circuit and its driving method are disclosed. The LED driving circuit includes a data transmission device, a bridging integrated circuit, and a plurality of data driving devices. The driving method of the LED driving circuit includes: a step of sequentially registering IDs for the first to Nth data driving devices, where N is a natural number greater than or equal to 3; a step of sequentially writing instructions to the first to Nth data driving devices; a step of sequentially writing to registers by the first to Nth data driving devices; and a step of sequentially reading from registers by the first to Nth data driving devices. The first data driving device among the plurality of data driving devices receives an identifier from the data transmission device and stores it as its own identifier, modulates the identifier, and transmits it to the adjacent data driving device. This reduces the necessary number of channels compared to the existing control method of directly controlling each driving integrated circuit in a microcontroller unit.

Description

Technical Field

[0001] This embodiment relates to an LED driving circuit and its driving method. Background Technology

[0002] With the advancement of information technology, various display devices capable of visualizing information have been developed. Liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), and plasma display panels (PDPs) are representative examples of display devices developed or under development in recent years. These devices are evolving towards the ability to clearly display high-resolution images.

[0003] In LED display device technology, a large panel can be formed by configuring modular LED pixels in the required number, or a large panel structure can be formed by configuring unit panels composed of a plurality of LED pixels in the required number. As mentioned above, in LED display device technology, large display devices can be easily realized by expanding the number of LED pixels as needed.

[0004] LED display devices not only have advantages in terms of large size, but also in terms of diverse panel sizes. In LED display device technology, the horizontal and vertical dimensions can be adjusted in various ways by appropriately configuring LED pixels. Summary of the Invention

[0005] The problem that the invention aims to solve

[0006] The purpose of this embodiment is to provide an LED driver circuit and its driving method that can reduce the number of necessary channels (LANEs) compared to the existing control method of directly controlling the respective driver integrated circuits in the microcontroller unit.

[0007] The purpose of this embodiment is to provide an LED driving circuit and driving method that enables the synchronization of the start time of frequency pulse width modulation (FPWM) by resetting multiple driving integrated circuits through a vertical synchronization signal.

[0008] The purpose of this embodiment is to provide an LED driving circuit and driving method in which multiple driving integrated circuits can synchronize the dimming start time through an input synchronization signal generated by FPWM.

[0009] Technical solutions to the problem

[0010] The LED driving circuit of this embodiment includes: a data transmission device for transmitting a clock signal, a data signal, and an identifier for adjusting the LED driving current; a bridging integrated circuit including a plurality of channels (LANEs) and receiving the clock signal and the data signal; and a plurality of data driving devices for receiving the clock signal and the data signal from the channels and transmitting them sequentially; a first data driving device among the plurality of data driving devices receives the identifier and stores it as its own identifier, modulates the identifier, and transmits it to an adjacent data driving device.

[0011] When multiple data driving devices register IDs, the data transmission device can load the number of integrated circuits connected to the channel (LANE) of the bridging integrated circuit minus 1 into the ID, and send a preamble signal, the ID, and an ID allocation command to the first data driving device; if the first data driving device is input with the preamble signal and the ID allocation command, it can register the ID received from the data transmission device as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal, the ID, and the ID allocation command to the second data driving device; if the second data driving device is input with the preamble signal and the ID allocation command, it can register the ID received from the first data driving device as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal, the ID, and the ID allocation command to the third data driving device; if the Nth data driving device is input with the preamble signal and the ID allocation command, it can register the ID received from the (N-1)th data driving device as its own ID, where N is a natural number greater than or equal to 3.

[0012] It may also include the step of sending an ID allocation completion signal to the data transmission device if the ID registered by the Nth data driver device becomes 0.

[0013] It may also include the step of transmitting a wait command to the second data driving device if the first data driving device is input with the preamble signal and the ID allocation command.

[0014] It may also include the step of transmitting a wait command to the third data driver if the second data driver is input with the preamble signal and the ID allocation command.

[0015] When the first data driving device to the Nth data driving device writes an instruction, the process may include the following steps: the data transmission device sends the preamble signal, the instruction write command, and the address to the first data driving device; when the first data driving device is input with the instruction write command, it decodes and latches the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then writes the latched instruction; when the second data driving device is input with the instruction write command, it decodes and latches the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then writes the latched instruction; when the Nth data driving device is input with the instruction write command, it decodes and latches the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then writes the latched instruction.

[0016] The first to the Nth data driving devices can be synchronized to the start time of FPWM (Frequency Pulse Width Modulation) by resetting with a vertical synchronization signal.

[0017] The first to Nth data driving devices can synchronize the dimming start time using the input synchronization signal generated by FPWM (Frequency Pulse Width Modulation).

[0018] When the first data driving device to the Nth data driving device writes to the register, the data transmission device can send the preamble signal, the register write command, the address, and N data to the first data driving device. When the first data driving device is given a register write command by the data transmission device, it can receive the address and, after multiplying its own ID by the number of bits in the N input data, identify the input data as its own data and then update it. When the second data driving device is given a register write command by the first data driving device, it can receive the address and, after multiplying its own ID minus 1 by the number of bits in the N input data, identify the input data as its own data and then update it. When the Nth data driving device is given a register write command by the (N-1)th data driving device, it receives the address and, after identifying the input data as its own data, identify the input data as its own data and then update it.

[0019] When the first data driver device to the Nth data driver device reads the register, the process may include the following steps: the data transmission device sends the preamble signal, the register read command, and the address to the first data driver device; when the first data driver device is input with the register read command from the data transmission device, it receives the address and prepares the data corresponding to the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data; when the second data driver device is input with the register read command from the data driver device, it receives the address and prepares the data corresponding to the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data; when the Nth data driver device is input with the register read command from the (N-1)th data driver device, it prepares the data corresponding to the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data.

[0020] In a driving method for an LED driving circuit according to an embodiment of the present invention, the LED driving circuit includes a data transmission device, a bridging integrated circuit, and a plurality of data driving devices. The driving method for the LED driving circuit includes: a step of sequentially registering IDs for a first data driving device to an Nth data driving device, where N is a natural number greater than or equal to 3; a step of sequentially writing instructions to the first data driving device to the Nth data driving device; a step of sequentially writing instructions to a register by the first data driving device to the Nth data driving device; and a step of sequentially reading instructions from the register by the first data driving device to the Nth data driving device; wherein the first data driving device among the plurality of data driving devices receives an identifier from the data transmission device and stores it as its own identifier, modulates the identifier, and transmits it to an adjacent data driving device.

[0021] The steps for registering IDs from the first data driver device to the Nth data driver device may include: the data transmission device loading the number obtained by subtracting 1 from the number of integrated circuits connected to the channel (LANE) of the bridging integrated circuit into the ID, and sending a preamble signal, the ID, and an ID allocation command to the first data driver device; the first data driver device registering the ID received from the data transmission device as its own ID if it is input with the preamble signal and the ID allocation command; and the first data driver device loading the number obtained by subtracting 1 from the registered ID into the ID, and sending the preamble signal, the ID, and an ID allocation command to the first data driver device. The steps include: sending a preamble signal, the ID, and the ID allocation command to a second data driving device; registering the ID received from the first data driving device as its own ID if the second data driving device is input with the preamble signal and the ID allocation command; loading the number obtained by subtracting 1 from the registered ID into the ID, and sending the preamble signal, the ID, and the ID allocation command to a third data driving device; and registering the ID received from the (N-1)th data driving device as its own ID if the Nth data driving device is input with the preamble signal and the ID allocation command.

[0022] Invention Effects

[0023] According to this embodiment, compared to the existing control method of directly controlling each driver integrated circuit in the microcontroller unit, the number of necessary channels (LANEs) can be reduced.

[0024] According to this embodiment, multiple driver integrated circuits are reset by a vertical synchronization signal, which can synchronize the start time of FPWM (Frequency Pulse Width Modulation).

[0025] According to this embodiment, multiple driver integrated circuits can synchronize the dimming start time through the input synchronization signal generated by FPWM. Attached Figure Description

[0026] Figure 1 This is a block diagram of an LED driving circuit according to an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram showing the state in which an ID is assigned when registering an ID in the first to third driver integrated circuits of an embodiment of the present invention.

[0028] Figure 3 This is a timing diagram illustrating the registration ID process of the first driver integrated circuit to the third driver integrated circuit according to an embodiment of the present invention.

[0029] Figure 4 This is a schematic diagram showing the state in which an instruction is assigned an ID when writing an instruction to a first driver integrated circuit and a second driver integrated circuit according to an embodiment of the present invention.

[0030] Figure 5 This is a timing diagram illustrating the process of writing instructions to the first driver integrated circuit and the second driver integrated circuit according to an embodiment of the present invention.

[0031] Figure 6 This is a timing diagram illustrating the process of writing registers from the first driver integrated circuit to the Nth driver integrated circuit according to an embodiment of the present invention.

[0032] Figure 7 This is a timing diagram illustrating the process of reading registers from the first driver integrated circuit to the Nth driver integrated circuit according to an embodiment of the present invention.

[0033] Figure 8 This is a block diagram illustrating the logic of a driver integrated circuit according to an embodiment of the present invention.

[0034] Figure 9 This is a timing diagram illustrating the synchronization of a driver integrated circuit according to an embodiment of the present invention.

[0035] Figure 10 This is a timing diagram used to illustrate the vertical synchronization signal command of an embodiment of the present invention.

[0036] Figure 11 This is a timing diagram illustrating how an input synchronization signal is generated by frequency division using FPWM and SCK according to an embodiment of the present invention.

[0037] Figure 12 This is a timing diagram illustrating an embodiment of the present invention of performing LED dimming by synchronizing FPWM between driver integrated circuits. Detailed Implementation

[0038] If refer to and append Figure 1 The advantages, features, and methods of implementing the present invention will become clear from the detailed description of the embodiments. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms that differ from each other. These embodiments are provided to complete the description of the invention and to fully inform those skilled in the art of the scope of the invention, which is defined only by the claims.

[0039] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings illustrating embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters illustrated. Throughout the specification, the same reference numerals denote the same constituent elements. Furthermore, in the process of describing the present invention, detailed descriptions of well-known technologies related to the present invention are omitted when it is determined that such detailed descriptions would obscure the spirit of the present invention. When using terms such as "comprising," "having," or "constituting" as mentioned in this specification, other parts may be added unless "only" is used. When a constituent element is expressed in the singular, it includes cases where there are plural elements, unless otherwise explicitly stated.

[0040] When interpreting constituent elements, even if there is no separate explicit record, it should be interpreted as including the range of error.

[0041] When describing a positional relationship, for example, when describing the positional relationship between two parts using terms such as "above," "upper part," "lower part," or "beside," at least one other part may be placed between the two parts unless "exactly" or "directly" is used.

[0042] When describing temporal relationships, such as when using words like "after," "next," "afterwards," or "before" to indicate a sequence of events, discontinuous situations may also be included unless "immediately" or "directly" is used.

[0043] As used in this specification, "section" refers to a unit that performs at least one function or action, such as a software or hardware component. The functions provided in a "section" may be performed separately by multiple components, or they may be combined with other additional components. A "section" in this specification may be implemented by a single circuit or multiple circuits, or by a single device or multiple devices.

[0044] The features of the various embodiments in this specification can be combined or integrated with each other in part or in whole, and various linkages and drives can be achieved technically. The embodiments can be implemented independently of each other, or they can be implemented together through association.

[0045] In this specification, both the data transmission device and the data driving device are implemented by a microcontroller unit, and the data driving device is implemented by a driver integrated circuit.

[0046] In this embodiment, the LED driving circuit includes a data transmission device for transmitting clock signals, data signals, and identification numbers for adjusting the LED driving current; a bridging integrated circuit including a plurality of channels (LANE) and receiving the clock signals and the data signals; and a plurality of data driving devices that receive the clock signals and the data signals from the channels and transmit them sequentially. A first data driving device among the plurality of data driving devices receives the identification number and stores it as its own identification number, modulates the identification number, and transmits it to the adjacent data driving device.

[0047] In this embodiment, the driving method of the LED driving circuit includes a data transmission device, a bridging integrated circuit, and a plurality of data driving devices. The driving method of the LED driving circuit includes: a step of sequentially registering an ID by the first data driving device to the Nth data driving device; a step of sequentially writing instructions by the first data driving device to the Nth data driving device; a step of sequentially writing to a register by the first data driving device to the Nth data driving device; and a step of sequentially reading from the register by the first data driving device to the Nth data driving device; the first data driving device among the plurality of data driving devices receives an identifier from the data transmission device and stores it as its own identifier, modulates the identifier, and transmits it to the adjacent data driving device.

[0048] The LED driving circuit and driving method of this embodiment will be described below with reference to the accompanying drawings.

[0049] Figure 1 This is a block diagram of an LED driving circuit according to an embodiment of the present invention.

[0050] Reference Figure 1 The LED driving circuit may include a micro controller unit (MCU) 100, a bridge integrated circuit 200, and a first driving integrated circuit to the Nth (N is a natural number greater than 3) driving integrated circuits 311, 312, ..., 369.

[0051] The microcontroller unit 100 is equipped with standard SPI (Serial Peripheral Interface) 1 and standard SPI2. Standard SPI1 is equipped with terminals CSB (Chip Select Bar) 1, SCLK (Serial Clock) 1, SDI (Serial Data Input) 1 and SDO (Serial Data Output) 1, and standard SPI2 is equipped with terminals CSB2, SCLK2, SDI2 and SDO2.

[0052] The microcontroller unit 100 generates a serial clock signal for adjusting the LED drive current via SCLK1 and SCLK2, and generates a serial data input signal via SDI1 and SDI2. Furthermore, the microcontroller unit 100 receives a serial data output signal from the SPI control unit 210.

[0053] The bridging integrated circuit 200 includes an SPI (Serial Peripheral Interface) control unit 210 and a plurality of channels (LANEs) 221, 222, 223, 224, 225, and 226. The plurality of channels includes a first channel 221, a second channel 222, a third channel 223, a fourth channel 224, a fifth channel 225, and a sixth channel 226. The first channel 221 is connected to CSB1, SCLK1, SDI1, and SDO1 of the SPI control unit 210; the second channel 222 is connected to CSB2, SCLK2, SDI2, and SDO2 of the SPI control unit 210; the third channel 223 is connected to CSB3, SCLK3, SDI3, and SDO3 of the SPI control unit 210; and the fourth channel 224 is connected to CSB4, SCLK4, SDI4, and SDO4 of the SPI control unit 210. The fifth channel 225 is connected to CSB5, SCLK5, SDI5, and SDO5 of the SPI control unit 210, and the sixth channel 226 is connected to CSB6, SCLK6, SDI6, and SDO6 of the SPI control unit 210. The SPI control unit 210 sends its respective CSB signal, serial clock signal, and serial data input signal to the first channel 221, the second channel 222, the third channel 223, the fourth channel 224, the fifth channel 225, and the sixth channel 226, and receives serial data output signals from the first channel 221, the second channel 222, the third channel 223, the fourth channel 224, the fifth channel 225, and the sixth channel 226.

[0054] The bridging integrated circuit 200 receives serial clock signals SCLK1 and SCLK2 and serial data input signals SDI1 and SDI2 from the microcontroller unit 100.

[0055] The first driver integrated circuit to the Nth driver integrated circuit 311, 312, ..., 369 receive serial clock signals and serial data input signals from channels 221, 222, 223, 224, 225, 226 and transmit them sequentially. That is, the serial clock signals and serial data input signals are transmitted in the order of the first driver integrated circuit 311, 321, 331, 341, 351, 361, the second driver integrated circuit 312, 322, 332, 342, 352, 362, ..., and the Nth driver integrated circuit 319, 329, 339, 349, 359, 369. Furthermore, when the Nth driver integrated circuit 319, 329, ..., 369 receives the serial clock signal and serial data input signal, it sends a serial clock signal output and a serial data output signal to the first channel 221, the second channel 222, the third channel 223, the fourth channel 224, the fifth channel 225, and the sixth channel 226.

[0056] The first driver integrated circuit to the Nth driver integrated circuit 311, 312, ..., 369 sequentially execute the actions of registering ID, writing instructions, writing to registers, and reading from registers. That is, the actions of registering ID, writing instructions, writing to registers, and reading from registers are transmitted in the order of the first driver integrated circuit 311, 321, 331, 341, 351, 361, the second driver integrated circuit 312, 322, 332, 342, 352, 362, ..., and the Nth driver integrated circuit 319, 329, 339, 349, 359, 369.

[0057] Figure 2 This is a schematic diagram illustrating the state in which an ID is assigned during registration in the first to third driver integrated circuits of an embodiment of the present invention. Figure 3 This is a timing diagram illustrating the process of registering IDs for the first driver integrated circuit to the third driver integrated circuit according to an embodiment of the present invention.

[0058] Reference Figure 2 When there are three driver integrated circuits D-IC#2, DC#1, and D-IC#0, the ID of the first driver integrated circuit that receives the serial clock signal SCK and the serial data input signal SDI is 2, the ID of the second driver integrated circuit is 1, and the ID of the third driver integrated circuit is 0.

[0059] Reference Figure 3 This illustrates the process of registering IDs for the first driver integrated circuit to the Nth driver integrated circuit. In this embodiment, for convenience, only the first driver integrated circuit D-IC#2, the second driver integrated circuit DC#1, and the third driver integrated circuit D-IC#0 are illustrated.

[0060] The microcontroller unit loads the number of integrated circuits connected to the channel (LANE) of the bridging integrated circuit minus 1 into the ID, and sends the preamble signal (SIF_START=8'hFA), the ID, and the ID allocation command (CMD=000) to the first driver integrated circuit D-IC#2. The reason for setting the ID as the number of integrated circuits minus 1 and sending it to the first driver integrated circuit D-IC#2 is that the ID needs to be decremented by 1 sequentially from the first driver integrated circuit D-IC#2 to the Nth driver integrated circuit until the ID of the Nth driver integrated circuit becomes 0. When the ID becomes 0, the Nth driver integrated circuit sends the ID allocation completion signal to the microcontroller unit through the bridging integrated circuit.

[0061] If a preamble signal (SIF_START=8′hFA) and an ID allocation command (CMD=000) are input, the first driver integrated circuit D-IC#2 will register the ID[4:0] (=2) received from the microcontroller unit as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal (SIF_START=8′hFA), the ID, and the ID allocation command (CMD=000) to the second driver integrated circuit DC#1. However, if a preamble signal (SIF_START=8′hFA) and an ID allocation command (CMD=000) are input, the first driver integrated circuit D-IC#2 will first transmit a wait command (CMD=001) to the second driver integrated circuit DC#1. Because of the transmission of the wait command (CMD=001), the second driver integrated circuit DC#1 waits until it receives the ID allocation command (CMD=000) from the first driver integrated circuit D-IC#2.

[0062] If a preamble signal (SIF_START=8′hFA) and an ID allocation command (CMD=000) are input, the second driver integrated circuit DC#1 will register the ID[4:0] (=2) received from the first driver integrated circuit D-IC#2 as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal (SIF_START=8′hFA), the ID, and the ID allocation command to the third driver integrated circuit D-IC#0. However, if a preamble signal (SIF_START=8′hFA) and an ID allocation command are input, the second driver integrated circuit DC#1 will first transmit a wait command (CMD=001) to the third driver integrated circuit D-IC#0. Because of the transmission of the wait command (CMD=001), the third driver integrated circuit D-IC#0 will wait until it receives the ID allocation command (CMD=000) from the second driver integrated circuit DC#1.

[0063] If a preamble signal (SIF_START=8′hFA) and an ID allocation command (CMD=000) are input, the third driver integrated circuit D-IC#0 can register the ID[4:0] (=2) received from the second driver integrated circuit DC#1 as its own ID. If the ID[4:0] (=2) registered by the third driver integrated circuit D-IC#0 is 0, an ID allocation completion signal (ID[4:0] = "11111") is sent to the microcontroller unit through the bridge integrated circuit.

[0064] As described above, if a preamble signal and an ID allocation command (CMD=000) are input, the Nth driver integrated circuit can register the ID received from the (N-1)th driver integrated circuit (not shown) as its own ID. If the ID registered by the Nth driver integrated circuit is 0, an ID allocation completion signal (ID[4:0]="11111") is sent to the microcontroller unit through the bridge integrated circuit.

[0065] Figure 4 This is a schematic diagram illustrating the state in which an instruction is assigned an ID when writing an instruction to a first driver integrated circuit and a second driver integrated circuit according to an embodiment of the present invention. Figure 5 This is a timing diagram illustrating the process of writing instructions to the first driver integrated circuit and the second driver integrated circuit according to an embodiment of the present invention.

[0066] Reference Figure 4 In the case of having two driver integrated circuits D-IC#1 and D-IC#0, the ID of the first driver integrated circuit D-IC#1, which is input with the serial clock signal SCK and the serial data input signal SDI, is 1, and the ID of the second driver integrated circuit D-IC#0 is 0.

[0067] Reference Figure 5 This describes the process of writing instructions from the first driver integrated circuit to the Nth driver integrated circuit. In this embodiment, for convenience, only the first driver integrated circuit D-IC#1 and the second driver integrated circuit D-IC#0 are illustrated.

[0068] The microcontroller unit sends the preamble signal (SIF_START=8′hF5), the instruction write command (CMD=010), and the address (ADDR[4:0]) to the first driver integrated circuit D-IC#1.

[0069] When the input instruction writes the command (CMD=010), the first driver integrated circuit D-IC#1 decodes the address (ADDR[4:0]) and latches the instruction. It decrements its own ID by 1 in each clock cycle until the ID becomes 0, and then writes the latched instruction.

[0070] When the input instruction writes the command (CMD=010), the second driver integrated circuit D-IC#0 decodes the address (ADDR[4:0]) and latches the instruction. It also decrements its own ID by 1 at each clock cycle until the ID becomes 0, at which point the latched instruction is written.

[0071] In the manner described above, when an input instruction is written to the command (CMD=010), the Nth driver integrated circuit (not shown) decodes the address (ADDR[4:0]) and latches the instruction, and decrements its own ID by 1 in each clock cycle until the ID becomes 0, at which point the latched instruction is written.

[0072] The first to Nth driver integrated circuits can synchronize the start time of FPWM (Frequency Pulse Width Modulation) by resetting with a vertical synchronization signal, or they can synchronize the start time of dimming by an input synchronization signal generated by FPWM (Frequency Pulse Width Modulation).

[0073] Figure 6 This is a timing diagram illustrating the process of writing registers from the first driver integrated circuit to the Nth driver integrated circuit according to an embodiment of the present invention.

[0074] Reference Figure 4 In the case of having two driver integrated circuits D-IC#1 and D-IC#0, the ID of the first driver integrated circuit D-IC#1, which is input with the serial clock signal SCK and the serial data input signal SDI, is 1, and the ID of the second driver integrated circuit D-IC#0 is 0.

[0075] Reference Figure 6 This illustrates the process of writing registers from the first driver integrated circuit to the Nth driver integrated circuit. In this embodiment, for convenience, only the first driver DC#1 and the second driver D-IC#0 are illustrated.

[0076] The microcontroller unit sends the preamble signal (SIF_START=8′hF5), register write command (CMD=011), address (ADDR[4:0]), and N data [23:0] (number of driver ICs) to the first driver IC DC#1.

[0077] When the microcontroller unit's register is written with a command (CMD=011), the first driver integrated circuit DC#1 receives the address (ADDR[4:0]), and after multiplying its own ID by the number of bits in the input N data, it identifies the input data as its own data and updates it.

[0078] When the register write command (CMD=011) of the first driver integrated circuit DC#1 is input, the second driver integrated circuit DC#0 receives the address (ADDR[4"0]), and after multiplying the number obtained by subtracting 1 from its own ID by the number of bits in the input N data, it identifies the input data as its own data and then updates it.

[0079] In the manner described above, when the register write command (CMD=011) of the (N-1)th driver integrated circuit is input, the Nth driver integrated circuit (not shown) can receive the address (ADDR[4"0]), and after multiplying the number obtained by subtracting 1 from its own ID by the number of bits in the N input data, the input data is identified as its own data and then updated.

[0080] Figure 7 This is a timing diagram illustrating the process of reading registers from the first driver integrated circuit to the Nth driver integrated circuit according to an embodiment of the present invention.

[0081] Reference Figure 4 In the case of having two driver integrated circuits D-IC#1 and D-IC#0, the ID of the first driver integrated circuit D-IC#1, which is input with the serial clock signal SCK and the serial data input signal SDI, is 1, and the ID of the second driver integrated circuit D-IC#0 is 0.

[0082] Reference Figure 7 This illustrates the process of reading registers from the first driver integrated circuit to the Nth driver integrated circuit. In this embodiment, for convenience, only the first driver D-IC#2 and the second driver DC#1 are illustrated.

[0083] The microcontroller unit sends the preamble signal (SIF_START=8′hF5), register read command (CMD=111), and address (ADDR[4:0]) to the first driver integrated circuit D-IC#1.

[0084] When the register read command (CMD=111) is input to the microcontroller unit, the first driver integrated circuit D-IC#1 receives the address (ADDR[4:0]) and prepares the data for the corresponding address (ADDR[4:0]). It decrements its own ID by 1 at each clock cycle until the ID becomes 0, and then outputs the prepared data.

[0085] When the register read command (CMD=111) is input to the first driver integrated circuit D-IC#1, the second driver integrated circuit D-IC#0 receives the address (ADDR[4:0]) and prepares the data for the corresponding address (ADDR[4:0]). It decrements its own ID by 1 at each clock cycle until the ID becomes 0, and then outputs the prepared data.

[0086] As described above, when the register read command (CMD=111) of the (N-1)th driver integrated circuit is input, the Nth driver integrated circuit prepares the data for the corresponding address (ADDR[4:0]) and decrements its own ID by 1 at each clock cycle until the ID becomes 0, at which point it outputs the prepared data. Since the ID of the last driver integrated circuit is 0, the prepared data is output immediately after the data at the address (ADDR[4:0]) is prepared.

[0087] Figure 8 This is a block diagram illustrating the logic of a driver integrated circuit according to an embodiment of the present invention.

[0088] Reference Figure 8 The SPI (Serial Peripheral Interface) 10 receives the SCK (serial clock signal) and SDI (serial data input) and sends them to the command register 20. The command register 20 sends PWM_Div[7.0] to the clock divider 30, which divides the clock frequency and adjusts the SCK-divided FPWM frequency according to the value of PWM_DIV[7.0]. By adjusting the SCK-divided FPWM frequency, the number of necessary channels (LAMEs) can be reduced compared to the existing control method of directly controlling each driver IC in the microcontroller unit.

[0089] SPI10 sends a vertical synchronization signal command (VSYNC Command) to the input synchronization signal generator (I_VSYNC Generator) 40. At this time, FPWM is input to the input synchronization signal generator 40. By sending the vertical synchronization signal command (VSYNC Command) to the input synchronization signal generator (I_VSYNC Generator) 40, SPI10 can reduce the number of necessary lanes compared to the existing control method of directly controlling each driver IC in the microcontroller unit.

[0090] The input synchronization signal generator 40 sends an input synchronization signal to the dimming data control unit 50, and the FPWM is input into the dimming data control unit 500. Dimming data is transmitted and received between SPI10 and the dimming data control unit 50.

[0091] The dimming data control unit 50 sends dimming data to the PWM (Pulse Width Modulation) timing control unit 60, and the PWM timing control unit 60 controls the PWM timing of the connected channels 1 to N.

[0092] Figure 9 This is a timing diagram illustrating the synchronization of a driver integrated circuit according to an embodiment of the present invention.

[0093] Reference Figure 9 During one cycle of SCK clock signal generation, the vertical sync signal is enabled (ON) while the FPWM is disabled (OFF). At this time, the vertical sync signal is reset.

[0094] After the vertical sync signal is reset, the input sync signal i_VSYNC is enabled within one cycle of FPWM, at which point dimming begins.

[0095] Through the process described above, the first to Nth driver integrated circuits can synchronize the start times of FPWM (Frequency Pulse Width Modulation) when the vertical synchronization signal is reset. Furthermore, the first to Nth driver integrated circuits can synchronize the dimming start times using the input synchronization signal generated by FPWM.

[0096] Figure 10 This is a timing diagram used to illustrate the vertical synchronization signal command of an embodiment of the present invention.

[0097] Reference Figure 10 SCK (serial clock signal) and SDI (serial data input signal) are arranged as N in the timing diagram.

[0098] D-IC#1 generates SCK#N and SDI#N, D-IC#2 generates SCK#N-1 and SDI#N-1, and D-IC#N generates SCK#1 and SDI#1 in the manner described above. SCK#1 to SCK#N form a clock with a specified period, and when the vertical synchronization signal command is enabled, the vertical synchronization signal is latched.

[0099] The input steps for the vertical synchronization signal command protocol are as follows.

[0100] 1) Send START[7:0], CMD[2:0], and ADDR[4:0] to D-IC (driver integrated circuit) #1; 2) While bypassing all D-ICs with SCK / SDI, a signal is sent to D-IC#N; 3) Decode CMD[2:0] and ADDR[4:0]; 4) In the case of the command protocol, the command is latched to all D-ICs after a clock cycle corresponding to its own ID#; 5) While generating the vertical synchronization signal command to synchronize FPWM between D-ICs, I_VSYNC (input synchronization signal) is generated.

[0101] Figure 11 This is a timing diagram illustrating how an input synchronization signal is generated by frequency division using FPWM and SCK according to an embodiment of the present invention.

[0102] Reference Figure 11 SCK (serial clock signal) #1 has a specified period, and FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 have specified periods, but with different pulse widths.

[0103] If the VSYNC command is enabled, the VSYNC signal is latched. If the VSYNC signal is latched and then reset, FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 are disabled. If the VSYNC signal is de-reset, SCK, FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 are all enabled.

[0104] After the vertical sync signal is reset, with the widest pulse width FPWM_DIV 3 disabled, the input sync signal i_VSYNC is enabled with the pulse width size of FPWM_DIV 3.

[0105] The steps for generating the FPWM clock and input synchronization signal i_VSYNC are as follows.

[0106] 1) Write PWM_DIV[7:0] registers to all daisy-chained D-ICs; 2) Generate the FPWM clock by dividing PWM_DIV[7:0] by SCK; 3) Write dimming data and transmit VSYNC commands; 4) Synchronize the FPWM start time between D-ICs using the VSYNC command; 5) Generate i_VSYNC and start LED dimming.

[0107] Figure 12 This is a timing diagram illustrating an embodiment of the present invention of performing LED dimming by synchronizing FPWM between driver integrated circuits.

[0108] Reference Figure 12The vertical synchronization signal VSYNC command consists of pulses, with the intervals between pulses having a frame rate such as 60Hz, 120Hz, 144Hz, etc.

[0109] After generating each pulse via the vertical synchronization signal command, the input synchronization signal i_VSYNC is generated.

[0110] The driver integrated circuits D-IC#1, D-IC#2, D-IC#3, D-IC#4, ..., D-IC#N achieve LED dimming within the dimming time through FPWM_DIV(n).

[0111] As mentioned above, in a two-wire interface, dimming can be smoothly controlled by solving the synchronization problem between driver integrated circuits.

[0112] To aid understanding, embodiments of the invention described above are illustrated with reference to the accompanying drawings. However, these are merely exemplary, and those skilled in the art can implement various modifications and other embodiments within the same scope. Therefore, the true scope of protection of this invention should be determined by the appended claims.

Claims

1. An LED driver circuit, wherein, include: Data transmission device for transmitting clock signals, data signals, and identification numbers used to regulate LED drive current; A bridging integrated circuit includes a plurality of channels and receives the clock signal and the data signal; as well as A plurality of data driving devices receive the clock signal and the data signal from the channel and transmit them sequentially; The first data driving device among the plurality of data driving devices receives the identifier and stores it as its own identifier, and modulates the identifier and transmits it to the adjacent data driving device.

2. The LED driving circuit according to claim 1, wherein, When a plurality of the data driving devices register IDs The data transmission device loads the number obtained by subtracting 1 from the number of integrated circuits connected to the channels of the bridging integrated circuit into the ID, and sends the preamble signal, the ID, and the ID allocation command to the first data driving device. If the first data driving device is input with the preamble signal and the ID allocation command, it will register the ID received from the data transmission device as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal, the ID, and the ID allocation command to the second data driving device. If the second data driver is input with the preamble signal and the ID allocation command, it will register the ID received from the first data driver as its own ID, load the number obtained by subtracting 1 from the registered ID into the ID, and send the preamble signal, the ID, and the ID allocation command to the third data driver. If the Nth data driver is input with the preamble signal and the ID allocation command, it will register the ID received from the (N-1)th data driver as its own ID, where N is a natural number greater than or equal to 3.

3. The LED driving circuit according to claim 2, wherein, It also includes the step of sending an ID allocation completion signal to the data transmission device if the ID registered by the Nth data driver is 0.

4. The LED driving circuit according to claim 2, wherein, It also includes the step of transmitting a wait command to the second data driving device if the first data driving device is input with the preamble signal and the ID allocation command.

5. The LED driving circuit according to claim 2, wherein, It also includes the step of transmitting a wait command to the third data driver if the second data driver is input with the preamble signal and the ID allocation command.

6. The LED driving circuit according to claim 2, wherein, When the first data driving device to the Nth data driving device writes instructions, the following steps are included: The data transmission device sends the preamble signal, instruction writing command, and address to the first data driving device. When the first data driving device is input with the instruction to write the command, it decodes the address and latches the instruction, and decrements its own ID by 1 every clock cycle until the ID becomes 0, then writes the latched instruction. When the second data driving device is input with the instruction to write the command, it decodes the address and latches the instruction, and decrements its own ID by 1 every clock cycle until the ID becomes 0, then writes the latched instruction. When the Nth data driving device is input with the instruction to write the command, it decodes the address and latches the instruction, and decrements its own ID by 1 every clock cycle until the ID becomes 0, then writes the latched instruction.

7. The LED driving circuit according to claim 6, wherein, The first data driving device to the Nth data driving device synchronize the start time of frequency pulse width modulation by resetting the vertical synchronization signal.

8. The LED driving circuit according to claim 2, wherein, The first data driving device to the Nth data driving device synchronize the dimming start time through the input synchronization signal generated by frequency pulse width modulation.

9. The LED driving circuit according to claim 2, wherein, When the first data driver device to the Nth data driver device writes to the register... The data transmission device sends the preamble signal, register write command, address, and N data to the first data driving device. When the first data driving device is written to the register of the data transmission device by the input command, it receives the address, and after multiplying its own ID by the number of bits in the input N data, it identifies the input data as its own data and updates it. When the second data driver is written to the register of the first data driver, it receives the address, and after multiplying the number obtained by subtracting 1 from its own ID by the number of bits in the N input data, it identifies the input data as its own data and updates it. When the Nth data driver is written to the register of the (N-1)th data driver, it receives the address, and after multiplying the number obtained by subtracting 1 from its own ID by the number of bits in the input N data, it identifies the input data as its own data and updates it.

10. The LED driving circuit according to claim 2, wherein, When the first data driver reads a register from the Nth data driver, the following steps are included: The data transmission device sends the preamble signal, register read command and address to the first data driving device. When the first data driving device is input with a register read command from the data transmission device, it receives the address and prepares the data corresponding to the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data. When the second data driver is input with a register read command, it receives the address and prepares the data corresponding to the address, and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data. When the Nth data driver is given a register read command by the (N-1)th data driver, it prepares the data at the corresponding address and decrements its own ID by 1 at each clock cycle until the ID becomes 0, then outputs the prepared data.

11. A driving method for an LED driving circuit, the LED driving circuit comprising a data transmission device, a bridging integrated circuit, and a plurality of data driving devices, wherein, The driving method includes: The step of sequentially registering IDs from the first data driver to the Nth data driver, where N is a natural number greater than or equal to 3; The step of sequentially writing instructions from the first data driving device to the Nth data driving device; The steps of sequentially writing data into registers from the first data driver to the Nth data driver; and The step of sequentially reading registers from the first data driving device to the Nth data driving device; The first data driving device among the plurality of data driving devices receives an identifier from the data transmission device and stores it as its own identifier, and modulates the identifier and transmits it to the adjacent data driving device.

12. The driving method for the LED driving circuit according to claim 11, wherein, The steps for registering the ID from the first data driver device to the Nth data driver device include: The step of the data transmission device loading the number obtained by subtracting 1 from the number of integrated circuits connected to the channel of the bridging integrated circuit into the ID, and sending the preamble signal, the ID and the ID allocation command to the first data driving device; If the first data driving device is input with the preamble signal and the ID allocation command, it will register the ID received from the data transmission device as its own ID. The steps include: the first data driving device loading the number obtained by subtracting 1 from the registered ID into the ID, and sending the preamble signal, the ID, and the ID allocation command to the second data driving device; If the second data driving device is input with the preamble signal and the ID allocation command, it will register the ID received from the first data driving device as its own ID. The steps include: the second data driver loading the number obtained by subtracting 1 from the registered ID into the ID, and sending the preamble signal, the ID, and the ID allocation command to the third data driver; and... If the Nth data driver is input with the preamble signal and the ID allocation command, it will register the ID received from the (N-1)th data driver as its own ID.

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