System and method for continuous-time dc-blocked transimpedance amplifier circuit

Abstract

An example of an apparatus includes a transimpedance amplifier (TIA) and an integrator circuit including: an operational amplifier; a capacitor coupled between an inverting input of the operational amplifier and an output of the operational amplifier; a first FET coupled between the inverting input of the op amp and an output of the TIA; a resistive element connected to a lower supply rail; and a second FET coupled between an inverting input of the TIA and the resistive element and having a second gate connected to the output of the operational amplifier.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 593,695, filed March 1, 2024, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure relates in general to integrated circuits, transimpedance amplifiers, integrators, and more particularly to circuits for measuring the low-frequency AC component of a signal with a large DC bias. Background Technology

[0004] Sensor signals, such as those from photoplethysmography (PPG) sensors, have an AC component that can be used for pulse rate measurement and a DC component that can be used for other measurements, such as peripheral oxygen saturation (SpO2) measurement. The ratio of the AC to DC components in a PPG signal can range from 0.02% to 2%. The frequency of the AC component can be approximately 1 Hz. Therefore, a filter that removes the AC component from the DC component may require discrete resistors or discrete capacitors, or both. Summary of the Invention

[0005] The following is a simplified overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all envisioned implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] One aspect of this disclosure relates to an apparatus. The apparatus may include a transimpedance amplifier (TIA) (e.g., FIG. 1110), the transimpedance amplifier (TIA) including an inverting input terminal of the TIA (e.g., ...). Figure 1 112) TIA non-inverting input (e.g., Figure 1 114) and TIA output (e.g., Figure 1 116); Integrator circuit (e.g., Figure 1 120), the integrator circuit includes: an operational amplifier (e.g., Figure 1 124), the operational amplifier includes an inverting input terminal of the op amp (operational amplifier) ​​(e.g., Figure 4 418), op amp non-inverting input (e.g., Figure 4 416) and op amp output (e.g., Figure 4 420); capacitors (e.g., Figure 1 123), the capacitor is coupled between the inverting input of the operational amplifier and the output of the operational amplifier; the first field-effect transistor (FET) (e.g., Figure 2 202), the first field-effect transistor (FET) is coupled between the inverting input of the operational amplifier and the output of the TIA; the first resistive element (e.g., Figure 1 128), the first side of the first resistive element is connected to the lower power supply rail (e.g., Figure 1 133); and the second FET (e.g., Figure 1 126), the second FET is coupled between the second side of the first resistive element and the TIA inverting input of the TIA, and the second FET has a second gate connected to the op amp output of the operational amplifier.

[0007] Another aspect of this disclosure relates to a method. The method may include: receiving a signal at the inverting input of a transimpedance amplifier (TIA), the signal including an AC component and a DC component; and passing the output signal of the TIA to an integrator circuit configured to eliminate the DC component of the signal, the integrator circuit including: an operational amplifier including an op-amp inverting input, an op-amp non-inverting input, and an op-amp output; a capacitor coupled between the op-amp inverting input and the op-amp output of the operational amplifier; a first field-effect transistor (FET) coupled between the op-amp inverting input and the TIA output of the TIA; a first resistive element, a first side of which is connected to a lower power supply rail; and a second FET coupled between a second side of the first resistive element and the TIA inverting input of the TIA, the second FET having a second gate connected to the op-amp output of the operational amplifier.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus may include: an input component for receiving an input current comprising a first component and a second component; an integrator component for subtracting the second component from the input current; a transimpedance component for converting the first component into a voltage; and a resistor component for switching between a high-resistance state and a low-resistance state, wherein: the integrator component includes the resistor component; the output terminal of the transimpedance component is connected to the resistor component; the input component and the output terminal of the integrator component are connected to the input terminal of the transimpedance component; and the integrator component and the transimpedance component are implemented by an integrated circuit.

[0009] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] Figure 1 A circuit diagram illustrating an example of an integrated circuit configured to measure the AC and DC components of a signal according to one aspect of this disclosure is shown.

[0011] Figure 2 A circuit diagram illustrating an example of a switch floating body device according to another aspect of this disclosure is shown.

[0012] Figure 3 A circuit diagram illustrating an example of a transimpedance amplifier according to another aspect of this disclosure is shown.

[0013] Figure 4 A circuit diagram illustrating an example of a static phase sustaining circuit according to another aspect of this disclosure is shown.

[0014] Figure 5 A circuit diagram illustrating an example of a C2 switch circuit in a transimpedance amplifier (TIA) according to another aspect of this disclosure is shown.

[0015] Figure 6 A circuit diagram illustrating an example of a DC output circuit according to another aspect of this disclosure is shown.

[0016] Figure 7 An example of an operational phase table according to another aspect of this disclosure is illustrated.

[0017] Figure 8 A flowchart illustrating an example method for converting the AC component of an input signal into an AC voltage signal using a continuous-time DC blocking transimpedance circuit, according to another aspect of this disclosure, is shown. Detailed Implementation

[0018] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0019] Sensor signals, such as photoplethysmography (PPG) sensor signals, have an AC component that can be used for pulse rate measurement and a DC component that can be used for other measurements, such as peripheral oxygen saturation (SpO2) measurement. The ratio of the AC to DC components in a PPG signal can range from 0.02% to 2%. Therefore, a fine-resolution analog-to-digital converter (ADC) may be needed to digitize the signal so that the AC component of the digitized signal can be isolated. However, a fine-resolution ADC requires a large area on an integrated circuit chip. One option is to eliminate the DC component of the signal in the analog domain, so that the ADC measures the AC component but not the DC component. An integrator circuit can be used to eliminate the DC component. However, the integrator circuit may include a filtering aspect that should have a cutoff frequency close to the frequency of the AC signal. The filtering aspect may include resistors and capacitors and has a cutoff frequency that is a function of the resistance of the resistor multiplied by the capacitance of the capacitor. When measuring a heartbeat, the frequency of the AC component may be approximately 1 Hz. Implementing the required resistors in an integrated circuit can be difficult, and the required capacitors may require a large area on the integrated circuit chip. Therefore, resistors and capacitors may be located off-chip, which increases the bill of materials and the size of devices used to measure signals such as PPG signals.

[0020] The resistive element in an integrator circuit can be a floating-body field-effect transistor (FET) instead of a resistor. FETs in integrated circuits typically have a connection between the FET's gate and its body, making the FET's body non-floating. Tests have shown that a floating-body FET can have a source-to-drain resistance greater than 100 gigahertz. Therefore, an integrator circuit with a floating-body FET as a resistive element and a 25pF integrating capacitor (Cint) can be used to eliminate the DC component of the signal, allowing measurement of the AC component at approximately 1 Hz. The circuit can operate in phases such as the DC acquisition phase and the AC measurement phase. The integrator circuit can lock onto the DC component during the DC measurement phase, thus eliminating the DC component from the input to the TIA during the AC measurement phase.

[0021] Figure 1A circuit diagram illustrating an example of an integrated circuit 100 configured to measure the AC and DC components of a signal according to one aspect of this disclosure is shown. The signal may be carried by a photodiode current 107 generated by a photodiode (PD), which may be connected to input pads of the integrated circuit 100 (e.g., first input pad 102 and second input pad 103). The PD current 107 is split into a first component and a second component at node 108. The first component enters the TIA inverting input 112 of a TIA 110, which converts the first component into a voltage as a TIA output signal 118. The TIA inverting input 112 of the TIA 110 may be connected to the first input pad 102 and node 108. The TIA non-inverting input 114 of the TIA 110 may be connected to the second input pad 103, and thus to the PD 106. The TIA output 116 is connected to the switch floating body device 122 of an integrator circuit 120. The integrator circuit 120 includes an operational amplifier (op amp) 124. A switching floating body device 122 is coupled between the TIA output 116 and the op amp inverting input. A capacitor (Cint) 123 is coupled between the op amp inverting input and the op amp output of the op amp 124. The switching floating body device 122 may be a floating body FET that can switch between a high-resistance state (e.g., >100 gigahertz) and a low-resistance state (e.g., <1 ohm). For example, the floating body FET may be an n-channel device that can be turned on and off by a resistance state control signal input to the gate of the floating body FET. The switching floating body device 122 may be in a high-resistance state when the floating body FET is on and in a low-resistance state when the floating body FET is off.

[0022] The output of integrator circuit 120 is connected to the gate of second FET (M2) 126. Resistor (R1) 128 is coupled between the drain of M2 126 and the lower supply rail 133. The lower supply rail 133 is indicated by a ground symbol. As discussed above, the first component of the PD current enters the TIA inverting input 112 of the TIA. The second component of the PD current 107 passes through M2, through R1, and then reaches the lower supply rail 133.

[0023] The switching floating body device 122 can be in a low-resistance state during the DC acquisition phase. The integrator circuit has a cutoff frequency that is a function of the capacitance of Cint 123 (e.g., 25 pF) and the resistance of the switching floating body device 122 (e.g., <1 ohm in the low-resistance state). Therefore, the integrator circuit 120 stores charge on Cint 123 such that the current through R1 is equal to the DC component of the PD current. Furthermore, the integrator circuit converts the DC component of the PD current into a voltage at the op amp output of op amp 124 during the DC acquisition phase, and thereby acquires the DC component. Therefore, the op amp output of op amp 124 is connected to the input of DC output circuit 130, which generates a DC voltage signal 132 at DC voltage output terminal 134. The input to DC output circuit 130 can be a high-impedance input terminal 136 (e.g., the gate of a FET) such that DC output circuit 130 does not draw current from Cint 123. PPG applications, such as measuring SpO2, can use a DC voltage signal at the end of the DC acquisition phase to measure the DC component of the PD current.

[0024] The floating switch body device 122 can be in a high-resistance state during the AC measurement phase. The integrator circuit has a cutoff frequency that is a function of the capacitance of Cint 123 (e.g., 25 pF) and the resistance of the floating switch body device 122 (e.g., >100 gigaohms in the high-resistance state). Therefore, the charge on Cint 123 is locked in place because every current path from Cint 123 is a high-impedance path when the floating switch body device 122 is in the high-resistance state. Therefore, the DC component of the PD current 107 is discharged through M2 126 and R1 128. The remaining portion of the PD current (the AC component) flows into the TIA inverting input of TIA 110, which converts the AC component into an AC voltage signal that is available at the TIA output 116 of TIA 110 during the AC measurement phase.

[0025] Figure 2A circuit diagram illustrating an example of a switch-floating body device 200 according to another aspect of this disclosure is shown. The switch-floating body device 200 may include a floating body FET (M1) 202. In the example, M1 202 is an n-channel FET with its drain connected to the TIA output and its source connected to the op amp inverting input of an operational amplifier in an integrator circuit. A resistance state control signal 216 may be input to the gate 206 of M1 202, such that the resistance state control signal 216 places the switch-floating body device 200 in a high-resistance state (e.g., >100 gigahertz) or a low-resistance state (e.g., <1 ohm). The body 204 of M1 202 is allowed to float when the body reset switch 210 is open. The FET can be used as the body reset switch. Experiments have shown that when the body is not floating, the source-to-drain resistance is insufficient for AC acquisition phase. However, when the body is allowed to float, charge can accumulate on the body, which is why most other applications connect the body to the gate. The gate of the floating body FET 202 is not directly connected to the body of the floating body FET. Here, "direct connection" means a connection via a wire, conductive trace, conductive via, or wire. A body reset switch 210 may be coupled between the body bias voltage line 212 and the body connection 208 of the first FET. The body potential can be set relative to the body bias voltage line 212 by closing the body reset switch 210. When the floating body device 200 is in a high-resistance state (e.g., during AC acquisition phase), the body reset switch 210 should be open, because otherwise the resistance between the source and drain may be insufficient. The body reset switch 210 may be pulse-controlled, causing the body reset switch 210 to close and then open to set the body potential relative to the voltage of the body bias voltage line 212.

[0026] Figure 3A circuit diagram illustrating an example of a transimpedance amplifier 300 according to another aspect of this disclosure is shown. The TIA includes a second op amp 302 having a second op amp inverting input, a second op amp non-inverting input, and a second op amp output. A signal 314, such as a PD current, is split into a first component 316 and a second component 318. The second component can be input to an integrator circuit. The first component 316 can be input to the TIA inverting input of the TIA 300. The TIA inverting input 308 is connected to the second op amp inverting input of the second op amp 302, a second resistor 306 (R2), and a second capacitor 304 (C2). The TIA non-inverting input 310 is connected to the second op amp non-inverting input of the second op amp 302. R2 306 is coupled between the second op amp inverting input and the second op amp output of the second op amp 302. The second op-amp output of the second op-amp 302 is the TIA output. The TIA converts the AC component of the signal into an AC voltage signal. The TIA output 312 carries the AC voltage signal during the AC measurement phase and can therefore be connected to a digital version of the DAC that generates the AC voltage signal. Switching circuit 320 of C2 is coupled between C2 304 and the second op-amp output of the second op-amp. The following discussion... Figure 5 An example of the C2 switch circuit is shown.

[0027] Figure 4A circuit diagram illustrating an example of a static phase sustaining circuit 400 according to another aspect of this disclosure is shown. As discussed above, the circuit can operate in an operating phase that includes a DC acquisition phase and an AC measurement phase. The static phase is another operating phase that can be entered to save energy. PPG applications may have light-emitting diodes (LEDs) that illuminate tissue and a PD that generates a PD current proportional to the light reflected from the tissue and entering the PD. To save energy, many PPG applications (e.g., smartwatches) pulse-control the LED. When the LED is off, the PD current may drop to near zero. Integrator circuit 412 may include operational amplifier 422 having an op amp inverting input 418, an op amp non-inverting input 416, and an op amp output 420. The op amp non-inverting input 416 may be connected to a bias voltage (VBIAS). The integrator circuit may be supplied with a sustaining current during the static phase, such that the integrator circuit sustains the charge stored by Cint. The sustaining current may be supplied by a constant current source 408. An integrator power supply switch 410 (M5) is coupled between a constant current source 408 and an integrator circuit 412. The integrator power supply switch 410 can be closed during the static phase, allowing the integrator circuit 412 to receive a sustaining current. An integrator cut-off switch 402 (M3) can be coupled between the inverting input of the TIA and the integrator circuit, thereby preventing the sustaining current from entering the PD or the TIA or acting as a simulacrum of the PD current. During the DC acquisition phase and during the AC measurement phase, the integrator power supply switch 410 (M5) can be opened, and the integrator cut-off switch 402 (M3) can be closed, allowing the second signal component 404 to be received by the integrator circuit 412 during those operating phases, and preventing the sustaining current from being received by the integrator circuit 412.

[0028] Figure 5 A circuit diagram illustrating an example of a C2 switching circuit 500 in a transimpedance amplifier (TIA) according to another aspect of this disclosure is shown. The C2 switching circuit 500 may include an R2 bias switch 502 (S1) and a C2 cut-off switch 504 (S2). The switches may be implemented using FETs. The TIA includes the C2 switching circuit 500, a second op amp (e.g., Figure 3 302), a second capacitor (C2), and a second resistor (R2). R2 is coupled between the second op amp's inverting input and output. One side of C2 is coupled between the second op amp's inverting input and the C2 cut-off switch 504 (S2). The C2 cut-off switch 504 (S2) is coupled between C2 and the second op amp's output.

[0029] Closing C2 disconnects switch 504 (S2), electrically connecting C2 and R2 in parallel. Opening S2 disconnects one side of C2 from R2 and from the output of the second op amp. Closing S1 connects the output of the second op amp and one side of R2 to the bias voltage (VBIAS). During the DC acquisition phase and during the AC measurement phase, S2 can be closed and S1 can be open, allowing C2 and R2 to be electrically connected in parallel and TIA to operate as TIA. During the static phase, S2 can be open and S1 can be closed, effectively staticating the circuit. S1 and S2 can be implemented using FETs.

[0030] Figure 6 A circuit diagram illustrating an example of a DC output circuit 600 according to another aspect of this disclosure is shown. This example of the DC output circuit uses a current mirror similar to those known in the art. Reference Figure 1 The opamp output terminal of the integrator circuit is connected to the gate of M2126 and the input terminal of the DC output circuit. Figure 5 An example is illustrated where the gate of M6 602 (n-channel FET) is a high-impedance input to the DC output circuit 600. Therefore, the op amp output of the integrator circuit is connected to the gate of M6 602, thereby setting the current through R3 604. When R3 = R1, the current through R3 can be equal to the current through R1. The current through R1 can be the DC component of the PD current. Therefore, the current mirror circuit delivers a current equal to the DC component of the PD current through R4. The voltage across R4 is a DC voltage signal 606, which can be used, for example, to measure SpO2 in PPG applications. The DC voltage output terminal 610 is indicated as the line on which the DC output circuit generates the DC voltage signal. The DC output circuit 600 may include a current trimmer 608, which can be used for calibration or adjustment of the current through R4. The DC output circuit 600 is an example of a circuit that can be efficiently implemented within an integrated circuit.

[0031] Figure 7 An example of an operating phase table 700 according to another aspect of this disclosure is illustrated. The operating phase may include a DC acquisition phase, a static phase, and an AC measurement phase. In the example, the phase sequence may repeat the following series: DC acquisition phase - static phase - AC measurement phase - static phase. During the DC acquisition phase, the floating body device (e.g., Figure 2 200) can be in a low-resistance state, integrator-powered switch (e.g., Figure 4 410) can be disconnected, the integrator cuts off the switch (e.g., Figure 4 402) can be closed, R2 bias switch (e.g., Figure 5 502) can be disconnected, C2 cuts off the switch (e.g., Figure 5 504) can be closed, and the body reset switch (e.g., Figure 2 210) can be disconnected. During the static phase, the switching floating body device (e.g., Figure 2 200) can be in a high-resistance state, integrator-powered switch (e.g., Figure 4 410) can be closed, and the integrator cuts off the switch (e.g., Figure 4 402) can be disconnected, R2 bias switch (e.g., Figure 5 502) can be closed, C2 cuts off the switch (e.g., Figure 5 504) can be disconnected, and the body reset switch (e.g., Figure 2 210) can be pulse-controlled. During the static phase, the body reset switch can be pulse-controlled by briefly closing and then opening it. During the AC measurement phase, the switch floats the body device (e.g., Figure 2 200) can be in a high-resistance state, integrator-powered switch (e.g., Figure 4 410) can be disconnected, the integrator cuts off the switch (e.g., Figure 4 402) can be closed, R2 bias switch (e.g., Figure 5 502) can be disconnected, C2 cuts off the switch (e.g., Figure 5 504) can be closed, and the body reset switch (e.g., Figure 2 210) can be disconnected.

[0032] PPG applications can use LEDs to illuminate the tissue. Light from the LED can be reflected from the tissue to a photodiode (e.g., Figure 1 In 106), the photodiode generates a photodiode current (e.g., Figure 1 107). The OD current can be a signal that is processed to obtain an AC voltage signal (for pulse measurement) and a DC voltage signal (for SpO2 measurement). In this application, the LED can be turned on during the DC acquisition phase and the AC measurement phase, but can be turned off during the static phase.

[0033] Figure 8A flowchart illustrating an example method 800 for converting the AC component of an input signal into an AC voltage signal using a continuous-time DC blocking transimpedance circuit according to another aspect of this disclosure is shown. At block 810, a signal comprising both AC and DC components can be received at the inverting input of a transimpedance amplifier (TIA). At block 820, the output signal of the TIA can be passed to an integrator circuit configured to eliminate the DC component of the signal. This integrator circuit includes: an operational amplifier including an op-amp inverting input, an op-amp non-inverting input, and an op-amp output; a capacitor coupled between the op-amp inverting input and the op-amp output of the operational amplifier; a first field-effect transistor (FET) coupled between the op-amp inverting input and the TIA output of the TIA; a first resistive element with a first side connected to a lower power rail; and a second FET coupled between the second side of the first resistive element and the TIA inverting input of the TIA, the second FET having a second gate connected to the op-amp output of the operational amplifier, wherein when the first FET is in a high-resistance state, the resistance between the first source and the first drain of the first FET is greater than 100 gigahertz.

[0034] The examples disclosed herein can be implemented using integrated circuits when the component sizes are chosen to allow the integrated circuits to be implemented in an efficient and cost-effective manner. For example, Cint can be 25pF; R1, R2, and R3 can be 1 megohm, and C2 can be 1.4pF. In such an example, VBIAS can be 1V, the Vcc of the op amp can be 1.8V, and the Vcc of the DC output circuit can be 2.5V.

[0035] The following provides an overview of the various aspects of this disclosure: Aspect 1: An apparatus comprising: a transimpedance amplifier (TIA) including an inverting input, a non-inverting input, and an output; an integrator circuit including: an operational amplifier including an inverting input, a non-inverting input, and an output; a capacitor coupled between the inverting input and the output of the operational amplifier; a first field-effect transistor (FET) coupled between the inverting input and the output of the TIA; a first resistive element having a first side connected to a lower power supply rail; and a second FET coupled between a second side of the first resistive element and the inverting input of the TIA, the second FET having a second gate connected to the output of the operational amplifier.

[0036] Aspect 2: The apparatus according to Aspect 1, wherein the first FET is configured to switch between a high-resistance state and a low-resistance state; when the first FET is in the high-resistance state, the resistance between the first source and the first drain of the first FET is greater than 100 gigahertz; and the integrator circuit is configured to eliminate the DC component of the signal input to the node connected to the inverting input of the TIA.

[0037] Aspect 3: The apparatus according to aspects 1 to 2, wherein the signal has an AC component and a DC component; the TIA is configured to convert the AC component into an AC voltage signal at the TIA output terminal of the TIA when the first FET is in the high resistance state; the integrator circuit is configured to eliminate the DC component of the signal when the first FET is in the high resistance state; and the integrator circuit is configured to acquire the DC component when the first FET is in the low resistance state.

[0038] Aspect 4: The apparatus according to aspects 1 to 3 further includes a DC output circuit comprising: a high-impedance input terminal connected to the op amp output terminal of the operational amplifier; and a DC voltage output terminal generating a DC voltage signal proportional to the DC component of the signal.

[0039] Aspect 5: The apparatus according to aspect 4, wherein the TIA, the integrator circuit and the DC output circuit are implemented by integrated circuits.

[0040] Aspect 6: The apparatus according to aspects 1 to 3 further includes: an integrator cut-off switch coupled between the TIA inverting input terminal of the TIA and the second FET; and an integrator power supply switch coupled between a current source and a second source terminal of the second FET.

[0041] Aspect 7: The apparatus according to Aspect 6, wherein: the apparatus is configured to operate in multiple phases including a DC acquisition phase, a static phase, and an AC measurement phase, during the DC acquisition phase, the first FET is in the low resistance state, the integrator cut-off switch is closed, the integrator power supply switch is open, and the integrator circuit acquires the DC component of the signal; during the static phase, the first FET is in the high resistance state, the integrator cut-off switch is open, and the integrator power supply switch is closed; and during the AC measurement phase, the first FET is in the high resistance state, the integrator cut-off switch is closed, the integrator power supply switch is open, and the TIA converts the AC component of the signal into the AC voltage signal.

[0042] Aspect 8: The apparatus according to aspect 7 further includes: a body reset switch coupled between the body of the first FET and a body bias voltage line, wherein the body reset switch is disconnected during the DC acquisition phase and the AC measurement phase.

[0043] Aspect 9: The apparatus according to aspects 1 to 8, wherein the body reset switch is closed and then opened during the static phase.

[0044] Aspect 10: The apparatus according to aspects 2 to 10 further includes a DC output circuit, the DC output circuit including: a high-impedance input terminal connected to the op amp output terminal of the operational amplifier; and a DC voltage output terminal generating a DC voltage signal proportional to the DC component of the signal.

[0045] Aspect 11: The apparatus according to aspects 1 to 9, wherein the body of the first FET is not directly connected to the first gate of the first FET.

[0046] Aspect 12: A method comprising: receiving a signal at an inverting input of a transimpedance amplifier (TIA), the signal including an AC component and a DC component; and passing an output signal of the TIA to an integrator circuit configured to eliminate the DC component of the signal, the integrator circuit comprising: an operational amplifier including an inverting op-amp input, an inverting op-amp input, and an op-amp output; a capacitor coupled between the inverting op-amp input and the op-amp output of the operational amplifier; a first field-effect transistor (FET) coupled between the inverting op-amp input and the TIA output of the TIA; a first resistive element having a first side connected to a lower power supply rail; and a second FET coupled between a second side of the first resistive element and the inverting op-amp input of the TIA, the second FET having a second gate connected to the op-amp output of the operational amplifier.

[0047] Aspect 13: The method according to aspect 12, the method further comprising: controlling the first FET to place the first FET in a high-resistance state or in a low-resistance state, wherein: when the first FET is in the high-resistance state, the resistance between the first source and the first drain of the first FET is greater than 100 gigahertz; the TIA is configured to convert the AC component into an AC voltage signal at the TIA output terminal of the TIA when the first FET is in the high-resistance state; the integrator circuit is configured to eliminate the DC component of the signal when the first FET is in the high-resistance state; and the integrator circuit is configured to acquire the DC component when the first FET is in the low-resistance state.

[0048] Aspect 14: The method according to aspect 13, the method further comprising: generating a DC voltage signal proportional to the DC component of the signal at a DC voltage output terminal of a DC output circuit, the DC output circuit including a high-impedance input terminal connected to the op amp output terminal of the operational amplifier.

[0049] Aspect 15: According to the method of aspect 14, wherein the TIA, the integrator circuit and the DC output circuit are implemented by integrated circuits.

[0050] Aspect 16: The method according to aspect 13, wherein: an integrator cut-off switch is coupled between the TIA inverting input of the TIA and the second FET; and an integrator power supply switch is coupled between a constant current source and the second FET.

[0051] Aspect 17: The method according to aspects 12 to 16, wherein: when the body reset switch is open, the first FET is a floating body device; and when the body reset switch is closed, the body of the first FET is coupled to the body bias voltage line.

[0052] Aspect 18: An apparatus comprising: an input component for receiving an input current comprising a first component and a second component; an integrator component for subtracting the second component from the input current; a transimpedance component for converting the first component into a voltage; and a resistor component for switching between a high resistance state and a low resistance state, wherein: the integrator component includes the resistor component; an output terminal of the transimpedance component is connected to the resistor component; the input component and the output terminal of the integrator component are connected to the input terminal of the transimpedance component; and the integrator component and the transimpedance component are implemented by an integrated circuit.

[0053] Aspect 19: The apparatus according to aspect 18, wherein: when the body reset switch is open, the resistive element is a floating body device; and when the body reset switch is closed, the body of the resistive element is coupled to the body bias voltage line.

[0054] Aspect 20: The apparatus according to aspects 18 to 19, wherein when the resistive element is in the high-resistance state, the resistance of the resistive element is greater than 100 gigaohms.

[0055] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A transimpedance amplifier (TIA) includes an inverting input terminal, a non-inverting input terminal, and an output terminal. Integrator circuit, the integrator circuit comprising: An operational amplifier, comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; A capacitor coupled between the inverting input of the operational amplifier and the output of the operational amplifier; A first field-effect transistor (FET) is coupled between the inverting input of the operational amplifier and the output of the TIA. A first resistive element, wherein a first side of the first resistive element is connected to a lower power supply rail; and The second FET is coupled between the second side of the first resistive element and the inverting input of the TIA, and the second FET has a second gate connected to the op amp output of the operational amplifier.

2. The apparatus according to claim 1, wherein: The first FET is configured to switch between a high-resistance state and a low-resistance state; When the first FET is in the high resistance state, the resistance between the first source and the first drain of the first FET is greater than 100 gigaohms. and The integrator circuit is configured to eliminate the DC component of the signal input to the node connected to the inverting input of the TIA.

3. The apparatus according to claim 2, wherein: The signal has an AC component and a DC component; The TIA is configured to convert the AC component into an AC voltage signal at the TIA output terminal when the first FET is in the high resistance state. The integrator circuit is configured to eliminate the DC component of the signal when the first FET is in the high-resistance state; and The integrator circuit is configured to acquire the DC component when the first FET is in the low-resistance state.

4. The apparatus according to claim 3, further comprising a DC output circuit, the DC output circuit comprising: A high-impedance input terminal is connected to the op amp output terminal of the operational amplifier; and a DC voltage output terminal, wherein the DC voltage output terminal generates a DC voltage signal that is proportional to the DC component of the signal.

5. The apparatus of claim 4, wherein the TIA, the integrator circuit, and the DC output circuit are implemented by integrated circuits.

6. The apparatus according to claim 3, further comprising: An integrator cut-off switch is coupled between the TIA's inverting input and the second FET. as well as An integrator power supply switch is coupled between a current source and the second source of the second FET.

7. The apparatus according to claim 6, wherein: The device is configured to operate in multiple phases, including a DC acquisition phase, a static phase, and an AC measurement phase. During the DC acquisition phase, the first FET is in the low resistance state, the integrator cut-off switch is closed, the integrator power supply switch is open, and the integrator circuit acquires the DC component of the signal. During the static phase, the first FET is in the high-resistance state, the integrator cut-off switch is open, and the integrator power supply switch is closed; and During the AC measurement phase, the first FET is in the high resistance state, the integrator cut-off switch is closed, the integrator power supply switch is open, and the TIA converts the AC component of the signal into the AC voltage signal.

8. The apparatus according to claim 7, further comprising: A body reset switch is coupled between the body of the first FET and the body bias voltage line, wherein the body reset switch is disconnected during the DC acquisition phase and the AC measurement phase.

9. The apparatus of claim 8, wherein the body reset switch is closed and then opened during the static phase.

10. The apparatus of claim 2, further comprising a DC output circuit, the DC output circuit comprising: A high-impedance input terminal is connected to the op amp output terminal of the operational amplifier; and a DC voltage output terminal, wherein the DC voltage output terminal generates a DC voltage signal that is proportional to the DC component of the signal.

11. The apparatus of claim 1, wherein the body of the first FET is not directly connected to the first gate of the first FET.

12. A method, the method comprising: A signal is received at the inverting input of a transimpedance amplifier (TIA), the signal comprising an AC component and a DC component; as well as The output signal of the TIA is passed to an integrator circuit, which is configured to eliminate the DC component of the signal. The integrator circuit includes: An operational amplifier, comprising an inverting input terminal, a non-inverting input terminal, and an output terminal; A capacitor coupled between the inverting input of the operational amplifier and the output of the operational amplifier; A first field-effect transistor (FET) is coupled between the inverting input of the operational amplifier and the output of the TIA. A first resistive element, wherein a first side of the first resistive element is connected to a lower power supply rail; and The second FET is coupled between the second side of the first resistive element and the inverting input of the TIA, and the second FET has a second gate connected to the op amp output of the operational amplifier.

13. The method according to claim 12, further comprising: Control the first FET to place it in a high-resistance state or a low-resistance state. in: When the first FET is in the high resistance state, the resistance between the first source and the first drain of the first FET is greater than 100 gigaohms. The TIA is configured to convert the AC component into an AC voltage signal at the TIA output terminal when the first FET is in the high resistance state. The integrator circuit is configured to eliminate the DC component of the signal when the first FET is in the high-resistance state; and The integrator circuit is configured to acquire the DC component when the first FET is in the low-resistance state.

14. The method according to claim 13, further comprising: A DC voltage signal proportional to the DC component of the signal is generated at the DC voltage output terminal of the DC output circuit, the DC output circuit including a high-impedance input terminal connected to the op amp output terminal of the operational amplifier.

15. The method of claim 14, wherein the TIA, the integrator circuit, and the DC output circuit are implemented by integrated circuits.

16. The method of claim 13, wherein: The integrator cut-off switch is coupled between the TIA's inverting input and the second FET; and The integrator power supply switch is coupled between the constant current source and the second FET.

17. The method according to claim 12, wherein: When the body reset switch is off, the first FET is a floating body device; and When the body reset switch is closed, the body of the first FET is coupled to the body bias voltage line.

18. An apparatus comprising: An input component for receiving an input current including a first component and a second component; An integrator component for subtracting the second component from the input current; A transimpedance component used to convert the first component into a voltage; A resistor component used to switch between high resistance and low resistance states. in: The integrator component includes the resistor component; The output terminal of the mutual impedance component is connected to the resistor component; The output terminals of the input component and the integrator component are connected to the input terminal of the mutual impedance component; and The integrator component and the mutual impedance component are implemented by integrated circuits.

19. The apparatus according to claim 18, wherein: When the body reset switch is off, the resistive component is a floating body device; and When the body reset switch is closed, the body of the resistor component is coupled to the body bias voltage line.

20. The apparatus of claim 18, wherein when the resistive component is in the high-resistance state, the resistance of the resistive component is greater than 100 gigaohms.

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