Circuit arrangement of the transmission gate type

Abstract

This invention relates to a transmission gate type circuit device having two parallel-connected transistors, one of which is designed as an NMOS transistor (MN) and the other as a PMOS transistor (MP). The gate contacts of the two parallel-connected transistors can be applied with control voltage potentials (Vc) that are opposite in phase to each other. The drain and source terminals of the two parallel-connected transistors are interconnected and respectively form the connection contacts (Vin, Vout) of the circuit device. The invention is characterized by having 2n NMOS transistors (MNa, MNb, MNc, MNd), where n ≥ 2, connected in parallel with the source-drain path of the NMOS transistor (MN). These NMOS transistors each have a series-connected source-drain path. The NMOS transistor (MN) has a substrate terminal connected to a voltage potential obtainable from the contact point, which is located between the interconnected source-drain paths of a pair of transistors centrally arranged along the series-connected sequence of 2n transistors (MNa, MNb, MNc, MNd). The contact point is connected to the source-drain path of another NMOS transistor (MNe), which is connected to the negative power supply voltage (VSS), and the inverting control voltage potential is applied to the gate contact of the other NMOS transistor. The gate contacts of the centrally arranged transistor pair are respectively connected to the connection contacts (in, out) opposite to the corresponding transistors of the transistor pair with respect to the contact point. The 2n series-connected transistors (MNa, MNb, MNc, MNd) have gate contacts connected to the power supply voltage VC and substrate terminals connected to the negative power supply voltage (VSS) of the NMOS transistors (MNc, MNd) adjacent to the centrally arranged NMOS transistor pair on both sides. Finally, the PMOS transistor (MP) is assigned an arrangement of 2n PMOS transistors (MPa, MPb, MPc, MPd) that is reverse-symmetrical to the above transistor arrangement, as well as another PMOS transistor (MPe).

Description

Technical Field

[0001] The present invention relates to a transmission gate type circuit device having two transistors connected in parallel, one of which is designed as an NMOS transistor and the other as a PMOS transistor. The gate contacts of the two parallel transistors can be applied with control voltage potentials that are opposite to each other. The drain and source terminals of the two parallel transistors are respectively connected to each other and respectively form the connection contacts of the circuit device. Background Technology

[0002] In microelectronics, a transmission gate is understood as an integrated electronic circuit device that can be bidirectionally turned on or off by a control signal.

[0003] Typically, a transmission gate consists of two field-effect transistors connected in parallel: an NMOS-FET and a PMOS-FET, with their drain and source contacts interconnected. Their gate contacts are interconnected via inverters, allowing control signals that are inversely related to each other to be applied to the two gate contacts.

[0004] Because the transmission gate allows current to flow bidirectionally and can also block current, the substrate terminal is connected to the corresponding power supply voltage potential to ensure that the substrate diode always operates in the cutoff direction. Therefore, the substrate terminal of an n-channel MOSFET is connected to a negative power supply voltage potential, and the substrate terminal of a p-channel MOSFET is connected to a positive power supply voltage potential.

[0005] Figure 1 The diagram illustrates a known circuit arrangement for constructing a transmission gate (TG), wherein NMOS (MN) and PMOS (MP) transistors, operated in opposite directions, serve as switches between an input voltage Vin and an output voltage Vout. Complementary control voltages Vc and Vout are applied to the gate contacts of the two parallel-connected transistors MN and MP via an inverter (not shown). .

[0006] When the control voltage Vc corresponds to the negative supply voltage Vss of the NMOS transistor MN, the resistance between the two voltage nodes Vin and Vout is very large, meaning the transfer gate has a very large resistance Roff, and therefore TG is in an off-state. When the control voltage Vc corresponds to the positive supply voltage VDD of the NMOS transistor MP, i.e., Vc = VDD, it is desirable for both transistors MN and MP to be on, i.e., to have a low on-resistance Ron. However, especially at low supply voltages (e.g., V... DD / 2 ~ Vth), resulting in a relatively large resistance Ron (tens of kΩ), which is not tolerable in all cases.

[0007] A simple measure is to increase the transistor size. While this can further reduce Ron, it also leads to a decrease in Roff. Besides the associated space issues, especially in low-power circuits, it's important to avoid leakage currents on the order of nA. However, this means Roff must be in the GΩ range.

[0008] One known method for reducing the on-resistance Ron in a transmission gate involves controlling the substrate voltages of the two transistors MN and MP, known as bulk-kontrolle control. Therefore, the substrate voltage of transistor MP needs to be maintained at the corresponding highest voltage of the circuit, and the substrate voltage of transistor MN needs to be maintained at the corresponding lowest voltage of the circuit, so that punch-through occurs at the parasitic diodes in the transistors. However, studies on transmission gates with bulk-kontrolle control have shown that while this significantly reduces the on-resistance Ron, it also negatively impacts the reduction of the turn-off resistance Roff.

[0009] Patent documents US 6 020 778 A and US 5 767 733 A disclose a transmission gate with body voltage control, but they have the aforementioned disadvantages. Summary of the Invention

[0010] This invention is based on the task of extending a transmission gate type circuit device having two parallel-connected transistors, one of which is designed as an NMOS transistor and the other as a PMOS transistor. The gate contacts of the two parallel-connected transistors can be applied with control voltage potentials that are opposite to each other. The drain and source terminals of the two parallel-connected transistors are respectively connected to each other and form the connection contacts of the circuit device. This extension is made such that the on-resistance Ron should be as small as possible, while the off-resistance Roff should be as large as possible.

[0011] The solution to the task upon which this invention is based is given in claim 1. Features that advantageously extend the inventive concept are the subject matter of the dependent claims and derive from the following description (particularly with reference to the drawings).

[0012] The circuit arrangement according to this solution, having the features of the preamble of claim 1, is characterized in that: 2n NMOS transistors, where n ≥ 2, are connected in parallel with the source-drain path of the NMOS transistor, each having a series-connected source-drain path. The NMOS transistor has a substrate terminal connected to a voltage potential obtainable from a contact point located between the interconnected source-drain paths of a pair of transistors centrally arranged along the series-connected sequence of 2n transistors. This contact point is connected to the source-drain path of another NMOS transistor connected to a negative power supply voltage, and an inverting control voltage potential is applied to the gate contact of this other NMOS transistor.

[0013] The gate contacts of the centrally arranged transistor pair are respectively connected to connection contacts opposite to the corresponding transistors of the transistor pair relative to the contact points.

[0014] Furthermore, the 2n series-connected transistors, adjacent to the centrally arranged NMOS transistor, have gate contacts connected to the power supply voltage and substrate terminals connected to the negative power supply voltage on both sides of the NMOS transistor pair. Finally, the PMOS transistors are assigned an arrangement of 2n PMOS transistors that is symmetrical to the above-described transistor arrangement, as well as additional PMOS transistors.

[0015] For further explanation of the circuit based on this solution, please refer to the following combination. Figure 1 The description. Attached Figure Description

[0016] The invention is described below by way of an embodiment with reference to the accompanying drawings, but this does not limit the general inventive concept. The drawings show: Figure 1 : Transmission gate based on existing technology; Figure 2 : Circuit arrangement according to this solution. Detailed Implementation

[0017] Figure 2 A transmission gate type circuit arrangement is shown, having two transistors connected in parallel. One of the two parallel transistors is designed as an NMOS transistor MN, and the other is designed as a PMOS transistor MP. The gate contacts of the two parallel transistors can be applied with control voltage potentials Vc that are opposite to each other. The inverters required for this are omitted from the diagram. The drain and source terminals of the NMOS transistor MN and the PMOS transistor MP are interconnected and form the connection contacts in and out of the circuit device, respectively, through which input and output voltages Vin and Vout are applied.

[0018] Four NMOS transistors, MNa, MNb, MNc, and MNd, are connected in parallel with the source-drain path of the NMOS transistor MN. These transistors each have a series-connected source-drain path. The NMOS transistor MN also has a substrate terminal connected to a voltage potential obtainable from a contact point K, which is located between the interconnected source-drain paths of the transistor pairs arranged centrally along the series-connected sequence of four transistors MNa, MNb, MNc, and MNd.

[0019] Contact point K is also connected to the source-drain path of another NMOS transistor MNe, which is connected to the negative power supply voltage VSS, and an inverting control voltage potential is applied to the gate contact of this other NMOS transistor. ).

[0020] The gate contacts of the centrally arranged transistor pairs MNa and MNb are connected to the connection contacts in and out, respectively. These connection contacts are opposite to the corresponding transistors of the transistor pairs MNa and MNb relative to contact point K.

[0021] The four transistors MNa, MNb, MNc, and MNd connected in series are adjacent to the centrally arranged NMOS transistor pair MNa and MNb. The NMOS transistors MNc and MNd on both sides of MNa and MNb have gate contacts connected to the power supply voltage VC and substrate terminals connected to the negative power supply voltage VSS, respectively.

[0022] The PMOS side of the circuit device is mirror-symmetrical to the above-described arrangement of the NMOS transistors MN, MNa, MNb, MNc, MNd, and MNE, that is: Four PMOS transistors, MPa, MPb, MPc, and MPd, are connected in parallel with the source-drain path of the PMOS transistor MP. These transistors each have a series-connected source-drain path. The PMOS transistor MP also has a substrate terminal connected to a voltage potential obtainable from a contact point K' located between the interconnected source-drain paths of the transistor pairs MPa and MPb, arranged centrally along the series-connected sequence of four PMOS transistors MPa, MPb, MPc, and MPd.

[0023] Contact point K' is also connected to the source-drain path of another PMOS transistor MPe, which is connected to the positive power supply voltage VDD, and the control voltage potential Vc is applied at the gate contact of the other PMOS transistor.

[0024] The gate contacts of the centrally arranged transistor pairs MPa and MPb are connected to the connection contacts in and out, respectively. These connection contacts are opposite to the corresponding transistors of the transistor pairs MPa and MPb relative to the contact K'.

[0025] The four PMOS transistors MPa, MPb, MPc, and MPd connected in series are adjacent to the centrally positioned PMOS transistor. The PMOS transistors MPc and MPd on either side of MPa and MPb are respectively connected to an inverting control voltage. The gate contacts and the substrate terminals are connected to the positive power supply voltage VDD.

[0026] The working principle of the circuit device is explained based on the NMOS circuit section, specifically for the on / off switching state (i.e., VC = VDD): When VC = VDD, transistor MNE is in the "off" state, i.e., blocked; while MNc and MNd are in the "on" state, i.e., turned on. Transistors MNa and MNb are active, thus ensuring that the lower of the input and output voltages Vin and Vout is applied as the body voltage to transistor MN. For the PMOS circuit section, it is important to note that a correspondingly higher voltage is applied as the body voltage to PMOS transistor MP.

[0027] This method of controlling the body voltage on transistors MN and MP, especially in cases of higher currents that could cause a significant voltage drop between the in and out contact points, ensures that the corresponding body potentials are assigned specific voltages (as described above), which serve as fairly robust and safe operating potentials.

[0028] As a result, transistor MN turns on and forms a significantly lower resistance Ron.

[0029] In the off-switch state (i.e., Vc = VSS), transistor MNe is in the "on" state, while transistors MNc and MNd are in the "off" state. In this case, transistors MNa and MNb cannot transfer any potential because their drain contacts represent high-impedance nodes. The body voltage of transistor MN is determined solely by transistor MNe and is pulled down to the supply voltage VSS. Therefore, resistor Roff becomes very high impedance, significantly higher than with similar measures.

[0030] The extremely high resistance in the off-switch state is crucial, particularly for highly sensitive applications such as implantable electronic devices used to treat various types of neurological disorders through electrical stimulation of nerves. The circuitry underlying these implants represents multifunctional, highly integrated circuits designed to meet the requirements of maximum operational reliability, maximum energy efficiency, and maximum miniaturization. Leakage current on electrodes in contact with biological tissue is unacceptable, especially when performing in vivo electrical stimulation of specific body areas (e.g., nerve fibers). Such leakage current can lead to continuous charge buildup on the electrodes, which must be avoided.

[0031] List of reference numerals in input terminal contact output terminal contact Vin input voltage Vout output voltage MN, MNa NMOS transistors MNb, MNc NMOS transistors MNd, MNe NMOS transistor MP, MPa PMOS transistor MPb, MPc PMOS transistors MPd, MPe PMOS transistors VDD positive power supply voltage VSS negative power supply voltage Vc control voltage Inverting control voltage K, K' nodes

Claims

1. A transmission gate type circuit device having two transistors connected in parallel, one of the two transistors being designed as an NMOS transistor (MN) and the other as a PMOS transistor (MP), wherein the gate contacts of the two parallel transistors can be applied with a control voltage potential (Vc, ...) that is opposite to each other. The drain and source terminals of the two parallel transistors are interconnected and respectively form the connection contacts (in, out) of the circuit device. Its features are, 2n NMOS transistors (MNa, MNb, MNc, MNd) are connected in parallel with the source-drain path of the NMOS transistor (MN), where n ≥ 2. These NMOS transistors each have a series-connected source-drain path. The NMOS transistor (MN) has a substrate terminal connected to a voltage potential obtainable from a contact point located between the interconnected source-drain paths of transistor pairs arranged centered along the series-connected sequence of 2n transistors (MNa, MNb, MNc, MNd). The contact point is connected to the source-drain path of another NMOS transistor (MNe), the source-drain path is connected to the negative power supply voltage (VSS), and the inverting control voltage potential is applied to the gate contact of the other NMOS transistor. ), The gate contacts of the centrally arranged transistor pair are respectively connected to connection contacts (in, out) opposite to the corresponding transistors of the transistor pair relative to the contact points. The 2n transistors (MNa, MNb, MNc, MNd) connected in series are respectively adjacent to the centrally arranged NMOS transistor pair. The NMOS transistors (MNc, MNd) on both sides have gate contacts connected to the power supply voltage VC and substrate terminals connected to the negative power supply voltage (VSS). The PMOS transistor (MP) is assigned an arrangement of 2n PMOS transistors (MPa, MPb, MPc, MPd) that is reverse symmetrical to the above-described transistor arrangement, as well as another PMOS transistor (MPe).

2. The circuit device according to claim 1, Its features are, The reverse symmetrical arrangement consists of 2n PMOS transistors (MPa, MPb, MPc, MPd) connected in parallel with the source-drain path of the PMOS transistor (MP), where n ≥ 2. Each PMOS transistor has a series-connected source-drain path. The PMOS transistor (MP) has a substrate terminal connected to a voltage potential obtainable from a contact point (K'), which is located between the source-drain paths of interconnected transistor pairs (MPa, MPb) arranged in the center along the series-connected sequence of 2n transistors (MPa, MPb, MPc, MPd). The contact point (K') is connected to the source-drain path of another PMOS transistor (MPe), which is connected to the positive power supply voltage (VDD), and the control voltage potential (Vc) is applied at the gate contact of the other PMOS transistor. The gate contacts of the centrally arranged transistor pair (MPa, MPb) are respectively connected to connection contacts (in, out) opposite to the corresponding transistors of the transistor pair relative to the contact point (K'), and The 2n series-connected transistors (MPa, MPb, MPc, MPd) each have PMOS transistors (MPc, MPd) adjacent to the centrally arranged PMOS transistor pair (MPa, MPb) on either side connected to the inverting control voltage. The gate contacts of the device and the substrate terminals connected to the positive power supply voltage (VDD).

Images