Circuit for switch matching

Abstract

A circuit (100) can include a first switch (102) and a second switch (104). The first switch (122) has a first current terminal and a second current terminal and a first control terminal (112), wherein the first current terminal or the second current terminal is coupled to a switch output (114). The second switch (104) has a third current terminal and a fourth current terminal and a second control terminal (120), wherein the second control terminal (120) is coupled to the first control terminal (112) and the fourth current terminal is coupled to the switch output (114). A switch network (106) is coupled between the first switch (102) and the second switch (104).

Description

Technical Field

[0001] This specification relates to switches, such as circuits for switch matching. Background Technology

[0002] Mismatches between the sensing circuitry and the associated switches can occur over time due to the different conditions experienced by the sensing circuitry and the associated switches. For example, a sensing transistor may be coupled to a power transistor in a power converter, and the sensing transistor is configured to provide an indication of the sensed electrical parameter (e.g., current or voltage). For example, one or more operating parameters of the sensing transistor and the power transistor may drift over time due to different stresses and / or temperatures. Summary of the Invention

[0003] An example circuit may include a first switch and a second switch. The first switch has a first current terminal, a second current terminal, and a first control terminal, wherein the first current terminal is coupled to a switch output. The second switch has a third current terminal, a fourth current terminal, and a second control terminal, wherein the second control terminal is coupled to the first control terminal, and the fourth current terminal is coupled to the switch output. A switch network is coupled between the first switch and the second switch.

[0004] Another example circuit includes a first transistor configured to conduct current through the first transistor between a first current terminal and a second current terminal in response to a control signal having a first value at a control input to the first transistor. A second transistor is coupled to the first transistor and configured to provide a sensor signal at a sensor output in response to the control signal, wherein the sensor signal represents the current through the first transistor. A switching network is coupled between at least one terminal of the second transistor and at least one terminal of the first transistor in response to the control signal having a second value.

[0005] Another described example relates to an integrated circuit comprising a first transistor having a first current terminal and a second current terminal, and a first control terminal. The integrated circuit also includes a plurality of second transistors, each of which has a corresponding third current terminal and a fourth current terminal, and a second control terminal, with each second control terminal coupled to the first control terminal. The first transistor occupies a region of the integrated circuit larger than each of the second transistors, and each of the second transistors is spatially distributed over the region occupied by the first transistor. A switching network is coupled between at least some of the first and third current terminals. A sensing circuit system has a sensor input and a sensor output, wherein a fourth current terminal of at least one of the second transistors is coupled to the sensor input. Attached Figure Description

[0006] Figure 1It is a block diagram illustrating an example circuit.

[0007] Figure 2 It is a plan view of an integrated circuit that shows the distribution of the components of the circuit.

[0008] Figure 3 This is a circuit diagram illustrating an example power converter.

[0009] Figure 4 It is a drawing from Figure 3 Signal diagram of an example of a circuit.

[0010] Figure 5 This is a circuit diagram illustrating an example of a power converter with a sensing circuit system.

[0011] Figure 6 and 7 It is a graph illustrating an example of parameter matching between a switch and a sensing circuit system.

[0012] Figure 8 It is a graph showing an example of simulated drift between components over time.

[0013] Figure 9 This is a block diagram illustrating an example system that includes a power converter circuit system. Detailed Implementation

[0014] This specification relates to reducing mismatch between switches, such as between switches and power switches in a sensing circuit system.

[0015] As an example, the circuit includes a first switch (e.g., a transistor) configured to conduct current through the first switch in response to a control signal having a first value (e.g., a value for turning the first switch on or off). In some instances, the first switch may be a power switch, such as a field-effect transistor (e.g., a FET), which may be part of a bridge circuit (e.g., a half-bridge of a power converter). A sensor is coupled to the first switch, the sensor including one or more sensor switches (e.g., one or more transistors). The one or more sensor switches may be configured to provide a sensor signal representing the current through the first switch in response to a control signal. The circuit also includes a switch network configured to couple at least one corresponding terminal of the one or more sensor switches to at least one corresponding terminal of the first switch in response to a control signal having a second value (e.g., a value for turning the first switch off). The switch network enables the one or more sensor switches to withstand approximately the same voltage stress as the first switch, including when the first switch is off.

[0016] Furthermore, or as an alternative example, the circuit is implemented as an integrated circuit (IC), where the first switch is a first transistor and the sensor switch comprises multiple sensor transistors. The switch network can also be implemented as an arrangement of sensor transistors within the same IC. The first transistor may occupy a region within the IC larger than the region individually or collectively occupied by each of the sensor transistors, for example, by one or more orders of magnitude. To enable the sensor transistors to withstand approximately the same temperature stress as the first transistor, the sensor transistors (as smaller devices) reside in the same region of the IC as the first transistor, i.e., at corresponding locations spatially distributed within the region occupied by the first transistor.

[0017] By implementing the layout and / or configuration of the circuit as described herein, one or more sensor switches may be subjected to voltage and temperature stresses approximating those on the first switch over time and in response to circuit operation. This can thus reduce the potentially different effects of aging on the respective switches. For example, if drift over time is allowed, different aging effects, such as those due to voltage and / or temperature stresses, can alter the drain-to-source on-resistance (RDSon) of the FET. Changes in the RDSon between the first FET and the sensing FET can reduce sensing accuracy over time and adversely affect circuit performance. The layout and / or inclusion of the switching network in the circuit can mitigate these other effects of aging.

[0018] Figure 1 An example circuit 100 is illustrated. In some instances, circuit 100 may include or be implemented as a power converter or other type of circuit system. Circuit 100 includes switches 102 and 104 and a switch network 106. Switch (e.g., transistor) 102 has current terminals 108 and 110 and a control terminal 112. Figure 1 In one example, current terminal 110 is coupled to switch output 114, and a load may be coupled to said switch output. In other examples, another current terminal 108 may be coupled to switch output 114. Switch (e.g., one or more transistors) 104 has current terminals 116 and 118 and a control terminal 120. In some examples, switch 104 is referred to as a sensing switch. Control terminal 120 is coupled to control terminal 112 of switch 102, and current terminal 118 is coupled to current terminal 110 and to switch output 114. Figure 1 In one example, the switch network 106 includes a switch (e.g., a transistor) 122 having terminals 124 and 126 coupled between current terminals 108 and 116. Alternatively, or in an alternative embodiment, such as where current terminal 108 is coupled to switch output 114, the switch network 106 may be coupled between current terminals 110 and 118.

[0019] Controller 128 has controller outputs 130 and 132 and a controller input 134. Controller output 130 is coupled to control terminals 112 and 120 of switches 102 and 104, respectively. Controller output 132 is coupled to control input 136 of switch 122. Controller input 134 is coupled to current terminal 116 of switch 104. Controller 128 is configured to provide corresponding control signals at controller outputs 130 and 132 to control the operation of circuit 100. For example, switch 102 is configured to conduct current through a first transistor between current terminals 108 and 110 in response to a control signal at control terminal 112 having a first value (e.g., a value used to activate the switch to a closed position). Switch 104 may be implemented as part of a sensing circuit system (e.g., a sensor) 138, which is configured to provide a sensor signal at current terminal 116 in response to a control signal at control terminal 120. For example, the sensor signal represents the current passing through switch 102 in response to the control signal at 112.

[0020] Switching network 106 is configured to couple terminal 116 of switch 104 to terminal 108 of switch 102, and corresponding terminal of the second transistor, in response to a control signal having a second value that may be different from the first value. For example, switching network 106 may couple one or more terminals 116, 118 of switch 104 to corresponding terminals 108, 110 of switch 102 in response to switch 102 being open. In this way, switch 104, configured to sense current through the switch (e.g., as a sensor switch), can withstand substantially the same voltage as switch 102.

[0021] Although Figure 1Examples of switches 102, 104, and 122 are illustrated as general-purpose switches, but one or more (e.g., all) of such switches may be implemented as transistors, such as FETs (e.g., p-channel or n-channel FETs). As another example, switch 102 may be implemented as a power transistor, such as a gallium nitride (GaN) FET, a silicon carbide (SiC) FET, a metal-oxide-semiconductor FET (e.g., MOSFET), or other FETs. In other examples, other types of transistors may be used to implement switch 102, such as bipolar junction transistors (BJTs) or insulated-gate bipolar transistors (IGBTs). Similarly, each of switches 104 and 122 may be implemented as one or more FETs or other types of transistors, which may be the same type or different type of transistor used to implement switch 102. In some examples, switch 104 includes one or more FETs, and switch 102 is a power FET, wherein the power FET has a region larger than each of the one or more FETs defining switch 104 (e.g., one or more orders of magnitude larger). To reduce the impact of temperature variations, the FET constituting switch 104 can be located in the same trench as the power FET constituting switch 102, for example, uniformly distributed over the region of the power FET. For example, the trench is an isolation well, such as an n-well or p-well, formed within the IC substrate containing the FETs defining switches 102 and 104.

[0022] Figure 2 It is to draw circuits (e.g.) Figure 1 A plan view of the integrated circuit 200, showing the distribution of components of the circuit 100. Figure 2 In one example, integrated circuit 200 includes transistor 202 (e.g., switch 102) and multiple other transistors 204 (e.g., defining transistors). Figure 1 Switch 104 Figure 3 320 or Figure 5 (Switch 506). Transistors 202 and 204 may each be FETs or other types of transistors. For example, transistor 202 occupies a region of IC 200 that is larger than the region of each of transistors 204 (e.g., several orders of magnitude), and each of transistors 204 is spatially distributed over the region occupied by the first transistor. In another example, the first transistor (e.g., FET) 202 has a region that is at least one hundred times larger than each of the second transistors (e.g., FET) 204 (e.g., transistor 202 may be 1,000 to 100,000 times larger than transistor 204).

[0023] Transistor 202, which may be referred to as a main transistor, is formed in or contains an n-well or p-well during a semiconductor manufacturing process, the n-well or p-well having a region larger than each of transistors 204. During manufacturing, each of transistors 204 may also be formed within a region occupied by the same p-well or n-well constituting transistor 202. Any number of one or more transistors 204 (e.g., 2, 3, 4, 5, 6, 7, 8, or more) may be present, the one or more transistors forming at corresponding locations on the region of transistor 202. Figure 2 In one example, five transistors in transistor 204 are evenly (e.g., uniformly) distributed over a region of transistor 202, for example... Figure 2 As illustrated in the example. The uniform distribution of transistors 204 allows at least some of the transistors 204 to withstand temperature variations present on the larger transistor 202. Compared to existing configurations that typically contain a single transistor at a given location, by implementing multiple transistors 204 in the same trench and uniformly distributed over a region of transistor 202, transistors 204 can exhibit improved thermoelectric matching with the main transistor 202. In other examples, transistors 204 are not uniformly distributed over the region occupied by transistor 202, for example, they are more closely located within one or more regions of the region occupied by transistor 202.

[0024] Figure 3 This is a circuit diagram illustrating an example power converter (also called a power circuit) 300. The power converter 300 can be used to implement... Figure 1 and 2 The circuit 100 or IC 200. The power converter includes transistors (e.g., FETs) 302 and 304 coupled between a voltage supply terminal 306 and a ground terminal 308. For example, the transistors are power FETs configured as a bridge circuit (e.g., a half-bridge) with a switching output 310 that can be coupled to a load 312, and the power converter 300 can provide a regulated output (e.g., voltage and / or current). The load 312 may include a processor, data storage device, motor, lighting system, automotive system, network infrastructure, audio and video device, robot, computing device, or other type of load. Transistor 302 has a first current terminal (e.g., drain) coupled to the switching output 310 and a second current terminal (e.g., source) coupled to the ground terminal 308. Transistor 304 has a first current terminal (e.g., drain) coupled to the voltage supply terminal 306 and a second current terminal (e.g., source) coupled to the switching output 310. Each of transistors 302 and 304 also has a corresponding control terminal (e.g., a corresponding gate).

[0025] Controller 314 has outputs 316 and 318 coupled to control terminals of corresponding transistors 302 and 304. Controller 314 is configured to provide control signals at 316 and 318 to control power converter 300. Transistor 302 is configured to conduct current through the transistor and to the output in response to a given value of the control signal at 316. Transistor 304 is also configured to conduct current through the transistor and to the switching output 310 in response to a given value of the control signal at 318. For example, the value used to turn on the corresponding transistors 302 and 304 (e.g., the gate-to-source voltage used to operate transistor 314 in saturation mode) may depend on the type of transistor implemented in power converter 300, such as whether transistors 302 and / or 304 are p-channel or n-channel metal-oxide-semiconductor (MOS) FETs or other types of FETs. Transistors 302 and 304 may be the same or different types of transistors.

[0026] The circuit also includes a switch (e.g., switch 104) 320, which comprises a plurality of transistors (e.g., FETs) 322, 324, 326, 328, and 330. Each of transistors 322, 324, 326, 328, and 330 has a corresponding control terminal (e.g., gate) coupled to a control terminal of transistor 302. Each of transistors 322, 324, 326, 328, and 330 also has a first current terminal (e.g., drain) and a second current terminal (e.g., source). Figure 3 In this example, the first current terminal of transistor 322 is coupled to the first terminal of transistor 302. A first switching network 331 (e.g., a portion of switching network 106) includes transistors (e.g., FETs) 332 and 334 coupled between the first current terminal of each of transistors 324, 326, 328, and 330 and the first terminal of transistor 302. A second switching network 335 (e.g., another portion of switching network 106) includes transistors (e.g., FETs) 336, 338, and 340 coupled between the second current terminal of each of transistors 324, 326, 328, and 330 and the second terminal of transistor 302 (also coupled to ground terminal 308).

[0027] exist Figure 3In this example, transistor 332 is coupled between a first current terminal of transistor 302 and a common first terminal (e.g., common drain) of transistors 328 and 330, and transistor 334 is coupled between a first current terminal of transistor 302 and a common first terminal (e.g., common drain) of transistors 324 and 326. Control terminals (e.g., gates) of transistors 332 and 334 are coupled to a control terminal of transistor 304 (and also to a controller output 318), such that transistors 332 and 334 receive a control signal provided to transistor 304 at 318. Transistor 336 is coupled between the source of transistor 302 and the common source of transistors 322 and 324. Transistor 338 is coupled between the source of transistor 302 and the common source of transistors 326 and 328, and transistor 340 is coupled between the source of transistor 302 and the source of transistor 330. Inverter 344 may be coupled between the control terminal (e.g., gate) of transistor 302 and the control terminal (e.g., gate) of each of transistors 336, 338 and 340 of switching network 335, such that the control terminal of each of transistors 336, 338 and 340 receives an inverted version of the control signal provided for transistor 302 at 316.

[0028] A switch 320, comprising transistors (e.g., FETs) 322, 324, 326, 328, and 330, has a switch output 342 coupled to a sensing input of a controller 314. The switch 320 is configured to sense the current through transistor 302 in response to a control signal provided at 316 and to provide a sensor signal at the switch output 342. For example, the sensor signal at 342 is a current signal representing the current through transistor 302, which can be provided to the sensing circuitry and loop control of the controller 314 to control the power converter 300. During operation of the power converter 300, in the absence of switch networks 331 and 335, the switch 320, comprising transistors 322, 324, 326, 328, and 330, will experience different electrical stresses than the transistor 302 configured to operate as a switch. The varying electrical stresses experienced by the switch 320 and transistor 302 over time and due to aging effects can degrade circuit performance.

[0029] Transistors 332 and 334 of switching network 331 are configured to couple one or more current terminals (e.g., drains) of transistors 322, 324, 326, 328, and 330 to corresponding current terminals (e.g., drains) of transistor 302 in response to a control signal at 318 (e.g., coupled to the gates of transistors 304, 332, and 334) having a value that commands transistor 304 to turn on. Similarly, transistors 336, 338, and 340 of switching network 335 are configured to couple one or more current terminals (e.g., sources) of transistors 322, 324, 326, 328, and 330 to corresponding current terminals (e.g., sources) of transistor 302 in response to an inverted version of a control signal at 316 (coupled to the gates of transistors 336, 338, and 340) having a value that commands transistor 302 to turn off (e.g., through inverter 344). In some instance operating modes, controller 314 is configured to turn on transistor 304 at the same time (or after) transistor 302 is turned off (e.g., operating transistor 314 in saturation mode), for example in Figure 4 As shown in Figure 400. Figure 400 illustrates an example where the control signal at output 318 goes high (shown at 402), which occurs simultaneously with the control signal at 316 going low (shown at 404). Figure 4 Signal 406 is also shown, which represents the signal at the control input of transistors 336, 338 and 340 (e.g., the inverted version of the signal at 316).

[0030] exist Figure 3 In the example, where transistors 302, 304, 322, 324, 326, 328, and 330 are FETs, switching networks 331 and 335 can force the drain-to-source voltage and gate-to-source voltage of transistor 302 onto each of transistors 322, 324, 326, 328, and 330 to reduce the aging effects that may occur due to stress over time. Furthermore, by implementing a common drain and common source configuration for transistors 322, 324, 326, 328, and 330 in switch 320, a reduced number of transistors can be used in switching networks 331 and 335 to subject transistors 322, 324, 326, 328, and 330 to the stress of transistor 302. Therefore, according to Figure 3 The configuration of the examples shown can be implemented efficiently in a cost-effective manner and provides improved performance compared to existing methods.

[0031] In view of the foregoing, switch 320 and switch networks 331, 335 may define an example of a sensing circuit system configured to sense the current through transistor 302 in a manner that reduces the effects of aging and thus improves performance over time. Another example of a sensing circuit system (shown as sensing circuit system 350) may be coupled to transistor 304. Thus, sensing circuit system 350 may be configured similarly to a sensing circuit system associated with the transistors defined by 302, 331, and 335. Sensing circuit system 350 has inputs coupled to a first current terminal and a second current terminal of transistor 304. Sensing circuit system 350 may include a first control input 352 coupled to a control input of transistor 304 (and also coupled to controller output 318). Sensing circuit system 350 may also include a second control input 354 coupled to control output 316, which is also coupled to a control input of transistor 302. Sensing circuit system 350 has an output 356 coupled to a sensing input of controller 314. The controller 314 is configured to control one or more sensing transistors (e.g., FETs) of the sensing circuit system 350 to provide a signal representing the current through the transistor 304 in response to a control signal at 352 having a value that commands the transistor 304 to turn on. The sensing circuit system 350 also includes a switching network configured to couple the current terminals of the sensing transistors to corresponding current terminals (e.g., drain and source) of the transistor 304 in response to a control signal at 352 having a value that commands the transistor 304 to turn off. Additionally, the sensing transistors of the sensing circuit system may reside in the same trench (e.g., a well formed in an IC) and be distributed above the area occupied by the larger transistor 304 to provide enhanced thermoelectric matching. In this way, the sensing circuit system 350 can withstand electrical and thermal stresses commensurate with those of the transistor 304, resulting in improved performance compared to existing sensing methods.

[0032] Figure 5 This is a circuit diagram illustrating an example of a power converter 500 that includes a sensing circuitry system (e.g., a sensor) 502, the sensing circuitry system having inputs to outputs 504 coupled to one or more sensing switches 506. Figure 5 The example sensing circuit system 502 (or other sensing circuit system) can be respectively connected with Figure 1The circuit 100 or power converter 300 may be used in combination, for example, coupled to the output of switch 104 or switch output 342 to receive a sensed corresponding signal (e.g., current). In an example where the sensing switch 506 includes multiple transistors (e.g., transistors 322, 324, 326, 328, and 330, such as FETs), a current terminal (e.g., source or drain) of at least one of the second transistors is coupled to output 504, which is coupled to the input of sensing circuit system 502. In some instances, sensing switch 506 may be implemented as part of sensing circuit system 502.

[0033] Power converter 500 includes transistors (e.g., switches) 508 and 510 coupled between supply terminal 512 and ground terminal 514. The voltage supply terminal may be coupled to a DC voltage (e.g., a voltage rail). Transistors 508 and 510 may be power FETs or other types of transistors configured as a bridge circuit (e.g., a half-bridge) with a switch output 516. An LC network including inductor L1 and capacitor C1 may be coupled between switch output 516 and output terminal 518, and a load 520 may be coupled to said output terminal. Load 520 may include a processor, data storage device, electric motor, lighting system, automotive system, network infrastructure, audio and video device, robot, computing device, or other type of load. Power converter 500 may be configured to provide a regulated output (e.g., voltage and / or current) at output terminal 518. Sensing switch 506 has first and second inputs, wherein the first input is coupled to switch output 516 and the second input is coupled to a control input of transistor 508. In an example, sensing switch 506 is configured to provide a regulated output (e.g., voltage and / or current) according to the following parameters: Figure 1 and 3 The example described uses switch 104 or 320 for implementation. In other examples, other switch configurations can be used.

[0034] The power converter 500 also includes a switching network 522. In some instances, the switching network 522 is based on... Figure 3 Switching networks 331 and 335 are used for implementation. Switching network 522 can be implemented in other configurations, such as those indicated by the operating environment of power converter 500. Switching network 522 has inputs coupled to corresponding current terminals of transistor 508, and one or more other inputs coupled to control inputs of transistor 508 and / or control inputs of transistor 510. As described herein, switching network 522 is configured to subject sensing switch 506 (or multiple sensing switches) to electrical stress commensurate with the stress experienced by transistor 508. Sensing switch 506 is also configured to provide a signal (e.g., current) at output 504 representing the current flowing through transistor 508 in response to a control signal at the control input of the transistor having a value that commands the transistor to turn on.

[0035] As described herein, the sensing circuitry 502 has an input coupled to an output 504 of a sensing switch 506. The sensing circuitry 502 includes outputs 524 and 526. The sensing circuitry 502 is configured to provide a sense signal at each of the sensor outputs 524 and 526 representing the current passing through a transistor (e.g., a switch) 508. For example, output 524 is coupled to an input of a controller (e.g., controller 128 or 314), which may be implemented in the same IC as other components of the power converter 500, and output 526 may be coupled to an output terminal of the IC.

[0036] exist Figure 5 In one example, the sensing circuit system 502 includes an amplifier (e.g., an operational amplifier) ​​530 having a first input 532 and a second input 534, wherein the first input 532 is coupled to an output 504 and the second input 534 is coupled to a ground terminal 514. A switch 536 is coupled between the first input and ground. A capacitor (e.g., a DC blocking capacitor) C2 is coupled in series with a current source 538 between the first amplifier input 532 and the ground terminal 514. Another switch 539 is coupled between the current source 538 and a supply terminal 512. As another example, when the switch network is activated to perform stress matching between the sensing switch 506 and the transistor 508, for example in response to a control signal from a controller, each of the switches closes. In response to the closure of switches 536 and 539, the amplifier input is reset (e.g., zeroed) to its initial value and the capacitor C2 is precharged. Each of switches 536 and 539 may be turned off in response to (e.g., during sensing) allowing measurement of the signal at 504 and scaling it to the desired output values ​​at 524 and 526, as described herein.

[0037] Amplifier 530 has an output 540 that is coupled to an input 541 of an output stage of a sensing circuit system via switch 542. That is, the switch is coupled between the output 540 of amplifier 530 and the input 541 of the output stage. Amplifier 530 is configured to amplify the sensed signal at 532 to provide an amplified sensed signal. The output stage includes an RC network comprising a resistor R1 and a capacitor C3 coupled between the input 541 of the output stage and a supply terminal 512. Input 541 is coupled to a control input (e.g., gate) of transistor 546 (e.g., FET). Transistor 546 has a first current terminal (e.g., drain) coupled to the output 504 of sensing switch 506 and a second current terminal (e.g., drain) coupled to the supply terminal 512. Therefore, the RC network is coupled between the control terminal and the second current terminal of transistor 546. The output of switch 542 is also coupled to the control input of another transistor (e.g., FET) 548. Transistor 548 has a first current terminal (e.g., drain) coupled to output 524 of a sensing circuit system and a second current terminal (e.g., drain) coupled to supply terminal 512. The first current terminal of transistor 548 is also coupled to ground terminal 514 through current source 550 and to output 526 through a resistor (e.g., variable resistor R2).

[0038] In this example, each of transistors 546 and 548 is a PMOS FET and forms a current mirror configured to mirror the amplified sensed signal at 541 to corresponding outputs 524 and 526. Switch 542 is configured to close in response to a control signal at the control input of the transistor having a value that commands the transistor to turn on (e.g., during sensing). Therefore, the amplifier output signal at 540 is provided to the control terminals of transistors 546 and 548 to mirror the amplified signal to outputs 524 and 526.

[0039] Figure 6 and 7 These are plots 600 and 700 illustrating examples of parameter matching between switching and sensing circuit systems under different load conditions. Plots 600 and 700 are... Figure 3 The power converter provides signal indication. Figure 6 In the above, for a 25 A load condition, signal 602 represents the drain-to-source voltage on each of transistors 322, 324, 326, 328, and 330, and signal 604 represents the drain-to-source voltage on transistor 302. Figure 7 In the diagram, for a -5 A load condition, signal 702 represents the drain-to-source voltage on each of transistors 322, 324, 326, 328, and 330, and signal 704 represents the drain-to-source voltage on transistor 302. Therefore, Figure 6 and7 The rising and falling edges of the voltage signal are closely matched, which is the result of switching networks 331 and 335.

[0040] Figure 8 It is a display of how things change over time. Figure 3 A plot 800 showing instances of current supplied by switches 320 (including transistors 322, 324, 326, 328, and 330) in the circuit, which logarithmically displays aging time periods from 0 seconds to 10 years on the x-axis. Figure 8 The example assumes that the on-resistance of transistor 302 has decreased by approximately 8% to 9% during the aging cycle and that the measured current through transistor 302 remains at 25 A. A comparison of the current measurement of 25 A at 0 seconds (shown at 802) with the current measurement at 10 years (shown at 804) shows that the sensed current measurement has shifted by only about 0.1%, indicating that the stress-matching circuit system described herein is effective.

[0041] Figure 9 This is a block diagram illustrating an example system 900, which includes a power converter circuit system described herein for a given usage environment. The power converter circuit system includes one or more multiphase power converters 902, wherein each phase of the multiphase power converter may include a power stage 904. Each power stage 904 may include an example of a power converter described herein (e.g., circuit 100, power converter 300, or power converter 500). For example, each power stage 904 may include one or more power transistors (e.g., arranged as a bridge circuit) and one or more sensing circuit systems coupled to the power transistors (e.g., [missing information]). Figure 1 106 and 138; Figure 3 320, 331, and 335 or 350; or Figure 5 (502, 506, 522), as described in this article.

[0042] exist Figure 9 In one example, each power stage 904 has an output coupled to a corresponding load 908 through an inductor 906. The load may be a CPU and / or memory or other types of load, such as those described herein. In other examples, a multiphase power converter 902 may be used to supply power to other types of loads. Additionally, the system 900 may include one or more controllers 910 configured to control each power stage 904 (e.g., as described herein) to provide regulated power to the load for each of its phases. The controllers 910 may be implemented as follows: Figure 1 Examples of controllers 128 or 314. Power supply 912 can also be configured to provide centralized power to each multiphase power converter 902.

[0043] In this description, the term "based on" means "at least partially based on".

[0044] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0045] Furthermore, in this specification, a device "configured" to perform a task or function may be configured by the manufacturer during manufacturing (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device or a combination thereof.

Claims

1. A circuit comprising: A first switch has a first current terminal, a second current terminal, and a first control terminal, wherein the first current terminal is coupled to a switch output; A second switch has a third current terminal and a fourth current terminal and a second control terminal, wherein the second control terminal is coupled to the first control terminal and the fourth current terminal is coupled to the switch output; and A switch network coupled between the first switch and the second switch.

2. The circuit of claim 1, further comprising a third switch having a fifth current terminal and a sixth current terminal and a third control terminal, wherein the first current terminal is coupled to the switch output, the switch network is coupled between the second current terminal and the fourth current terminal, the fifth current terminal is coupled to a voltage supply terminal, and the sixth current terminal is coupled to the first current terminal of the first switch.

3. The circuit according to claim 2, wherein: The first switch includes a first field-effect transistor (FET). The third switch includes a third FET. The first current terminal and the fifth current terminal are corresponding drain terminals. The second current terminal and the sixth current terminal are corresponding sources, and The first control terminal and the third control terminal are corresponding gates.

4. The circuit according to claim 3, wherein: The second switch includes a plurality of second FETs, wherein each of the second FETs has a corresponding gate coupled to the gate of the first FET. The switching network includes: A fourth switch, coupled between at least some of the drains of the second FET and the drains of the first FET, and A fifth switch, coupled between at least some of the sources of the second FET and the sources of the first FET.

5. The circuit according to claim 4, wherein: The fourth switch includes a plurality of fourth FETs, each fourth FET having a corresponding gate coupled to the gate of the third FET, and The fifth switch includes a plurality of fifth FETs.

6. The circuit of claim 5, further comprising a controller having a first controller output coupled to the gate of the first FET and a second controller output coupled to the gate of the third FET and a corresponding gate of the third FET.

7. The circuit according to claim 6, wherein: The controller is configured to provide a first control signal and a second control signal. The first FET is configured to conduct current through the first FET in response to the first control signal having a first value. The third FET is configured to conduct current through the third FET in response to the second control signal having a first value. The plurality of fourth FETs are configured to couple the drain of the first FET to the drain of at least some of the second FETs in response to the second control signal having the first value, and The plurality of fifth FETs are configured to couple the source of the first FET to the source of at least some of the second FETs in response to the first control signal having a second value.

8. The circuit of claim 4, wherein the first FET has a region that is at least one hundred times larger than each of the second FETs.

9. The circuit of claim 8, implemented as an integrated circuit, wherein the plurality of second FETs reside in a region of the integrated circuit, and the first FETs are spatially distributed at corresponding locations on the region of the first FETs.

10. The circuit of claim 1, further comprising a sensing circuit system having a sensor input and a sensor output, wherein the sensor input of the sensing circuit system is coupled to the switch output, and the sensing circuit system is configured to provide a sensing signal at the sensor output representing a current through the first switch.

11. The circuit of claim 10, wherein the sensing circuit system comprises: An amplifier having a first amplifier input, a second amplifier input, and an amplifier output, wherein the first amplifier input is coupled to the switch output and the second amplifier input is coupled to a ground terminal; A capacitor, which is coupled in series with a current source between the input of the first amplifier and the ground terminal; and A current mirror is coupled between the amplifier output and the sensor output. The amplifier is configured to amplify the sensing signal, and the current mirror is configured to provide an output current at the sensor output based on the amplified sensing signal.

12. A circuit comprising: A first transistor is configured to conduct current through the first transistor between a first current terminal and a second current terminal in response to a control signal having a first value at a control input of the first transistor. A second transistor, coupled to the first transistor and configured to provide a sensor signal at a sensor output in response to the control signal, the sensor signal representing the current through the first transistor; and A switching network that, in response to the control signal having a second value, is coupled between at least one terminal of the second transistor and at least one terminal of the first transistor.

13. The circuit of claim 12, wherein the control signal is a first control signal, and the circuit further includes a third transistor, wherein the third transistor is configured to conduct current through the third transistor between a third current terminal and a fourth current terminal in response to a second control signal having a corresponding value, and the fourth current terminal is coupled to the first current terminal.

14. The circuit of claim 13, wherein the switching network comprises: A first switch is configured to couple the first current terminal of the first transistor to the fifth current terminal of the second transistor in response to the second control signal having the corresponding value. and A second switch is configured to couple the second current terminal of the first transistor to the sixth current terminal of the second transistor in response to the first control signal having the second value.

15. The circuit according to claim 14, wherein: The first transistor includes a first field-effect transistor (FET), wherein the first current terminal is the drain of the first FET and the second current terminal is the source of the first FET. The second transistor includes a plurality of second FETs, each of which has a corresponding gate coupled to the gate of the first FET. The third transistor includes a third FET, wherein the third current terminal is the drain of the third FET and the fourth current terminal is the source of the third FET. The first switch includes a plurality of fourth FETs between the drains of at least some of the second FETs and the drains of the first FET, and The second switch includes a plurality of fifth FETs coupled between the sources of at least some of the second FETs and the sources of the first FETs.

16. The circuit of claim 15, further comprising a controller configured to transmit the first control signal to the gate of the first FET and to transmit the second control signal to a corresponding gate of the second FET, wherein: The plurality of fourth FETs are configured to couple the drain of the first FET to the corresponding drain of at least some of the second FETs in response to the second control signal having the corresponding value, and The plurality of fifth FETs are configured to couple the source of the first FET to the corresponding source of at least some of the second FETs in response to the first control signal having the second value.

17. The circuit of claim 15, implemented as an integrated circuit, wherein: The first FET is a power FET, having a region that is at least one hundred times larger than each of the second FETs, and The plurality of second FETs reside in the same slots as the power FET, at corresponding locations in the region of the power FET.

18. An integrated circuit comprising: The first transistor has a first current terminal, a second current terminal, and a first control terminal; A plurality of second transistors, wherein each of the second transistors has a corresponding third current terminal and a fourth current terminal and a second control terminal, each second control terminal being coupled to a first control terminal, the first transistor occupying a region of the integrated circuit larger than each of the second transistors, and each of the second transistors being spatially distributed over the region occupied by the first transistor. A switching network coupled between at least some of the first current terminals and the third current terminals; and A sensing circuit system having a sensor input and a sensor output, wherein the fourth current terminal of at least one of the second transistors is coupled to the sensor input.

19. The integrated circuit of claim 18, further comprising: The third transistor has a fifth current terminal and a sixth current terminal as well as a third control terminal, wherein the fifth current terminal is coupled to a voltage supply terminal and the sixth current terminal is coupled to the first current terminal.

20. The integrated circuit according to claim 19, wherein: The first transistor is a first field-effect transistor (FET). The plurality of second transistors include a plurality of second FETs located in the same trench as the first FET, uniformly spatially distributed over the region occupied by the first FET, and each of the second FETs having a corresponding gate coupled to the gate of the first FET. The third transistor is a third FET, and The switching network includes: A fourth FET, coupled between the drain of the first FET and the drains of at least some of the second FETs; and A fifth FET is coupled between the source of the first FET and the source of at least some of the second FETs.

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