Semiconductor device and power conversion device

Abstract

A semiconductor device (1) includes: a collector layer (5); a drift layer (4) stacked on the collector layer (5); a base layer (32) stacked on the drift layer (4); a first gate (21) disposed side-by-side on the drift layer (4) along the gate length direction; and a second gate (22) that can be driven independently of the first gate (21) and is disposed side-by-side with a portion of the first gate (21). The device is divided into a first region (Hc) and a third region (Ts) on which the first gate (21) is disposed, and a second region (Hs) on which the first gate (21) and the second gate (22) are disposed, such that the third region (Ts) is disposed between the first region (Hc) and the second region (Hs) in the gate length direction. In the collector layer (5), the carrier concentration in the second region (Hs) and the third region (Ts) is lower than the carrier concentration in the first region (Hc).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device having the same. Background Technology

[0002] Due to the global trend towards a decarbonized society, the market for electric vehicles (EVs), mobile applications such as railways, and power grids is continuously growing. In this application, power conversion devices are used to control loads such as motors by outputting AC current based on DC power supplied from a DC power source. To miniaturize and increase the efficiency of these power conversion devices, the semiconductor switching elements, which are key components, require low losses (reduction of conduction and switching losses). Therefore, IGBTs (Insulated Gate Bipolar Transistors), capable of switching large currents at high speeds, are widely used as semiconductor switching elements. Furthermore, for high reliability of the power conversion devices, semiconductor switching elements must be able to interrupt the large current flowing through them without damage; that is, ensuring the maximum current that can be interrupted normally without damage during turn-off (= turn-off capacity).

[0003] As a technique for reducing the conduction loss and switching loss (turn-off loss) of IGBTs, Patent Document 1 discloses a technique related to dual-gate IGBTs. Furthermore, regarding dual-gate IGBTs, Patent Document 2 discloses a technique involving high damage resistance.

[0004] Dual-gate IGBTs have Figure 5 The circuit structure shown, as described in Patent Documents 1 and 2, involves dividing the active region into regions with independently drivable first and second gates, and a region with only the first gate. Furthermore, when the IGBT is turned on, one region accumulates a lower concentration of carriers than the other. In Patent Documents 1 and 2, when the IGBT transitions from an on-state to a non-on-state, it moves from a state where driving voltages are applied to both the first and second gates (high conduction period), through a low conduction period where the first gate is turned off and only the second gate is driven, and then turns the second gate off as well, becoming a non-on-state. With this structure, during the low conduction period, the region with only the first gate discharges the carriers that accumulate during the high conduction period, while in the region with both the first and second gates, a low concentration of carriers is formed by applying a voltage to the second gate. As a result, when the second gate is turned off, electrons and holes are rapidly discharged from the low-concentration accumulated carriers, thus applying a reverse blocking voltage to the IGBT at high speed and reducing the current at high speed, achieving low-loss turn-off.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2022-167435

[0008] Patent Document 2: Japanese Patent Application Publication No. 2023-115995 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] In the technologies described in Patent Documents 1 and 2, since the carrier injection efficiency of the two regions is different, when the accumulated carriers are discharged in one region during the low conduction period, current concentration occurs at the boundary between the two regions, which cannot fully demonstrate the improvement effect of turn-off cutoff capacity, and there is room for improvement.

[0011] Therefore, the object of the present invention is to provide a highly reliable semiconductor device that can improve turn-off tolerance without increasing conduction loss and switching loss, and a power conversion device using the semiconductor device.

[0012] Methods for solving problems

[0013] To address the aforementioned issues, the semiconductor device of the present invention is characterized by comprising: a collector layer; a drift layer stacked on the collector layer; a base layer stacked on the drift layer; a first gate disposed side-by-side on the drift layer along the gate length direction; and a second gate capable of being driven independently of the first gate, disposed side-by-side with a portion of the first gate, and divided into a first region and a third region where the first gate is disposed, and a second region where the first gate and the second gate are disposed, such that the third region is disposed between the first region and the second region along the gate length direction, wherein one or more of the first region, the second region, and the third region are disposed, and the base layer is disposed separately in the first region, the second region, and the third region, wherein the carrier concentration in the second region and the third region of the collector layer is lower than the carrier concentration in the first region.

[0014] Invention Effects

[0015] According to the present invention, a highly reliable semiconductor device and power conversion device can be realized that improves turn-off tolerance without increasing conduction loss and switching loss. Attached Figure Description

[0016] Figure 1This is a diagram showing the overall structure of the motor control system of the power conversion device of the semiconductor device to which the embodiments of the present invention are applied.

[0017] Figure 2 This is a top view of a semiconductor chip constituting a semiconductor device according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present invention. Figure 2 A partial sectional view along line AA.

[0019] Figure 4 This is a schematic diagram illustrating the configuration of the emitter layer of a semiconductor device according to an embodiment of the present invention. Figure 2 A magnified view of a portion of the image.

[0020] Figure 5 This is a circuit diagram of a semiconductor device and its driving device according to an embodiment of the present invention.

[0021] Figure 6 This is a timing diagram of the driving signals of the semiconductor device according to an embodiment of the present invention.

[0022] Figure 7A It is a conceptual representation Figure 3 A diagram showing the carrier distribution during the high conductivity period of the semiconductor device.

[0023] Figure 7B It is a conceptual representation Figure 3 A diagram showing the carrier distribution during the low conduction period of the semiconductor device.

[0024] Figure 8 It is a conceptual representation of the carrier distribution during the low conduction period of existing semiconductor devices.

[0025] Figure 9 It is a graph showing the relationship between the turn-off loss of an IGBT and the ratio of the length of the third region of the IGBT to the thickness of the drift layer, based on semiconductor device simulation.

[0026] Figure 10 It means based on Figure 9 The simulation results shown are a graph illustrating the relationship between the length of the third region of the IGBT and the thickness of the drift layer.

[0027] Figure 11 This is a schematic diagram illustrating the structure of a semiconductor device according to a modified embodiment of the present invention. Figure 2 A partial sectional view along line AA.

[0028] Figure 12This is a schematic diagram illustrating the structure of a semiconductor device according to a modified embodiment of the present invention. Figure 2 A partial sectional view along line AA.

[0029] Figure 13 This is a top view of a semiconductor chip in a semiconductor device constituting a modified embodiment of the present invention. Detailed Implementation

[0030] Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as "implementations") will be described with appropriate reference to the accompanying drawings. Elements of the same or homogeneous structure will be labeled with the same reference numerals, and descriptions will be omitted where appropriate.

[0031] [Power Conversion Device]

[0032] Figure 1 This diagram illustrates the overall structure of a motor control system 100 using a power conversion device according to an embodiment of the present invention. A power conversion device is a device that uses power semiconductor devices to convert electrical energy. In this embodiment, a motor control system 100 using an inverter circuit with IGBTs as power semiconductor devices will be described as an example. The motor control system 100 is a control system for an inductive load using a three-phase inverter, and includes a DC power supply DC, an inverter circuit 90, and a motor M as an inductive load.

[0033] The inverter circuit 90 includes a smoothing capacitor 91, three-phase inverter units 9 (U-phase inverter unit 9U, V-phase inverter unit 9V, and W-phase inverter unit 9W) and an instruction logic unit 96. The inverter circuit 90 outputs AC power based on DC power supplied from a DC power source to drive the motor M. A smoothing capacitor 91 is provided between the DC power source (power supply voltage = Vcc) and the positive connection line 93 and the negative connection line 94 of the inverter circuit 90.

[0034] Inverter unit 9 consists of an upper arm and a lower arm, and has a series circuit of semiconductor devices 1. The semiconductor devices 1 of each arm constitute the semiconductor switching element of that arm. Here, the semiconductor devices 1 are IGBTs. A gate signal is sent to the IGBT from the gate drive device 80. The high-potential side terminal of the upper arm's IGBT is connected to the first terminal (positive connection line 93) of the smoothing capacitor 91. The high-potential side terminal of the lower arm's IGBT is connected to the low-potential side of the upper arm's IGBT. The low-potential side terminal of the lower arm's IGBT is connected to the second terminal (negative connection line 94) of the smoothing capacitor 91.

[0035] In each phase, the connection point 95 between the low-potential terminal of the upper IGBT and the high-potential terminal of the lower IGBT is connected to one end of the winding of the motor M. The other end of the winding of each phase is connected to the neutral point. The motor M is, for example, an induction motor.

[0036] The return diode 92 (freewheeling diode) is connected in reverse parallel with each IGBT. As the return diode 92, various diodes can be used, such as pn junction diodes, Schottky barrier diodes, and diodes combining pn junctions and Schottky junctions.

[0037] The instruction logic unit 96 outputs a turn-on command indicating an on state or a turn-off command indicating an off state as a drive command signal P for the semiconductor device 1 to the gate drive device 80. Thus, in order to control the control quantity of the motor M to its command value, the instruction logic unit 96 alternately turns on the upper and lower semiconductor devices 1 in each phase. The control quantity is, for example, the torque of the motor.

[0038] The gate driving device 80 is respectively provided corresponding to each semiconductor device 1, and obtains the driving command signal P from the instruction logic unit 96. Based on the obtained driving command signal P, the semiconductor device 1 is turned on or off.

[0039] [Semiconductor Devices]

[0040] Figure 2 This is a top view of the semiconductor chip constituting the semiconductor device 1 of the embodiment of the present invention. Figure 2 Indicates composition Figure 1 The semiconductor chip of the semiconductor device in the lower arm of the U-phase in the inverter circuit 90 shown. Furthermore, the semiconductor devices in the upper arm of the U-phase, the V-phase, and the upper and lower arms of the W-phase have the same structure. Multiple semiconductor devices 1 can also be installed in parallel. Figure 2 The diagram shows the form of a power module (IGBT module) using a semiconductor (IGBT) chip. The following is a detailed explanation of each element of the semiconductor chip.

[0041] The semiconductor device (semiconductor chip) 1 comprises an active region including a termination region (also called a termination or guard ring) Ter disposed on the outer periphery of the chip for electric field mitigation, and an active region inside the termination region Ter. The active region of the semiconductor device 1 is further divided into a first region Hc, a third region Ts, and a second region Hs along the length of the chip's top-view shape. The active region is a region through which no current flows, and includes, in addition to the termination region Ter, a gate finger region disposed with gate wirings 71 and 72 supplying power to gate electrodes 21 and 22, and a pad region for the gate wirings 71 and 72. The active region is a region through which current flows, for example, an electrode 73 (refer to) formed to connect to the emitter layer 33. Figure 3 ,exist Figure 2 The regions (not shown in the diagram) are as follows: The first region Hc is a high-conductivity region, meaning it can accumulate a high concentration of charge carriers when the semiconductor device 1 is turned on. The second region Hs is a low-conductivity region, where the concentration of charge carriers that can accumulate when the semiconductor device 1 is turned on is lower than that in the first region Hc. The third region Ts is the boundary region sandwiched between the first region Hc and the second region Hs; it can accumulate a concentration of charge carriers equal to that in the second region Hs when the semiconductor device 1 is turned on.

[0042] In the first region Hc and the third region Ts, along the gate length direction ( Figure 2 In the region Hs, first gate electrodes 21 extending across the entire width of the region are arranged side-by-side in the horizontal direction. In the second region Hs, the first gate electrodes 21 and second gate electrodes 22, which extend in the same manner as described above, are arranged alternately in two columns. In other words, the first gate electrodes 21 are arranged side-by-side throughout the active region, characterized in that, in the second region Hs, they are arranged at intervals from regions Hc and Ts, and in the second region Hs, second gate electrodes 22 are arranged side-by-side with the first gate electrodes 21.

[0043] Figure 3 yes Figure 2 The partial cross-sectional view along line AA, specifically, is the third region Ts and the first region Hc and the second region Hs on either side. Furthermore, in Figure 3 And in the subsequent cross-sectional views, the p-type semiconductor layer is labeled "p", "p", etc. + "or "p - The n-type semiconductor layer is labeled with "n" and "n". + "or "n - The order of carrier concentration from highest to lowest is represented as "p". + “p”, “p” - Additionally, it is represented as "n". + “n”, “n” - ".

[0044] Semiconductor device 1 is a dual-gate trench-gate IGBT. Semiconductor device 1 has n cells constituting the drift layer 4. - One main surface side of the semiconductor substrate ( Figure 3 On the upper side of the n-side, a p-well layer including a floating layer 31 and a base layer 32 is formed, along with a first gate electrode 21 and a second gate electrode 22 that can be independently controlled. Furthermore, in n - One main surface of the type semiconductor substrate is composed of n +A semiconductor layer forms the emitter layer 33. A gate oxide film 61 is formed inside the drift layer 4, in contact with the base layer 32 and the emitter layer 33. Gate electrodes 21 and 22 are disposed inside the drift layer 4, separated by the gate oxide film 61, and insulated from the emitter electrode 73 by an interlayer insulating film 62. The emitter electrode 73 is formed on one main surface side of the drift layer 4, in contact with the p-well layer (i.e., the base layer 32) and the emitter layer 33 in the region with a narrower gate spacing. The p-well layer (i.e., the floating layer 31) in the region with a wider gate spacing is insulated from the emitter electrode 73 by the interlayer insulating film 62. On the other main surface side of the drift layer 4 (… Figure 3 A collector layer 5, composed of a p-type semiconductor layer, is formed on the lower side of the n-type semiconductor layer. Furthermore, on the n-type semiconductor layer... - On another main surface (back side) of the semiconductor substrate, a collector electrode 74 is formed in contact with the collector layer 5. That is, the semiconductor device 1... Figure 3 Starting from the bottom (back side), a well layer is provided, in sequence, including a collector electrode 74, a collector layer 5, a drift layer 4, a floating layer 31, and a base layer 32. It also includes gate electrodes 21 and 22 buried between the floating layer 31 and the base layer 32 and covered by a gate oxide film 61; an emitter layer 33 stacked on top of the base layer 32 in a portion of the area; an emitter electrode 73 connected to all emitter layers 33 and the base layer 32; and gate wirings 71 and 72 respectively connected to the gate electrodes 21 and 22 (see reference). Figure 2 ).

[0045] The collector layer 5 and drift layer 4 also include non-active regions and are disposed throughout the entire region of the semiconductor device 1. The drift layer 4 is composed of an n-type semiconductor layer. The collector layer 5 is composed of a p-type semiconductor layer. The collector layer 5 is a hole injection layer that injects holes into the drift layer 4 when the semiconductor device 1 is turned on. Furthermore, the collector layer 5 is composed of a high-concentration carrier layer 51 in the first region Hc and a low-concentration carrier layer 52 in the second region Hs and the third region Ts, where the carrier concentration is lower than that of the high-concentration carrier layer 51. In the semiconductor device 1, as... Figure 2 As shown, a high-concentration carrier layer 51 is formed in the first region Hc, and a low-concentration carrier layer 52 is formed in other regions, including the non-active region. In the on-state of the semiconductor device 1, holes are injected from the collector layer 5 into the drift layer 4, but the high-concentration carrier layer 51 and the low-concentration carrier layer 52 are formed in such a way that the amount of holes injected from the low-concentration carrier layer 52 is sufficiently small compared to the high-concentration carrier layer 51. As an example, the concentration ratio of p-type impurities in the high-concentration carrier layer 51 to the low-concentration carrier layer 52 is approximately 10:1 to 100:1. Such a collector layer 5 allows for the fabrication of the semiconductor device 1 while maintaining the p-type density of the p-type carrier layer. -The substrate is formed by irradiating the entire back surface of a semiconductor substrate with a low concentration of p-type impurities, then setting a mask to create a region (first region Hc) that becomes a high concentration carrier layer 51, and irradiating it with a high concentration of p-type impurities.

[0046] The first gate electrode 21 is a carrier control gate, which extends along the gate width direction throughout the entire width of the active region in each of the regions Hc, Hs, and Ts, and has a contact 71c at one end with the first gate wiring 71. Figure 4 The first gate electrode 21 and the second gate electrode 22 are connected. The second gate electrode 22 is a switching gate, which extends in the gate width direction in the second region Hs, similar to the first gate electrode 21, and is connected at one end to the contact (not shown) of the second gate wiring 72. Therefore, the first gate electrode 21 and the second gate electrode 22 can be controlled independently of each other. The side surfaces and lower surfaces of the gate electrodes 21 and 22 are covered by the gate oxide film 61, and the upper surfaces, except for the connection portions with the contacts of the gate wirings 71 and 72, are covered by the interlayer insulating film 62. The first gate electrode 21, together with the gate oxide film 61, the emitter layer 33 adjacent to the gate oxide film 61, and the power supply layer of the adjacent base layer 32, together constitute the first switching element 11. The second gate electrode 22, together with the gate oxide film 61, the emitter layer 33 adjacent to the gate oxide film 61, and the power supply layer of the adjacent base layer 32, together constitute the second switching element 12.

[0047] The floating layer 31 and the base layer 32 are composed of p-type well layers. The base layer 32 is arranged separately in each region Hc, Hs, and Ts. The base layer 32 is sandwiched from both sides by the first gate electrode 21 in the first region Hc and the third region Ts, and sandwiched by the first gate electrode 21 and the second gate electrode 22 in the second region Hs. An emitter layer 33 is stacked on a portion of the base layer 32, and the portion that does not form an emitter layer and is sandwiched from the side by the emitter layer 33 serves as a power supply layer, which is connected to the emitter electrode 73 together with the emitter layer 33. The floating layer 31 is alternately arranged with the base layer 32 across the first gate electrode 21 or the second gate electrode 22, and its upper surface is covered by an interlayer insulating film 62.

[0048] The emitter layer 33 is composed of a high-concentration n-type semiconductor layer. The emitter layer 33 is the region where electrons are injected into the drift layer 4 when the semiconductor device 1 is turned on. The emitter layer 33 is stacked such that a portion of the base layer 32 is buried within it. Specifically, the emitter layer 33 is disposed separately from the power supply layer at the center of the gate length direction of the base layer 32, and is adjacent to the first gate electrode 21 or the second gate electrode 22 on both sides of the base layer 32, respectively, separated by the gate oxide film 61. The emitter layer 33 can be continuously disposed along the gate electrodes 21 and 22 in the gate width direction, or it can be disposed as follows: Figure 4The emitter layer 33 is configured discontinuously as shown. Specifically, the emitter layer 33 is regularly arranged in the gate width direction with a length w1 and a period a1 (gap (a1 to w1)). If the length of each period of the emitter layer 33 (discontinuity ratio) (w1 / a1) is small, the saturation current of the IGBT decreases, resulting in an increase in the on-state voltage. Conversely, if the discontinuity ratio (w1 / a1) of the emitter layer 33 is large, the saturation current of the IGBT increases, resulting in a decrease in short-circuit withstand capability; therefore, an appropriate value is preferred. Furthermore, the discontinuity ratio of the emitter layer 33 in the third region Ts is preferably greater than or equal to that in regions Hc and Hs. Figure 4 In the third region Ts, the emitter layer 33 is configured with a length w2 and a period a2, for example, w1 = w2 and a1 > a2, thereby configuring the emitter layer 33 of the third region Ts with a relatively high density. By setting it to such a structure, when the semiconductor device 1 is turned on, electron injection into the drift layer 4 in the third region Ts is promoted, and the on-state voltage of the IGBT can be reduced.

[0049] The collector electrode 74 is disposed on the entire back side of the semiconductor device 1 and is in contact with the collector layer 5. The emitter electrode 73 is disposed on the entire active region of the surface of the semiconductor device 1 and is in contact with the power supply layers of all emitter layers 33 and all base layers 32. The collector electrode 74 and the emitter electrode 73 are a pair of electrodes, with the collector electrode 74 being positive to supply current to the semiconductor device 1. The first gate wiring 71 and the second gate wiring 72 are disposed on the non-active region of the surface of the semiconductor device 1, extending along the gate length direction, and have pads for external connection formed at one end. The first gate wiring 71 is connected to one end of each of the first gate electrodes 21. The second gate wiring 72 is connected to one end of each of the second gate electrodes 22.

[0050] The semiconductor chip constituting such a semiconductor device 1 is in n - One main surface side of the type semiconductor substrate (drift layer 4) Figure 3 A p-well layer, including a floating layer 31 and a base layer 32, is formed on the upper side of the n-well. Furthermore, in n - One main surface of the type semiconductor substrate is composed of n + A semiconductor layer forms the emitter layer 33. A gate oxide film 61 is formed inside the drift layer 4, in contact with the base layer 32 and the emitter layer 33. Gate electrodes 21 and 22 are disposed inside the drift layer 4, separated by the gate oxide film 61, and insulated from the emitter electrode 73 by an interlayer insulating film 62. The emitter electrode 73 is formed on a main surface side of the drift layer 4, in contact with the p-well layer (i.e., the base layer 32) and the emitter layer 33 in the region with a narrow gate spacing. The p-well layer (i.e., the floating layer 31) in the region with a wider gate spacing is insulated from the emitter electrode 73 by the interlayer insulating film 62.

[0051] Here, the region comprising a base layer 32 and two rows of first gate electrodes 21 on both sides thereof (first gate electrode 21 and second gate electrode 22 in the second region Hs) is referred to as a unit cell, and its spacing L is defined as follows: c This is called the cell length. It can be said that semiconductor device 1 has cells spaced at a certain interval L in the active region. c The unit cells are arranged side by side. Furthermore, in the second region Hs, the unit cells are arranged side by side by reversing their orientation, so that the first gate electrodes 21, 21 face each other, and the second gate electrodes 22, 22 face each other, sandwiching the floating layer 31. Moreover, it is preferable that the first gate electrode 21 is disposed at the end of the third region Ts side of the second region Hs.

[0052] In semiconductor device 1, the third region Ts is shorter than the first region Hc and the second region Hs in the gate length direction, and the number of first gate electrodes 21 configured therein is less than the total number (columns) of first gate electrodes 21 in the first region Hc and the total number of gate electrodes 21 and 22 in the second region Hs. The third region Ts has at least one base layer 32 and two columns of first gate electrodes 21 on both sides thereof. Figure 3 As shown, the third region Ts preferably has two base layers 32 and four rows of first gate electrodes 21 on both sides of each base layer 32 in the gate length direction, separated by the floating layer 31. That is, the gate length length Δ of the third region Ts is equal to the cell length L. c The same, or the unit length L c Twice that. The length Δ along the gate length direction of the third region Ts becomes the cell length L. c The length is doubled to achieve sufficient length, further enhancing the turn-off cut-off capacity. Furthermore, as described above, by configuring the first gate electrode 21 at the end of the third region Ts side of the second region Hs, the region of the second region Hs with the first gate electrode 21 has the same structure as the third region Ts, so it can be said that the third region Ts is extended. The length Δ′ of the extension is L. c / 2. On the other hand, even if the third region Ts has more than three base layers 32, the length Δ (Δ≥3L) is further increased. c Furthermore, the effect is difficult to improve further, and if it is longer, the conduction loss (conduction voltage) will increase. Details regarding the preferred range of the gate length Δ of the third region Ts will be described later.

[0053] In the semiconductor device 1, there is no particular specification regarding the area ratio of the first region Hc to the second region Hs, or the relationship between the number of first gate electrodes 21 in the first region Hc and the total number of gate electrodes 21 and 22 in the second region Hs. Figure 2The top view of the semiconductor device 1 shown, and the number of gate electrodes 21 and 22 respectively disposed in regions Hc, Hs, and Ts, are examples. By having a larger area and more gate columns in the first region Hc than in the second region Hs, and a larger area in the high-concentration carrier layer 51 than in the low-concentration carrier layer 52 in the collector layer 5, conduction losses (IGBT turn-on voltage) can be effectively reduced. This structure is suitable for power conversion devices used in power grids where the switching perimeter fraction is relatively low and the proportion of conduction losses is high. Conversely, the area and more gate columns in the second region Hs are larger than in the first region Hc, resulting in a larger area in the low-concentration carrier layer 52 than in the high-concentration carrier layer 51. This reduces the number of accumulated carriers, and consequently, effectively reduces switching losses (IGBT turn-off losses). This structure is suitable for power conversion devices used in mobile applications such as railways and EVs where the switching perimeter fraction is relatively high and the proportion of switching losses is relatively high.

[0054] (Operation of semiconductor devices)

[0055] The operation of the semiconductor device in this embodiment will be explained. Figure 5 This is a circuit diagram of semiconductor device 1 and its driving device. Additionally, Figure 6 This is a timing diagram of the drive signals for the semiconductor device. Semiconductor device 1 operates with low loss by driving the gate drivers 81 and 82 of the first gate electrode 21 and the second gate electrode 22, respectively. The period before time t2 (t≤t2) is the IGBT's conduction period, and the period after time t2 (t≥t2) represents the non-conduction period. The conduction period is defined as the high conduction period before time t1 (t≤t1) and the low conduction period before the transition to the non-conduction period (t1≤t≤t2). The low conduction period is also referred to as the switch preparation period t. pre_off (=t2-t1).

[0056] During high conduction, a voltage Vth or higher is applied to the first gate electrode 21 and the second gate electrode 22 at a threshold voltage Vth that forms the inversion layer in the base layer 32 of the semiconductor device 1. Gc V Gs Additionally, the collector electrode 74 of semiconductor device 1 ( Figure 3 A positive voltage is applied relative to the emitter electrode 73. Figure 7A The carrier distribution during the high conductivity period of semiconductor device 1 is conceptually illustrated. At the collector electrode 74 of semiconductor device 1 ( Figure 3 When a positive voltage is applied relative to the emitter electrode 73, from Figure 1The gate driving device 80 supplies power to the gate electrodes 21 and 22 of the semiconductor device 1 via gate wirings 71 and 72. If a voltage Vth greater than the threshold voltage Vth of the semiconductor device 1 is applied between the first gate electrode 21 and the emitter electrode 73, and between the second gate electrode 22 and the emitter electrode 73, respectively... Gc V Gs The semiconductor surface of the base layer 32, which is in contact with the gate oxide film 61, experiences strong reversal, resulting in a high electron carrier concentration and the formation of an n-type reversal layer. Consequently, the emitter layer 33 and the drift layer 4 are connected via the n-type reversal layer, allowing electron carriers to be injected from the emitter layer 33 into the drift layer 4. Electrons are injected from the emitter electrode 73 into the drift layer 4 via the emitter layer 33 and the electron channel, while holes are injected from the collector layer 5, causing conductivity modulation. The resistance of the drift layer 4 decreases due to the accumulation of multiple carriers, and the semiconductor device 1 becomes conductive. Particularly in the first region Hc, holes are injected at a high concentration from the high-concentration carrier layer 51, resulting in a high concentration of accumulated carriers. On the other hand, in the regions Hs and Ts where the low-concentration carrier layer 52 is provided, the accumulated carrier concentration is sufficiently low compared to the first region Hc.

[0057] At time t1, only the first gate electrode 21 is turned off and biased to a voltage lower than the threshold voltage (Vth), while the second gate electrode 22 remains on. Figure 7B The carrier distribution during the low conduction period (switching preparation period) of semiconductor device 1 is conceptually illustrated.

[0058] During switch preparation t pre_off This period is from the time the first gate electrode 21 is turned off until the second gate electrode 22 is turned off. Since the first gate electrode 21 is turned off, no n-type inversion layer is formed in the first region Hc and the third region Ts, and the injection of electrons from the emitter electrode 73 into the drift layer 4 stops. Therefore, the accumulated holes are discharged through the base layer 32 to the emitter electrode 73, and furthermore, the accumulated holes and electrons annihilate each other through recombination, thus reducing the accumulated carrier concentration. On the other hand, in the second region Hs, only the second gate electrode 22 is in the conducting state; therefore, as described above, during the high conduction period, the accumulated carrier concentration is low, but even lower.

[0059] At time t2, the second gate electrode 22 is also turned off, biased to a voltage lower than the threshold voltage (Vth). Thus, the semiconductor device 1 transitions to the turn-off operation. During the switching preparation period t... pre_offThe accumulated carrier concentration in the first region Hc and the third region Ts, especially in the first region Hc, is sufficiently low. In addition, the accumulated carrier concentration in the second region Hs is sufficiently low. Therefore, the depletion rate of the drift layer 4 during turn-off, i.e., the increase rate of the collector voltage (dV / dt), becomes high, and the tail current during turn-off of the semiconductor device 1 is reduced. As a result, the switching loss (turn-off loss) is reduced.

[0060] Here, a comparison is made between the semiconductor device of the present invention and an existing semiconductor device (IGBT) in which the first region Hc and the second region Hs are adjacent without the third region Ts. Figure 8 This is a diagram conceptually representing the carrier distribution during the low conductivity period of a conventional semiconductor device. During the low conductivity period, in the region where the first gate electrode 21 is disposed in the first region Hc and the adjacent second region Hs, the distribution is similar to that of the present invention (…). Figure 7B Similarly, without the injection of holes from the collector layer 5, the accumulated carriers during conduction are annihilated through the recombination of holes and electrons, reducing their size over time. However, in the region of the second region Hs where the second gate electrode 22 is located, as during high conduction, electrons are injected from the emitter layer 33 into the drift layer 4, and consequently, a certain amount of holes are continuously injected from the collector layer 5, particularly from the high-concentration carrier layer 51 near the second region Hs. As a result, especially in region 4b near the boundary between the first region Hc and the second region Hs, the accumulated carriers cannot be sufficiently reduced and remain. The accumulated carriers remaining in region 4b near the boundary cause an increase in tail current when the IGBT is turned off, resulting in an increase in switching losses (turn-off losses).

[0061] In this embodiment, the semiconductor device 1 is in the switching preparation period t pre_off In, such as Figure 7B As shown, some of the holes that accumulate and remain at a high concentration in the first region Hc sometimes move and accumulate in the region near the boundary between the second region Hs and the third region Ts, as indicated by reference numeral 4b, through the second gate electrode 22, which remains in a conducting state in the second region Hs. However, the nearest second gate electrode 22 from the first region Hc to the second region Hs has a sufficient distance through the third region Ts, so the number of carriers accumulated in region 4b is sufficiently small. Similarly, regarding the third region Ts adjacent to the second region Hs, since the concentration of accumulated carriers during high conduction is sufficiently low, the number of carriers accumulated in region 4b is also sufficiently small. As a result, the tail current generated by the accumulated carriers in region 4b during turn-off is sufficiently small, preventing an increase in switching losses (turn-off losses).

[0062] Furthermore, by providing an emitter layer 33 in the third region Ts, just like in regions Hc and Hs, the semiconductor device 1 allows electrons to be injected into the drift layer 4 from the emitter layer 33 via an electron channel in the third region Ts during conduction. Therefore, the high-concentration carrier layer 51 in the adjacent first region Hc injects holes, causing conductivity modulation, and the resistance of the drift layer 4 decreases due to the accumulation of multiple carriers. As a result, compared to a structure where there is no emitter layer 33 in the third region Ts, or in other words, where the distance between the first region Hc and the second region Hs is only provided by the floating layer 31, the conduction loss (conduction voltage) is reduced.

[0063] As described above, the semiconductor device according to this embodiment improves the turn-off tolerance without increasing conduction loss and switching loss by setting the collector layer 5 as a low-concentration carrier layer 52 and setting the third region Ts having the first gate electrode 21 and the emitter layer 33 between the first region Hc and the second region Hs.

[0064] The appropriate length of the third region Ts is explained. If the third region Ts is long enough, and the distance from the first region Hc to the second region Hs is long enough, the improvement in turn-off cutoff capacity is significant. However, if the third region Ts, with its low carrier concentration, is long and occupies a large proportion of the chip, the conduction loss (conduction voltage) will increase. Figure 9 This illustrates the turn-off loss E of an IGBT based on semiconductor device simulation. off A graph illustrating the relationship between the length Δ of the third region and the thickness D of the IGBT's drift layer. The turn-off loss E generated in the third region Ts. off (Ts) is relative to the turn-off loss E generated in the entire chip (active regions: first region Hc, second region Hs, and third region Ts). off The scale is set as the vertical axis. Figure 9 The diagram shows the dependence of the length Δ of the third region on the ratio (Δ / D) of the drift layer thickness D, which accounts for the proportion of the turn-off loss generated in the third region Ts. Furthermore, in the simulation, the length Δ of the third region was varied using a driver with the following settings: drift layer thickness D and resistivity ρ. Additionally, in this simulation, the turn-off loss E is set to... off The minimum switch preparation period t pre_off .

[0065] 6.5kV device: D=630μm, ρ=550Ωcm, t pre_off =70μs

[0066] 3.3kV device: D = 350μm, ρ = 250Ωcm, t pre_off =30μs

[0067] 1.2kV device: D=120μm, ρ=55Ωcm, t pre_off =10μs

[0068] like Figure 9 As shown, regardless of the IGBT's rated withstand voltage, increasing Δ / D further suppresses the increase in switching losses (turn-off losses). This is because during the IGBT's switching preparation period t... pre_off In the process, the accumulated carriers remaining near the boundary between the first region Hc and the second region Hs, the larger the Δ / D, the more they are suppressed by ensuring the distance between the first region Hc and the second region Hs, preventing the increase of tail current when the IGBT is turned off. As a result, the turn-off loss generated in the third region can be reduced.

[0069] according to Figure 9 The results show that the minimum length Δ of the third region Ts required to suppress the turn-off loss generated in the third region Ts to less than 5% relative to the generation in the entire active region is obtained. min The relationship between the thickness D of the drift layer and the a, b, and c of the drift layer is given by equation (1′). This relationship can be expressed by equation (1′). In equation (1′), a, b, and c are constants determined by the device design. Figure 10 The curve shown represents this.

[0070] [Mathematical Expression 1]

[0071]

[0072] (a, b, and c are constants. 0) <c≤1)

[0073] Besides the drift layer thickness D, another factor determining the rated withstand voltage of an IGBT is the resistivity ρ of the drift layer. This can be replaced by substituting D on the right-hand side of equation (1′) to form equation (2′). Equation (2′) can... Figure 10 The horizontal axis of the curve shown is replaced with ρ.

[0074] [Mathematical Expression 2]

[0075]

[0076] (a, b, and c are constants. 0) <c≤1)

[0077] Equations (1′) and (2′) can be respectively expressed as Equation (1) and Equation (2).

[0078] [Mathematical Expression 3]

[0079]

[0080] (a, b, c are constants. 0) <c≤1)

[0081] When the third region Ts of semiconductor device 1 is relatively long, the conduction loss (conduction voltage) increases. In order to suppress this situation, when the upper limit of Δ / D is determined in the semiconductor device simulation, as shown in the following formula (3), the gate length direction length Δ of the third region Ts is preferably less than 3 times the thickness D of the drift layer 4.

[0082] [Formula 4]

[0083]

[0084] By appropriately varying the length Δ of the third region Ts according to the thickness D or resistivity ρ of the drift layer 4, the increase in switching losses and the turn-off breaking capacity can be universally suppressed regardless of the rated withstand voltage of the IGBT.

[0085] (Modified example)

[0086] The semiconductor device 1 can have a collector layer 5 comprising a high-concentration carrier layer 51 and a low-concentration carrier layer 52 configured as follows. For example... Figure 11 As shown, the semiconductor device 1 can form a low-concentration carrier layer 52 by alternately and intermittently arranging a high-concentration carrier layer 51 and a low-concentration carrier layer 52a. In this modified example, by locally forming a region with a high carrier concentration in the low-concentration carrier layer 52, the back-side electric field of the semiconductor device 1 during a short circuit is reduced, which can relatively improve the short-circuit withstand capability and improve reliability. Such a collector layer 5 is the same as in the above embodiment, capable of handling n... - After irradiating the entire back surface of a semiconductor substrate with a low concentration of p-type impurities, a region is left open to become a high-concentration carrier layer 51. A mask with multiple holes is then formed in the region becoming a low-concentration carrier layer 52, and irradiated with high-concentration p-type impurities to create this layer. The arrangement pattern of the alternating high-concentration carrier layers 51 in the low-concentration carrier layer 52 is not particularly defined; for example, it can be formed by a mesh mask, or it can be a stripe pattern arranged alternately and intermittently only in one dimension. Furthermore, the length (diameter) of each of the alternating high-concentration carrier layers 51 in the low-concentration carrier layer 52 is preferably set to a range of 0.01 to 1 times the thickness D of the drift layer 4. Sufficiently long lengths of the alternating high-concentration carrier layers 51 reduce the on-state voltage; conversely, excessive lengths reduce the improvement in turn-off withstand capability.

[0087] Semiconductor device 1 can also selectively suppress the lifetime of charge carriers in a specific region. In this case, it is preferable to suppress the lifetime of charge carriers in the third region Ts. With such a structure, during the switching preparation period t pre_offIn this process, the accumulated carriers remaining near the boundaries of the first region Hc and the second region Hs, which are adjacent to the third region Ts, are effectively reduced. As a result, current concentration during turn-off at the boundary is suppressed, localized heating in that area is reduced, and consequently, the turn-off tolerance is improved more effectively. Such a semiconductor device 1... Figure 12 As shown, from n - The back or surface of the semiconductor substrate is irradiated with light ions or electron beams through an absorber that leaves a third region Ts empty, forming crystal defects in the drift layer 4 and thus becoming a carrier lifetime suppression layer 41.

[0088] Semiconductor device 1 can also suppress the lifetime of carriers in a portion or all of the second region Hs together with the third region Ts. Specifically, this refers to the region of the second region Hs where the second gate electrode 22 is formed, or the entire region of the second region Hs. With this structure, during the switching preparation period t... pre_off This not only suppresses the accumulated carriers remaining in the third region Ts, but also suppresses the accumulated carriers remaining in the second region Hs, thus more effectively suppressing turn-off losses. In particular, during the switch preparation period t... pre_off By selectively suppressing only a portion of the second gate electrode 22 that is the primary cause of increased turn-off losses due to electron injection (= during the switch preparation period t), the lifetime of that portion is reduced. pre_off The portion of the first gate electrode 21 that does not inject electrons does not suppress lifetime, thus more effectively suppressing turn-off losses and preventing the drawback of increased on-state voltage caused by reduced lifetime of the portion of the first gate electrode 21.

[0089] like Figure 13 As shown, the semiconductor device 1 can also be configured with two or more regions Hc, Hs, and Ts, with a third region Ts disposed between the first region Hc and the second region Hs. In particular, by separately distributing the first region Hc at two or more locations on the chip, temperature uniformity within the chip can be achieved. When the semiconductor device 1 is turned on, holes injected from the collector layer 5 are injected particularly frequently from the high-concentration carrier layer 51, so the first region Hc becomes the primary source of heat reduction in the semiconductor device 1. Furthermore, to improve turn-off tolerance, it is preferable to place the first region Hc near the outer periphery of the chip, compared to the second region Hs. For example, the regions can be arranged in the following order: first region Hc - third region Ts - second region Hs - third region Ts - first region Hc - third region Ts - second region Hs - third region Ts - first region Hc.

[0090] This invention is not limited to the embodiments described above. Other modifications and applications are included as long as they do not depart from the spirit of the invention as set forth in the claims. For example, the embodiments described above are detailed to aid in understanding the invention and are not limited to having all the described structures. Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can be added to the structure of one embodiment. Additionally, regarding a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0091] Symbol Explanation

[0092] 100: Motor control system; 1: Semiconductor device; 21: First gate electrode (first gate); 22: Second gate electrode (second gate); 32: Base layer; 33: Emitter layer; 4: Drift layer; 41: Carrier lifetime suppression layer; 5: Collector layer; 51: High-concentration carrier layer; 52: Low-concentration carrier layer; Hc: First region; Hs: Second region; Ts: Third region.

Claims

1. A semiconductor device comprising: a collector layer; a drift layer stacked on the collector layer; a base layer stacked on the drift layer; a first gate disposed side-by-side on the drift layer along a gate length direction; and a second gate capable of being driven independently of the first gate and disposed side-by-side with a portion of the first gate, characterized in that... The system is divided into a first region and a third region, and a second region, which is configured with the first gate and the second gate, such that the third region is disposed between the first region and the second region along the gate length direction. Each of the first region, the second region, and the third region has one or more of these regions. The base layers are respectively disposed in the first region, the second region, and the third region, respectively. In the collector layer, the carrier concentration in the second region and the third region is lower than the carrier concentration in the first region.

2. The semiconductor device according to claim 1, characterized in that, In the gate length direction, there is a repeating structure in the order of the first region, the third region, the second region, the third region, and the first region.

3. The semiconductor device according to claim 1 or 2, characterized in that, It also has: An emitter layer, which is stacked on the base layer, is adjacent to the first gate or the second gate through a gate oxide film. In a direction orthogonal to the gate length direction when viewed from above, the emitter layer is discontinuously disposed at a predetermined period, and the first region and the second region are below the third region in terms of the ratio of the length of the emitter layer to the period.

4. The semiconductor device according to claim 1 or 2, characterized in that, The first gate in the second region and the gate in the second gate that is closest to the third region are the first gate.

5. The semiconductor device according to claim 1 or 2, characterized in that, The length of the gate length direction of the third region depends on at least one of the thickness and resistivity of the drift layer.

6. The semiconductor device according to claim 5, characterized in that, The length Δ of the gate length direction of the third region satisfies equation (1) with the thickness D of the drift layer as a variable, or equation (2) with the thickness D of the drift layer and the resistivity ρ as variables. [Mathematical Expression 5] Where a, b, and c are constants, 0 <c≤1。 7. The semiconductor device according to claim 5, characterized in that, The length of the third region along the gate length direction is less than three times the thickness of the drift layer.

8. The semiconductor device according to claim 1 or 2, characterized in that, In the third region, or further in the region of the second region where at least the second gate is disposed, a carrier lifetime suppression layer is provided within the drift layer.

9. The semiconductor device according to claim 1 or 2, characterized in that, The collector layers in the second region and the third region are formed by alternating and repeatedly configuring two regions with different carrier concentrations.

10. A power conversion device, characterized in that, have: The semiconductor device according to claim 1 or 2.

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