Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a planarization layer, an anode layer including a plurality of anodes on the planarization layer, a pixel definition layer on a side of the anode layer distal to the planarization layer, and a plurality of isolation trenches extending into the planarization layer. The array substrate also includes a display area. A first side, a second side, a third side, and a fourth side surround the display area. The first side is opposite the second side. The third side is opposite the fourth side. The array substrate also includes an integrated circuit on the second side relative to the display area. An isolation trench of the plurality of isolation trenches is on the second side relative to a respective anode of the plurality of anodes.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] With continuous advancements in performance, efficiency, and user experience, display technology has become the cornerstone of modern electronic devices. As devices evolve, there is an increasing expectation for display panels to deliver superior brightness, consistent color accuracy, and optimized power consumption across a wide range of applications, including smartphones, televisions, and wearables. To meet these demands, sophisticated panel architectures and material innovations are utilized, combined with technologies that enable precise control over light emission, pixel alignment, and visual uniformity. These developments aim to achieve high-resolution images, extended lifespan, and seamless integration with evolving device functionalities. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate comprising: a planarization layer; an anode layer including a plurality of anodes located on the planarization layer; a pixel defining layer located on a side of the anode layer away from the planarization layer; and a plurality of isolation trenches extending into the planarization layer; wherein the array substrate further comprises a display area; wherein a first side, a second side, a third side, and a fourth side surround the display area; the first side is opposite to the second side; and the third side is opposite to the fourth side; wherein the array substrate further comprises an integrated circuit located on the second side relative to the display area; wherein an isolation trench among the plurality of isolation trenches is located on the second side relative to a corresponding anode among the plurality of anodes.

[0004] Optionally, the isolation groove divides a portion of the pixel-defining layer between two adjacent sub-pixels into a first portion and a second portion.

[0005] Optionally, along a plane intersecting the two adjacent sub-pixels, the isolation slot, the first portion, and the second portion; the first portion has a first width; the second portion has a second width; and the second width is greater than the first width.

[0006] Optionally, the first portion has a first thickness relative to the surface of the anode layer, and the second portion has a second thickness; and the second thickness is greater than the first thickness.

[0007] Optionally, the corresponding sub-pixel opening of the corresponding sub-pixel is at least partially surrounded by the first portion on one side and at least partially surrounded by the second portion on the other side; the first portion is at least located on the second side of the corresponding sub-pixel opening; the second portion is at least located on the first side of the corresponding sub-pixel opening; and the second portion surrounds the combination of the isolation groove, the first portion, and the corresponding sub-pixel opening.

[0008] Optionally, a portion of the pixel defining layer is located at least partially within one of the plurality of isolation slots.

[0009] Optionally, the pixel defining layer includes: a plurality of first portions spaced apart from each other, the plurality of first portions including the first portions; and a second portion, which is an integral structure; wherein the second portion is located at least on the first side of each of at least a plurality of sub-pixel openings in the plurality of sub-pixel openings; and the plurality of first portions are located at least on the second side of each of the at least a plurality of sub-pixel openings.

[0010] Optionally, the isolation slots in the plurality of isolation slots space out a corresponding first portion of the plurality of first portions from the second portion; and the corresponding first portion space out a corresponding sub-pixel opening of the plurality of sub-pixel openings from the isolation slots.

[0011] Optionally, at least a portion of the corresponding sub-pixel opening has a rectangular shape, the rectangular shape having a first edge, a second edge connected to the first edge, a third edge connected to the second edge, and a fourth edge connected to the third edge and connected to the first edge; the first edge is opposite to the third edge; the second edge is opposite to the fourth edge; the first portion at least partially surrounds the first edge and the second edge; and the second portion at least partially surrounds the third edge and the fourth edge.

[0012] Optionally, the first corner between the first edge and the second edge is located on the second side of the corresponding sub-pixel opening; the second corner between the third edge and the fourth edge is located on the first side of the corresponding sub-pixel opening; the third corner between the first edge and the fourth edge is located on the third side of the corresponding sub-pixel opening; and the fourth corner between the second edge and the third edge is located on the fourth side of the corresponding sub-pixel opening.

[0013] Optionally, the first portion has an L-shaped shape; and the isolation groove has an L-shaped shape.

[0014] Optionally, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein, the first sub-pixel opening of the first sub-pixel is spaced apart by a first shortest distance from the first nearest isolation groove; the second sub-pixel opening of the second sub-pixel is spaced apart by a second shortest distance from the second nearest isolation groove; the third sub-pixel opening of the third sub-pixel is spaced apart by a third shortest distance from the third nearest isolation groove; the first shortest distance is greater than the second shortest distance; and the third shortest distance is greater than the second shortest distance.

[0015] Optionally, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein, the first sub-pixel opening of the first sub-pixel is spaced apart from the first nearest isolation groove; the second sub-pixel opening of the second sub-pixel is spaced apart from the second nearest isolation groove; the third sub-pixel opening of the third sub-pixel is spaced apart from the third nearest isolation groove; and the shape of the second nearest isolation groove is different from that of the first nearest isolation groove and different from that of the third nearest isolation groove.

[0016] Optionally, the first closest isolation groove has an L-shaped shape, wherein the width of the first closest isolation groove is substantially uniform; the third closest isolation groove has an L-shaped shape, wherein the width of the third closest isolation groove is substantially uniform; and the second closest isolation groove has an L-shaped shape, wherein the width of the second closest isolation groove gradually decreases relative to each arm of the L-shape from the position where the two arms are joined together to the end of each arm.

[0017] Optionally, the second closest isolation groove includes a first arm and a second arm connected to each other; the width of the first arm gradually decreases from the position where the first arm and the second arm are connected to the end of the first arm; and the width of the second arm gradually decreases from the position where the first arm and the second arm are connected to the end of the second arm.

[0018] Optionally, the first closest isolation groove has an L-shaped shape, wherein the width of the first closest isolation groove is substantially uniform; the third closest isolation groove has an L-shaped shape, wherein the width of the third closest isolation groove is substantially uniform; and the second closest isolation groove has an L-shaped shape, wherein the portion where the two arms of the L-shape are joined together has an increased width.

[0019] Optionally, the second closest isolation groove includes a first arm, a second arm, and a connecting portion connected to each other; the first arm is connected to the connecting portion; the second arm is connected to the connecting portion; the width of the connecting portion is greater than the width of the first arm and greater than the width of the second arm; and the connecting portion has a triangular shape.

[0020] Optionally, the array substrate further includes a plurality of spacers; wherein, one of the plurality of spacers is located on the first side of the second sub-pixel opening.

[0021] Optionally, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein, the first sub-pixel opening of the first sub-pixel is spaced apart from a first nearest isolation groove; the second sub-pixel opening of the second sub-pixel is spaced apart from a second nearest isolation groove; the third sub-pixel opening of the third sub-pixel is spaced apart from a third nearest isolation groove; and the spacer among the plurality of spacers is located on the second portion adjacent to the second sub-pixel opening.

[0022] In another aspect, this disclosure provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This illustrates the crosstalk phenomenon in the light-emitting layer of the relevant display panel.

[0025] Figure 2 This is a schematic diagram illustrating an array substrate according to some embodiments of the present disclosure.

[0026] Figure 3 The anode is shown as not tilted relative to the second direction.

[0027] Figure 4 The anode is shown tilted relative to the second direction.

[0028] Figure 5 The tilt of the anode in the red subpixel is shown.

[0029] Figure 6 This shows the tilt of the anode in the green subpixel.

[0030] Figure 7 This shows the tilt of the anode in the blue sub-pixel.

[0031] Figure 8The anodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel along the first direction are shown.

[0032] Figure 9 The anodes of the first, second, and third sub-pixels along the second direction are shown.

[0033] Figure 10 These are microscopic images of a portion of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 11 These are microscopic images of a portion of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 12 Multiple anodes in an array substrate are shown, without isolation pillars.

[0036] Figure 13 The array substrate shows multiple anodes and multiple isolation pillars.

[0037] Figure 14 The array substrate shows multiple anodes and multiple isolation trenches.

[0038] Figure 15 The array substrate shows multiple anodes and multiple isolation trenches.

[0039] Figure 16 The array substrate shows multiple anodes and multiple isolation trenches.

[0040] Figure 17 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 18 It is along Figure 16 A cross-sectional view of line A-A' in the diagram.

[0042] Figure 19 yes Figure 16 An enlarged view of a portion of the array substrate shown.

[0043] Figure 20 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0044] Figure 21 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown.

[0045] Figure 22 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0046] Figure 23 The array substrate shows multiple anodes and multiple isolation trenches.

[0047] Figure 24 It is along Figure 23 A cross-sectional view of line B-B' in the diagram.

[0048] Figure 25 yes Figure 23 An enlarged view of a portion of the array substrate shown.

[0049] Figure 26 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 27 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown.

[0051] Figure 28 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0052] Figure 29 The structure of the second closest isolation trench in an array substrate according to some embodiments of the present disclosure is shown.

[0053] Figure 30 The array substrate shows multiple anodes and multiple isolation trenches.

[0054] Figure 31 It is along Figure 30 A cross-sectional view of line C-C' in the diagram.

[0055] Figure 32 yes Figure 30 An enlarged view of a portion of the array substrate shown.

[0056] Figure 33 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0057] Figure 34 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown.

[0058] Figure 35 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0059] Figure 36The structure of the second closest isolation trench in an array substrate according to some embodiments of the present disclosure is shown.

[0060] Figure 37 The array substrate shows multiple anodes and multiple isolation trenches.

[0061] Figure 38 It is along Figure 37 A cross-sectional view of the D-D' line in the diagram.

[0062] Figure 39 yes Figure 37 An enlarged view of a portion of the array substrate shown.

[0063] Figure 40 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure.

[0064] Figure 41 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown.

[0065] Figure 42 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0066] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0067] Mobile phone products have adopted Low-Temperature Polycrystalline Oxide (LTPO) technology and in-panel fan-out (FIP) technology, combined with tandem organic light-emitting diode (OLED) technology. However, both technologies have inherent drawbacks. Tandem OLED technology is susceptible to crosstalk in the light-emitting layer due to the influence of the common organic material layer. Figure 1 This illustrates crosstalk in the light-emitting layer of the relevant display panel. (Refer to...) Figure 1 The arrows indicate areas where crosstalk occurs in the emissive layer. This defect arises due to insufficient isolation between sub-pixels within the emissive layer. Furthermore, dense wiring beneath the anode in the relevant display panel causes incomplete asymmetry, thus limiting the leveling of the planarization layer beneath the anode. This results in uneven anode tilt, causing visually asymmetrical color shifts.

[0068] In relevant display panels (e.g., LTPO and FIP implementations), the main problem is color shift asymmetry along the vertical direction. By comparing the symmetry of the color shift trajectory along the left-right direction, the root cause is identified: in the vertical direction, the tilt direction of the green sub-pixel's annode is inconsistent with the tilt direction of the red or blue sub-pixel's annode. This results in different brightness attenuation trends on both sides of the green sub-pixel's annode in the vertical direction compared to the red and blue sub-pixels, leading to a larger trajectory offset towards the annode of the upper green sub-pixel.

[0069] For tandem organic light-emitting diode (OLED) products, the inventors of this disclosure have discovered that isolation trenches around the edges of subpixels block the common light-emitting layer and reduce crosstalk. In one example, isolation pillars are used on all four sides of the subpixel to reduce crosstalk. However, this does not resolve color shift asymmetry. The inventors of this disclosure have also discovered that single-sided isolation trenches are more effective at reducing crosstalk. However, a right-sided single-sided isolation trench affects the thickness and tilt angle of the pixel-defining layer located on one side of the subpixel, further exacerbating color shift asymmetry in the left-right direction.

[0070] Figure 2 This is a schematic diagram illustrating an array substrate according to some embodiments of the present disclosure. Reference Figure 2 In some embodiments, the array substrate has a first side S1, a second side S2 opposite to the first side S1, a third side S3, and a fourth side S4 opposite to the third side S3. The third side S3 is located between the first side S1 and the second side S2. The fourth side S4 is located between the first side S1 and the second side S2. The third side S3 connects the first side S1 and the second side S2. The fourth side S4 connects the first side S1 and the second side S2. A first direction DR1 is located between the first side S1 and the second side S2. A second direction DR2 is located between the third side S3 and the fourth side S4.

[0071] In the relevant array substrate, the anode exhibits good uniformity along the second direction DR2 (between the third side S3 and the fourth side S4), but has a significant tilt along the first direction DR1 (between the first side S1 and the second side S2). Figure 3 The anode is shown as not tilted relative to the second direction. Figure 4 The anodes are shown tilted relative to the second direction. In one example, the anode of the green sub-pixel is tilted towards the first side S1. In another example, the anodes of the red and blue sub-pixels are tilted towards the second side S2. The anode tilting results in inconsistent light output on both sides of the pixel-defining layer, causing the brightness attenuation on the tilted side to be less than the brightness attenuation on the opposite side when viewed from a wide angle. Figure 5 This shows the tilt of the anode in the red subpixel. (Refer to...) Figure 5 The anode in the red sub-pixel is tilted toward the second side S2. Figure 6 This shows the tilt of the anode in the green subpixel. (See reference) Figure 6 The anode in the green sub-pixel is tilted toward the first side S1. Figure 7 This shows the tilt of the anode in the blue sub-pixel. (See reference) Figure 7 The anode in the blue sub-pixel is tilted toward the second side S2.

[0072] Figure 8 The anodes of the first, second, and third sub-pixels along the first direction are shown. (Refer to...) Figure 8 Along the first direction DR1 (between the first side S1 and the second side S2), the side of the second sub-pixel (e.g., the green sub-pixel) with an anodizing tendency (e.g., the first side S1) is opposite to the side of the first sub-pixel (e.g., the red sub-pixel) with an anodizing tendency (e.g., the second side), and is opposite to the side of the third sub-pixel (e.g., the blue sub-pixel) with an anodizing tendency (e.g., the second side).

[0073] Table 1 shows the brightness attenuation on the first and second sides of the first, second, and third sub-pixels.

[0074]

[0075] As shown in Table 1, for the first sub-pixel, the luminance attenuation on the first side is greater than that on the second side; for the third sub-pixel, the luminance attenuation on the first side is greater than that on the second side. However, for the second sub-pixel, the luminance attenuation on the first side is less than that on the second side. The luminance ratio of the second sub-pixel is higher on the first side, causing the trajectory on the first side to shift more towards the direction of the color of the light emitted by the second sub-pixel (e.g., towards green light).

[0076] Figure 9 The anodes of the first, second, and third sub-pixels along the second direction are shown. (Refer to...) Figure 9 Along the second direction DR2 (between the third side S3 and the fourth side S4), the anodes of the first sub-pixel (e.g., the red sub-pixel), the second sub-pixel (e.g., the green sub-pixel), and the third sub-pixel (e.g., the blue sub-pixel) are tilted toward the same side (e.g., the fourth side).

[0077] Table 2 shows the brightness attenuation on the third and fourth sides of the first, second, and third sub-pixels.

[0078]

[0079] As shown in Table 2, for the first sub-pixel, the brightness attenuation on the fourth side is greater than that on the third side; for the second sub-pixel, the brightness attenuation on the fourth side is greater than that on the third side; and for the third sub-pixel, the brightness attenuation on the fourth side is greater than that on the third side. The brightness ratio of the first, second, and third sub-pixels is higher on the fourth side.

[0080] In a series organic light-emitting diode array substrate, an isolation trench or isolation pillar is included to prevent crosstalk caused by the common light-emitting layer of the series organic light-emitting diode array substrate.

[0081] Figure 10 These are microscopic images of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 10 In a portion of the array substrate without isolation pillars (e.g., on one side of a subpixel), the pixel defining layer (PDL) has a relatively large thickness and a relatively large tilt angle α1.

[0082] Figure 11 These are microscopic images of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 11 In the portion of the array substrate containing multiple isolation pillars IP (e.g., on one side of a sub-pixel), the pixel defining layer PDL has a relatively small thickness and a relatively small tilt angle α2.

[0083] In a correlated array substrate with relatively small color shift values ​​on the third and fourth sides, adding an isolation pillar on the fourth side (e.g., the right side) of the sub-pixel produces a variation consistent with prediction. On the side with the isolation pillar (e.g., the fourth side or the right side), the thickness of the pixel-defining layer is reduced, and the tilt angle of the pixel-defining layer is reduced by more than 10 degrees. This increases the light output over a wide viewing angle and reduces the brightness attenuation on the fourth side (e.g., the right side). However, in a correlated array substrate with originally good color shift symmetry relative to the third and fourth sides, this design leads to a deterioration of color shift symmetry without changing the anode uniformity, resulting in an increase in color shift values ​​relative to the third and fourth sides.

[0084] Figure 12 Multiple anodes in an array substrate are shown, without isolation pillars. (See reference...) Figure 12 The array substrate includes a first anode AD1 for a first sub-pixel, a second anode AD2 for a second sub-pixel, and a third anode AD3 for a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0085] Figure 13 This illustrates multiple anodes and multiple isolation pillars in the array substrate. (See reference...) Figure 13The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation pillars IP. Each isolation pillar of the plurality of isolation pillars IP is located on a fourth side S4 relative to a corresponding anode of the plurality of anodes.

[0086] Table 3 shows... Figure 12 and Figure 13 The tilt angle of the pixel definition layer adjacent to the first sub-pixel, the second sub-pixel, and the third sub-pixel in the array substrate shown.

[0087]

[0088]

[0089] As shown in Table 3, Figure 12 In the array substrate shown, the tilt angles relative to the corresponding anodes on the fourth and third sides are not significantly different from each other. Figure 13 In the array substrate shown, the tilt angle of the fourth side is much smaller than that of the third side.

[0090] Table 4 lists Figure 12 and Figure 13 The difference between the brightness attenuation on the third side and the brightness attenuation on the fourth side of the array substrate shown.

[0091]

[0092] As shown in Table 4, for the first and third sub-pixels, the difference between the brightness attenuation on the third side and the brightness attenuation on the fourth side is relatively small. For Figure 12 In the array substrate shown, the difference between the brightness attenuation on the third side and the brightness attenuation on the fourth side of the second sub-pixel is small. However, for Figure 13 The difference between the brightness attenuation on the third side and the brightness attenuation on the fourth side of the second sub-pixel in the array substrate shown is relatively large.

[0093] Table 5 lists Figure 12 and Figure 13 The color shift values ​​in the array substrate shown.

[0094]

[0095] As shown in Table 5, with Figure 12 Compared to the array substrate shown, Figure 13 The color shift value in the array substrate shown is much higher.

[0096] Figure 14This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 14 The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate also includes a plurality of isolation trenches IG. Each of the plurality of anodes is at least partially surrounded by isolation trenches on all sides. Figure 14 The array substrate shown effectively reduces crosstalk; however, it cannot adequately solve the color shift problem.

[0097] Figure 15 This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 15 The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation trenches IG. Each isolation trench in the plurality of isolation trenches IG is located on a fourth side S4 relative to a corresponding anode in the plurality of anodes. Figure 14 Compared to the array substrate shown, Figure 15 The array substrate shown further reduces crosstalk. However, as mentioned above, compared with... Figure 14 Compared to the array substrate shown, Figure 15 The color shift value in the array substrate shown is much higher.

[0098] Therefore, this disclosure particularly provides an array substrate and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a planarization layer; an anode layer including a plurality of anodes located on the planarization layer; a pixel defining layer located on a side of the anode layer away from the planarization layer; and a plurality of isolation trenches extending into the planarization layer. Optionally, the array substrate also includes a display area. Optionally, a first side, a second side, a third side, and a fourth side surround the display area. Optionally, the first side is opposite to the second side. Optionally, the third side is opposite to the fourth side. Optionally, the array substrate also includes an integrated circuit located on the second side relative to the display area. Optionally, each of the plurality of isolation trenches is located on the second side relative to a corresponding anode of the plurality of anodes.

[0099] Figure 16 This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 16The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation trenches IG. Each isolation trench in the plurality of isolation trenches IG is located on a second side S2 relative to a corresponding anode in the plurality of anodes. The inventors of this disclosure have found, surprisingly and unexpectedly, Figure 16 The array substrate shown achieves excellent color shift symmetry along the first direction DR1 and the second direction DR2. Figure 16 In the array substrate shown, crosstalk is also significantly reduced.

[0100] Figure 17 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, the array substrate includes a display area DA. In some embodiments, the array substrate further includes an integrated circuit (e.g., a flexible printed circuit, FPC) located on a second side S2 relative to the display area DA. Optionally, the array substrate further includes a source drive circuit SDC located on the second side S2 relative to the display area DA. The source drive circuit SDC is configured to provide data signals to the display area DA. In some embodiments, the array substrate further includes a gate drive circuit GOA located on a third side S3 and / or a fourth side S4 relative to the display area DA. Optionally, the second side S2 is opposite to the first side S1. Optionally, the fourth side S4 is opposite to the third side S3. Optionally, the third side S3 is between the first side S1 and the second side S2. Optionally, the fourth side S4 is between the first side S1 and the second side S2. Optionally, the third side S3 is connected to the first side S1 and the second side S2. Optionally, the fourth side S4 is connected to the first side S1 and the second side S2. A first direction DR1 is between the first side S1 and the second side S2. The second direction DR2 is located between the third side S3 and the fourth side S4.

[0101] Figure 18 It is along Figure 16 A cross-sectional view of line A-A' in the diagram. Figure 19 yes Figure 16 An enlarged view of a portion of the array substrate shown. (Refer to...) Figure 16 , Figure 18 and Figure 19In some embodiments, the array substrate includes a substrate BS; a blocking layer BL located on the substrate BS; a plurality of signal lines SL located on the side of the blocking layer BL away from the substrate BS; a planarization layer PLN located on the side of the plurality of signal lines SL away from the substrate BS; an anode layer ADL including a plurality of anodes AD located on the side of the planarization layer PLN away from the substrate BS; a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS; and a light-emitting layer EML including a plurality of light-emitting blocks EL located on the side of the anode layer ADL away from the substrate BS.

[0102] In some embodiments, the array substrate further includes a plurality of isolation trenches IG extending into the planarization layer PLN. Optionally, a portion of the pixel defining layer PDL is at least partially located in the isolation trenches of the plurality of isolation trenches IG. A corresponding isolation trench RIG divides a portion of the pixel defining layer between two adjacent sub-pixels (e.g., sub-pixels sp1 and sp2) into a first portion P1 and a second portion P2.

[0103] In some embodiments, along a plane intersecting two adjacent sub-pixels, the corresponding isolation slot RIG, the first portion P1, and the second portion P2, the first portion P1 has a first width w1, and the second portion P2 has a second width w2. Optionally, the second width w2 is greater than the first width w1.

[0104] In some embodiments, the first portion P1 has a first thickness t1 relative to the surface of the anode layer ADL, and the second portion P2 has a second thickness t2. Optionally, the second thickness t2 is greater than the first thickness t1. The inventors of this disclosure have discovered that by making the second thickness t2 greater than the first thickness t1, the tilt angle of the pixel defining layer can be significantly improved to reduce the amount of light shading of the first portion P1, thereby reducing color shift.

[0105] In some embodiments, the corresponding subpixel opening RSA of each subpixel is at least partially surrounded by a first portion P1 on one side and at least partially surrounded by a second portion P2 on the other side.

[0106] In some embodiments, the first portion P1 is located at least on the second side S2 of the corresponding sub-pixel opening RSA, and the second portion P2 is located at least on the first side S1 of the corresponding sub-pixel opening RSA, with the first side S1 and the second side S2 opposite to each other.

[0107] In some embodiments, the second portion P2 surrounds the combination of the corresponding isolation groove RIG, the first portion P1, and the corresponding sub-pixel opening RSA.

[0108] Figure 20The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure. Figure 21 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown. For illustrative purposes, Figure 21 The pixel-defining layer is indicated by shading. In some embodiments, the pixel-defining layer PDL includes a plurality of first portions (including the first portion P1 described above) spaced apart from each other and a second portion P2 that is an integral structure. In some embodiments, the second portion P2 is located at least on the second side S2 of each of at least a plurality of sub-pixel openings. In some embodiments, the plurality of first portions are located at least on the second side S2 of each of at least a plurality of sub-pixel openings.

[0109] In some embodiments, each isolation slot in the plurality of isolation slots IG spacees a corresponding first portion of the plurality of first portions with a second portion P2. In some embodiments, each first portion spaces a corresponding sub-pixel opening of the plurality of sub-pixel openings with a corresponding isolation slot.

[0110] In some embodiments, reference Figure 19 At least a portion of the corresponding sub-pixel opening RSA has a rectangular shape, the rectangular shape having a first edge E1, a second edge E2 connected to the first edge E1, a third edge E3 connected to the second edge E2, and a fourth edge E4 connected to both the third edge E3 and the first edge E1. Optionally, the first edge E1 is opposite to the third edge E3. Optionally, the second edge E2 is opposite to the fourth edge E4. In some embodiments, a first portion P1 at least partially surrounds the first edge E1 and the second edge E2; a second portion P2 at least partially surrounds the third edge E3 and the fourth edge E4.

[0111] In some embodiments, reference Figure 17 and Figure 19 The first corner between the first edge E1 and the second edge E2 is located on the second side S2 of the corresponding sub-pixel opening RSA; the second corner between the third edge E3 and the fourth edge E4 is located on the first side S1 of the corresponding sub-pixel opening RSA; the third corner between the first edge E1 and the fourth edge E4 is located on the third side S3 of the corresponding sub-pixel opening RSA; and the fourth corner between the second edge E2 and the third edge E3 is located on the fourth side S4 of the corresponding sub-pixel opening RSA.

[0112] In some embodiments, the first portion P1 at least partially surrounds the first edge E1 and the second edge E2. Optionally, the first portion P1 has an L-shaped shape. Optionally, the corresponding isolation groove RIG has an L-shaped shape.

[0113] Figure 22This illustration shows the arrangement of a plurality of first portions, second portions, and a plurality of sub-pixel openings in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 22 In some embodiments, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0114] In some embodiments, the first sub-pixel opening SA1 of the first sub-pixel is spaced apart from the first nearest isolation slot IG1 by a first shortest distance; the second sub-pixel opening SA2 of the second sub-pixel is spaced apart from the second nearest isolation slot IG2 by a second shortest distance; and the third sub-pixel opening SA3 of the third sub-pixel is spaced apart from the third nearest isolation slot IG3 by a third shortest distance. Optionally, the first shortest distance is greater than the second shortest distance. Optionally, the third shortest distance is greater than the second shortest distance. The inventors of this disclosure have found that by making the first shortest distance greater than the second shortest distance and making the third shortest distance greater than the second shortest distance, the color shift problem in the second sub-pixel can be further solved compared with the first sub-pixel and the third sub-pixel.

[0115] Figure 23 This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 23 The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation trenches IG. Each isolation trench in the plurality of isolation trenches IG is located on a second side S2 relative to a corresponding anode in the plurality of anodes. The inventors of this disclosure have found, surprisingly and unexpectedly, Figure 23 The array substrate shown achieves excellent color shift symmetry along the first direction DR1 and the second direction DR2. Figure 23 In the array substrate shown, crosstalk is also significantly reduced.

[0116] Reference Figure 17In some embodiments, the array substrate includes a display area DA. In some embodiments, the array substrate further includes an integrated circuit (e.g., a flexible printed circuit, FPC) located on a second side S2 relative to the display area DA. Optionally, the array substrate further includes a source drive circuit SDC located on the second side S2 relative to the display area DA. The source drive circuit SDC is configured to provide data signals to the display area DA. In some embodiments, the array substrate further includes a gate drive circuit GOA located on a third side S3 and / or a fourth side S4 relative to the display area DA. Optionally, the second side S2 is opposite to the first side S1. Optionally, the fourth side S4 is opposite to the third side S3. Optionally, the third side S3 is between the first side S1 and the second side S2. Optionally, the fourth side S4 is between the first side S1 and the second side S2. Optionally, the third side S3 is connected to the first side S1 and the second side S2. Optionally, the fourth side S4 is connected to the first side S1 and the second side S2. A first direction DR1 is between the first side S1 and the second side S2. The second direction DR2 is located between the third side S3 and the fourth side S4.

[0117] Figure 24 It is along Figure 23 A cross-sectional view of line B-B' in the diagram. Figure 25 yes Figure 23 An enlarged view of a portion of the array substrate shown. (Refer to...) Figure 23 , Figure 24 and Figure 25 In some embodiments, the array substrate includes a substrate BS; a blocking layer BL located on the substrate BS; a plurality of signal lines SL located on the side of the blocking layer BL away from the substrate BS; a planarization layer PLN located on the side of the plurality of signal lines SL away from the substrate BS; an anode layer ADL including a plurality of anodes AD located on the side of the planarization layer PLN away from the substrate BS; a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS; and a light-emitting layer EML including a plurality of light-emitting blocks EL located on the side of the anode layer ADL away from the substrate BS.

[0118] In some embodiments, the array substrate further includes a plurality of isolation trenches IG extending into the planarization layer PLN. Optionally, a portion of the pixel defining layer PDL is at least partially located in the isolation trenches of the plurality of isolation trenches IG. A corresponding isolation trench RIG divides a portion of the pixel defining layer between two adjacent sub-pixels (e.g., sub-pixels sp1 and sp2) into a first portion P1 and a second portion P2.

[0119] In some embodiments, along a plane intersecting two adjacent sub-pixels, the corresponding isolation slot RIG, the first portion P1, and the second portion P2, the first portion P1 has a first width w1, and the second portion P2 has a second width w2. Optionally, the second width w2 is greater than the first width w1.

[0120] In some embodiments, the first portion P1 has a first thickness t1 relative to the surface of the anode layer ADL, and the second portion P2 has a second thickness t2. Optionally, the second thickness t2 is greater than the first thickness t1. The inventors of this disclosure have discovered that by making the second thickness t2 greater than the first thickness t1, the tilt angle of the pixel defining layer can be significantly improved to reduce the amount of light shading of the first portion P1, thereby reducing color shift.

[0121] In some embodiments, the corresponding subpixel opening RSA of each subpixel is at least partially surrounded by a first portion P1 on one side and at least partially surrounded by a second portion P2 on the other side.

[0122] In some embodiments, the first portion P1 is located at least on the second side S2 of the corresponding sub-pixel opening RSA, and the second portion P2 is located at least on the first side S1 of the corresponding sub-pixel opening RSA, with the first side S1 and the second side S2 opposite to each other.

[0123] In some embodiments, the second portion P2 surrounds the combination of the corresponding isolation groove RIG, the first portion P1, and the corresponding sub-pixel opening RSA.

[0124] Figure 26 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure. Figure 27 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown. For illustrative purposes, Figure 27 The pixel-defining layer is indicated by shading. In some embodiments, the pixel-defining layer PDL includes a plurality of first portions (including the first portion P1 described above) spaced apart from each other and a second portion P2 that is an integral structure. In some embodiments, the second portion P2 is located at least on the second side S2 of each of at least a plurality of sub-pixel openings. In some embodiments, the plurality of first portions are located at least on the second side S2 of each of at least a plurality of sub-pixel openings.

[0125] In some embodiments, each isolation slot in the plurality of isolation slots IG spacees a corresponding first portion of the plurality of first portions with a second portion P2. In some embodiments, each first portion spaces a corresponding sub-pixel opening of the plurality of sub-pixel openings with a corresponding isolation slot.

[0126] In some embodiments, reference Figure 25At least a portion of the corresponding sub-pixel opening RSA has a rectangular shape, the rectangular shape having a first edge E1, a second edge E2 connected to the first edge E1, a third edge E3 connected to the second edge E2, and a fourth edge E4 connected to both the third edge E3 and the first edge E1. Optionally, the first edge E1 is opposite to the third edge E3. Optionally, the second edge E2 is opposite to the fourth edge E4. In some embodiments, a first portion P1 at least partially surrounds the first edge E1 and the second edge E2; a second portion P2 at least partially surrounds the third edge E3 and the fourth edge E4.

[0127] In some embodiments, reference Figure 17 and Figure 25 The first corner between the first edge E1 and the second edge E2 is located on the second side S2 of the corresponding sub-pixel opening RSA; the second corner between the third edge E3 and the fourth edge E4 is located on the first side S1 of the corresponding sub-pixel opening RSA; the third corner between the first edge E1 and the fourth edge E4 is located on the third side S3 of the corresponding sub-pixel opening RSA; and the fourth corner between the second edge E2 and the third edge E3 is located on the fourth side S4 of the corresponding sub-pixel opening RSA.

[0128] In some embodiments, the first portion P1 at least partially surrounds the first edge E1 and the second edge E2. Optionally, the first portion P1 has an L-shaped shape. Optionally, the corresponding isolation groove RIG has an L-shaped shape.

[0129] Figure 28 This illustration shows the arrangement of a plurality of first portions, second portions, and a plurality of sub-pixel openings in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 28 In some embodiments, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0130] In some embodiments, the first sub-pixel opening SA1 of the first sub-pixel is spaced apart from the first nearest isolation slot IG1 by a first shortest distance; the second sub-pixel opening SA2 of the second sub-pixel is spaced apart from the second nearest isolation slot IG2 by a second shortest distance; and the third sub-pixel opening SA3 of the third sub-pixel is spaced apart from the third nearest isolation slot IG3 by a third shortest distance. Optionally, the first shortest distance is greater than the second shortest distance. Optionally, the third shortest distance is greater than the second shortest distance. The inventors of this disclosure have found that by making the first shortest distance greater than the second shortest distance and making the third shortest distance greater than the second shortest distance, the color shift problem in the second sub-pixel can be further solved compared with the first sub-pixel and the third sub-pixel.

[0131] In some embodiments, the shape of the second closest isolation groove IG2 differs from the shape of the first closest isolation groove IG1 and the shape of the third closest isolation groove IG3. In one particular example, the first closest isolation groove IG1 has an L-shaped shape, wherein the width of the first closest isolation groove IG1 is substantially uniform (e.g., within 10% deviation from the average). In one particular example, the third closest isolation groove IG3 has an L-shaped shape, wherein the width of the third closest isolation groove IG3 is substantially uniform (e.g., within 10% deviation from the average). In another example, the second closest isolation groove IG2 has an L-shaped shape, wherein the width of the second closest isolation groove IG2 gradually decreases relative to each arm of the L-shape from the point where the two arms are joined together to the end of each arm.

[0132] Figure 29 The structure of the second closest isolation trench in an array substrate according to some embodiments of the present disclosure is shown. Reference Figure 29 In some embodiments, the second closest isolation groove IG2 includes a first arm AM1 and a second arm AM2 connected to each other. The width of the first arm AM1 gradually decreases from the point where the first arm AM1 and the second arm AM2 are joined together to the end of the first arm AM1. The width of the second arm AM2 gradually decreases from the point where the first arm AM1 and the second arm AM2 are joined together to the end of the second arm AM2.

[0133] Figure 30 This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 30 The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation trenches IG. Each isolation trench in the plurality of isolation trenches IG is located on a second side S2 relative to a corresponding anode in the plurality of anodes. The inventors of this disclosure have found, surprisingly and unexpectedly, Figure 30 The array substrate shown achieves excellent color shift symmetry along the first direction DR1 and the second direction DR2. Figure 30 In the array substrate shown, crosstalk is also significantly reduced.

[0134] Reference Figure 17In some embodiments, the array substrate includes a display area DA. In some embodiments, the array substrate further includes an integrated circuit (e.g., a flexible printed circuit, FPC) located on a second side S2 relative to the display area DA. Optionally, the array substrate further includes a source drive circuit SDC located on the second side S2 relative to the display area DA. The source drive circuit SDC is configured to provide data signals to the display area DA. In some embodiments, the array substrate further includes a gate drive circuit GOA located on a third side S3 and / or a fourth side S4 relative to the display area DA. Optionally, the second side S2 is opposite to the first side S1. Optionally, the fourth side S4 is opposite to the third side S3. Optionally, the third side S3 is between the first side S1 and the second side S2. Optionally, the fourth side S4 is between the first side S1 and the second side S2. Optionally, the third side S3 is connected to the first side S1 and the second side S2. Optionally, the fourth side S4 is connected to the first side S1 and the second side S2. A first direction DR1 is between the first side S1 and the second side S2. The second direction DR2 is located between the third side S3 and the fourth side S4.

[0135] Figure 31 It is along Figure 30 A cross-sectional view of line C-C' in the diagram. Figure 32 yes Figure 30 An enlarged view of a portion of the array substrate shown. (Refer to...) Figure 30 , Figure 31 and Figure 32 In some embodiments, the array substrate includes a substrate BS; a blocking layer BL located on the substrate BS; a plurality of signal lines SL located on the side of the blocking layer BL away from the substrate BS; a planarization layer PLN located on the side of the plurality of signal lines SL away from the substrate BS; an anode layer ADL including a plurality of anodes AD located on the side of the planarization layer PLN away from the substrate BS; a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS; and a light-emitting layer EML including a plurality of light-emitting blocks EL located on the side of the anode layer ADL away from the substrate BS.

[0136] In some embodiments, the array substrate further includes a plurality of isolation trenches IG extending into the planarization layer PLN. Optionally, a portion of the pixel defining layer PDL is at least partially located in the isolation trenches of the plurality of isolation trenches IG. A corresponding isolation trench RIG divides a portion of the pixel defining layer between two adjacent sub-pixels (e.g., sub-pixels sp1 and sp2) into a first portion P1 and a second portion P2.

[0137] In some embodiments, along a plane intersecting two adjacent sub-pixels, the corresponding isolation slot RIG, the first portion P1, and the second portion P2, the first portion P1 has a first width w1, and the second portion P2 has a second width w2. Optionally, the second width w2 is greater than the first width w1.

[0138] In some embodiments, the first portion P1 has a first thickness t1 relative to the surface of the anode layer ADL, and the second portion P2 has a second thickness t2. Optionally, the second thickness t2 is greater than the first thickness t1. The inventors of this disclosure have discovered that by making the second thickness t2 greater than the first thickness t1, the tilt angle of the pixel defining layer can be significantly improved to reduce the amount of light shading of the first portion P1, thereby reducing color shift.

[0139] In some embodiments, the corresponding subpixel opening RSA of each subpixel is at least partially surrounded by a first portion P1 on one side and at least partially surrounded by a second portion P2 on the other side.

[0140] In some embodiments, the first portion P1 is located at least on the second side S2 of the corresponding sub-pixel opening RSA, and the second portion P2 is located at least on the first side S1 of the corresponding sub-pixel opening RSA, with the first side S1 and the second side S2 opposite to each other.

[0141] In some embodiments, the second portion P2 surrounds the combination of the corresponding isolation groove RIG, the first portion P1, and the corresponding sub-pixel opening RSA.

[0142] Figure 33 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure. Figure 34 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown. For illustrative purposes, Figure 34 The pixel-defining layer is indicated by shading. In some embodiments, the pixel-defining layer PDL includes a plurality of first portions (including the first portion P1 described above) spaced apart from each other and a second portion P2 that is an integral structure. In some embodiments, the second portion P2 is located at least on the second side S2 of each of at least a plurality of sub-pixel openings. In some embodiments, the plurality of first portions are located at least on the second side S2 of each of at least a plurality of sub-pixel openings.

[0143] In some embodiments, each isolation slot in the plurality of isolation slots IG spacees a corresponding first portion of the plurality of first portions with a second portion P2. In some embodiments, each first portion spaces a corresponding sub-pixel opening of the plurality of sub-pixel openings with a corresponding isolation slot.

[0144] In some embodiments, reference Figure 32At least a portion of the corresponding sub-pixel opening RSA has a rectangular shape, the rectangular shape having a first edge E1, a second edge E2 connected to the first edge E1, a third edge E3 connected to the second edge E2, and a fourth edge E4 connected to both the third edge E3 and the first edge E1. Optionally, the first edge E1 is opposite to the third edge E3. Optionally, the second edge E2 is opposite to the fourth edge E4. In some embodiments, a first portion P1 at least partially surrounds the first edge E1 and the second edge E2; a second portion P2 at least partially surrounds the third edge E3 and the fourth edge E4.

[0145] In some embodiments, reference Figure 17 and Figure 32 The first corner between the first edge E1 and the second edge E2 is located on the second side S2 of the corresponding sub-pixel opening RSA; the second corner between the third edge E3 and the fourth edge E4 is located on the first side S1 of the corresponding sub-pixel opening RSA; the third corner between the first edge E1 and the fourth edge E4 is located on the third side S3 of the corresponding sub-pixel opening RSA; and the fourth corner between the second edge E2 and the third edge E3 is located on the fourth side S4 of the corresponding sub-pixel opening RSA.

[0146] In some embodiments, the first portion P1 at least partially surrounds the first edge E1 and the second edge E2. Optionally, the first portion P1 has an L-shaped shape. Optionally, the corresponding isolation groove RIG has an L-shaped shape.

[0147] Figure 35 This illustration shows the arrangement of a plurality of first portions, second portions, and a plurality of sub-pixel openings in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 35 In some embodiments, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0148] In some embodiments, the first sub-pixel opening SA1 of the first sub-pixel is spaced apart from the first nearest isolation slot IG1 by a first shortest distance; the second sub-pixel opening SA2 of the second sub-pixel is spaced apart from the second nearest isolation slot IG2 by a second shortest distance; and the third sub-pixel opening SA3 of the third sub-pixel is spaced apart from the third nearest isolation slot IG3 by a third shortest distance. Optionally, the first shortest distance is greater than the second shortest distance. Optionally, the third shortest distance is greater than the second shortest distance. The inventors of this disclosure have found that by making the first shortest distance greater than the second shortest distance and making the third shortest distance greater than the second shortest distance, the color shift problem in the second sub-pixel can be further solved compared with the first sub-pixel and the third sub-pixel.

[0149] In some embodiments, the shape of the second closest isolation groove IG2 differs from the shape of the first closest isolation groove IG1 and the shape of the third closest isolation groove IG3. In one particular example, the first closest isolation groove IG1 has an L-shaped shape, wherein the width of the first closest isolation groove IG1 is substantially uniform (e.g., within 10% deviation from the average). In one particular example, the third closest isolation groove IG3 has an L-shaped shape, wherein the width of the third closest isolation groove IG3 is substantially uniform (e.g., within 10% deviation from the average). In another example, the second closest isolation groove IG2 has an L-shaped shape, wherein the portion where the two arms of the L-shape join together has an increased width.

[0150] Figure 36 The structure of the second closest isolation trench in an array substrate according to some embodiments of the present disclosure is shown. Reference Figure 36 In some embodiments, the second closest isolation groove IG2 includes a first arm AM1, a second arm AM2, and a connecting portion JP connected to each other. The first arm AM1 is connected to the connecting portion JP, and the second arm AM2 is connected to the connecting portion JP. In some embodiments, the width of the connecting portion JP is greater than the width of the first arm AM1 and greater than the width of the second arm AM2. In one example, the connecting portion JP has a triangular shape.

[0151] Figure 37 This shows multiple anodes and multiple isolation trenches in the array substrate. (See reference...) Figure 37 The array substrate includes a first anode AD1 of a first sub-pixel, a second anode AD2 of a second sub-pixel, and a third anode AD3 of a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. In some embodiments, the array substrate further includes a plurality of isolation trenches IG. Each isolation trench in the plurality of isolation trenches IG is located on a second side S2 relative to a corresponding anode in the plurality of anodes. The inventors of this disclosure have found, surprisingly and unexpectedly, Figure 37 The array substrate shown achieves excellent color shift symmetry along the first direction DR1 and the second direction DR2. Figure 37 In the array substrate shown, crosstalk is also significantly reduced.

[0152] Reference Figure 17In some embodiments, the array substrate includes a display area DA. In some embodiments, the array substrate further includes an integrated circuit (e.g., a flexible printed circuit, FPC) located on a second side S2 relative to the display area DA. Optionally, the array substrate further includes a source drive circuit SDC located on the second side S2 relative to the display area DA. The source drive circuit SDC is configured to provide data signals to the display area DA. In some embodiments, the array substrate further includes a gate drive circuit GOA located on a third side S3 and / or a fourth side S4 relative to the display area DA. Optionally, the second side S2 is opposite to the first side S1. Optionally, the fourth side S4 is opposite to the third side S3. Optionally, the third side S3 is between the first side S1 and the second side S2. Optionally, the fourth side S4 is between the first side S1 and the second side S2. Optionally, the third side S3 is connected to the first side S1 and the second side S2. Optionally, the fourth side S4 is connected to the first side S1 and the second side S2. A first direction DR1 is between the first side S1 and the second side S2. The second direction DR2 is located between the third side S3 and the fourth side S4.

[0153] Figure 38 It is along Figure 37 A cross-sectional view of the D-D' line in the diagram. Figure 39 yes Figure 37 An enlarged view of a portion of the array substrate shown. (Refer to...) Figure 37 , Figure 38 and Figure 39 In some embodiments, the array substrate includes a substrate BS; a blocking layer BL located on the substrate BS; a plurality of signal lines SL located on the side of the blocking layer BL away from the substrate BS; a planarization layer PLN located on the side of the plurality of signal lines SL away from the substrate BS; an anode layer ADL including a plurality of anodes AD located on the side of the planarization layer PLN away from the substrate BS; a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS; and a light-emitting layer EML including a plurality of light-emitting blocks EL located on the side of the anode layer ADL away from the substrate BS.

[0154] In some embodiments, the array substrate further includes a plurality of isolation trenches IG extending into the planarization layer PLN. Optionally, a portion of the pixel defining layer PDL is at least partially located in the isolation trenches of the plurality of isolation trenches IG. A corresponding isolation trench RIG divides a portion of the pixel defining layer between two adjacent sub-pixels (e.g., sub-pixels sp1 and sp2) into a first portion P1 and a second portion P2.

[0155] In some embodiments, along a plane intersecting two adjacent sub-pixels, the corresponding isolation slot RIG, the first portion P1, and the second portion P2, the first portion P1 has a first width w1, and the second portion P2 has a second width w2. Optionally, the second width w2 is greater than the first width w1.

[0156] In some embodiments, the first portion P1 has a first thickness t1 relative to the surface of the anode layer ADL, and the second portion P2 has a second thickness t2. Optionally, the second thickness t2 is greater than the first thickness t1. The inventors of this disclosure have discovered that by making the second thickness t2 greater than the first thickness t1, the tilt angle of the pixel defining layer can be significantly improved to reduce the amount of light shading of the first portion P1, thereby reducing color shift.

[0157] In some embodiments, the corresponding subpixel opening RSA of each subpixel is at least partially surrounded by a first portion P1 on one side and at least partially surrounded by a second portion P2 on the other side.

[0158] In some embodiments, the first portion P1 is located at least on the second side S2 of the corresponding sub-pixel opening RSA, and the second portion P2 is located at least on the first side S1 of the corresponding sub-pixel opening RSA, with the first side S1 and the second side S2 opposite to each other.

[0159] In some embodiments, the second portion P2 surrounds the combination of the corresponding isolation groove RIG, the first portion P1, and the corresponding sub-pixel opening RSA.

[0160] Figure 40 The diagram illustrates the arrangement of a plurality of first portions, second portions, and a plurality of subpixel openings in an array substrate according to some embodiments of the present disclosure. Figure 41 The structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure is shown. For illustrative purposes, Figure 41 The pixel-defining layer is indicated by shading. In some embodiments, the pixel-defining layer PDL includes a plurality of first portions (including the first portion P1 described above) spaced apart from each other and a second portion P2 that is an integral structure. In some embodiments, the second portion P2 is located at least on the second side S2 of each of at least a plurality of sub-pixel openings. In some embodiments, the plurality of first portions are located at least on the second side S2 of each of at least a plurality of sub-pixel openings.

[0161] In some embodiments, each isolation slot in the plurality of isolation slots IG spacees a corresponding first portion of the plurality of first portions with a second portion P2. In some embodiments, each first portion spaces a corresponding sub-pixel opening of the plurality of sub-pixel openings with a corresponding isolation slot.

[0162] In some embodiments, reference Figure 39At least a portion of the corresponding sub-pixel opening RSA has a rectangular shape, the rectangular shape having a first edge E1, a second edge E2 connected to the first edge E1, a third edge E3 connected to the second edge E2, and a fourth edge E4 connected to both the third edge E3 and the first edge E1. Optionally, the first edge E1 is opposite to the third edge E3. Optionally, the second edge E2 is opposite to the fourth edge E4. In some embodiments, a first portion P1 at least partially surrounds the first edge E1 and the second edge E2; a second portion P2 at least partially surrounds the third edge E3 and the fourth edge E4.

[0163] In some embodiments, reference Figure 17 and Figure 39 The first corner between the first edge E1 and the second edge E2 is located on the second side S2 of the corresponding sub-pixel opening RSA; the second corner between the third edge E3 and the fourth edge E4 is located on the first side S1 of the corresponding sub-pixel opening RSA; the third corner between the first edge E1 and the fourth edge E4 is located on the third side S3 of the corresponding sub-pixel opening RSA; and the fourth corner between the second edge E2 and the third edge E3 is located on the fourth side S4 of the corresponding sub-pixel opening RSA.

[0164] In some embodiments, the first portion P1 at least partially surrounds the first edge E1 and the second edge E2. Optionally, the first portion P1 has an L-shaped shape. Optionally, the corresponding isolation groove RIG has an L-shaped shape.

[0165] Figure 42 This illustration shows the arrangement of a plurality of first portions, second portions, and a plurality of sub-pixel openings in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 42 In some embodiments, the array substrate includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0166] In some embodiments, the first sub-pixel opening SA1 of the first sub-pixel is spaced apart from the first nearest isolation slot IG1 by a first shortest distance; the second sub-pixel opening SA2 of the second sub-pixel is spaced apart from the second nearest isolation slot IG2 by a second shortest distance; and the third sub-pixel opening SA3 of the third sub-pixel is spaced apart from the third nearest isolation slot IG3 by a third shortest distance. Optionally, the first shortest distance is greater than the second shortest distance. Optionally, the third shortest distance is greater than the second shortest distance. The inventors of this disclosure have found that by making the first shortest distance greater than the second shortest distance and making the third shortest distance greater than the second shortest distance, the color shift problem in the second sub-pixel can be further solved compared with the first sub-pixel and the third sub-pixel.

[0167] In some embodiments, the array substrate further includes a plurality of spacers PS. The spacers PS are located on a first side S1 of the second sub-pixel opening SA2. In some embodiments, the second sub-pixel opening SA2 is at least partially surrounded on one side by a first portion P1 and at least partially surrounded on the other side by a second portion P2. In some embodiments, the first portion P1 is located at least on a second side S2 of the second sub-pixel opening SA2, and the second portion P2 is located at least on a first side S1 of the second sub-pixel opening SA2, with the first side S1 opposite to the second side S2. In some embodiments, the second portion P2 surrounds a combination of the second isolation groove IG2, the first portion P1, and the second sub-pixel opening SA2. In some embodiments, the spacers PS are located on the second portion P2 adjacent to the second sub-pixel opening SA2.

[0168] The inventors of this disclosure have discovered that by positioning each spacer in the plurality of spacers PS on the first side S1 of the second sub-pixel opening SA2, the thickness and tilt angle of the pixel-defining layer can be increased, thereby reducing the light output on the second side S2. This unique structure further improves color shift asymmetry.

[0169] In another aspect, this disclosure provides a display device including an array substrate described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0170] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a planarization layer; forming an anode layer including a plurality of anodes located on the planarization layer; forming a pixel defining layer located on a side of the anode layer away from the planarization layer; and forming a plurality of isolation trenches extending into the planarization layer. Optionally, the array substrate further includes a display region. Optionally, a first side, a second side, a third side, and a fourth side surround the display region. Optionally, the first side is opposite to the second side. Optionally, the third side is opposite to the fourth side. Optionally, the method further includes forming an integrated circuit located on the second side relative to the display region. Optionally, each of the plurality of isolation trenches is located on the second side relative to a corresponding anode of the plurality of anodes.

[0171] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: Planarization layer; An anode layer comprising a plurality of anodes located on the planarization layer; A pixel-defining layer is located on the side of the anode layer away from the planarization layer; as well as Multiple isolation trenches extend into the planarization layer; The array substrate further includes a display area; The first side, the second side, the third side, and the fourth side surround the display area; The first side is opposite to the second side; and The third side is opposite to the fourth side; The array substrate further includes an integrated circuit located on the second side relative to the display area; In this configuration, the isolation tank in the plurality of isolation tanks is located on the second side relative to the corresponding anode in the plurality of anodes.

2. The array substrate according to claim 1, wherein, The isolation slot divides a portion of the pixel-defining layer between two adjacent sub-pixels into a first portion and a second portion.

3. The array substrate according to claim 2, wherein, Along the plane that intersects the two adjacent sub-pixels, the isolation slot, the first portion, and the second portion; The first portion has a first width; The second portion has a second width; and The second width is greater than the first width.

4. The array substrate according to claim 2, wherein, The first portion has a first thickness relative to the surface of the anode layer, and the second portion has a second thickness; and The second thickness is greater than the first thickness.

5. The array substrate according to claim 2, wherein, The corresponding sub-pixel opening is at least partially surrounded by the first portion on one side and at least partially surrounded by the second portion on the other side; The first portion is located at least on the second side of the corresponding sub-pixel opening; The second portion is located at least on the first side of the corresponding sub-pixel opening; as well as The second part surrounds the combination of the isolation groove, the first part, and the corresponding sub-pixel opening.

6. The array substrate according to any one of claims 1 to 5, wherein, A portion of the pixel-defining layer is located at least partially in one of the isolation slots of the plurality of isolation slots.

7. The array substrate according to any one of claims 1 to 6, wherein, The pixel definition layer includes: A plurality of first portions spaced apart from each other, the plurality of first portions including the first portion; and The second part is the overall structure; Wherein, the second portion is located at least on the first side of each of at least a plurality of sub-pixel openings in a plurality of sub-pixel openings; and The plurality of first portions are located at least on the second side of the at least plurality of sub-pixel openings.

8. The array substrate according to claim 7, wherein, The isolation groove separates a corresponding first portion from the second portion among the plurality of first portions; as well as The corresponding first portion separates the corresponding sub-pixel opening among the plurality of sub-pixel openings from the isolation groove.

9. The array substrate according to any one of claims 2 to 5, wherein, At least a portion of the corresponding sub-pixel opening has a rectangular shape, the rectangular shape having a first edge, a second edge connected to the first edge, a third edge connected to the second edge, and a fourth edge connected to the third edge and connected to the first edge; The first edge is opposite to the third edge; The second edge is opposite to the fourth edge; The first portion at least partially surrounds the first edge and the second edge; as well as The second portion at least partially surrounds the third edge and the fourth edge.

10. The array substrate according to claim 9, wherein, The first corner between the first edge and the second edge is located on the second side of the corresponding sub-pixel opening; The second corner between the third edge and the fourth edge is located on the first side of the corresponding sub-pixel opening; The third corner between the first edge and the fourth edge is located on the third side of the corresponding sub-pixel opening; and The fourth corner between the second edge and the third edge is located on the fourth side of the corresponding sub-pixel opening.

11. The array substrate according to any one of claims 1 to 10, wherein, The first part has an L-shaped form; and The isolation groove has an L-shaped form.

12. The array substrate according to any one of claims 1 to 11, comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel; in, The first sub-pixel opening of the first sub-pixel is separated from the first nearest isolation groove by a first shortest distance; The second sub-pixel opening of the second sub-pixel is separated from the second nearest isolation groove by the second shortest distance; The third sub-pixel opening of the third sub-pixel is separated from the third nearest isolation groove by the third shortest distance; The first shortest distance is greater than the second shortest distance; and The third shortest distance is greater than the second shortest distance.

13. The array substrate according to any one of claims 1 to 11, comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel; in, The first sub-pixel opening of the first sub-pixel is spaced apart from the first nearest isolation groove; The second sub-pixel opening of the second sub-pixel is spaced apart from the second nearest isolation slot; The third sub-pixel opening of the third sub-pixel is spaced apart from the third nearest isolation groove; as well as The shape of the second closest isolation groove is different from that of the first closest isolation groove and also different from that of the third closest isolation groove.

14. The array substrate according to claim 13, wherein, The first closest isolation groove has an L-shaped shape, wherein the width of the first closest isolation groove is substantially uniform. The third closest isolation groove has an L-shaped form, wherein the width of the third closest isolation groove is substantially uniform; and The second closest isolation groove has an L-shaped form, wherein the width of the second closest isolation groove gradually decreases relative to each arm of the L-shape from the position where the two arms are joined together to the end of each arm.

15. The array substrate according to claim 13, wherein, The second closest isolation slot includes a first arm and a second arm that are connected to each other; The width of the first arm gradually decreases from the point where the first and second arms are joined to the end of the first arm; and The width of the second arm gradually decreases from the point where the first and second arms are joined together to the end of the second arm.

16. The array substrate according to claim 13, wherein, The first closest isolation groove has an L-shaped shape, wherein the width of the first closest isolation groove is substantially uniform. The third closest isolation groove has an L-shaped form, wherein the width of the third closest isolation groove is substantially uniform; and The second closest isolation groove has an L-shaped shape, wherein the portion where the two arms of the L-shape are joined together has an increased width.

17. The array substrate according to claim 13, wherein, The second closest isolation groove includes a first arm, a second arm, and a connecting portion that are connected to each other; The first arm is connected to the connecting portion; The second arm is connected to the connecting portion; The width of the connecting portion is greater than the width of the first arm and greater than the width of the second arm; as well as The connecting portion has a triangular shape.

18. The array substrate according to any one of claims 1 to 17, further comprising a plurality of spacers; in, The spacer among the plurality of spacers is located on the first side of the second sub-pixel opening.

19. The array substrate according to claim 18, comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel; in, The first sub-pixel opening of the first sub-pixel is spaced apart from the first nearest isolation groove; The second sub-pixel opening of the second sub-pixel is spaced apart from the second nearest isolation slot; The third sub-pixel opening of the third sub-pixel is spaced apart from the third nearest isolation groove; as well as The spacer of the plurality of spacers is located on the second portion adjacent to the second sub-pixel opening.

20. A display device comprising an array substrate according to any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.

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