Method of singulating and shaping uncut and cut singulated dies using laser based system, by substrate lattice manipulation

Abstract

Aspects of the present disclosure provide a method for correcting a deformation of a semiconductor substrate. For example, the method can include receiving a semiconductor substrate that has undergone a deformation, measuring the semiconductor substrate to identify a deformation in a plurality of locations on the semiconductor substrate, and implanting a lattice configuration feature into the semiconductor substrate according to the deformation identified in the locations such that the identified deformation of the semiconductor substrate is corrected.

Description

Cross-references to related applications

[0001] This disclosure claims the benefit of U.S. non-provisional application No. 18 / 616,634, filed on March 26, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure generally pertains to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, and includes microfabrication methods. Background Technology

[0003] In the fabrication of semiconductor devices (especially at the microscale), various manufacturing processes are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Historically, microfabrication has been used to create transistors in a plane and to form wiring / metallization above the active device plane; this is thus characterized as two-dimensional (2D) circuitry or 2D fabrication. Scaling efforts have dramatically increased the number of transistors per unit area in 2D circuits, enabling the integration of heterogeneous functional circuits, such as logic and memory circuits, onto the same semiconductor substrate. However, as scaling enters the single-nanometer level of semiconductor device fabrication, 2D scaling efforts will face even greater challenges. Semiconductor device manufacturers have expressed interest in three-dimensional (3D) semiconductor circuits where transistors are stacked on top of each other, as another means of further miniaturizing integrated circuits (ICs). Summary of the Invention

[0004] Various aspects of this disclosure provide a method for correcting deformation of a semiconductor substrate. For example, the method may include: receiving a deformed semiconductor substrate; measuring the semiconductor substrate to identify deformation at multiple locations on the semiconductor substrate; and embedding lattice configuration features into the semiconductor substrate based on the identified deformation at these locations, such that the identified deformation of the semiconductor substrate is corrected. In one embodiment, these locations may include XY locations. In another embodiment, deformation at these XY locations may be identified by determining alignment mark registration, overlay mark registration, and / or reference grid registration on the semiconductor substrate.

[0005] In one embodiment, embedding lattice configuration features into a semiconductor substrate may include focusing a beam of light with a certain amount of energy at these locations on the semiconductor substrate. In another embodiment, focusing a beam of light with a certain amount of energy may include focusing a laser beam with a certain amount of laser energy. In yet another embodiment, the laser beam may have power, pulse duration, and number of pulses adjusted according to deformations identified at these locations. In this embodiment, the laser beam may be tuned to the material and lattice of the semiconductor substrate, as well as to the interface beneath the semiconductor substrate.

[0006] Various aspects of this disclosure also provide an apparatus for correcting deformation of a semiconductor substrate. For example, the apparatus may include a deformation measuring device configured to measure the semiconductor substrate to identify deformation at multiple locations on the semiconductor substrate; a light source configured to embed lattice configuration features into the semiconductor substrate to deform the semiconductor substrate; and a controller coupled to the deformation measuring device and the light source, configured to control the light source to embed the lattice configuration features into the semiconductor substrate according to the deformation identified at these locations on the semiconductor substrate.

[0007] In one embodiment, the light source can be configured to implant lattice features into the semiconductor substrate by focusing a beam of light with a certain amount of energy at these locations on the semiconductor substrate. In another embodiment, the light source can be a laser source configured to implant lattice features into the semiconductor substrate by focusing a laser beam with a certain amount of laser energy at these locations on the semiconductor substrate.

[0008] It should be noted that the Summary of this Scope does not specify every embodiment and / or incremental novelty aspect of this disclosure or the claimed disclosure. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding novel points that outperform conventional techniques. For additional details and / or possible perspectives regarding this disclosure and its embodiments, the reader should refer to the Detailed Description of this Scope and the corresponding drawings, which are further discussed below. Attached Figure Description

[0009] Various embodiments of this disclosure presented as examples will be described in detail with reference to the following accompanying drawings, wherein the same reference numerals refer to the same elements, and wherein:

[0010] Figure 1 A simplified cross-sectional view of the semiconductor segment is shown;

[0011] Figure 2 A semiconductor substrate is shown, comprising two semiconductor segments fabricated in face-to-face 3D integration (3Di).

[0012] Figure 3A A top view of an undeformed semiconductor substrate is shown;

[0013] Figures 3B to 3D , Figure 4A and Figure 4B Top views of other semiconductor substrates that have undergone various types of deformation, which can be corrected using this method; and

[0014] Figure 5 This is a flowchart illustrating an exemplary method for correcting deformation of a semiconductor substrate according to some embodiments of this disclosure; and

[0015] Figure 6 This is a functional block diagram of an exemplary apparatus for correcting deformation of a semiconductor substrate according to some embodiments of this disclosure. Detailed Implementation

[0016] The term “exemplary” is used herein to mean “as an example, instance, or illustration.” Any embodiment of a construction, process, design, technique, etc., specified herein as exemplary is not necessarily to be construed as being more preferred or advantageous than other such embodiments. The particular quality or suitability of the examples indicated herein as exemplary is neither intentional nor should be inferred.

[0017] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between an element or feature as shown in the accompanying figures and one or more other elements or features. In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device (or apparatus) during use or operation. The device (or apparatus) may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially relative descriptors used herein can also be interpreted in the same way.

[0018] For clarity, the order of discussion of the different steps described herein has been presented. In general, these steps can be performed in any suitable order. Additionally, while each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that each of these concepts can be performed independently of or in combination with each other. Accordingly, this disclosure can be implemented and viewed in many different ways.

[0019] As noted in the background section, semiconductor device manufacturers have expressed interest in 3D semiconductor devices with transistors stacked on top of each other as an alternative to conventional 2D miniaturization of ICs. 3D integration (3Di), the vertical stacking of semiconductor devices, aims to overcome the limitations of 2D miniaturization by increasing transistor density in terms of volume rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking with the adoption of 3D NAND, its application to random logic designs is significantly more challenging. 3D integration of logic chips such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and systems-on-chips (SoCs) is primarily achieved through two approaches: heterogeneous stacking and a more homogeneous stacking approach.

[0020] Heterogeneous stacking utilizes wafer / chip (or die) stacking and through-silicon via (TSV) technology, as disclosed in: Process Integration Aspects enabling 3D sequential stacked planar and FINfet Technology, Anne VanDooren, IMEC PTW, Spring 2018. For example, in this 3D integration approach, two chips can be optimized in design and manufacturing for different specific tasks; for instance, one chip might contain chemical and biological sensors, while the other contains nanodevices and microelectromechanical systems (MEMS) devices, and TSVs can be used to integrate these two different functional chips to build a stacked SoC. Details of heterogeneous integration methods are provided in the 2019 edition of the Heterogeneous Integration Roadmap, released in October 2019, at [link missing]. http: / / eps.ieee.org / hir .

[0021] Homogeneous stacking uses wafer bonding processes to overcome the density loss associated with micron-sized TSVs used in heterogeneous stacking. For example, a base wafer can be fabricated to form devices such as n-type metal-oxide-semiconductor (nMOS) and p-type MOS (pMOS), as well as several metallization / wiring layers. A thinned silicon-on-insulator (SOI) layer can then be positioned on top of the base wafer and bonded to the base wafer via oxide-oxide bonding to form a complete structure.

[0022] Figure 1A simplified cross-sectional view of semiconductor segment 100 is shown. A substrate (or wafer) 110 may be provided, such as a silicon or SiGe substrate. A layer (or semiconductor device layer) 150 of semiconductor devices may be disposed on the front side 110a of substrate 110. For example, semiconductor device layer 150 may include one or more semiconductor devices, such as field-effect transistors (FETs), forming functional circuits such as logic circuits or memory circuits. Further, these FETs may be n-type or p-type FETs arranged along the front side 110a or stacked vertically on top of each other along the thickness direction of substrate 110.

[0023] One or more power rails 120 may be embedded in the substrate 110 and electrically connect the semiconductor device layer 150 to the power delivery network (PDN) 130 via TSVs (e.g., nanoscale) 140 to provide, for example, low-voltage (Vss) and high-voltage (VDD) power delivery from the PDN 130 to the semiconductor device layer 150. The PDN 130 may be formed on the back side 110b of the substrate 110.

[0024] A signal wiring structure (or wiring level) 160 may be disposed above a layer 150 of a semiconductor device and is used to electrically connect the layer 150 of the semiconductor device to, for example, a layer (not shown) of another semiconductor device disposed above the wiring level 160. The wiring level 160 may include one or more wiring layers (or wiring stages), wherein each wiring layer includes one or more wiring tracks extending in a direction along the front side 110a of the substrate 110. Typically, the wiring tracks in a wiring layer extend in a direction perpendicular to the direction of the wiring tracks in adjacent wiring layers. For example, the wiring level 160 may include multiple wiring layers, such as three wiring layers 1601, 1602, and 1603, and wiring layer 1601 may include multiple wiring tracks, such as seven wiring tracks 1601a to 1601g, which extend in a direction perpendicular to the direction of the wiring tracks in wiring layer 1602 along the front side 110a of the substrate 110 (e.g., perpendicular to the plane of the drawing sheet).

[0025] Figure 2 A semiconductor substrate 200 is shown, comprising two semiconductor segments fabricated in face-to-face 3D integration (3Di), i.e., a multi-level stack of semiconductor devices having high-density inter-level wiring for efficient logic-to-memory or logic-to-logic connections. The two semiconductor segments can be constructed separately, and each segment may include power distribution, semiconductor devices (such as FETs), and signal wiring structures. For example, the semiconductor substrate 200 may include two... Figure 1The semiconductor segments 100 shown are vertically stacked on top of each other by flipping them over, and each of the semiconductor segments 100 may include power distribution (e.g., power rails 120, PDN 130, and TSV 140), semiconductor devices (e.g., semiconductor device layer 150), and signal wiring structures (e.g., signal wiring structure 160). In face-to-face 3Di fabrication, the two separately constructed semiconductor segments 100 must be carefully aligned with each other and face-to-face bonded together at interconnect bonding sites (e.g., bonding pads, not shown) by face-to-face bonding. Typically, one of the semiconductor segments 100 may include TSVs leading to bumps (not shown) disposed on the top of the semiconductor segment 100, which are used to connect the semiconductor substrate 200 to its package, such as... https: / / spectrum.ieee.org / tech-talk / semiconductors / processors / globalfoundries-arm-close-in-on-3d-chip-integration As described in detail.

[0026] High-density interconnects between two or more 3D stacked semiconductor devices (e.g., semiconductor segment 100) can ensure a combination of high performance and a small form factor. Reliable interconnects between two stacked semiconductor devices require positional accuracy in the nanometer range. Unlike overlay in optical systems where stage and lens manipulation can be used to improve overlay accuracy, in 3Di bonding, deformation of the semiconductor device must be controlled and corrected by dimensional shaping of the semiconductor device. Aspects of this disclosure provide a method for controlling and adapting the dimensions of diced and undiced dies (e.g., semiconductor segment 100) using lattice manipulation of the semiconductor device material via a focused (localized) beam (e.g., a laser).

[0027] Typical die dimensions are a maximum of 26 mm wide × 33 mm long, with typical thicknesses ranging from 800 micrometers to thinner, even as low as 50 micrometers. The body or carrier material of the die can be silicon, but can also be, for example, silicon oxide or silicon nitride. Active circuitry (e.g., layer 150 of a semiconductor device) can be embedded in the body or placed on top of the body or carrier die. Typical lateral dimension and shape deviations to be corrected are on the order of 100 nm.

[0028] Figure 3A A top view of an undeformed semiconductor substrate 300A (e.g., semiconductor segment 100) is shown. As more layers of semiconductor devices (e.g., semiconductor device layer 150) and signal wiring structures (e.g., signal wiring structure 160) are formed, the semiconductor substrate 300A may become a deformed semiconductor device. For example, during the formation of a semiconductor device, the semiconductor substrate 300A may become a semiconductor substrate 300B with symmetrical or scaled deformation (e.g., ...). Figure 3B As shown), it becomes a semiconductor substrate 300C with trapezoidal deformation (as shown). Figure 3C(as shown), or become a semiconductor substrate 300D with shear deformation (such as... Figure 3D (As shown). Semiconductor substrate 300A may be transformed into a semiconductor substrate with symmetrical radial deformation. For example, semiconductor substrate 300A may be transformed into semiconductor substrate 400A with barrel (negative) deformation (as shown). Figure 4A (as shown) or become a semiconductor substrate 400B with a pincushion (positive) deformation. Aspects of this disclosure provide a method for controlling and correcting these deformed semiconductor substrates 300B-300D, 400A and 400B by lattice manipulation of the semiconductor substrate material through a focused beam (e.g., a laser).

[0029] Laser processing (e.g., femtosecond laser processing) can be used to functionalize semiconductor materials (e.g., silicon, silicon oxide, and silicon nitride) in a controlled manner. The high peak intensity and the fact that the interaction with semiconductor materials is faster than the timescale of lattice disorder and thermal diffusion allow femtosecond lasers to precisely control the state of semiconductor materials, thereby inducing changes in nanostructure and affecting material properties such as hydrophobicity, reflectivity, hardness, wear resistance, and corrosion resistance.

[0030] The interaction between femtosecond lasers and semiconductor materials can involve energy transfer and thermomechanical dynamics across different timescales (or pulse durations). In the initial stages of femtosecond laser irradiation of a semiconductor material, electrons in the valence band are excited to the conduction band and thus rapidly heated to high temperatures. For example, the laser excites nonlinear ionization of Si electrons, and photon energy is transferred to the free electrons. Electron-lattice coupling then causes a rise in lattice temperature over a picosecond timescale. For instance, energy is transferred from the free electrons to the lattice, leading to lattice instability, thermal melting, and the generation of high stress. Femtosecond laser-induced thermal stress can affect atomic structure. Finally, lattice thermalization leads to rapid melting and resolidification, changes in interatomic forces, and structural transformations in solid-state semiconductor materials, inducing lattice defects on timescales ranging from hundreds of picoseconds to nanoseconds.

[0031] In an embodiment, a focused beam (e.g., a laser) can implant predetermined lattice configuration features into a die. The die can be deformed according to the lattice configuration features. The lattice configuration features may include a certain amount of laser power (or energy) directed in the form of a focused beam to the XY positions on the die where deformation occurs. The combination of laser type power, pulse duration, number of pulses (i.e., pulse frequency), and the XY position matrix on the die achieves correction for the die deformation. For example, sufficient laser pulse energy can trigger ultrafast melting of silicon from solid to liquid, caused by many electrons in the valence band absorbing photon energy and being excited to the conduction band, thereby destabilizing the lattice and causing the temperature at certain locations to exceed the melting point of Si. As another example, the laser irradiation area can gradually expand with increasing number of pulses.

[0032] Figure 5 This is a flowchart illustrating an exemplary method 500 for controlling and adapting the dimensions of a semiconductor substrate using lattice manipulation of semiconductor material via a focused beam, according to some embodiments of this disclosure. For example, the semiconductor substrate may be a diced die or an undicated die. In embodiments, some steps of the illustrated exemplary method 500 may be performed simultaneously or in a different order than shown, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as needed. In another embodiment, the exemplary method 500 may be used to correct deformed semiconductor substrates 300B-300D, 400A, and 400B. The method may begin at step S510.

[0033] At step S510, a first semiconductor substrate may be received. In this embodiment, the first semiconductor substrate has been deformed. Method 500 may proceed to step S520.

[0034] At step S520, the first semiconductor substrate is measured to identify deformation of the first semiconductor substrate at the XY position. For example, the first semiconductor substrate (e.g., semiconductor substrates 300B-300D, 400A, and 400B) can be compared with a second semiconductor substrate (e.g., semiconductor substrate 300A) that has not undergone any deformation to identify deformation of the first semiconductor substrate at the XY position. In embodiments, a deformation measurement device can be used to identify deformation of the first semiconductor substrate at the XY position. For example, the deformation measurement device can identify deformation of the first semiconductor substrate at the XY position by determining alignment mark registration, overlay mark registration, or reference grid registration on the first semiconductor substrate, or by using an algorithm based on die shape metrology. Method 500 can proceed to step S530.

[0035] At step S530, a predetermined lattice configuration feature is implanted into the deformed first semiconductor substrate. In an embodiment, a light beam (e.g., a laser) is used to implant the lattice configuration feature. For example, the lattice configuration feature may include a certain amount of laser power (or energy) directed in the form of a focused beam to the XY positions on the die where deformation has occurred, thereby correcting the die deformation. In an embodiment, the power, pulse duration, and number of pulses of the laser beam can be adjusted according to the identified die deformation at the XY positions.

[0036] For example, for semiconductor substrate 300B with symmetrical or scaled deformation, semiconductor substrate 300C with trapezoidal deformation, and semiconductor substrate 300D with shear deformation, the power, pulse duration, and number of pulses can be adjusted according to the laser type and function, tuned for the material, lattice, and underlying interface of semiconductor structures 300B, 300C, and 300D, and guided to the XY positions on semiconductor structures 300B, 300C, and 300D where deformation occurs (e.g., shaded areas, such as...). Figures 3B to 3D (as shown), so as to trigger, for example, the ultrafast melting of silicon from solid to liquid, thereby destabilizing the lattice and causing the temperature at the XY position to exceed the melting point of silicon, thereby correcting the die deformation.

[0037] For semiconductor substrates 400A with barrel (negative) deformation and semiconductor substrates 400B with pincushion (positive) deformation, the power, pulse duration, and number of pulses of the laser beam can be adjusted according to the laser type and function, tuned for the material, lattice, and underlying interface of semiconductor structures 400A and 400B, and guided to the XY positions on semiconductor structures 400A and 400B where deformation occurs (e.g., the edges of barrel and pincushion shapes) in order to, for example, trigger ultrafast melting of silicon material from solid to liquid, thereby destabilizing the lattice and causing the temperature at the XY position to exceed the melting point of silicon material, thereby correcting the die deformation.

[0038] Figure 6 This is a functional block diagram of an exemplary apparatus 600 for correcting deformation of a semiconductor structure according to some embodiments of this disclosure. Apparatus 600 can be used to implement method 500. Apparatus 600 may include a deformation measuring device 610 configured to measure a semiconductor substrate to identify deformation at multiple locations (e.g., XY locations) on the semiconductor substrate. Apparatus 600 may further include a light source 620 configured to embed a predetermined lattice configuration feature into the semiconductor substrate to deform the semiconductor substrate. Apparatus 600 may further include a controller 630 coupled to the deformation measuring device 610 and the light source 620. In an embodiment, controller 630 may be configured to control the light source 620 to embed the predetermined lattice configuration into the semiconductor substrate based on the identified deformation at locations on the semiconductor substrate.

[0039] In embodiments, the light source 620 may be configured to embed lattice configuration features into the semiconductor substrate by focusing a beam of light having a certain amount of energy at these locations on the semiconductor substrate. For example, the light source 620 may be a laser source configured to embed lattice configuration features into the semiconductor substrate by focusing a laser beam having a certain amount of laser energy at these locations. In some embodiments, the laser beam may have power, pulse duration, and number of pulses adjusted according to deformations identified at these locations. In various embodiments, the laser beam may be tuned to the material and lattice of the semiconductor substrate, as well as to the interface beneath the semiconductor substrate.

[0040] In the foregoing description, specific details, such as the particular geometry of the machining system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes rather than limiting. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional construction are indicated by the same reference numerals, and therefore any redundant descriptions may be omitted.

[0041] Various techniques have been described as multiple discrete operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations must be performed in a specific order. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in an order different from the order of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0042] As used herein, "substrate" or "target substrate" generally refers to the object being processed according to some embodiments of this disclosure. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, a photomask), or a layer on or overlying a base substrate structure (such as a thin film). Therefore, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0043] Those skilled in the art will also understand that many changes can be made to the operation of the techniques explained above while still achieving the same purpose as this disclosure. The scope of this disclosure is intended to cover such changes. Therefore, the foregoing description of embodiments of this disclosure is not intended to be limiting. Rather, any limitations on embodiments of this disclosure are provided in the appended claims.

Claims

1. A method for correcting deformation of a semiconductor substrate, the method comprising: Receive a deformed semiconductor substrate; The semiconductor substrate was measured to identify deformations at multiple locations on the semiconductor substrate. as well as Based on the deformations identified at these locations on the semiconductor substrate, lattice configuration features are implanted into the semiconductor substrate, thereby correcting the identified deformations of the semiconductor substrate.

2. The method as described in claim 1, wherein, Implanting the lattice configuration feature into the semiconductor substrate involves focusing a beam of light with a certain amount of energy at these locations on the semiconductor substrate.

3. The method as described in claim 2, wherein, A focused beam of light with a certain amount of energy includes a focused laser beam with a certain amount of laser energy.

4. The method of claim 3, wherein, The laser beam has power that is adjusted based on the deformations identified at these locations.

5. The method of claim 3, wherein, The laser beam has a pulse duration that is adjusted based on the deformations identified at these locations.

6. The method of claim 3, wherein, The laser beam has a number of pulses that are adjusted based on the deformations identified at these locations.

7. The method of claim 3, wherein, The laser beam is tuned to the material of the semiconductor substrate.

8. The method of claim 3, wherein, The laser beam is tuned to the lattice of the semiconductor substrate.

9. The method of claim 4, wherein, The laser beam is tuned to the interface beneath the semiconductor substrate.

10. The method of claim 1, wherein, These locations include X and Y positions.

11. The method of claim 10, wherein, Deformations in these XY locations are identified by determining the alignment mark registration, overlay mark registration, and / or reference grid registration on the semiconductor substrate.

12. An apparatus for correcting deformation of a semiconductor substrate, the apparatus comprising: A deformation measuring device configured to measure the semiconductor substrate to identify deformation at multiple locations on the semiconductor substrate; A light source configured to implant lattice configuration features into the semiconductor substrate to deform the semiconductor substrate; as well as A controller, connected to the deformation measuring device and the light source, is configured to control the light source to implant the lattice configuration features into the semiconductor substrate based on the deformations identified at these locations on the semiconductor substrate.

13. The apparatus of claim 12, wherein, The light source is configured to embed the lattice configuration features into the semiconductor substrate by focusing a beam of light with a certain amount of energy at these locations on the semiconductor substrate.

14. The apparatus of claim 13, wherein, The light source is a laser source configured to implant the lattice configuration features into the semiconductor substrate by focusing a laser beam with a certain amount of laser energy at these locations on the semiconductor substrate.

15. The apparatus of claim 14, wherein, The laser beam has power that is adjusted based on the deformations identified at these locations.

16. The apparatus of claim 14, wherein, The laser beam has a pulse duration that is adjusted based on the deformations identified at these locations.

17. The apparatus of claim 14, wherein, The laser beam has a number of pulses that are adjusted based on the deformations identified at these locations.

18. The apparatus of claim 14, wherein, The laser beam is tuned to the material of the semiconductor substrate.

19. The apparatus of claim 14, wherein, The laser beam is tuned to the lattice of the semiconductor substrate.

20. The apparatus of claim 12, wherein, These locations include X and Y positions.

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