Semiconductor chip and semiconductor device

Abstract

Semiconductor chips (1, 2) are overlaid and joined. The semiconductor chip (1) includes electrode pads (e11, e12) arranged at a joining surface (J) and a node (P1) that supplies a first voltage to the electrode pads (e11, e12). The semiconductor chip (2) includes electrode pads (e21, e22) arranged at the joining surface (J) and a node (P2) that supplies a second voltage to the electrode pads (e21, e22). The electrode pads (e11, e12) and the electrode pads (e21, e22) are aligned in the X direction when viewed from above.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device for overlapping and bonding semiconductor chips. Background Technology

[0002] To date, the known structure for semiconductor devices is the overlapping and bonding of multiple semiconductor chips (3D structure). With the increasing density of components integrated into semiconductor chips and the accompanying miniaturization of semiconductor chips, it is foreseeable that 3D structures will be widely used in the future.

[0003] Patent document 1 discloses a technique for detecting positional offsets that occur during the bonding of semiconductor chips in a 3D structure of a semiconductor device.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent document 1: International Publication No. 2023 / 145329. Summary of the Invention

[0007] -The technical problem the invention aims to solve-

[0008] Considering the widespread application of 3D structures in the future, there is a need for simpler and smaller circuits to detect positional offsets during the bonding of semiconductor chips.

[0009] This disclosure provides a structure in which the positional offset of a semiconductor chip during bonding can be detected using a simpler and smaller circuit in the 3D structure of a semiconductor device.

[0010] - Technical solutions used to solve technical problems -

[0011] One aspect of this disclosure is a semiconductor chip that is overlapped and bonded with other semiconductor chips to form a semiconductor device. The semiconductor chip includes a plurality of electrode pads, a voltage supply node, and a detection pad. The plurality of electrode pads are disposed on the bonding surfaces of the semiconductor chip that are bonded to the other semiconductor chips. The voltage supply node is connected to the plurality of electrode pads, and a first voltage is supplied to the voltage supply node. The detection pads are disposed for at least a portion of the plurality of electrode pads and are used to monitor the potential of the electrode pads from outside the semiconductor chip. The plurality of electrode pads are arranged in a first direction, and the electrode pads in the first direction are of the same size and the spacing between the electrode pads in the first direction is constant.

[0012] According to this aspect, a semiconductor chip has electrode pads arranged in a first direction on its bonding surface with other semiconductor chips. In the first direction, all electrode pads are of the same size, and the spacing between the electrode pads is constant. A first voltage is supplied to the electrode pads from a voltage supply node. When the semiconductor chip is overlapped and bonded with other semiconductor chips, by monitoring the potential of the electrode pads through pad detection, it is possible to detect whether the electrode pad is in contact with the electrode pads of other semiconductor chips. Based on the contact / non-contact state of the electrode pads, it is possible to determine whether a positional shift occurred during the bonding of the semiconductor chips.

[0013] -The effects of the invention-

[0014] According to this disclosure, in the 3D structure of a semiconductor device, it is possible to detect the positional offset of a semiconductor chip during bonding using a simpler and smaller structure. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a semiconductor device formed by overlapping and bonding semiconductor chips.

[0016] Figure 2 The following is a structural example of a mechanism for detecting the offset of the bonding position of a semiconductor chip in the first embodiment: (a) is a cross-sectional view, and (b) is a top view.

[0017] Figure 3 This is a diagram illustrating the state in which the engagement position offset has occurred.

[0018] Figure 4 Examples of coding the contact / non-contact state of electrode pads are shown: (a) shows no position offset, (b) shows offset to the left, (c) shows offset to the right, and (d) shows the coding rules.

[0019] Figure 5 An example structure for detecting the contact / non-contact state of electrode pads is shown.

[0020] Figure 6 The diagram shows a structure in which electrode pads are arranged on the four sides of a semiconductor chip.

[0021] Figure 7 (a), (b), and (c) show Figure 6 An example of positional offset in a structure.

[0022] Figure 8 This example illustrates how the contact / non-contact status of the electrode pads on each side is encoded.

[0023] Figure 9Examples of electrode pad arrangement and coding in a variation of the first embodiment are shown: (a) showing no positional offset, (b) showing offset to the left, (c) showing offset to the right, and (d) showing coding rules.

[0024] Figure 10 The following is a structural example of a mechanism for detecting the offset of the bonding position of a semiconductor chip in the second embodiment: (a) is a cross-sectional view, and (b) is a top view.

[0025] Figure 11 Examples of coding the contact / non-contact state of electrode pads are shown: (a) shows offset to the left, (b) shows offset to the right, and (c) shows the coding rules.

[0026] Figure 12 An example structure for detecting the contact / non-contact state of electrode pads is shown.

[0027] Figure 13 Examples of electrode pad arrangement and coding in a variation of the second embodiment are shown: (a) shows no positional offset, (b) shows offset to the left, (c) shows offset to the right, and (d) shows coding rules. Detailed Implementation

[0028] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, "top view" refers to viewing a semiconductor chip or the like from a direction perpendicular to the surface of the semiconductor chip.

[0029] Figure 1 This is a structural example of a semiconductor device in this disclosure. The semiconductor device 100 is constructed by overlapping and bonding semiconductor chip 1 and semiconductor chip 2. Semiconductor chips 1 and 2 are bonded such that their wiring layers face each other.

[0030] (First Implementation)

[0031] Figure 2 An example of the structure of the mechanism for detecting the offset of the bonding position of a semiconductor chip in the first embodiment is shown. Figure 2 (a) is a cross-sectional view showing the bonding state of semiconductor chips 1 and 2 and the outline of the detection circuit, and (b) is a top view showing the bonding state of semiconductor chips 1 and 2. Figure 2 (a) in the middle shows along Figure 2 The cross-section cut by line I-I in (b) of the diagram.

[0032] Semiconductor chip 1 includes a wiring layer 1a and a substrate layer 1b. Semiconductor chip 2 includes a wiring layer 2a and a substrate layer 2b. Semiconductor chips 1 and 2 are bonded together such that wiring layer 1a and wiring layer 2a face each other at bonding surface J.

[0033] Semiconductor chip 1 comprises electrode pads e11 and e12 exposed on a bonding surface J in a wiring layer 1a. The electrode pads e11 and e12 are arranged in a row along an edge E. A direction extending along the edge E is defined as an X-axis direction, and a direction orthogonal to the X-axis direction is defined as a Y-axis direction. In addition, a direction perpendicular to the surface of the semiconductor chip is defined as a Z-axis direction. The planar shape of the electrode pads e11 and e12 is a rectangle with a width w1 (dimension in the X-axis direction) and a length l1 (dimension in the Y-axis direction). A spacing between the electrode pads e11 and e12 is d1.

[0034] Semiconductor chip 2 comprises electrode pads e21 and e22 exposed on the bonding surface J in a wiring layer 2a. The electrode pads e21 and e22 are arranged in a row along the edge E. The planar shape of the electrode pads e21 and e22 is a rectangle with a width w2 and a length l2. A spacing between the electrode pads e21 and e22 is d2. In Figure 2 , the relationship w1+d1=w2+d2 is satisfied.

[0035] It should be noted that, as will be described later, the number of electrode pads arranged on the semiconductor chip may also be three or more. In addition, the number of arranged electrode pads of semiconductor chip 1 and semiconductor chip 2 may also be different.

[0036] In Figure 2 , the electrode pads e11, e12 of the semiconductor chip 1 and the electrode pads e21, e22 of the semiconductor chip 2 are alternately arranged in a row along the X-axis direction in a top view. That is, the electrode pad e11 is arranged between the electrode pads e21 and e22, and the electrode pad e22 is arranged between the electrode pads e11 and e12. The electrode pad e11 is not in contact with the electrode pads e21 and e22 (w1<d2). The electrode pad e22 is not in contact with the electrode pads e11 and e12 (w2<d1). When there is no bonding position offset between the semiconductor chips, the position of a midpoint a of the electrode pad e11 coincides with the position of a midpoint b between the electrode pads e21 and e22 in the X-axis direction.

[0037] In the semiconductor chip 1, a voltage supply node P1 is connected to the electrode pads e11 and e12 via a resistor R1. In the semiconductor chip 2, a voltage supply node P2 is connected to the electrode pads e21 and e22 via a resistor R2. It should be noted that the connecting resistors R1 and R2 are provided to prevent damage caused by a short-circuit current flowing between the voltage supply nodes when the electrode pads of the two semiconductor chips 1 and 2 are in contact. The resistance values of the resistors R1 and R2 only need to be designed to a value that does not cause damage.

[0038] In Figure 2In this structure, the operation of detecting the offset of the bonding position of semiconductor chips 1 and 2 will be explained. In this embodiment, the contact or non-contact between the electrode pads of semiconductor chip 1 and the electrode pads of semiconductor chip 2 is detected, thereby detecting the offset of the semiconductor chips 1 and 2 when they are bonded.

[0039] like Figure 3 As shown, voltage is supplied to voltage supply nodes P1 and P2. Here, a reference voltage (GND) is supplied to voltage supply node P2, and a high voltage (VDD) is supplied to voltage supply node P1. Alternatively, the opposite can be true: VDD is supplied to voltage supply node P2, and GND is supplied to voltage supply node P1. It should be noted that voltage supply to voltage supply nodes P1 and P2 can also be achieved by providing dedicated supply terminals on the semiconductor chip. Alternatively, the power supply voltage supply terminals can be shared with other circuits within the semiconductor chip.

[0040] Figure 3 It shows in Figure 2 In (a), the bonding of semiconductor chips 1 and 2 results in a positional offset. Figure 3 In the process, due to the positional offset caused by the bonding of semiconductor chips 1 and 2 in the X-axis direction, the electrode pad e11 of semiconductor chip 1 contacts the electrode pad e21 of semiconductor chip 2, and the electrode pad e12 of semiconductor chip 1 contacts the electrode pad e22 of semiconductor chip 2.

[0041] When the electrode pads e11 and e12 of semiconductor chip 1 are not in contact with the electrode pads e21 and e22 of semiconductor chip 2, the potential of the electrode pads e11 and e12 of semiconductor chip 1 becomes VDD, and the potential of the electrode pads e21 and e22 of semiconductor chip 2 becomes GND. On the other hand, in Figure 3 In this state, the potentials of electrode pads e11 and e12 of semiconductor chip 1 and electrode pads e21 and e22 of semiconductor chip 2 become the intermediate potentials between VDD and GND. Therefore, by detecting the potential of the electrode pads, it is possible to detect whether the electrode pads are in contact with the electrode pads of other semiconductor chips.

[0042] Figure 4 An example of encoding the contact / non-contact state of the electrode pads of semiconductor chip 1 is shown. Here, the potential of the electrode pad is set to "1" when it is VDD, and set to "0" when the potential of the electrode pad is between VDD and GND. That is, "1" represents a non-contact state where the electrode pads of semiconductor chip 2 are not in contact, and "0" represents a contact state where the electrode pads of semiconductor chip 2 are in contact. Furthermore, a two-bit code is generated, with the state of electrode pad e11 as the high-order bit and the state of electrode pad e12 as the low-order bit.

[0043] like Figure 4 As shown in (a), when semiconductor chips 1 and 2 do not experience positional shifts, electrode pads e11 and e12 are both in a non-contact state, hence the code "11". Figure 4 As shown in (b), when semiconductor chip 1 is offset to the left relative to semiconductor chip 2, electrode pads e11 and e12 are both in contact, therefore the code is "00". Figure 4 As shown in (c), when semiconductor chip 1 is offset to the right relative to semiconductor chip 2, the code is "01" because electrode pad e11 is in contact and electrode pad e12 is in non-contact.

[0044] Based on the above, we can obtain the following: Figure 4 The code rule is as follows (d). That is, when the high-order bit is "1", it can be determined that there is no position offset, and when the high-order bit is "0", it can be determined that there is a position offset (A). Furthermore, when there is a position offset, the direction of the offset can be determined by the low-order bits (B). That is, when the high-order bit is "0", when the low-order bit is "0", it can be determined that the offset is to the left, and when the low-order bit is "1", it can be determined that the offset is to the right.

[0045] It should be noted that the same encoding and judgment can also be performed on the electrode pads of semiconductor chip 2.

[0046] Figure 5 An example structure for detecting the contact / non-contact state of electrode pads is shown. Figure 5 In semiconductor chip 1, detection pads TP11 and TP12 are respectively provided for electrode pads e11 and e12. The potentials of electrode pads e11 and e12 can be monitored from outside semiconductor chip 1 via detection pads TP11 and TP12. In semiconductor chip 2, detection pads TP21 and TP22 are respectively provided for electrode pads e21 and e22. The potentials of electrode pads e21 and e22 can be monitored from outside semiconductor chip 2 via detection pads TP21 and TP22. The detection pads are arranged similarly to signal pads, which transmit and receive signals with the outside of the semiconductor chip.

[0047] When detecting the state of electrode pads e11 and e12 of semiconductor chip 1, probes T1 and T2 are brought into contact with the detection pads TP11 and TP12 to detect their potential, and the tester (inspection device) determines the code "1" or "0". Alternatively, a buffer circuit can be set between electrode pads e11 and e12 and detection pads TP11 and TP12, and a logic level high or low can be output to the detection pads TP11 and TP12.

[0048] Similarly, when detecting the state of electrode pads e21 and e22 on a semiconductor chip, simply contact the probe with the detection pads TP21 and TP22 and detect their potential or logic level. It should be noted that... Figure 5 In this design, a structure is adopted in which detection pads are set on all electrode pads, but it is also possible to set detection pads only on a portion of the electrode pads, such as electrode pads that measure potential and detect codes.

[0049] Figure 6 The diagram shows a structure with electrode pads arranged on the four sides of a semiconductor chip. e1x is the electrode pad arranged on semiconductor chip 1, and e2x is the electrode pad arranged on semiconductor chip 2 (x is an integer from 1 to 8). Two electrode pads are arranged on each side of semiconductor chips 1 and 2. In a top view, the electrode pads of semiconductor chip 1 and semiconductor chip 2 are arranged alternately in a row on each side.

[0050] Figure 7 Show Figure 6 An example of positional offset in a structure. Figure 7 In (a), semiconductor chip 1 is offset to the right relative to semiconductor chip 2 (mode A). In this case, the positional offset can be detected by the contact / non-contact of the electrode pads arranged on the first and third sides. Figure 7 In (b), semiconductor chip 1 is offset relative to semiconductor chip 2 in the direction shown in the figure (mode B). In this case, the positional offset can be detected by the contact / non-contact of the electrode pads arranged on the second and fourth sides. Figure 7 In (c), semiconductor chip 1 is rotated to the right and offset relative to semiconductor chip 2 (mode C). In this case, the positional offset can be detected by the contact / non-contact of the electrode pads arranged on the first to fourth sides. It should be noted that... Figure 7 The contact / non-contact state of the electrode pads shown is an example; for instance, the contact / non-contact state of the electrode pads may change depending on the degree of positional offset.

[0051] Figure 8 Yes Figure 6 Structure and Figure 7 The state of the electrode pads on each side of the position offset is encoded in the diagram. Figure 6 In the structure, no positional shift occurs, and the electrode pads of semiconductor chip 1 are all in a non-contact state. Therefore, the first to fourth sides are all "11".

[0052] exist Figure 7In mode A of (a), on the first side, electrode pad e11 is in contact, thus becoming "01". Additionally, on the third side, electrode pads e15 and e16 are in contact, thus becoming "00". That is, when the second and fourth sides are "11", the low-order bit of the first side is "1", and the low-order bit of the third side is "0", a positional offset in the positive X-axis direction (right direction in the attached diagram) can be detected.

[0053] exist Figure 7 In mode B of (b), on the second side, electrode pads e13 and e14 are in contact, thus becoming "00". Additionally, on the fourth side, electrode pad e17 is in contact, thus becoming "01". That is, when the first and third sides are "11", the low-order bit of the second side is "0", and the low-order bit of the fourth side is "1", a positional offset in the positive Y-axis direction (the direction shown in the attached diagram) can be detected.

[0054] exist Figure 7 In mode C of (c), since the electrode pads e11 on the first side, e13 on the second side, e15 on the third side, and e17 on the fourth side are in contact, the first to fourth sides become "01". That is, when all the high bits of the first to fourth sides are "0" and the low bits are "1", a positional shift in the rightward rotation direction (clockwise direction) can be detected.

[0055] According to this embodiment, positional misalignment during semiconductor chip bonding can be detected using a simple and small-scale structure. Furthermore, by displaying the positional misalignment in code, the tendency of the misalignment is easily grasped, thus easily improving alignment accuracy. Additionally, by maintaining a constant relationship between the spacing and width of the electrode pads between semiconductor chips, simple regularity can be obtained regardless of which semiconductor chip's electrode pads are used to extract the code. Moreover, by adhering to this relationship, the number of bondable semiconductor chips can be increased.

[0056] For example, inspecting defective semiconductor devices can be done simply by using codes to detect the misalignment of the semiconductor chip's bonding position, correcting the bonding based on the codes, and then re-inspecting. Alternatively, if re-inspection is not possible, the bonding position of subsequent semiconductor chips can be adjusted based on the codes. Furthermore, by statistically analyzing the detected codes to understand the trend of positional misalignment, the alignment accuracy of semiconductor chips can be improved.

[0057] (Variation example)

[0058] In the above embodiments, two electrode pads are arranged along the edge in semiconductor chips 1 and 2, but more than three electrode pads can also be arranged.

[0059] Figure 9 This example illustrates a configuration where three electrode pads are arranged on each of semiconductor chips 1 and 2. Electrode pads e11, e12, and e13 are located on semiconductor chip 1, and electrode pads e21, e22, and e23 are located on semiconductor chip 2. The encoding method is the same as described above. Three bits of code are assigned to electrode pads e11, e12, and e13.

[0060] like Figure 9 As shown in (a), when no positional offset occurs, electrode pads e11, e12, and e13 are all in a non-contact state, therefore the code is "111". Figure 9 As shown in (b), when semiconductor chip 1 is offset to the left relative to semiconductor chip 2, electrode pads e11, e12, and e13 are all in contact, hence the code "000". Figure 9 As shown in (c), when semiconductor chip 1 is offset to the right relative to semiconductor chip 2, the code is "001" because electrode pads e11 and e12 are in contact while electrode pad e13 is in non-contact.

[0061] Based on the above, we can obtain the following: Figure 9 The code follows the rules of (d). That is, when the highest bit is "1", it can be determined that there is no position offset, and when the highest bit is "0", it can be determined that there is a position offset (A). Furthermore, when the highest bit is "0", the direction of the position offset can be determined based on the lowest bit (B). That is, when the lowest bit is "0", it can be determined that the offset is to the left, and when the lowest bit is "1", it can be determined that the offset is to the right.

[0062] It should be noted that the same encoding and judgment can also be performed on the electrode pads of semiconductor chip 2.

[0063] As can be seen from this variation, even if the number of electrode pads changes, the codes representing the state of the electrode pads remain consistent with the embodiments described above, resulting in simple regularity. Therefore, it is easy to grasp the tendency of positional offset, thereby easily improving alignment accuracy.

[0064] (Second Implementation)

[0065] In the second embodiment, the structure with different numbers of electrode pads in the mechanism for detecting the positional offset of the bonding in semiconductor chip 1 and semiconductor chip 2 will be described.

[0066] Figure 10 This is a diagram illustrating a structural example of a mechanism for detecting the offset of the bonding position of a semiconductor chip in the second embodiment. Figure 10, (a) is a cross-sectional view schematically showing the bonding state of semiconductor chips 1 and 2 and an outline of a detection circuit, Figure 10 , (b) is a top view schematically showing the bonding state of semiconductor chips 1 and 2.

[0067] Semiconductor chip 1 includes, in a wiring layer 1a thereof, five electrode pads e31, e32, e33, e34, e35 exposed at a bonding surface J. The electrode pads e31, e32, e33, e34, e35 are arranged in a line in the X-axis direction. The planar shape of the electrode pads e31, e32, e33, e34, e35 is a rectangle with a width w1. A distance between adjacent ones of the electrode pads e31, e32, e33, e34, e35 is d1.

[0068] Semiconductor chip 2 includes, in a wiring layer 2a thereof, electrode pads e21 and e22 exposed at a bonding surface J. The electrode pads e21 and e22 are arranged in a line in the X-axis direction. The planar shape of the electrode pads e21 and e22 is a rectangle with a width w2. A distance between the electrode pads e21 and e22 is d2.

[0069] The width and pitch of the electrode pads e31, e32, e33, e34, e35 of the semiconductor chip 1 are smaller than the width and pitch of the electrode pads e21 and e22 of the semiconductor chip 2. That is, the relations w1<w2 and d1<d2 are satisfied.

[0070] In Figure 10 , the electrode pad e33 of the semiconductor chip 1 is arranged between the electrode pads e21 and e22 of the semiconductor chip 2. The electrode pad e33 does not contact the electrode pads e21 and e22 (w1<d2). When there is no positional misalignment in the bonding of the semiconductor chips 1 and 2, the position of a midpoint a of the electrode pad e33 coincides with the position of a midpoint b between the electrode pads e21 and e22 in the X-axis direction. The electrode pads e31 and e32 of the semiconductor chip 1 are in contact with the electrode pad e21 of the semiconductor chip 2. The electrode pads e34 and e35 of the semiconductor chip 1 are in contact with the electrode pad e22 of the semiconductor chip 2. Therefore, as shown in Figure 10 (b), when no positional misalignment occurs, the code is "00100".

[0071] Figure 11 , (a) illustrates a state where Figure 10 in (b), the semiconductor chip 1 is positionally offset to the left in the drawing relative to the semiconductor chip 2. As shown in Figure 11As shown in (a), when a small positional offset occurs and electrode pad e34 is in a non-contact state, the code becomes "00110". When a large positional offset occurs and electrode pad e33 is in a contact state, the code becomes "00010". When an even larger positional offset occurs and electrode pad e35 is in a non-contact state, the code becomes "00011".

[0072] Figure 11 (b) is in Figure 10 In (b), semiconductor chip 1 is offset relative to semiconductor chip 2 in the right direction of the attached diagram. Figure 11 As shown in (b), when a small positional offset occurs and electrode pad e32 is in a non-contact state, the code becomes "01100". When a large positional offset occurs and electrode pad e33 is in a contact state, the code becomes "01000". When an even larger positional offset occurs and electrode pad e31 is in a non-contact state, the code becomes "11000".

[0073] Based on the above, we can obtain the following: Figure 11 The rule is shown in (c). That is, when the third bit (electrode pad e33) is "0", a positional offset can be determined (A). Furthermore, when the third bit is "1", if the second bit (electrode pad e32) is "1", a rightward offset can be determined (B). Additionally, when the third bit is "1", if the fourth bit (electrode pad e34) is "1", a leftward offset can be determined (C). Thus, rightward offsets can be detected by changes in the code of electrode pad e32, and leftward offsets can be detected by changes in the code of electrode pad e34; therefore, the detection accuracy is higher than that of judging solely by the code of electrode pad e33.

[0074] Figure 12 An example structure for detecting the state of electrode pads is shown. Figure 12 In semiconductor chip 1, detection pads TP31, TP32, TP33, TP34, and TP35 are respectively provided for electrode pads e31, e32, e33, e34, and e35. The potentials of electrode pads e31, e32, e33, e34, and e35 are output to detection pads TP31, TP32, TP33, TP34, and TP35, respectively. The detection pads are arranged in the same manner as signal pads, and the signal pads transmit and receive signals with the outside of the semiconductor chip.

[0075] Similar to the first embodiment, when detecting the state of the electrode pads e31, e32, e33, e34, and e35 of the semiconductor chip 1, the probe is brought into contact with the detection pads TP31, TP32, TP33, TP34, and TP35 to detect their potential, and the tester (inspection device) determines the code "1" or "0". Alternatively, a buffer circuit may be provided between the electrode pads e31, e32, e33, e34, and e35 and the detection pads TP31, TP32, TP33, TP34, and TP35 to output a high or low logic level to the detection pads TP31, TP32, TP33, TP34, and TP35.

[0076] It should be noted that, in Figure 12 In this design, a structure is adopted in which detection pads are set on all electrode pads, but it is also possible to set detection pads only on the electrode pads that measure potential and detect codes.

[0077] According to this embodiment, similar to the first embodiment, positional misalignment during semiconductor chip bonding can be detected using a simple and small-scale structure. Furthermore, regarding the electrode pads arranged on the semiconductor chip, even when the number, shape, and spacing differ between semiconductor chips, the detection accuracy of positional misalignment and the accuracy of alignment can be improved in the same manner as or further than in the first embodiment.

[0078] (Variation example)

[0079] In the above embodiments, the structure of the semiconductor chip 1 including five electrode pads has been described. In this modified example, the structure of the semiconductor chip 1 including four electrode pads has been described.

[0080] Figure 13 This is an example where four electrode pads are arranged on semiconductor chip 1. Electrode pads e41, e42, e43, and e44 are located on semiconductor chip 1. Figure 13 In the semiconductor chip 1, electrode pads e42 and e43 are arranged between electrode pads e21 and e22 of semiconductor chip 2. Electrode pads e42 and e43 do not contact electrode pads e21 and e22. Assuming no positional shift occurs during the bonding of semiconductor chips 1 and 2, in the X-axis direction, the midpoint a between electrode pads e42 and e43 coincides with the midpoint b between electrode pads e21 and e22.

[0081] like Figure 13 As shown in (a), the code is "0110" when no positional offset occurs. Figure 13 As shown in (b), when semiconductor chip 1 is offset to the left in the attached figure and electrode pad e42 contacts electrode pad e21, the code is "0010". Figure 13 As shown in (c), when semiconductor chip 1 is offset to the right in the figure and electrode pad e43 contacts electrode pad e22, the code is "0100".

[0082] Based on the above, we can obtain Figure 13 The rule shown in (d) is as follows. That is, when both the second and third bits (electrode pads e42 and e43) are "1", it can be determined that there is no positional offset. Furthermore, when the second bit is "0", it can be determined that there is an offset to the left (A). Additionally, when the third bit is "0", it can be determined that there is an offset to the right (B).

[0083] As can be seen from this variation, even if the number of electrode pads changes, the codes representing the state of the electrode pads remain consistent with the embodiments described above, resulting in simple regularity. Therefore, it is easy to grasp the tendency of positional offset, thereby easily improving alignment accuracy.

[0084] -Industry Applicability-

[0085] In this disclosure, in a semiconductor device in which semiconductor chips are overlapped and bonded, positional offset during bonding can be detected by a simple and small-scale structure, which is useful for, for example, miniaturization of semiconductor devices and improvement of yield.

[0086] - Symbol Explanation -

[0087] 1, 2 Semiconductor chips

[0088] 100 Semiconductor Devices

[0089] E11, E12, E13, E14, E15, E16, E17, E18 Electrode pads

[0090] E21, E22, E23, E24, E25, E26, E27, E28 Electrode pads

[0091] E31, E32, E33, E34, E35 electrode pads

[0092] E41, E42, E43, E44 electrode pads

[0093] P1, P2 voltage supply nodes

[0094] TP11, TP12, TP21, TP22 Inspection Pads

[0095] TP31, TP32, TP33, TP34, TP35 Inspection Pads

[0096] J Joint surface.

Claims

1. A semiconductor chip, which is overlapped and bonded with other semiconductor chips to form a semiconductor device, characterized in that: The semiconductor chip includes multiple electrode pads, voltage supply nodes, and detection pads. The plurality of electrode pads are disposed on the bonding surfaces of the semiconductor chip that are bonded to other semiconductor chips. The voltage supply node is connected to the plurality of electrode pads, and a first voltage is supplied to the voltage supply node. The detection pads are configured for at least a portion of the plurality of electrode pads, and are used to monitor the potential of the electrode pads from outside the semiconductor chip. The plurality of electrode pads are arranged in a first direction, wherein each electrode pad in the first direction has the same size and the spacing between each electrode pad in the first direction is constant.

2. The semiconductor chip according to claim 1, characterized in that: The semiconductor chip includes multiple second electrode pads and second detection pads. The plurality of second electrode pads are disposed on the bonding surface and connected to the voltage supply node. The second detection pad is configured for at least a portion of the plurality of second electrode pads, and is used to monitor the potential of the second electrode pad from outside the semiconductor chip. The plurality of second electrode pads are arranged in a second direction different from the first direction, wherein each electrode pad in the second direction has the same size and the spacing between each electrode pad in the second direction is constant.

3. A semiconductor device comprising overlapping and bonding a first semiconductor chip and a second semiconductor chip, characterized in that: The first semiconductor chip includes multiple first electrode pads, a first voltage supply node, and a first detection pad. The plurality of first electrode pads are disposed on the bonding surface of the first semiconductor chip and the second semiconductor chip. The first voltage supply node is connected to the plurality of first electrode pads, and a first voltage is supplied to the first voltage supply node. The first detection pad is configured for at least a portion of the plurality of first electrode pads, and is used to monitor the potential of the first electrode pad from outside the first semiconductor chip. The plurality of first electrode pads are arranged in a first direction, wherein each first electrode pad in the first direction has the same size, and the spacing between the first electrode pads in the first direction is constant. The second semiconductor chip includes multiple second electrode pads, a second voltage supply node, and a second detection pad. The plurality of second electrode pads are disposed on the bonding surface of the second semiconductor chip that is bonded to the first semiconductor chip. The second voltage supply node is connected to the plurality of second electrode pads, and a second voltage, different from the first voltage, is supplied to the second voltage supply node. The second detection pad is provided for at least a portion of the plurality of second electrode pads, and is used to monitor the potential of the second electrode pad from outside the second semiconductor chip. The plurality of second electrode pads are arranged in the first direction, and the second electrode pads in the first direction are of the same size, and the spacing between the second electrode pads in the first direction is constant. The plurality of first electrode pads and the plurality of second electrode pads are arranged in a row in the first direction when viewed from above.

4. The semiconductor device according to claim 3, characterized in that: The dimension of the first electrode pad in the first direction is smaller than the spacing of the plurality of second electrode pads in the first direction.

5. The semiconductor device according to claim 4, characterized in that: The sum of the dimension of the first electrode pad in the first direction and the spacing of the plurality of first electrode pads in the first direction is equal to the sum of the dimension of the second electrode pad in the first direction and the spacing of the plurality of second electrode pads in the first direction.

6. The semiconductor device according to claim 3, characterized in that: The first detection pad, which is set up for the first electrode pad that does not contact the second electrode pad, outputs the first voltage. The first detection pad, which is set to contact the first electrode pad with the second electrode pad, outputs a voltage between the first voltage and the second voltage, namely a third voltage.

7. The semiconductor device according to claim 3, characterized in that: The first semiconductor chip includes multiple third electrode pads and a third detection pad. The plurality of third electrode pads are disposed on the bonding surface of the first semiconductor chip and the second semiconductor chip, and are connected to the first voltage supply node. The third detection pad is provided for at least a portion of the plurality of third electrode pads, and is used to monitor the potential of the third electrode pad from outside the first semiconductor chip. The plurality of third electrode pads are arranged in a second direction different from the first direction, wherein each electrode pad in the second direction has the same size and the spacing between the electrode pads in the second direction is constant. The second semiconductor chip includes multiple fourth electrode pads and a fourth detection pad. The plurality of fourth electrode pads are disposed on the bonding surface of the second semiconductor chip that is bonded to the first semiconductor chip, and are connected to the second voltage supply node. The fourth detection pad is provided for at least a portion of the plurality of fourth electrode pads, and is used to monitor the potential of the fourth electrode pad from outside the second semiconductor chip. The plurality of fourth electrode pads are arranged in the second direction, wherein each electrode pad in the second direction has the same size and the spacing between the electrode pads in the second direction is constant. The plurality of third electrode pads and the plurality of fourth electrode pads are arranged in a row in the second direction when viewed from above.

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