Dram identification method, apparatus, and storage medium

Abstract

The application discloses a DRAM identification method and device and a storage medium, relates to the chip technical field, and comprises the following steps: setting a test environment corresponding to a DRAM based on a test environment parameter; writing to-be-written data into a full address space of the DRAM according to an address access sequence based on the test environment; disabling an automatic refresh function corresponding to the DRAM and recording a static duration; in the case where it is detected that the static duration reaches a preset delay time, the automatic refresh function is enabled, and the full address space of the DRAM is read; determining a first preset number of first error addresses based on error data in the read data; and determining a chip identification corresponding to the DRAM based on the first error addresses. According to the application, the chip identification corresponding to the DRAM is determined according to the error addresses, so that the uniqueness identification of the DRAM chip is obtained, and the uniqueness identification of each DRAM chip can be accurately generated by using an existing professional test machine.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a DRAM identification method, apparatus and storage medium. Background Technology

[0002] Currently, during the wafer manufacturing stage, each DRAM chip is manufactured based on different wafer locations, batches, and process parameters. Inevitably, yield fluctuations, defect distributions, and aging differences exist during the manufacturing process. If a DRAM chip malfunctions in a customer's system, the original manufacturer must be able to quickly pinpoint the root cause of the problem—whether it's a problem with a specific batch of wafers, a particular process step, or a specific chip. Therefore, during wafer testing or post-packaging testing (Final Test), the manufacturer generates and writes a unique chip serial number (SN) for each good chip. The chip serial number typically includes information such as the manufacturer code, manufacturing date, wafer number, wafer location, and serial number, and is stored in the chip's internal registers.

[0003] However, the chip serial number can only be read by granting access to the internal registers of the DRAM chip through the manufacturer's proprietary test mode code. Manufacturers typically do not grant this test mode code access to end users or third parties. This results in a lack of effective means for end users to uniquely identify and track individual chips throughout their entire lifecycle after the chip has undergone factory testing, screening, and subsequent system-level reliability testing (such as aging and high / low temperature shock).

[0004] Therefore, how to accurately obtain the unique identifier of DRAM chips is a problem that urgently needs to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a DRAM identification method, apparatus and storage medium, which aims to solve the technical problem of how to accurately obtain the unique identifier of a DRAM chip.

[0007] To achieve the above objectives, this application proposes a DRAM identification method, which includes: When the DRAM chip lifecycle is detected to be in a stable operating period, the test parameters corresponding to the DRAM are obtained, wherein the test parameters include test environment parameters, data to be written, and address access order; The test environment corresponding to the DRAM is set based on the test environment parameters; Based on the test environment, the data to be written is written into the full address space of the DRAM according to the address access order; Disable the automatic refresh function corresponding to the DRAM and record the duration of inactivity, which is the duration recorded from the moment the automatic refresh function is disabled; If the static duration is detected to have reached the preset delay time, the automatic refresh function is activated, and the full address space of the DRAM is read to obtain the read data. Based on the erroneous data in the read data, a first preset number of first error addresses are determined; The chip identifier corresponding to the DRAM is determined based on the first error address.

[0008] In one embodiment, the step of determining a first preset number of first error addresses based on the erroneous data in the read data includes: The data to be written is compared with the data to be read to obtain the error data; Obtain the second error address corresponding to the error data and the error time corresponding to each second error address; The second error addresses are sorted according to the order of the error times to obtain the sorting result; The first preset number of error addresses that appear at the top of the sorted results are taken as the first error address.

[0009] In one embodiment, the step of determining the chip identifier corresponding to the DRAM based on the first error address includes: The detection records whether the number of times the static duration has been recorded has reached a preset number; If the cumulative number of times the static duration is detected does not reach the preset number, the duration of the preset delay time is increased and used as the updated preset delay time. If the cumulative number of times the static duration is detected reaches a preset number, the occurrence frequency corresponding to each first error address is obtained based on all first error addresses obtained before the current time. The error address with the highest frequency among the first error addresses is taken as the target error address; The chip identifier corresponding to the DRAM is determined based on the target error address.

[0010] In one embodiment, the step of determining the chip identifier corresponding to the DRAM based on the target error address includes: The various target error addresses are concatenated, and the concatenation result is used as the chip identifier.

[0011] In one embodiment, the test environment parameters include target ambient temperature, target operating voltage, and target timing parameters. The step of setting the test environment corresponding to the DRAM based on the test environment parameters includes: The ambient temperature of the DRAM environment is set based on the target ambient temperature; The power supply voltage corresponding to the DRAM is set based on the target operating voltage; Set the target timing parameters to the timing parameters corresponding to the DRAM.

[0012] In one embodiment, the DRAM includes a chip lifecycle monitoring device. Before the step of obtaining the test parameters corresponding to the DRAM when the chip lifecycle of the DRAM is detected to be in a stable operating period, the DRAM identification method further includes: The oscillation characteristic parameters output by the chip lifecycle monitoring device are detected; Determine whether the DRAM chip is in a stable operating period based on the changes in oscillation characteristic parameters.

[0013] In one embodiment, the oscillation characteristic parameters include oscillation frequency and signal waveform, and the step of determining whether the DRAM chip lifecycle is in a stable operating period based on the changes in the oscillation characteristic parameters includes: If the oscillation frequency of the early output changes drastically, it is determined that the DRAM chip life cycle is in the first stage of the stable operating period. If the oscillation frequency stabilizes after the initial output oscillation frequency has changed drastically, or if the output oscillation frequency remains stable, then the DRAM chip lifecycle is determined to be in the second stage of the stable operating period. If, after entering the second stable phase, the output oscillation frequency fluctuates drastically, or the overall potential change of the output signal waveform exceeds the threshold, then the DRAM chip lifecycle is determined to be in the third stage of the stable operating period.

[0014] Furthermore, to achieve the above objectives, this application also proposes a DRAM identification device, the device comprising: The acquisition module is used to acquire the test parameters corresponding to the DRAM when the chip life cycle of the DRAM is detected to be in a stable working period. The test parameters include test environment parameters, data to be written, and address access order. The setting module is used to set the test environment corresponding to the DRAM based on the test environment parameters; The write module is used to write the data to be written into the full address space of the DRAM according to the address access order based on the test environment. The disabling module is used to disable the automatic refresh function corresponding to the DRAM and record the duration of inactivity, wherein the duration of inactivity is the duration recorded from the time the automatic refresh function is disabled. The enable module is used to enable the automatic refresh function and read the full address space of the DRAM to obtain the read data when the static duration is detected to have reached a preset delay time. The determining module is used to determine a first preset number of first error addresses based on the error data in the read data; The identification module is used to determine the chip identifier corresponding to the DRAM based on the first error address.

[0015] In addition, to achieve the above objectives, this application also proposes a DRAM identification device, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the DRAM identification method as described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the DRAM identification method described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: By acquiring test parameters for the DRAM when it is detected that the DRAM chip is in a stable operating period, the test parameters include test environment parameters, data to be written, and address access order. The test environment for the DRAM is set based on the test environment parameters. Based on the test environment, the data to be written is written into the full address space of the DRAM according to the address access order. The automatic refresh function for the DRAM is disabled, and the idle duration is recorded, starting from the time the automatic refresh function is disabled. If the idle duration reaches a preset delay, the automatic refresh function is enabled, and the full address space of the DRAM is read to obtain read data. Based on the error data in the read data, a first preset number of first error addresses are determined. The chip identifier corresponding to the DRAM is determined based on the first error addresses. By writing the data to be written into the full address space of the DRAM in a stable operating period and then disabling the automatic refresh function, the error addresses of the erroneous data are determined through the read data of the DRAM, and the chip identifier corresponding to the DRAM is determined based on the error addresses, a unique identifier for the DRAM chip is obtained. This allows for accurate generation of a unique identifier for each DRAM chip using existing professional testing equipment, without the need for dedicated and expensive testing equipment. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating an embodiment of the DRAM identification method of this application. Figure 2 This is a schematic diagram of the module structure of the DRAM identification device according to an embodiment of this application; Figure 3 This is a schematic diagram of the device structure of the hardware operating environment involved in the DRAM identification method in this application embodiment.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is as follows: When the DRAM chip lifecycle is detected to be in a stable operating period, the test parameters corresponding to the DRAM are obtained, wherein the test parameters include test environment parameters, data to be written, and address access order; the test environment corresponding to the DRAM is set based on the test environment parameters; based on the test environment, the data to be written is written to the full address space of the DRAM according to the address access order; the automatic refresh function corresponding to the DRAM is disabled and the idle duration is recorded, wherein the idle duration is the duration recorded from the time the automatic refresh function is disabled; when the idle duration is detected to reach a preset delay time, the automatic refresh function is enabled, and the full address space of the DRAM is read to obtain read data; based on the error data in the read data, a first preset number of first error addresses are determined; based on the first error addresses, the chip identifier corresponding to the DRAM is determined.

[0025] In this embodiment, for ease of description, the DRAM identification device will be used as the execution subject in the following description.

[0026] Currently, during the wafer manufacturing stage, each DRAM chip is manufactured based on different wafer locations, batches, and process parameters. Inevitably, yield fluctuations, defect distributions, and aging differences exist during the manufacturing process. If a DRAM chip malfunctions in a customer's system, the original manufacturer must be able to quickly pinpoint the root cause of the problem—whether it's a problem with a specific batch of wafers, a particular process step, or a specific chip. Therefore, during wafer testing or post-packaging testing (Final Test), the manufacturer generates and writes a unique chip serial number (SN) for each good chip. The chip serial number typically includes information such as the manufacturer code, manufacturing date, wafer number, wafer location, and serial number, and is stored in the chip's internal registers.

[0027] However, the chip serial number can only be read by granting access to the internal registers of the DRAM chip through the manufacturer's proprietary test mode code. Manufacturers typically do not grant this test mode code access to end users or third parties. This results in a lack of effective means for end users to uniquely identify and track individual chips throughout their entire lifecycle after the chip has undergone factory testing, screening, and subsequent system-level reliability testing (such as aging and high / low temperature shock).

[0028] Therefore, how to accurately obtain the unique identifier of DRAM chips is a problem that urgently needs to be solved.

[0029] This application provides a solution that disables the automatic refresh function after writing the data to be written to the full address space of a DRAM that is in a stable operating period. Then, the error address of the erroneous data is determined by reading the data from the DRAM, and the chip identifier corresponding to the DRAM is determined based on the error address to obtain the unique identifier of the DRAM chip. This allows for the accurate generation of the unique identifier of each DRAM chip using existing professional testing equipment, without the need for dedicated and expensive testing equipment.

[0030] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or DRAM identification device capable of performing the above functions. The following description uses a DRAM identification device as an example to illustrate this embodiment and the subsequent embodiments.

[0031] Based on this, embodiments of this application provide a DRAM identification method, referring to... Figure 1 , Figure 1This is a flowchart illustrating the first embodiment of the DRAM identification method of this application.

[0032] In this embodiment, the DRAM identification method includes steps S110~S150: Step S110: When it is detected that the DRAM chip life cycle is in a stable working period, the test parameters corresponding to the DRAM are obtained. The test parameters include test environment parameters, data to be written and address access order, and the DRAM is in a stable working period. Step S120: Set the test environment corresponding to the DRAM based on the test environment parameters; Step S130: Based on the test environment, write the data to be written into the full address space of the DRAM according to the address access order; Step S140: Disable the automatic refresh function corresponding to the DRAM and record the duration of inactivity. The duration of inactivity is the duration recorded from the time the automatic refresh function is disabled. Step S150: If the static duration is detected to have reached the preset delay time, the automatic refresh function is activated, and the full address space of the DRAM is read to obtain the read data. Step S160: Based on the erroneous data in the read data, determine a first preset number of first error addresses; Step S170: Determine the chip identifier corresponding to the DRAM based on the first error address.

[0033] It's important to note that a DRAM memory cell consists of a transistor and a capacitor. The capacitor stores electrical charge; when there is charge, the value is 1, and when there is no charge, it's 0. However, capacitors can leak current, and the charge naturally decays over time. If the charge isn't replenished in time, data will be lost. Therefore, a refresh operation is needed periodically to replenish the charge of all memory cells. The refresh process is as follows: 1. Read the data from the memory cell. 2. Write it back (replenish the charge).

[0034] It should be noted that, as chips enter a stable aging period (stable operating period), the address distribution must remain fixed and not drift over time. Therefore, the unique identifier of the chip generated using the physical aging characteristics of DRAM has high stability, which necessitates determining that the DRAM chip lifecycle is in a stable operating period.

[0035] It should be noted that control commands can be sent to the testing equipment via relevant components. After receiving the control commands, the testing equipment applies at least one of the following operations to the DRAM chip on the testing equipment: high and low temperature shock and voltage shock. This is to apply accelerated aging stress to the memory chip during its operation, thereby bringing the internal memory cells of the chip into a stable operating period.

[0036] Specifically, high and low temperature shock test chambers can be used to adjust the temperature to subject memory chips to high and low temperature shocks. For example, the temperature can be adjusted from -40℃ to 125℃ and then back to -40℃, with each cycle lasting approximately one hour, for a total of 500 cycles. Alternatively, voltage shocks can be applied to the memory chips on the test bench by adjusting the power supply voltage. This can be achieved by continuously applying a high voltage for a certain period or by applying periodically fluctuating voltages, switching according to a preset cycle.

[0037] In one feasible implementation, the DRAM includes a chip lifecycle monitoring device, and after step S170, the DRAM identification method may further include steps S180-S190: Step S180: Detect the oscillation characteristic parameters output by the chip lifecycle monitoring device; Step S190: Determine whether the DRAM chip lifecycle is in a stable operating period based on the change status of the oscillation characteristic parameters.

[0038] In one feasible implementation, a chip lifecycle monitoring device, such as an RC oscillator, is embedded in the DRAM, and the RC oscillator serves as a sensing device for the DRAM's entire lifecycle aging process. The RC oscillator includes a capacitor C, a resistor R, wires, and a transistor Tr. The aging state of the DRAM is determined by detecting the oscillation characteristic parameters output by the RC oscillator and analyzing their changes. These oscillation characteristic parameters may include the oscillation frequency and signal waveform; that is, the DRAM's chip lifecycle is determined to be in a stable operating period based on the changes in the oscillation frequency and signal waveform.

[0039] In one feasible implementation, the oscillation characteristic parameters include the oscillation frequency and the signal waveform, and step S190 may include steps S191~S193: Step S191: If the oscillation frequency of the early output changes drastically, it is determined that the DRAM chip life cycle is in the first stage of the stable working period. Step S192: After the oscillation frequency of the early output changes drastically, the oscillation frequency tends to stabilize, or the output oscillation frequency directly enters a period of sustained stability. Then, it is determined that the DRAM chip life cycle is in the second stage of the stable working period. Step S193: If, after entering the second stage of the stable period, the output oscillation frequency fluctuates violently, or the overall potential change of the output signal waveform exceeds the threshold, then the DRAM chip life cycle is determined to be in the third stage of the stable working period.

[0040] Specifically, if the oscillation frequency of the early output changes drastically, the DRAM is determined to be in the first stage of rapid aging, that is, the DRAM chip lifecycle is determined to be in the first stage of stable operation. By accelerating aging, unqualified chips are screened out, preventing defective chips from being released; by accelerating aging, the chip enters the stable period, and the chip's physical characteristics such as charge retention capability and leakage rate tend to stabilize, so that the ChipID generated based on the chip address will not change due to the stable physical characteristics, thus serving as a unique identifier.

[0041] If the oscillation frequency stabilizes after initial sharp fluctuations, or if it directly enters a period of sustained stability, the DRAM is considered to be in the second stage of slow aging, meaning the DRAM chip lifecycle is in the second stage of stable operation. If, after entering the second stage of stability, the output oscillation frequency fluctuates drastically again, or the overall potential change of the output signal waveform exceeds a threshold, the DRAM is considered to be in the third stage before instantaneous failure, meaning the DRAM chip lifecycle is in the third stage of stable operation.

[0042] In this embodiment, when the DRAM chip lifecycle is detected to be in a stable operating period, the corresponding test parameters of the DRAM are obtained. These test parameters include test environment parameters, data to be written, and address access order. The test environment parameters include target ambient temperature, target operating voltage, and target timing parameters. The test parameters can be a pre-set set of fixed test parameters.

[0043] It should be noted that the target ambient temperature refers to the physical ambient temperature of the DRAM chip during the subsequent data hold scan phase. The target operating voltage refers to the supply voltage applied to the DRAM chip during the subsequent data hold scan phase. The target timing parameters refer to the timing control parameters used by the DRAM chip during read and write operations in the subsequent data hold scan phase. The data to be written refers to the data written to the DRAM chip's address space during the subsequent data hold scan phase, which can be, for example, all 0s, all 1s, or a pseudo-random sequence. The address access order refers to the order in which the DRAM address is accessed during the "write" and "read" phases of the subsequent data hold scan phase, such as row-major, column-major, or random access.

[0044] When the test parameters are obtained, the test environment corresponding to the DRAM is set based on the test environment parameters. Specifically, the temperature of the test environment corresponding to the DRAM is set based on the target ambient temperature, the power supply voltage of the DRAM is set based on the target operating voltage, and the timing of the DRAM is set based on the timing parameters.

[0045] In one feasible implementation, step S120 may include steps S121 to S123: Step S121: Set the ambient temperature of the environment where the DRAM is located based on the target ambient temperature; Step S122: Set the power supply voltage corresponding to the DRAM based on the target operating voltage; Step S123: Set the target timing parameters to the timing parameters corresponding to the DRAM.

[0046] It's important to note that ambient temperature affects the charge retention capability of DRAM chips. When the temperature rises, transistor leakage increases, leading to faster charge decay and a higher likelihood of errors. Conversely, when the temperature decreases, transistor leakage decreases, resulting in longer charge retention time and fewer errors. Therefore, temperature fluctuations can cause the same chip to generate different error addresses in different tests, leading to unstable ChipIDs. Thus, it's necessary to lock in the ambient temperature. Specifically, this involves setting a target ambient temperature for the DRAM's environment to ensure that the ambient temperature remains consistently at that target temperature.

[0047] It's important to note that the operating voltage directly affects the charge retention capability of DRAM chip memory cells. When the voltage decreases, insufficient charge injection leads to a decline in charge retention capability, making errors more likely. When the voltage increases, the charge becomes more stable, thus extending the charge retention time and reducing errors. Therefore, voltage fluctuations can cause the same chip to produce different error addresses in different tests, resulting in unstable ChipIDs. Thus, it's necessary to lock the operating voltage. Specifically, this involves setting the DRAM's power supply voltage to a target operating voltage, ensuring that the DRAM's power supply voltage remains consistently at that target operating voltage.

[0048] It should be noted that different timing parameters affect read / write speed and stability, and if they are not fixed, test results will be incomparable. Therefore, it is necessary to lock the timing parameters, which may include parameters such as tCL, tRCD, tRP, and tRAS. The timing parameters are locked by setting the target timing parameters to the timing parameters corresponding to the DRAM.

[0049] It's important to note that different data patterns have varying impacts on charge retention. For example, all zeros typically result in higher leakage rates (because the transistors are in the on state), making it easier to expose "weakly retained memory cells." All one-digit data results in lower leakage rates, potentially masking weakly retained cells. Pseudo-random sequences more closely approximate the true data distribution but may increase testing complexity. By locking all addresses to be written with the same data, subsequent comparisons only reflect "physical differences" rather than "data pattern differences." Therefore, it's necessary to lock the content of the data to be written, meaning that the same data is written to the entire address space of the DRAM each time.

[0050] It should be noted that different access orders may lead to variations in the memory controller's prefetching, caching, and row activation strategies, thus affecting read / write stability. If the access order is not fixed, the same chip may produce different error addresses in different tests due to different access paths, ultimately causing the generated ChipID to drift. Therefore, to ensure test consistency, the address access order needs to be locked, meaning that the data to be written is written to the full address space of DRAM in the same address access order each time.

[0051] In this embodiment, once the test environment for the DRAM is set up, the data to be written is written to the full address space of the DRAM according to the address access order based on the current test environment. Specifically, the CPU's memory controller sends a write command according to the address access order to write the data to be written to the full address space of the DRAM. The writing method can also be in the form of blocks (e.g., by page or by row) to improve writing efficiency.

[0052] After writing the data to be written into the DRAM, the corresponding auto-refresh function of the DRAM is disabled, and the resting duration is recorded. Specifically, auto-refresh is disabled using the BIOS or memory controller registers, and all refresh signals are turned off to cut off the charge replenishment power, allowing the memory cells to decay naturally, thereby disabling the refresh mechanism. After disabling the refresh mechanism, the system enters a resting phase, where the resting duration is recorded. This resting duration is the time recorded from the moment the auto-refresh function is disabled, meaning the resting duration is the duration the auto-refresh function is disabled.

[0053] In this embodiment, when recording the duration of stillness, it can be determined in real time whether the duration of stillness has reached the preset delay time. If the duration of stillness has reached the preset delay time, the automatic refresh function is enabled, and the full address space of the DRAM is read to obtain the read data. Specifically, the automatic refresh mechanism of the DRAM is re-enabled using the BIOS or memory controller register. After the automatic refresh mechanism is enabled, the data in the full address space of the DRAM is read to obtain the read data.

[0054] After acquiring the read data, based on the erroneous data in the read data, a first preset number of first error addresses are determined. Specifically, the read data is compared with the data to be written to identify the erroneous data in the read data and to determine the error address corresponding to the erroneous data. This error address is the address where the erroneous data is located in the full address of the DRAM. Then, a first preset number of first error addresses are selected from the error addresses corresponding to the erroneous data. That is, the first error address is the address where a portion of the erroneous data is located in the full address of the DRAM.

[0055] Specifically, after disabling the automatic refresh function, no read or write operations are performed on the DRAM to avoid interference. The first preset number can be set appropriately, for example, to 3 or 5.

[0056] In one feasible implementation, step S160 may include steps S161 to S164: Step S161: Compare the data to be written with the data to be read to obtain erroneous data; Step S162: Obtain the second error address corresponding to the error data and the error time corresponding to each second error address; Step S163: Sort the second error addresses according to the order of the error times to obtain the sorting result; Step S164: Obtain the first preset number of error addresses that are ranked first in the sorting results as the first error addresses.

[0057] In this embodiment, when the read data is obtained, the data to be written is compared with the read data, that is, the data to be written and the read data are compared bit by bit to obtain erroneous data. The erroneous data is the data at the corresponding address in the read data that is inconsistent with the data at the corresponding address in the data to be written.

[0058] When erroneous data is obtained, the second error address corresponding to the erroneous data and the error time corresponding to each second error address are obtained; the second error address is the address where the erroneous data is located in the full address of DRAM.

[0059] In this embodiment, when the error time of the second error address is obtained, the second error addresses are sorted based on the error time. For example, the second error addresses are sorted according to the order of their error times to obtain a sorting result.

[0060] When obtaining the sorting result, the first preset number of error addresses at the top of the sorting result are taken as the first error addresses. For example, the first 3 error addresses at the top of the sorting result are taken as the first error addresses. The error addresses at the top of the sorting result have earlier error times, and the error addresses with earlier error times have weaker data retention capabilities. Therefore, the first N error addresses with the weakest data retention capabilities can be selected from the error addresses as the first error addresses, where N is the first preset number.

[0061] Specifically, when the first error address is obtained, the chip identifier corresponding to the DRAM is determined based on the first error address. If multiple rounds of scanning operations are performed on the DRAM, i.e., the operations in steps S120-S140, the target error address is obtained by filtering the first error addresses in all rounds, and the chip identifier corresponding to the DRAM is determined based on the target error address.

[0062] In one feasible implementation, step S170 may include steps S171 to S175: Step S171: Check whether the number of times the static duration is recorded has reached a preset number; Step S172: If the cumulative number of times the static duration is detected has not reached the preset number, the duration of the preset delay time is increased and used as the updated preset delay time. Step S173: Based on all the first error addresses obtained before the current time, obtain the occurrence frequency corresponding to each of the first error addresses; Step S174: Select the error address with the highest frequency among the first error addresses as the target error address; Step S175: Determine the chip identifier corresponding to the DRAM based on the target error address.

[0063] In this embodiment, the number of scans for the scanning operation can be preset, i.e., the preset number of scans. When the first error address is obtained, the number of records of the static duration is updated, i.e., the number of records of the static duration is increased by 1, and it is detected whether the number of records of the static duration has reached the preset number of scans.

[0064] If the number of times the static duration is recorded does not reach the preset number, the duration of the preset delay time is increased and used as the updated preset delay time. Then, the process returns to step S130 based on the updated preset delay time to perform the next round of scanning operation. That is, when the scanning operation is performed again, it is determined whether the static duration has reached the updated preset delay time.

[0065] If the number of times the static duration is recorded reaches a preset number, then all first error addresses obtained before the current time are obtained. Based on all the first error addresses, the occurrence frequency corresponding to each first error address is obtained, that is, the occurrence number of each first error address is counted.

[0066] When the frequency of occurrence is obtained, the error address with the highest frequency among the first error addresses is taken as the target error address. Specifically, the first error addresses can be sorted in descending order of the frequency of occurrence to obtain the error address sorting result. The second preset number of error addresses that appear at the top of the sorting result are taken as the target error address.

[0067] When the target error address is obtained, the chip identifier corresponding to the DRAM is determined based on the target error address. In one feasible implementation, step S175 may include: concatenating the target error addresses and using the concatenation result as the chip identifier.

[0068] In this embodiment, when the target error address is obtained, the target error address is concatenated, and the concatenation result is used as the chip identifier (ChipID) of the DRAM. Specifically, the target error addresses are concatenated in a preset order, for example, concatenating the target error addresses in descending order of frequency of occurrence, or concatenating the target error addresses in ascending order of frequency of occurrence, to obtain the concatenation result.

[0069] The second preset quantity can be set reasonably, for example, the second preset quantity is 3, 5, etc.

[0070] It should be noted that when determining the unique identifier (chip identifier) ​​of a DRAM chip, this chip identifier is not stored inside the DRAM chip itself. If, during subsequent use of the chip, it is necessary to determine whether the currently used DRAM chip is the one whose chip identifier was previously determined, the process of determining the DRAM identifier in this application can be repeated. When obtaining the first error address of the currently used DRAM chip, the first error address of the currently used DRAM chip can be compared with the first error address of the previously determined DRAM chip identifier. If there are target DRAMs with the same error address whose chip identifier has been determined in a number greater than or equal to a preset threshold, then the currently used DRAM chip can be considered to be that target DRAM.

[0071] In one feasible implementation, this embodiment provides a DRAM identification method. When the DRAM chip lifecycle is detected to be in a stable operating period, test parameters corresponding to the DRAM are obtained. These test parameters include test environment parameters, data to be written, and address access order. A test environment is set for the DRAM based on the test environment parameters. Based on the test environment, the data to be written is written to the full address space of the DRAM according to the address access order. The automatic refresh function corresponding to the DRAM is disabled, and a static duration is recorded, starting from the moment the automatic refresh function is disabled. When the static duration is detected to reach a preset delay time, the automatic refresh function is enabled, and the full address space of the DRAM is read to obtain read data. Based on the error data in the read data, a first preset number of first error addresses are determined. The chip identifier corresponding to the DRAM is determined based on the first error addresses. By writing the data to be written into the full address space of the DRAM in a stable operating period and then disabling the automatic refresh function, the error address of the erroneous data is determined by reading the data from the DRAM. Based on the error address, the chip identifier corresponding to the DRAM is determined to obtain the unique identifier of the DRAM chip. This allows for the accurate generation of the unique identifier of each DRAM chip using existing professional testing equipment, without the need for dedicated and expensive testing equipment.

[0072] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the DRAM identification method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0073] This application also provides a DRAM identification device, please refer to... Figure 2 The DRAM identification device includes: The acquisition module 10 is used to acquire the test parameters corresponding to the DRAM when the chip life cycle of the DRAM is detected to be in a stable working period. The test parameters include test environment parameters, data to be written, and address access order. Setting module 20 is used to set the test environment corresponding to the DRAM based on the test environment parameters; The writing module 30 is used to write the data to be written into the full address space of the DRAM according to the address access order based on the test environment. The disabling module 40 is used to disable the automatic refresh function corresponding to the DRAM and record the static duration, which is the duration recorded from the time the automatic refresh function is disabled. The enabling module 50 is used to enable the automatic refresh function and read the full address space of the DRAM to obtain the read data when the static duration is detected to have reached a preset delay time. The determining module 60 is used to determine a first preset number of first error addresses based on the error data in the read data; The identification module 70 is used to determine the chip identifier corresponding to the DRAM based on the first error address.

[0074] The DRAM identification device provided in this application, employing the DRAM identification method in the above embodiments, can solve the technical problem of how to accurately obtain the unique identifier of a DRAM chip. Compared with the prior art, the beneficial effects of the DRAM identification device provided in this application are the same as those of the DRAM identification method provided in the above embodiments, and other technical features in the DRAM identification device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0075] This application provides a DRAM identification device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the DRAM identification method in Embodiment 1 above.

[0076] The following is for reference. Figure 3 The diagram illustrates a structural schematic suitable for implementing the DRAM identification device in the embodiments of this application. The DRAM identification device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 3 The DRAM identification device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0077] like Figure 3As shown, the DRAM identification device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in the read-only memory 1002 or a program loaded from the storage device 1003 into the random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the DRAM identification device. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the DRAM identification device to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show DRAM identification devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0078] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0079] The DRAM identification device provided in this application, employing the DRAM identification method in the above embodiments, can solve the technical problem of how to accurately obtain the unique identifier of a DRAM chip. Compared with the prior art, the beneficial effects of the DRAM identification device provided in this application are the same as those of the DRAM identification method provided in the above embodiments, and other technical features in this DRAM identification device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0080] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0082] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the DRAM identification method in the above embodiments.

[0083] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0084] The aforementioned computer-readable storage medium may be included in the DRAM identification device; or it may exist independently and not assembled into the DRAM identification device.

[0085] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by the DRAM identification device, the DRAM identification device: when it detects that the DRAM chip lifecycle is in a stable operating period, acquires test parameters corresponding to the DRAM, wherein the test parameters include test environment parameters, data to be written, and address access order; sets the test environment corresponding to the DRAM based on the test environment parameters; writes the data to be written into the full address space of the DRAM according to the address access order based on the test environment; disables the automatic refresh function corresponding to the DRAM and records the idle duration, the idle duration being the duration recorded from the moment the automatic refresh function is disabled; when it is detected that the idle duration reaches a preset delay time, enables the automatic refresh function and reads the full address space of the DRAM to obtain read data; determines a first preset number of first error addresses based on the error data in the read data; and determines the chip identifier corresponding to the DRAM based on the first error addresses.

[0086] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0088] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0089] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described DRAM identification method, thereby solving the technical problem of how to accurately obtain the unique identifier of a DRAM chip. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the DRAM identification method provided in the above embodiments, and will not be repeated here.

[0090] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the DRAM identification method described above.

[0091] The computer program product provided in this application solves the technical problem of how to accurately obtain the unique identifier of a DRAM chip. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the DRAM identification method provided in the above embodiments, and will not be repeated here.

[0092] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A DRAM identification method, characterized in that, The DRAM identification method includes: When the DRAM chip lifecycle is detected to be in a stable working period, the test parameters corresponding to the DRAM are obtained, wherein the test parameters include test environment parameters, data to be written, and address access order; The test environment corresponding to the DRAM is set based on the test environment parameters; Based on the test environment, the data to be written is written into the full address space of the DRAM according to the address access order; Disable the automatic refresh function corresponding to the DRAM and record the duration of inactivity, which is the duration recorded from the moment the automatic refresh function is disabled; If the static duration is detected to have reached the preset delay time, the automatic refresh function is activated, and the full address space of the DRAM is read to obtain the read data. Based on the erroneous data in the read data, a first preset number of first error addresses are determined; The chip identifier corresponding to the DRAM is determined based on the first error address; The step of determining a first preset number of first error addresses based on the erroneous data in the read data includes: The data to be written is compared with the data to be read to obtain the error data; Obtain the second error address corresponding to the error data and the error time corresponding to each second error address; The second error addresses are sorted according to the order of the error times to obtain the sorting result; The first preset number of error addresses that appear at the top of the sorted results are taken as the first error address.

2. The DRAM identification method as described in claim 1, characterized in that, The step of determining the chip identifier corresponding to the DRAM based on the first error address includes: The detection records whether the number of times the static duration has been recorded has reached a preset number; If the cumulative number of times the static duration is detected does not reach the preset number, the duration of the preset delay time is increased and used as the updated preset delay time. If the cumulative number of times the static duration is detected reaches a preset number, the occurrence frequency corresponding to each first error address is obtained based on all first error addresses obtained before the current time. The error address with the highest frequency among the first error addresses is taken as the target error address; The chip identifier corresponding to the DRAM is determined based on the target error address.

3. The DRAM identification method as described in claim 2, characterized in that, The step of determining the chip identifier corresponding to the DRAM based on the target error address includes: The various target error addresses are concatenated, and the concatenation result is used as the chip identifier.

4. The DRAM identification method as described in claim 1, characterized in that, The test environment parameters include target ambient temperature, target operating voltage, and target timing parameters. The step of setting the test environment corresponding to the DRAM based on the test environment parameters includes: The ambient temperature of the DRAM environment is set based on the target ambient temperature; The power supply voltage corresponding to the DRAM is set based on the target operating voltage; Set the target timing parameters to the timing parameters corresponding to the DRAM.

5. The DRAM identification method according to any one of claims 1 to 4, characterized in that, The DRAM includes a chip lifecycle monitoring device. Before the step of obtaining the test parameters corresponding to the DRAM when the chip lifecycle of the DRAM is detected to be in a stable operating period, the DRAM identification method further includes: The oscillation characteristic parameters output by the chip lifecycle monitoring device are detected; Determine whether the DRAM chip is in a stable operating period based on the changes in oscillation characteristic parameters.

6. The DRAM identification method as described in claim 5, characterized in that, The oscillation characteristic parameters include oscillation frequency and signal waveform. The step of determining whether the DRAM chip lifecycle is in a stable operating period based on the changes in the oscillation characteristic parameters includes: If the oscillation frequency of the early output changes drastically, it is determined that the DRAM chip life cycle is in the first stage of the stable operating period. If the oscillation frequency stabilizes after the initial output oscillation frequency has changed drastically, or if the output oscillation frequency remains stable, then the DRAM chip lifecycle is determined to be in the second stage of the stable operating period. If, after entering the second stable phase, the output oscillation frequency fluctuates drastically, or the overall potential change of the output signal waveform exceeds the threshold, then the DRAM chip lifecycle is determined to be in the third stage of the stable operating period.

7. A DRAM identification device, characterized in that, The device includes: The acquisition module is used to acquire the test parameters corresponding to the DRAM when the chip life cycle of the DRAM is detected to be in a stable working period. The test parameters include test environment parameters, data to be written, and address access order. The setting module is used to set the test environment corresponding to the DRAM based on the test environment parameters; The write module is used to write the data to be written into the full address space of the DRAM according to the address access order based on the test environment. The disabling module is used to disable the automatic refresh function corresponding to the DRAM and record the duration of inactivity, wherein the duration of inactivity is the duration recorded from the moment the automatic refresh function is disabled. The enable module is used to enable the automatic refresh function and read the full address space of the DRAM to obtain the read data when the static duration is detected to have reached a preset delay time. The determination module is used to determine a first preset number of first error addresses based on the error data in the read data, wherein the data to be written is compared with the read data to obtain error data, the second error address corresponding to the error data and the error time corresponding to each second error address are obtained, the second error addresses are sorted according to the order of the error times to obtain a sorting result, and the first preset number of error addresses that are ranked first in the sorting result are obtained as the first error addresses. The identification module is used to determine the chip identifier corresponding to the DRAM based on the first error address.

8. A DRAM identification device, characterized in that, The apparatus includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the DRAM identification method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the DRAM identification method as described in any one of claims 1 to 6.

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